diff options
Diffstat (limited to 'bsps/powerpc/include/bsp')
| -rw-r--r-- | bsps/powerpc/include/bsp/consoleIo.h | 38 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/flashPgm.h | 209 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/flashPgmPvt.h | 274 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/irq_supp.h | 124 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/linker-symbols.h | 139 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/motorola.h | 69 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/openpic.h | 378 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/pci.h | 84 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/pnp.h | 644 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/residual.h | 356 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/start.h | 84 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/tictac.h | 78 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/tsec.h | 380 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/u-boot-board-info.h | 146 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/uart.h | 190 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/vectors.h | 493 | ||||
| -rw-r--r-- | bsps/powerpc/include/bsp/vpd.h | 143 |
17 files changed, 3829 insertions, 0 deletions
diff --git a/bsps/powerpc/include/bsp/consoleIo.h b/bsps/powerpc/include/bsp/consoleIo.h new file mode 100644 index 0000000000..e62c9d143c --- /dev/null +++ b/bsps/powerpc/include/bsp/consoleIo.h @@ -0,0 +1,38 @@ +/* + * consoleIo.h -- console I/O package interface + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CONSOLE_IO_H +#define __CONSOLE_IO_H + +typedef enum { + CONSOLE_LOG = 1, + CONSOLE_SERIAL = 2, + CONSOLE_VGA = 3, + CONSOLE_VACUUM = 4 +}ioType; + +typedef volatile unsigned char * __io_ptr; + +typedef struct { + __io_ptr io_base; + __io_ptr isa_mem_base; +} board_memory_map; + +extern board_memory_map *ptr_mem_map; + +extern int select_console(ioType t); +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern void debug_putc(const unsigned char c); +extern void debug_putc_onlcr(const char c); +extern int debug_getc(void); +extern int debug_tstc(void); +int kbdreset(void); + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgm.h b/bsps/powerpc/include/bsp/flashPgm.h new file mode 100644 index 0000000000..19f2c4708e --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgm.h @@ -0,0 +1,209 @@ +#ifndef BSP_FLASH_PGM_API_H +#define BSP_FLASH_PGM_API_H + +/* Trivial Flash Programmer */ + +/* Author: Till Straumann <strauman@slac.stanford.edu>, 2006 + * NOTE: copyright info at the bottom of this file + */ + +/* IMPORTANT NOTE + * + * The flash API is NOT THREAD SAFE. During the execution of any of the + * BSP_flashXXX() routines, flash (residing in the same device) + * MUST NOT be accessed by other threads in ANY way (NOT EVEN READ!). + * Read operations may return internal device register contents + * instead of memory array data when issued while a flash device + * is erased, written or queried by the library. + * + * The routines are intended for occasional maintenance use only + * (i.e., not for implementing a file system or similar). + * + * While polling for the completion of block erase operations the + * CPU is yielded to other threads. Busy waiting (interrupts and + * thread dispatching remain enabled) on write operations is employed. + */ + +#include <stdio.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/* Disengage flash write protection. Write protection is implemented + * at the board or chipset level by disabling all write operations/bus cycles + * to the flash device(s). + * With write protection enabled, nothing but 'ordinary' (array) read operations + * are possible. + * Write protection must be disabled not only to erase and write contents + * but also in order to read ID, size, status etc. + * None of the operations (except for BSP_flashWriteEnable()) are possible + * on a write-protected device. + * + * 'bank': flash bank # (usually 0) + * RETURNS: 0 on success, nonzero on error (printing message to stderr). + * + * NOTES: - some boards (MVME5500) don't support 'bank' granularity but + * enable/disable write protection for all devices at once. + * - a jumper-based protection mechanism might be in place + * in addition to the software-based one. Consult the user's + * manual of your board for more information. + */ +int +BSP_flashWriteEnable(int bank); + +/* Engage flash write protection (see above) + */ +int +BSP_flashWriteDisable(int bank); + +/* Erase a region of flash memory. + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'size': number of bytes to erase. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * RETURNS: 0 on success, nonzero on error (printing messages to stderr). + * + * NOTES: - 'offset' and 'size' must be block-aligned. Common 16-bit devices + * have a block size of 0x20000 bytes. If two such devices are + * operated in parallel to form a 32-bit word then the 'effective' + * block size is 0x40000 bytes. The block size can be queried by + * BSP_flashBlockSize(int bank); + * + * - erase operation is verified. + */ +int +BSP_flashErase(int bank, uint32_t offset, uint32_t size, int quiet); + +/* Write data from a buffer to flash. The target area is erased if necessary. + * + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'src': data source block address (in memory). + *'n_bytes': number of bytes to copy. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: - Erase operations are only performed where necessary. I.e., + * if one or both of the boundaries of the destination region is/are + * not block-aligned then adjacent data are preserved provided that + * the relevant chunks of the destination are blank (erased). + * + * | <neighbour> fffffff | + * ^--- destination ----- ^ + * | : block boundary + * f : blank/erased pieces + * + * (If the start of the destination region up to the next block boundary + * is blank then '<neighbour>'-data is preserved. The end of the + * destination is treated the same way.) + * + * - user confirmation is requested before changes are made + * + * - 'src' must not point into the destination bank (no copy + * within a flash bank). + * + * - erase and write operations are verified. + * + * RETURNS: 0 on success, nonzero on error (message printed to stderr). + */ +int +BSP_flashWrite(int bank, uint32_t offset, const char *src, uint32_t n_bytes, int quiet); + +/* Copy contents of a file to flash. + * + * 'fname': Path of a file. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: Convenience wrapper around BSP_flashWrite(); see above for + * args and return value. + */ +int +BSP_flashWriteFile(int bank, uint32_t offset, const char *path, int quiet); + +/* Dump info about available flash to file + * (stdout is used if f==NULL). + * + * RETURNS: 0 + * NOTES: Write protection must be disengaged (see above); + */ +int +BSP_flashDumpInfo(FILE *f); + +/* + * Obtain starting-address of flash bank (as seen from CPU) + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ + +uint32_t +BSP_flashStart(int bank); + +/* + * Obtain size of flash bank (returns ((uint32_t) -1) if the + * bank argument is invalid). + */ +uint32_t +BSP_flashSize(int bank); + +/* + * Obtain block size of flash bank (sector size times + * number of devices in parallel; the block size determines + * alignment and granularity accepted by BSP_flashErase() + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ +uint32_t +BSP_flashBlockSize(int bank); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgmPvt.h b/bsps/powerpc/include/bsp/flashPgmPvt.h new file mode 100644 index 0000000000..c26b8ed01d --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgmPvt.h @@ -0,0 +1,274 @@ +#ifndef FLASH_GLUE_INTERFACE_H +#define FLASH_GLUE_INTERFACE_H + + +/* Trivial flash programmer (for restrictions see below) */ + +/* Author: Till Straumann <strauman@slac.stanford.edu>, 2006 */ + +/* DO NOT INCLUDE THIS HEADER FROM APPLICATION CODE */ + +/* + * Glue interface -- to be used only internally by BSP + * and chip drivers: + * - BSP provides info about what chip drivers to use + * as well as 'wiring' info (how many devices are + * operated in parallel etc). + * - Chip drivers provide low-level 'methods' / 'ops' + * for performing basic operations which are used + * by the code in 'flash.c'. + */ + +/* To keep things simple, this API makes a few assumptions about the + * hardware: + * + * - devices operate with 16-bit data width + * - two devices are used in parallel (stride 4) to + * provide 32-bit data. I.e., the devices are + * organized like this: + * unsigned short flash[FLASH_SIZE][2]; + * - no endianness issues (i.e., flash endianness == CPU endianness) + * - fixed block size + * - fixed buffer size + * - all devices in a bank are identical + * - NOT THREAD SAFE; no locking scheme is implemented. + * - cannot copy within same flash bank. + * - write-timeout uses polling/busy-wait + * + * FIXME: code should be revised to remove assumptions on stride and 16-bit + * width to make it more generic. + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdint.h> + +#define NumberOf(arr) (sizeof(arr)/sizeof(arr[0])) + +#define FLASH_STRIDE(b) 4 /* bytes; currently fixed */ +#define FLASH_WIDTH(b) ((b)->width) +#define FLASH_NDEVS(b) (FLASH_STRIDE(b)/FLASH_WIDTH(b)) + +/* Type declarations */ + +/* Registers */ +typedef uint8_t _u8_a_t __attribute__((may_alias)); +typedef uint16_t _u16_a_t __attribute__((may_alias)); +typedef uint32_t _u32_a_t __attribute__((may_alias)); + +/* Register addresses */ +typedef volatile _u8_a_t *A8; +typedef volatile _u16_a_t *A16; +typedef volatile _u32_a_t *A32; + +struct flash_bank_ops; + +/* + * Description of a flash bank. Multiple + * devices that are used in parallel to + * make up words of FLASH_STRIDE bytes + * are a 'physical' bank. + * + * A bank can even be a 'logical' bank + * if it includes chip-select logic, i.e., + * int can contain multiple adjacent + * 'physical' banks + * + * The BSP must provide an array of 'bankdesc' + * structs and it must initialize the fields + * + * 'start' + * size of bank; may be set to zero to instruct + * the driver to scan a bank of 'max_size' for + * devices (i.e., bank may not be fully populated) + * 'max_size' + * size of fully populated bank (defines address range + * that is scanned for devices). + * If 'max_size' is negative then scanning starts from + * the top rather than from the bottom. + * 'width' + * width of a single device (in bytes). E.g., if + * 2 16-bit devices are used to form a (ATM fixed) + * stride of 4 then 'width = 2'. If four 8-bit + * devices are employed then 'width=1'. + * 'knownVendors' + * array of vendors descriptions to use for scanning + * the bank. + * + */ +struct bankdesc { + uint32_t start; /* start of bank (CPU address) */ + uint32_t size; /* in bytes (figured out automatically) */ + int max_size; /* in case multiple banks are adjacent; + * if max_size < 0 then the bank is scanned + * backwards (from top->bottom) for devices + */ + int width; /* FIXME there might be implicit assumptions still + * that width == 2 + */ + struct vendesc *knownVendors; + /* TODO: we assume identical devices within a bank... */ + + /* The next three variables cache information obtained + * from the applicable vendor and device descriptions. + * They are written by BSP_flashCheckId(). + */ + uint32_t fblksz; /* block size in bytes; includes counting + * parallel 16-bit devices, i.e., if a + * single device has a block-size of xxx + * then fblksz = xxx*ndevs. + */ + struct devdesc *dd; + struct flash_bank_ops *ops; +}; + +struct devdesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + uint32_t size; /* bytes */ + uint32_t bufsz; /* size of write buffer (bytes) */ + uint32_t fblksz; /* sector/block size (bytes) */ +}; + +struct vendesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + + /* array of supported devices; + * the 'ops' specified below + * are used to access these devices + */ + struct devdesc *known_devs; + /* access methods for talking to + * devices associated with this + * vendor description. + */ + struct flash_bank_ops *ops; +}; + +/* Device Access Methods ('ops'); these must be + * implemented by low-level chip drivers + */ + +struct flash_bank_ops { +/* Read vendor/device ID; Return 0 on success, nonzero if unable to read id */ + int (*get_id)(struct bankdesc *b, uint32_t addr, uint32_t *pVendorId, uint32_t *pDeviceId); +/* Unlock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*unlock_block)(struct bankdesc *b, uint32_t addr); +/* Lock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*lock_block)(struct bankdesc *b, uint32_t addr); +/* Erase single block holding 'addr'ess. The routine may + * assume that the address is block/sector aligned. + * + * RETURNS: zero on error, device status on failure. + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + int (*erase_block)(struct bankdesc *b, uint32_t addr); +/* Query the status of the device and assert it's readiness + * leave off in array-reading mode. + * + * RETURNS: 0 on success, error status (result of status query) on error. + * + * NOTES: - error message is printed to stderr. + * - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + uint32_t (*check_ready)(struct bankdesc *b, uint32_t addr); +/* Dump status bits (F_CMD_RD_STA results); + * 'verbose' prints non-error bits, too + */ + void (*print_stat)(struct bankdesc *b, uint32_t sta, int verbose); +/* Switch to array mode; 'addr' can be assumed to be stride-aligned */ + void (*array_mode)(struct bankdesc *b, uint32_t addr); +/* Write N bytes from 'src' to flash: + * 'src[0] .. src[N-1]' -> addr[0]..addr[N-1]. + * N may be assumed to be a multiple of 'stride' + * RETURNS: failure status or zero on success. + */ + uint32_t (*write_line)(struct bankdesc *b, uint32_t addr, const char *src, uint32_t N); +}; + +/* BSP ops (detect banks, handle write-protection on board); + * these must be implemented by the BSP. + */ + +struct flash_bsp_ops { +/* Return descriptor for bank # 'bank' or NULL (invalid arg) */ + struct bankdesc *(*bankcheck)(int bank, int quiet); +/* set (enbl:1), clear (enbl:0) or query (enbl:-1) + * on-board write protection. + * + * RETURNS 0 on success, nonzero on error. + */ + int (*flash_wp)(int bank, int enbl); +/* read a running us clock (for polling timeout) */ + uint32_t (*read_us_timer)(); +}; + +/* This must be provided by the BSP */ +extern struct flash_bsp_ops BSP_flashBspOps; + +/* Available low-level flash drivers, so far */ +extern struct vendesc BSP_flash_vendor_intel[]; +extern struct vendesc BSP_flash_vendor_spansion[]; + +#endif diff --git a/bsps/powerpc/include/bsp/irq_supp.h b/bsps/powerpc/include/bsp/irq_supp.h new file mode 100644 index 0000000000..65af48c87f --- /dev/null +++ b/bsps/powerpc/include/bsp/irq_supp.h @@ -0,0 +1,124 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IRQ_SHARED_IRQ_C_GLUE_H +#define IRQ_SHARED_IRQ_C_GLUE_H +/* + * This header describes the routines that are needed by the shared + * version of 'irq.c' (implementing the RTEMS irq API). They + * must be provided by the BSP. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef BSP_SHARED_HANDLER_SUPPORT +#define BSP_SHARED_HANDLER_SUPPORT 1 +#endif + +#include <rtems.h> +#include <rtems/irq.h> + +#include <bsp/vectors.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * PIC-independent functions to enable/disable interrupt lines at + * the pic. + * + * NOTE: the routines must ignore requests for enabling/disabling + * interrupts that are outside of the range handled by the + * PIC(s). + */ +extern void BSP_enable_irq_at_pic(const rtems_irq_number irqLine); +/* + * RETURNS: nonzero (> 0 ) if irq was enabled originally, zero if irq + * was off and negative value if there was an error. + */ +extern int BSP_disable_irq_at_pic(const rtems_irq_number irqLine); + +/* + * Initialize the PIC. + */ +extern int BSP_setup_the_pic(rtems_irq_global_settings* config); + +/* IRQ dispatcher to be defined by the PIC driver; note that it MUST + * implement shared interrupts. + * Note also that the exception frame passed to this handler is not very + * meaningful. Only the volatile registers and vector info are stored. + * + ******************************************************************* + * The routine must return zero if the interrupt was handled. If a + * nonzero value is returned the dispatcher may panic and flag an + * uncaught exception. + ******************************************************************* + */ +int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum); + +/* + * Snippet to be used by PIC drivers and by bsp_irq_dispatch_list + * traverses list of shared handlers for a given interrupt + * + */ + +static inline void +bsp_irq_dispatch_list_base( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + rtems_irq_connect_data* vchain; + for( vchain = &tbl[irq]; + ((intptr_t)vchain != -1 && vchain->hdl != sentinel); + vchain = (rtems_irq_connect_data*)vchain->next_handler ) + { + vchain->hdl(vchain->handle); + } +} + + +/* + * Snippet to be used by PIC drivers; + * enables interrupts, traverses list of + * shared handlers for a given interrupt + * and restores original irq level + * + * Note that _ISR_Get_level() & friends are preferable to + * manipulating MSR directly. + */ + +static inline void +bsp_irq_dispatch_list( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + register uint32_t l_orig; + + l_orig = _ISR_Get_level(); + + /* Enable all interrupts */ + _ISR_Set_level(0); + + + bsp_irq_dispatch_list_base( tbl, irq, sentinel ); + + /* Restore original level */ + _ISR_Set_level(l_orig); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/include/bsp/linker-symbols.h b/bsps/powerpc/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..de7a6c483d --- /dev/null +++ b/bsps/powerpc/include/bsp/linker-symbols.h @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup powerpc_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H + +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_linker Linker Support + * + * @ingroup powerpc_shared + * + * @brief Linker support. + * + * @{ + */ + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_sbss_begin) +LINKER_SYMBOL(bsp_section_sbss_end) +LINKER_SYMBOL(bsp_section_sbss_size) + +LINKER_SYMBOL(bsp_section_rwextra_begin) +LINKER_SYMBOL(bsp_section_rwextra_end) +LINKER_SYMBOL(bsp_section_rwextra_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_section_nvram_begin) +LINKER_SYMBOL(bsp_section_nvram_end) +LINKER_SYMBOL(bsp_section_nvram_size) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +#define BSP_NVRAM_SECTION __attribute__((section(".bsp_nvram"))) + +#define BSP_NVRAM_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nvram." # subsection))) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/powerpc/include/bsp/motorola.h b/bsps/powerpc/include/bsp/motorola.h new file mode 100644 index 0000000000..14360d56d1 --- /dev/null +++ b/bsps/powerpc/include/bsp/motorola.h @@ -0,0 +1,69 @@ +/* motorola.h + * + * This include file describe the data structure and the functions implemented + * by rtems to identify motorola boards. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H +#define LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H + +#include <bsp/residual.h> +#include <bsp/pci.h> + +typedef enum { + PREP_IBM = 0, + PREP_Radstone = 1, + PREP_Motorola = 2 +} prep_t; + +typedef enum { + MVME_2400 = 0, + MVME_2400_750 = 1, + GENESIS = 2, + POWERSTACK_E = 3, + BLACKAWK = 4, + OMAHA = 5, + UTAH = 6, + POWERSTACK_EX = 7, + MESQUITE = 8, + SITKA = 9, + MESQUITE_W_HAC = 10, + MTX_PLUS = 11, + MTX_WO_PP = 12, + MTX_W_PP = 13, + MVME_2300 = 14, + MVME_2300SC_2600 = 15, + MVME_2600_W_MVME712M = 16, + MVME_2600_2700_W_MVME761 = 17, + MVME_3600_W_MVME712M = 18, + MVME_3600_W_MVME761 = 19, + MVME_1600 = 20, + /* In the table, slot 21 is the marker for end of automatic probe and scan */ + MVME_2100 = 22, + MOTOROLA_UNKNOWN = 255 +} motorolaBoard; + +typedef enum { + HOST_BRIDGE_RAVEN = 0, + HOST_BRIDGE_HAWK = 1, + HOST_BRIDGE_UNKNOWN = 255 +} motorolaHostBridge; + +#define MOTOROLA_CPUTYPE_REG 0x800 +#define MOTOROLA_BASETYPE_REG 0x803 + +extern prep_t checkPrepBoardType(RESIDUAL *res); +extern prep_t currentPrepType; +extern motorolaBoard getMotorolaBoard(void); +extern motorolaBoard currentBoard; +extern const char* motorolaBoardToString(motorolaBoard); +extern const struct _int_map *motorolaIntMap(motorolaBoard board); +extern const void *motorolaIntSwizzle(motorolaBoard board); + +#endif /* LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H */ diff --git a/bsps/powerpc/include/bsp/openpic.h b/bsps/powerpc/include/bsp/openpic.h new file mode 100644 index 0000000000..df782596b5 --- /dev/null +++ b/bsps/powerpc/include/bsp/openpic.h @@ -0,0 +1,378 @@ +/* + * openpic.h -- OpenPIC definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * The Open Programmable Interrupt Controller (PIC) + * Register Interface Specification Revision 1.2 + * + * Issue Date: October 1995 + * + * Issued jointly by Advanced Micro Devices and Cyrix Corporation + * + * AMD is a registered trademark of Advanced Micro Devices, Inc. + * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc. + * All Rights Reserved. + * + * To receive a copy of this documentation, send an email to openpic@amd.com. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_OPENPIC_H +#define _RTEMS_OPENPIC_H + + /* + * OpenPIC supports up to 2048 interrupt sources and up to 32 processors + */ +#define OPENPIC_MAX_SOURCES 2048 +#define OPENPIC_MAX_PROCESSORS 32 + +#define OPENPIC_NUM_TIMERS 4 +#define OPENPIC_NUM_IPI 4 +#define OPENPIC_NUM_PRI 16 +#define OPENPIC_NUM_VECTORS 256 + + /* + * Vector numbers + */ + +#define OPENPIC_VEC_SOURCE 0x10 /* and up */ +#define OPENPIC_VEC_TIMER 0x40 /* and up */ +#define OPENPIC_VEC_IPI 0x50 /* and up */ +#define OPENPIC_VEC_SPURIOUS 99 + + /* + * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries + */ + +typedef struct _OpenPIC_Reg { + unsigned int Reg; /* Little endian! */ + char Pad[0xc]; +} OpenPIC_Reg; + + /* + * Per Processor Registers + */ + +typedef struct _OpenPIC_Processor { + /* + * Private Shadow Registers (for SLiC backwards compatibility) + */ + unsigned int IPI0_Dispatch_Shadow; /* Write Only */ + char Pad1[0x4]; + unsigned int IPI0_Vector_Priority_Shadow; /* Read/Write */ + char Pad2[0x34]; + /* + * Interprocessor Interrupt Command Ports + */ + OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */ + /* + * Current Task Priority Register + */ + OpenPIC_Reg _Current_Task_Priority; /* Read/Write */ + char Pad3[0x10]; + /* + * Interrupt Acknowledge Register + */ + OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */ + /* + * End of Interrupt (EOI) Register + */ + OpenPIC_Reg _EOI; /* Read/Write */ + char Pad5[0xf40]; +} OpenPIC_Processor; + + /* + * Timer Registers + */ + +typedef struct _OpenPIC_Timer { + OpenPIC_Reg _Current_Count; /* Read Only */ + OpenPIC_Reg _Base_Count; /* Read/Write */ + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Timer; + + /* + * Global Registers + */ + +typedef struct _OpenPIC_Global { + /* + * Feature Reporting Registers + */ + OpenPIC_Reg _Feature_Reporting0; /* Read Only */ + OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */ + /* + * Global Configuration Registers + */ + OpenPIC_Reg _Global_Configuration0; /* Read/Write */ + OpenPIC_Reg _Global_Configuration1; /* Future Expansion */ + /* + * Vendor Specific Registers + */ + OpenPIC_Reg _Vendor_Specific[4]; + /* + * Vendor Identification Register + */ + OpenPIC_Reg _Vendor_Identification; /* Read Only */ + /* + * Processor Initialization Register + */ + OpenPIC_Reg _Processor_Initialization; /* Read/Write */ + /* + * IPI Vector/Priority Registers + */ + OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */ + /* + * Spurious Vector Register + */ + OpenPIC_Reg _Spurious_Vector; /* Read/Write */ + /* + * Global Timer Registers + */ + OpenPIC_Reg _Timer_Frequency; /* Read/Write */ + OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; + char Pad1[0xee00]; +} OpenPIC_Global; + + /* + * Interrupt Source Registers + */ + +typedef struct _OpenPIC_Source { + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Source; + + /* + * OpenPIC Register Map + */ + +struct OpenPIC { + char Pad1[0x1000]; + /* + * Global Registers + */ + OpenPIC_Global Global; + /* + * Interrupt Source Configuration Registers + */ + OpenPIC_Source Source[OPENPIC_MAX_SOURCES]; + /* + * Per Processor Registers + */ + OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS]; +}; + +extern volatile struct OpenPIC *OpenPIC; + + /* + * Current Task Priority Register + */ + +#define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f + + /* + * Who Am I Register + */ + +#define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f + + /* + * Feature Reporting Register 0 + */ + +#define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000 +#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16 +#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00 +#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8 +#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff + + /* + * Global Configuration Register 0 + */ + +#define OPENPIC_CONFIG_RESET 0x80000000 +#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000 +#define OPENPIC_CONFIG_BASE_MASK 0x000fffff + + /* + * Vendor Identification Register + */ + +#define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000 +#define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16 +#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 +#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8 +#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff + + /* + * Vector/Priority Registers + */ + +#define OPENPIC_MASK 0x80000000 +#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ +#define OPENPIC_PRIORITY_MASK 0x000f0000 +#define OPENPIC_PRIORITY_SHIFT 16 +#define OPENPIC_VECTOR_MASK 0x000000ff + + /* + * Interrupt Source Registers + */ + +#define OPENPIC_SENSE_POLARITY 0x00800000 /* Undoc'd */ +#define OPENPIC_SENSE_LEVEL 0x00400000 + + /* + * Timer Registers + */ + +#define OPENPIC_COUNT_MASK 0x7fffffff +#define OPENPIC_TIMER_TOGGLE 0x80000000 +#define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000 + + /* + * Aliases to make life simpler + */ + +/* Per Processor Registers */ +#define IPI_Dispatch(i) _IPI_Dispatch[i].Reg +#define Current_Task_Priority _Current_Task_Priority.Reg +#define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg +#define EOI _EOI.Reg + +/* Global Registers */ +#define Feature_Reporting0 _Feature_Reporting0.Reg +#define Feature_Reporting1 _Feature_Reporting1.Reg +#define Global_Configuration0 _Global_Configuration0.Reg +#define Global_Configuration1 _Global_Configuration1.Reg +#define Vendor_Specific(i) _Vendor_Specific[i].Reg +#define Vendor_Identification _Vendor_Identification.Reg +#define Processor_Initialization _Processor_Initialization.Reg +#define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg +#define Spurious_Vector _Spurious_Vector.Reg +#define Timer_Frequency _Timer_Frequency.Reg + +/* Timer Registers */ +#define Current_Count _Current_Count.Reg +#define Base_Count _Base_Count.Reg +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + +/* Interrupt Source Registers */ +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + + /* + * Vendor and Device IDs + */ + +#define OPENPIC_VENDOR_ID_APPLE 0x14 +#define OPENPIC_DEVICE_ID_APPLE_HYDRA 0x46 + + /* + * OpenPIC Operations + */ + +/* + * Handle EPIC differences. Unfortunately, I don't know of an easy + * way to tell an EPIC from a normal PIC at run-time. Therefore, + * the BSP must enable a few quirks if it knows that an EPIC is being + * used: + * - If the BSP uses the serial interrupt mode / 'multiplexer' then + * EOI must be delayed by at least 16 SRAM_CLK cycles to avoid + * spurious interrupts. + * It is the BSP's responsibility to set up an appropriate delay + * (in timebase-clock cycles) at init time using + * 'openpic_set_eoi_delay()'. This is ONLY necessary when using + * an EPIC in serial mode. + * - The EPIC sources start at an offset of 16 in the register + * map, i.e., on an EPIC you'd say Sources[ x + 16 ] where + * on a PIC you would say Sources[ x ]. + * Again, the BSP can set an offset that is used by the + * calls dealing with 'Interrupt Sources' + * openpic_enable_irq() + * openpic_disable_irq() + * openpic_initirq() + * openpic_mapirq() + * openpic_set_sense() + * openpic_get_source_priority() + * openpic_set_source_priority() + * the desired source offset parameter is passed to openpic_init(). + * + * The routine 'openpic_set_eoi_delay()' returns the previous/old + * value of the delay parameter. + */ +extern unsigned openpic_set_eoi_delay(unsigned tb_cycles); + + +/* Global Operations */ + +/* num_sources: number of sources to use; if zero this value + * is read from the device, if nonzero the value read from + * the device is overridden. + * 'polarities' and 'senses' are arrays defining the desired + * polarities (active hi [nonzero]/lo [zero]) and + * senses (level [nonzero]/edge [zero]). + * Either of the two array pointers may be NULL resulting + * in the driver choosing default values of: 'active low' + * and 'level sensitive', respectively. + * NOTE: if you do pass arrays then their size must either + * match the number of sources read from the device or + * that value must be overridden by specifying + * a non-zero 'num_sources' parameter. + * + * Nonzero 'epic_freq' activates the EOI delay if the EPIC is + * configured in serial mode (driver assumes firmware performs initial + * EPIC setup). The BSP must pass the clock frequency of the EPIC + * serial interface here. + */ +extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq); + +extern void openpic_reset(void); +extern void openpic_enable_8259_pass_through(void); +extern void openpic_disable_8259_pass_through(void); +extern unsigned int openpic_irq(unsigned int cpu); +extern void openpic_eoi(unsigned int cpu); +extern unsigned int openpic_get_priority(unsigned int cpu); +extern void openpic_set_priority(unsigned int cpu, unsigned int pri); +extern unsigned int openpic_get_spurious(void); +extern void openpic_set_spurious(unsigned int vector); +extern void openpic_init_processor(unsigned int cpumask); + +/* Interprocessor Interrupts */ +extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector); +extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask); + +/* Timer Interrupts */ +extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector); +extern void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable); +extern unsigned int openpic_gettimer(unsigned int timer); +extern void openpic_maptimer(unsigned int timer, unsigned int cpumask); + +/* Interrupt Sources */ +extern void openpic_enable_irq(unsigned int irq); +extern int openpic_disable_irq(unsigned int irq); +extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity, + int is_level); +extern void openpic_mapirq(unsigned int irq, unsigned int cpumask); +extern void openpic_set_sense(unsigned int irq, int sense); +extern unsigned int openpic_get_source_priority(unsigned int irq); +extern void openpic_set_source_priority(unsigned int irq, unsigned int pri); + +#endif /* RTEMS_OPENPIC_H */ diff --git a/bsps/powerpc/include/bsp/pci.h b/bsps/powerpc/include/bsp/pci.h new file mode 100644 index 0000000000..42dc43875b --- /dev/null +++ b/bsps/powerpc/include/bsp/pci.h @@ -0,0 +1,84 @@ +/* + * PCI defines and function prototypes + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ + +/* + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> + */ + +#ifndef BSP_POWERPC_PCI_H +#define BSP_POWERPC_PCI_H + +#include <rtems/pci.h> +#include <stdio.h> + +struct _pin_routes +{ + int pin; + int int_name[4]; +}; +struct _int_map +{ + int bus; + int slot; + int opts; + struct _pin_routes pin_route[5]; +}; + +/* If there's a conflict between a name in the routing table and + * what's already set on the device, reprogram the device setting + * to reflect int_name[0] for the routing table entry + */ +#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) + +/* + * This is assumed to be provided by the BSP. + */ +void detect_host_bridge(void); + +void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); + +/* FIXME: This probably belongs into rtems/pci.h */ +extern unsigned char pci_bus_count(); + +/* FIXME: This also is generic and could go into rtems/pci.h */ + +/* Scan pci config space and run a user callback on each + * device present; the user callback may return 0 to + * continue the scan or a value > 0 to abort the scan. + * Return values < 0 are reserved and must not be used. + * + * RETURNS: a (opaque) handle pointing to the bus/slot/fn-triple + * just after where the scan was aborted by a callback + * returning 1 (see above) or NULL if all devices were + * scanned. + * The handle may be passed to this routine to resume the + * scan continuing with the device after the one causing the + * abort. + * Pass a NULL 'handle' argument to start scanning from + * the beginning (bus/slot/fn = 0/0/0). + */ +typedef void *BSP_PciScanHandle; +typedef int (*BSP_PciScannerCb)(int bus, int slot, int fun, void *uarg); + +BSP_PciScanHandle +BSP_pciScan(BSP_PciScanHandle handle, BSP_PciScannerCb cb, void *uarg); + +/* Dump basic config. space info to a file. The argument may + * be NULL in which case 'stdout' is used. + * NOTE: the C-library must be functional before you can use + * this routine. + */ +void +BSP_pciConfigDump(FILE *fp); + +#endif /* BSP_POWERPC_PCI_H */ diff --git a/bsps/powerpc/include/bsp/pnp.h b/bsps/powerpc/include/bsp/pnp.h new file mode 100644 index 0000000000..203a1a46d3 --- /dev/null +++ b/bsps/powerpc/include/bsp/pnp.h @@ -0,0 +1,644 @@ +/* 11/02/95 */ +/*----------------------------------------------------------------------------*/ +/* Plug and Play header definitions */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for PnP on PowerPC Reference Platform */ +/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ +/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ +/* This code has extensions to that specification, namely new short and */ +/* long tag types for platform dependent information */ + +/* Warning: LE notation used throughout this file */ + +/* For enum's: if given in hex then they are bit significant, i.e. */ +/* only one bit is on for each enum */ + + +#ifndef _PNP_ +#define _PNP_ + +#ifndef ASM +#define MAX_MEM_REGISTERS 9 +#define MAX_IO_PORTS 20 +#define MAX_IRQS 7 +/*#define MAX_DMA_CHANNELS 7*/ + +/* Interrupt controllers */ + +#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ +#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ +#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ +#define PNPinterrupt3 "PNP0003" /* APIC */ +#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ + +/* Timers */ + +#define PNPtimer0 "PNP0100" /* AT Timer */ +#define PNPtimer1 "PNP0101" /* EISA Timer */ +#define PNPtimer2 "PNP0102" /* MCA Timer */ + +/* DMA controllers */ + +#define PNPdma0 "PNP0200" /* AT DMA Controller */ +#define PNPdma1 "PNP0201" /* EISA DMA Controller */ +#define PNPdma2 "PNP0202" /* MCA DMA Controller */ + +/* start of August 15, 1994 additions */ +/* CMOS */ +#define PNPCMOS "IBM0009" /* CMOS */ + +/* L2 Cache */ +#define PNPL2 "IBM0007" /* L2 Cache */ + +/* NVRAM */ +#define PNPNVRAM "IBM0008" /* NVRAM */ + +/* Power Management */ +#define PNPPM "IBM0005" /* Power Management */ +/* end of August 15, 1994 additions */ + +/* Keyboards */ + +#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ +#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ +#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ +#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ +#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ +#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ +#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ +#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ + +/* Parallel port controllers */ + +#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ +#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ +#define PNPepp "IBM001C" /* EPP Parallel Port */ + +/* Serial port controllers */ + +#define PNPserial0 "PNP0500" /* Standard PC Serial port */ +#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ + +/* Disk controllers */ + +#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ +#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ +#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ + +/* Diskette controllers */ + +#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ + +/* Display controllers */ + +#define PNPdisplay0 "PNP0900" /* VGA Compatible */ +#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ +#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ +#define PNPdisplay3 "PNP0903" /* Trident VGA */ +#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ +#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ +#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ +#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ +#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ +#define PNPdisplay9 "PNP0909" /* S3 */ +#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ +#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ +#define PNPdisplayC "PNP090C" /* XGA Compatible */ +#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ +#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ +#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ + +/* Peripheral busses */ + +#define PNPbuses0 "PNP0A00" /* ISA Bus */ +#define PNPbuses1 "PNP0A01" /* EISA Bus */ +#define PNPbuses2 "PNP0A02" /* MCA Bus */ +#define PNPbuses3 "PNP0A03" /* PCI Bus */ +#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ + +/* RTC, BIOS, planar devices */ + +#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ +#define PNPrtc0 "PNP0B00" /* AT RTC */ +#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ +#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ +#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ +#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ + +/* PCMCIA controller */ + +#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ + +/* Mice */ + +#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ +#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ +#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ +#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ +#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ +#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ +#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ +#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ +#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ +#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ +#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ +#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ + +/* Modems */ + +#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ + +/* Network controllers */ + +#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ +#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ +#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ +#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ +#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ +#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ +#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ +#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ + +/* SCSI controllers */ + +#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ +#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ +#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ +#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ +#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ +#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ +#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ + +/* Sound/Video, Multimedia */ + +#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ +#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ +#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ +#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ +#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ +#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ +#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ +#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ + +/* Operator Panel */ +#define PNPopctl "IBM000B" /* Operator's panel */ + +/* Service Processor */ +#define PNPsp "IBM0011" /* IBM Service Processor */ +#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ +#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ + +/* Memory Controller */ +#define PNPmemctl "IBM000A" /* Memory controller */ + +/* Graphics Assist */ +#define PNPg_assist "IBM0014" /* Graphics Assist */ + +/* Miscellaneous Device Controllers */ +#define PNPtablet "IBM0019" /* IBM Tablet Controller */ + +/* PNP Packet Handles */ + +#define S1_Packet 0x0A /* Version resource */ +#define S2_Packet 0x15 /* Logical DEVID (without flags) */ +#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ +#define S3_Packet 0x1C /* Compatible device ID */ +#define S4_Packet 0x22 /* IRQ resource (without flags) */ +#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ +#define S5_Packet 0x2A /* DMA resource */ +#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ +#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ +#define S7_Packet 0x38 /* Depend funct end */ +#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ +#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ +#define S14_Packet 0x71 /* Vendor defined */ +#define S15_Packet 0x78 /* End of resource (w/o checksum) */ +#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ +#define L1_Packet 0x81 /* Memory range */ +#define L1_Shadow 0x20 /* Memory is shadowable */ +#define L1_32bit_mem 0x18 /* 32-bit memory only */ +#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ +#define L1_Decode_Hi 0x04 /* decode supports high address */ +#define L1_Cache 0x02 /* read cacheable, write-through */ +#define L1_Writeable 0x01 /* Memory is writeable */ +#define L2_Packet 0x82 /* ANSI ID string */ +#define L3_Packet 0x83 /* Unicode ID string */ +#define L4_Packet 0x84 /* Vendor defined */ +#define L5_Packet 0x85 /* Large I/O */ +#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ +#define END_TAG 0x78 /* End of resource */ +#define DF_START_TAG 0x30 /* Dependent function start */ +#define DF_START_TAG_priority 0x31 /* Dependent function start */ +#define DF_END_TAG 0x38 /* Dependent function end */ +#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ + +/* Device Base Type Codes */ + +typedef enum _PnP_BASE_TYPE { + Reserved = 0, + MassStorageDevice = 1, + NetworkInterfaceController = 2, + DisplayController = 3, + MultimediaController = 4, + MemoryController = 5, + BridgeController = 6, + CommunicationsDevice = 7, + SystemPeripheral = 8, + InputDevice = 9, + ServiceProcessor = 0x0A, /* 11/2/95 */ + } PnP_BASE_TYPE; + +/* Device Sub Type Codes */ + +typedef enum _PnP_SUB_TYPE { + SCSIController = 0, + IDEController = 1, + FloppyController = 2, + IPIController = 3, + OtherMassStorageController = 0x80, + + EthernetController = 0, + TokenRingController = 1, + FDDIController = 2, + OtherNetworkController = 0x80, + + VGAController= 0, + SVGAController= 1, + XGAController= 2, + OtherDisplayController = 0x80, + + VideoController = 0, + AudioController = 1, + OtherMultimediaController = 0x80, + + RAM = 0, + FLASH = 1, + OtherMemoryDevice = 0x80, + + HostProcessorBridge = 0, + ISABridge = 1, + EISABridge = 2, + MicroChannelBridge = 3, + PCIBridge = 4, + PCMCIABridge = 5, + VMEBridge = 6, + OtherBridgeDevice = 0x80, + + RS232Device = 0, + ATCompatibleParallelPort = 1, + OtherCommunicationsDevice = 0x80, + + ProgrammableInterruptController = 0, + DMAController = 1, + SystemTimer = 2, + RealTimeClock = 3, + L2Cache = 4, + NVRAM = 5, + PowerManagement = 6, + CMOS = 7, + OperatorPanel = 8, + ServiceProcessorClass1 = 9, + ServiceProcessorClass2 = 0xA, + ServiceProcessorClass3 = 0xB, + GraphicAssist = 0xC, + SystemPlanar = 0xF, /* 10/5/95 */ + OtherSystemPeripheral = 0x80, + + KeyboardController = 0, + Digitizer = 1, + MouseController = 2, + TabletController = 3, /* 10/27/95 */ + OtherInputController = 0x80, + + GeneralMemoryController = 0, + } PnP_SUB_TYPE; + +/* Device Interface Type Codes */ + +typedef enum _PnP_INTERFACE { + General = 0, + GeneralSCSI = 0, + GeneralIDE = 0, + ATACompatible = 1, + + GeneralFloppy = 0, + Compatible765 = 1, + NS398_Floppy = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26E_Floppy = 3, /* Ports 26E and 26F */ + NS15C_Floppy = 4, /* Ports 15C and 15D */ + NS2E_Floppy = 5, /* Ports 2E and 2F */ + CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ + + GeneralIPI = 0, + + GeneralEther = 0, + GeneralToken = 0, + GeneralFDDI = 0, + + GeneralVGA = 0, + GeneralSVGA = 0, + GeneralXGA = 0, + + GeneralVideo = 0, + GeneralAudio = 0, + CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ + + GeneralRAM = 0, + GeneralFLASH = 0, + PCIMemoryController = 0, /* PCI Config Method */ + RS6KMemoryController = 1, /* RS6K Config Method */ + + GeneralHostBridge = 0, + GeneralISABridge = 0, + GeneralEISABridge = 0, + GeneralMCABridge = 0, + GeneralPCIBridge = 0, + PCIBridgeDirect = 0, + PCIBridgeIndirect = 1, + PCIBridgeRS6K = 2, + GeneralPCMCIABridge = 0, + GeneralVMEBridge = 0, + + GeneralRS232 = 0, + COMx = 1, + Compatible16450 = 2, + Compatible16550 = 3, + NS398SerPort = 4, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26ESerPort = 5, /* Ports 26E and 26F */ + NS15CSerPort = 6, /* Ports 15C and 15D */ + NS2ESerPort = 7, /* Ports 2E and 2F */ + + GeneralParPort = 0, + LPTx = 1, + NS398ParPort = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26EParPort = 3, /* Ports 26E and 26F */ + NS15CParPort = 4, /* Ports 15C and 15D */ + NS2EParPort = 5, /* Ports 2E and 2F */ + + GeneralPIC = 0, + ISA_PIC = 1, + EISA_PIC = 2, + MPIC = 3, + RS6K_PIC = 4, + + GeneralDMA = 0, + ISA_DMA = 1, + EISA_DMA = 2, + + GeneralTimer = 0, + ISA_Timer = 1, + EISA_Timer = 2, + GeneralRTC = 0, + ISA_RTC = 1, + + StoreThruOnly = 1, + StoreInEnabled = 2, + RS6KL2Cache = 3, + + IndirectNVRAM = 0, /* Indirectly addressed */ + DirectNVRAM = 1, /* Memory Mapped */ + IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ + + GeneralPowerManagement = 0, + EPOWPowerManagement = 1, + PowerControl = 2, /* d1378 */ + + GeneralCMOS = 0, + + GeneralOPPanel = 0, + HarddiskLight = 1, + CDROMLight = 2, + PowerLight = 3, + KeyLock = 4, + ANDisplay = 5, /* AlphaNumeric Display */ + SystemStatusLED = 6, /* 3 digit 7 segment LED */ + CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ + + GeneralServiceProcessor = 0, + + TransferData = 1, + IGMC32 = 2, + IGMC64 = 3, + + GeneralSystemPlanar = 0, /* 10/5/95 */ + + } PnP_INTERFACE; + +/* PnP resources */ + +/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ + +typedef struct _SERIAL_ID { + unsigned char VendorID0; /* Bit(7)=0 */ + /* Bits(6:2)=1st character in */ + /* compressed ASCII */ + /* Bits(1:0)=2nd character in */ + /* compressed ASCII bits(4:3) */ + unsigned char VendorID1; /* Bits(7:5)=2nd character in */ + /* compressed ASCII bits(2:0) */ + /* Bits(4:0)=3rd character in */ + /* compressed ASCII */ + unsigned char VendorID2; /* Product number - vendor assigned */ + unsigned char VendorID3; /* Product number - vendor assigned */ + +/* Serial number is to provide uniqueness if more than one board of same */ +/* type is in system. Must be "FFFFFFFF" if feature not supported. */ + + unsigned char Serial0; /* Unique serial number bits (7:0) */ + unsigned char Serial1; /* Unique serial number bits (15:8) */ + unsigned char Serial2; /* Unique serial number bits (23:16) */ + unsigned char Serial3; /* Unique serial number bits (31:24) */ + unsigned char Checksum; + } SERIAL_ID; + +typedef enum _PnPItemName { + Unused = 0, + PnPVersion = 1, + LogicalDevice = 2, + CompatibleDevice = 3, + IRQFormat = 4, + DMAFormat = 5, + StartDepFunc = 6, + EndDepFunc = 7, + IOPort = 8, + FixedIOPort = 9, + Res1 = 10, + Res2 = 11, + Res3 = 12, + SmallVendorItem = 14, + EndTag = 15, + MemoryRange = 1, + ANSIIdentifier = 2, + UnicodeIdentifier = 3, + LargeVendorItem = 4, + MemoryRange32 = 5, + MemoryRangeFixed32 = 6, + } PnPItemName; + +/* Define a bunch of access functions for the bits in the tag field */ + +/* Tag type - 0 = small; 1 = large */ +#define tag_type(t) (((t) & 0x80)>>7) +#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) + +/* Small item name is 4 bits - one of PnPItemName enum above */ +#define tag_small_item_name(t) (((t) & 0x78)>>3) +#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) + +/* Small item count is 3 bits - count of further bytes in packet */ +#define tag_small_count(t) ((t) & 0x07) +#define set_tag_count(t,v) (t = (t & 0x78) | (v)) + +/* Large item name is 7 bits - one of PnPItemName enum above */ +#define tag_large_item_name(t) ((t) & 0x7f) +#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) + +/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ + +typedef union _PnP_TAG_PACKET { + struct _S1_Pack{ /* VERSION PACKET */ + unsigned char Tag; /* small tag = 0x0a */ + unsigned char Version[2]; /* PnP version, Vendor version */ + } S1_Pack; + + struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x15 or 0x16 */ + unsigned char DevId[4]; /* Logical device id */ + unsigned char Flags[2]; /* bit(0) boot device; */ + /* bit(7:1) cmd in range x31-x37 */ + /* bit(7:0) cmd in range x28-x3f (opt)*/ + } S2_Pack; + + struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x1c */ + unsigned char CompatId[4]; /* Compatible device id */ + } S3_Pack; + + struct _S4_Pack{ /* IRQ PACKET */ + unsigned char Tag; /* small tag = 0x22 or 0x23 */ + unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ + /* bit(0) is IRQ8 ... */ + unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ + /* bit(0) - high true edge sensitive */ + /* bit(1) - low true edge sensitive */ + /* bit(2) - high true level sensitive*/ + /* bit(3) - low true level sensitive */ + /* bit(7:4) - must be 0 */ + } S4_Pack; + + struct _S5_Pack{ /* DMA PACKET */ + unsigned char Tag; /* small tag = 0x2a */ + unsigned char DMAMask; /* bit(0) is channel 0 ... */ + unsigned char DMAInfo; + } S5_Pack; + + struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x30 or 0x31 */ + unsigned char Priority; /* Optional; if missing then x01; else*/ + /* x00 = best possible */ + /* x01 = acceptible */ + /* x02 = sub-optimal but functional */ + } S6_Pack; + + struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x38 */ + } S7_Pack; + + struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ + unsigned char Tag; /* small tag x47 */ + unsigned char IOInfo; /* x0 = decode only bits(9:0); */ +#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ + unsigned char RangeMin[2]; /* Min base address */ + unsigned char RangeMax[2]; /* Max base address */ + unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S8_Pack; + + struct _S9_Pack{ /* FIXED I/O PORT PACKET */ + unsigned char Tag; /* small tag = 0x4b */ + unsigned char Range[2]; /* base address 10 bits */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S9_Pack; + + struct _S14_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* small tag = 0x7m m = 1-7 */ + union _S14_Data{ + unsigned char Data[7]; /* Vendor defined */ + struct _S14_PPCPack{ /* Pr*p s14 pack */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[6]; /* Vendor defined */ + } S14_PPCPack; + } S14_Data; + } S14_Pack; + + struct _S15_Pack{ /* END PACKET */ + unsigned char Tag; /* small tag = 0x78 or 0x79 */ + unsigned char Check; /* optional - checksum */ + } S15_Pack; + + struct _L1_Pack{ /* MEMORY RANGE PACKET */ + unsigned char Tag; /* large tag = 0x81 */ + unsigned char Count0; /* x09 */ + unsigned char Count1; /* x00 */ + unsigned char Data[9]; /* a variable array of bytes, */ + /* count in tag */ + } L1_Pack; + + struct _L2_Pack{ /* ANSI ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x82 */ + unsigned char Count0; /* Length of string */ + unsigned char Count1; + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L2_Pack; + + struct _L3_Pack{ /* UNICODE ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x83 */ + unsigned char Count0; /* Length + 2 of string */ + unsigned char Count1; + unsigned char Country0; /* TBD */ + unsigned char Country1; /* TBD */ + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L3_Pack; + + struct _L4_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* large tag = 0x84 */ + unsigned char Count0; + unsigned char Count1; + union _L4_Data{ + unsigned char Data[1]; /* a variable array of bytes, */ + /* count in tag */ + struct _L4_PPCPack{ /* Pr*p L4 packet */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[1]; /* a variable array of bytes, */ + /* count in tag */ + } L4_PPCPack; + } L4_Data; + } L4_Pack; + + struct _L5_Pack{ + unsigned char Tag; /* large tag = 0x85 */ + unsigned char Count0; /* Count = 17 */ + unsigned char Count1; + unsigned char Data[17]; + } L5_Pack; + + struct _L6_Pack{ + unsigned char Tag; /* large tag = 0x86 */ + unsigned char Count0; /* Count = 9 */ + unsigned char Count1; + unsigned char Data[9]; + } L6_Pack; + + } PnP_TAG_PACKET; + +#endif /* ASM */ +#endif /* ndef _PNP_ */ diff --git a/bsps/powerpc/include/bsp/residual.h b/bsps/powerpc/include/bsp/residual.h new file mode 100644 index 0000000000..1bf1a34e20 --- /dev/null +++ b/bsps/powerpc/include/bsp/residual.h @@ -0,0 +1,356 @@ +/* 7/18/95 */ +/*----------------------------------------------------------------------------*/ +/* Residual Data header definitions and prototypes */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for RESIDUAL on PowerPC Reference Platform */ +/* residual.h - Residual data structure passed in r3. */ +/* Load point passed in r4 to boot image. */ +/* For enum's: if given in hex then they are bit significant, */ +/* i.e. only one bit is on for each enum */ +/* Reserved fields must be filled with zeros. */ + + +#ifndef _RESIDUAL_ +#define _RESIDUAL_ + +#ifndef ASM + +#include <stdint.h> + +#define MAX_CPUS 32 /* These should be set to the maximum */ +#define MAX_MEMS 64 /* number possible for this system. */ +#define MAX_DEVICES 256 /* Changing these will change the */ +#define AVE_PNP_SIZE 32 /* structure, hence the version of */ +#define MAX_MEM_SEGS 64 /* this header file. */ + +/*----------------------------------------------------------------------------*/ +/* Public structures... */ +/*----------------------------------------------------------------------------*/ + +#include <bsp/pnp.h> + +typedef enum _L1CACHE_TYPE { + NoneCAC = 0, + SplitCAC = 1, + CombinedCAC = 2 + } L1CACHE_TYPE; + +typedef enum _TLB_TYPE { + NoneTLB = 0, + SplitTLB = 1, + CombinedTLB = 2 + } TLB_TYPE; + +typedef enum _FIRMWARE_SUPPORT { + Conventional = 0x01, + OpenFirmware = 0x02, + Diagnostics = 0x04, + LowDebug = 0x08, + Multiboot = 0x10, + LowClient = 0x20, + Hex41 = 0x40, + FAT = 0x80, + ISO9660 = 0x0100, + SCSI_InitiatorID_Override = 0x0200, + Tape_Boot = 0x0400, + FW_Boot_Path = 0x0800 + } FIRMWARE_SUPPORT; + +typedef enum _FIRMWARE_SUPPLIERS { + IBMFirmware = 0x00, + MotoFirmware = 0x01, /* 7/18/95 */ + FirmWorks = 0x02, /* 10/5/95 */ + Bull = 0x03, /* 04/03/96 */ + QEMU = ('q'<<24) | ('e'<<16) | ('m'<<8) | ('u'<<0), + } FIRMWARE_SUPPLIERS; + +typedef enum _ENDIAN_SWITCH_METHODS { + UsePort92 = 0x01, + UsePCIConfigA8 = 0x02, + UseFF001030 = 0x03, + } ENDIAN_SWITCH_METHODS; + +typedef enum _SPREAD_IO_METHODS { + UsePort850 = 0x00, +/*UsePCIConfigA8 = 0x02,*/ + } SPREAD_IO_METHODS; + +typedef struct _VPD { + + /* Box dependent stuff */ + unsigned char PrintableModel[32]; /* Null terminated string. + Must be of the form: + vvv,<20h>,<model designation>,<0x0> + where vvv is the vendor ID + e.g. IBM PPS MODEL 6015<0x0> */ + unsigned char Serial[16]; /* 12/94: + Serial Number; must be of the form: + vvv<serial number> where vvv is the + vendor ID. + e.g. IBM60151234567<20h><20h> */ + unsigned char Reserved[48]; + unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ + unsigned long FirmwareSupports; /* See FirmwareSupport enum */ + unsigned long NvramSize; /* Size of nvram in bytes */ + unsigned long NumSIMMSlots; + unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ + unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ + unsigned long SmpIar; + unsigned long RAMErrLogOffset; /* Heap offset to error log */ + unsigned long Reserved5; + unsigned long Reserved6; + unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ + unsigned long ProcessorBusHz; /* Processor bus clock frequency */ + unsigned long Reserved7; + unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ + unsigned long WordWidth; /* Word width in bits */ + unsigned long PageSize; /* Page size in bytes */ + unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache + for which coherency is maintained; + normally <= CacheLineSize. */ + unsigned long GranuleSize; /* Unit of lock allocation to avoid */ + /* false sharing of locks. */ + + /* L1 Cache variables */ + unsigned long CacheSize; /* L1 Cache size in KB. This is the */ + /* total size of the L1, whether */ + /* combined or split */ + unsigned long CacheAttrib; /* L1CACHE_TYPE */ + unsigned long CacheAssoc; /* L1 Cache associativity. Use this + for combined cache. If split, put + zeros here. */ + unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use + for combined cache. If split, put + zeros here. */ + /* For split L1 Cache: (= combined if combined cache) */ + unsigned long I_CacheSize; + unsigned long I_CacheAssoc; + unsigned long I_CacheLineSize; + unsigned long D_CacheSize; + unsigned long D_CacheAssoc; + unsigned long D_CacheLineSize; + + /* Translation Lookaside Buffer variables */ + unsigned long TLBSize; /* Total number of TLBs on the system */ + unsigned long TLBAttrib; /* Combined I+D or split TLB */ + unsigned long TLBAssoc; /* TLB Associativity. Use this for + combined TLB. If split, put zeros + here. */ + /* For split TLB: (= combined if combined TLB) */ + unsigned long I_TLBSize; + unsigned long I_TLBAssoc; + unsigned long D_TLBSize; + unsigned long D_TLBAssoc; + + unsigned long ExtendedVPD; /* Offset to extended VPD area; + null if unused */ + } VPD; + +typedef enum _DEVICE_FLAGS { + Enabled = 0x4000, /* 1 - PCI device is enabled */ + Integrated = 0x2000, + Failed = 0x1000, /* 1 - device failed POST code tests */ + Static = 0x0800, /* 0 - dynamically configurable + 1 - static */ + Dock = 0x0400, /* 0 - not a docking station device + 1 - is a docking station device */ + Boot = 0x0200, /* 0 - device cannot be used for BOOT + 1 - can be a BOOT device */ + Configurable = 0x0100, /* 1 - device is configurable */ + Disableable = 0x80, /* 1 - device can be disabled */ + PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ + ReadOnly = 0x20, /* 1 - device is read only */ + Removable = 0x10, /* 1 - device is removable */ + ConsoleIn = 0x08, + ConsoleOut = 0x04, + Input = 0x02, + Output = 0x01 + } DEVICE_FLAGS; + +typedef enum _BUS_ID { + ISADEVICE = 0x01, + EISADEVICE = 0x02, + PCIDEVICE = 0x04, + PCMCIADEVICE = 0x08, + PNPISADEVICE = 0x10, + MCADEVICE = 0x20, + MXDEVICE = 0x40, /* Devices on mezzanine bus */ + PROCESSORDEVICE = 0x80, /* Devices on processor bus */ + VMEDEVICE = 0x100, + } BUS_ID; + +typedef struct _DEVICE_ID { + unsigned long BusId; /* See BUS_ID enum above */ + unsigned long DevId; /* Big Endian format */ + unsigned long SerialNum; /* For multiple usage of a single + DevId */ + unsigned long Flags; /* See DEVICE_FLAGS enum above */ + unsigned char BaseType; /* See pnp.h for bit definitions */ + unsigned char SubType; /* See pnp.h for bit definitions */ + unsigned char Interface; /* See pnp.h for bit definitions */ + unsigned char Spare; + } DEVICE_ID; + +typedef union _BUS_ACCESS { + struct _PnPAccess{ + unsigned char CSN; + unsigned char LogicalDevNumber; + unsigned short ReadDataPort; + } PnPAccess; + struct _ISAAccess{ + unsigned char SlotNumber; /* ISA Slot Number generally not + available; 0 if unknown */ + unsigned char LogicalDevNumber; + unsigned short ISAReserved; + } ISAAccess; + struct _MCAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short MCAReserved; + } MCAAccess; + struct _PCMCIAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short PCMCIAReserved; + } PCMCIAAccess; + struct _EISAAccess{ + unsigned char SlotNumber; + unsigned char FunctionNumber; + unsigned short EISAReserved; + } EISAAccess; + struct _PCIAccess{ + unsigned char BusNumber; + unsigned char DevFuncNumber; + unsigned short PCIReserved; + } PCIAccess; + struct _ProcBusAccess{ + unsigned char BusNumber; + unsigned char BUID; + unsigned short ProcBusReserved; + } ProcBusAccess; + } BUS_ACCESS; + +/* Per logical device information */ +typedef struct _PPC_DEVICE { + DEVICE_ID DeviceId; + BUS_ACCESS BusAccess; + + /* The following three are offsets into the DevicePnPHeap */ + /* All are in PnP compressed format */ + unsigned long AllocatedOffset; /* Allocated resource description */ + unsigned long PossibleOffset; /* Possible resource description */ + unsigned long CompatibleOffset; /* Compatible device identifiers */ + } PPC_DEVICE; + +typedef enum _CPU_STATE { + CPU_GOOD = 0, /* CPU is present, and active */ + CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ + CPU_OFF = 2, /* CPU is present, but inactive */ + CPU_FAILED = 3, /* CPU is present, but failed POST */ + CPU_NOT_PRESENT = 255 /* CPU not present */ + } CPU_STATE; + +typedef struct _PPC_CPU { + unsigned long CpuType; /* Result of mfspr from Processor + Version Register (PVR). + PVR(0-15) = Version (e.g. 601) + PVR(16-31 = EC Level */ + unsigned char CpuNumber; /* CPU Number for this processor */ + unsigned char CpuState; /* CPU State, see CPU_STATE enum */ + unsigned short Reserved; + } PPC_CPU; + +typedef struct _PPC_MEM { + unsigned long SIMMSize; /* 0 - absent or bad + 8M, 32M (in MB) */ + } PPC_MEM; + +typedef enum _MEM_USAGE { + Other = 0x8000, + ResumeBlock = 0x4000, /* for use by power management */ + SystemROM = 0x2000, /* Flash memory (populated) */ + UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ + IOMemory = 0x0800, + SystemIO = 0x0400, + SystemRegs = 0x0200, + PCIAddr = 0x0100, + PCIConfig = 0x80, + ISAAddr = 0x40, + Unpopulated = 0x20, /* Unpopulated part of System Memory */ + Free = 0x10, /* Free part of System Memory */ + BootImage = 0x08, /* BootImage part of System Memory */ + FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ + FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ + FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ + } MEM_USAGE; + +typedef struct _MEM_MAP { + unsigned long Usage; /* See MEM_USAGE above */ + unsigned long BasePage; /* Page number measured in 4KB pages */ + unsigned long PageCount; /* Page count measured in 4KB pages */ + } MEM_MAP; + +typedef struct _RESIDUAL { + unsigned long ResidualLength; /* Length of Residual */ + unsigned char Version; /* of this data structure */ + unsigned char Revision; /* of this data structure */ + unsigned short EC; /* of this data structure */ + /* VPD */ + VPD VitalProductData; + /* CPU */ + unsigned short MaxNumCpus; /* Max CPUs in this system */ + unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ + /* that there are unpopulated or */ + /* otherwise unusable cpu locations */ + PPC_CPU Cpus[MAX_CPUS]; + /* Memory */ + unsigned long TotalMemory; /* Total amount of memory installed */ + unsigned long GoodMemory; /* Total amount of good memory */ + unsigned long ActualNumMemSegs; + MEM_MAP Segs[MAX_MEM_SEGS]; + unsigned long ActualNumMemories; + PPC_MEM Memories[MAX_MEMS]; + /* Devices */ + unsigned long ActualNumDevices; + PPC_DEVICE Devices[MAX_DEVICES]; + unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; + } RESIDUAL; + +#ifndef NULL +#define NULL 0 +#endif + +static inline int +residual_fw_is_qemu(RESIDUAL *r) +{ + return QEMU == r->VitalProductData.FirmwareSupplier; +} + +extern RESIDUAL residualCopy; + +extern void print_residual_device_info(void); +#ifndef __BOOT__ +extern PPC_DEVICE *residual_find_device(RESIDUAL *res, unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#else +extern PPC_DEVICE *residual_find_device(unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#endif +extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, + int n); +extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +/* + * Prototypes for methods called only from .S for dependency tracking + */ +uint32_t res_copy(void); + +#endif /* ASM */ +#endif /* ndef _RESIDUAL_ */ diff --git a/bsps/powerpc/include/bsp/start.h b/bsps/powerpc/include/bsp/start.h new file mode 100644 index 0000000000..ab718a87ee --- /dev/null +++ b/bsps/powerpc/include/bsp/start.h @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup powerpc_start + * + * @brief System low level start. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_START_H +#define LIBBSP_POWERPC_SHARED_START_H + +#include <stddef.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_start PowerPC System Start + * + * @ingroup powerpc_shared + * + * @brief PowerPC low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/** +* @brief System start entry. +*/ +void _start(void); + +/** + * Zeros @a byte_count bytes starting at @a begin. + * + * It wraps around in case of an address overflow. The stack will not be used. + * The code is position independent. It uses the data cache block zero + * instruction in case the data cache is enabled. There are no alignment + * constains for @a begin and @a byte_count. + * + * @see bsp_start_zero_begin, bsp_start_zero_end, and bsp_start_zero_size. + */ +void BSP_START_TEXT_SECTION bsp_start_zero(void *begin, size_t byte_count); + +/** + * @brief Symbol which equals the bsp_start_zero() code begin. + */ +extern char bsp_start_zero_begin []; + +/** + * @brief Symbol which equals the bsp_start_zero() code end. + */ +extern char bsp_start_zero_end []; + +/** + * @brief Symbol which equals the bsp_start_zero() code size. + */ +extern char bsp_start_zero_size []; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_START_H */ diff --git a/bsps/powerpc/include/bsp/tictac.h b/bsps/powerpc/include/bsp/tictac.h new file mode 100644 index 0000000000..31c7386943 --- /dev/null +++ b/bsps/powerpc/include/bsp/tictac.h @@ -0,0 +1,78 @@ +/** + * @file + * + * @ingroup powerpc_shared + * + * @brief Header file for tic-tac code. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @brief Reset reference ticks for tac(). + */ +static inline void tic() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_tic_tac@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last tic(). + */ +static inline uint32_t tac() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_tic_tac@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} + +/** + * @brief Reset reference ticks for bam(). + */ +static inline void boom() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_boom_bam@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last boom(). + */ +static inline uint32_t bam() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_boom_bam@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} diff --git a/bsps/powerpc/include/bsp/tsec.h b/bsps/powerpc/include/bsp/tsec.h new file mode 100644 index 0000000000..4efbfa2ab0 --- /dev/null +++ b/bsps/powerpc/include/bsp/tsec.h @@ -0,0 +1,380 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares the MPC83xx TSEC networking driver | +\*===============================================================*/ + +#ifndef LIBCPU_POWERPC_TSEC_H +#define LIBCPU_POWERPC_TSEC_H + +#include <stdint.h> + +#include <bsp/irq.h> +#include <bsp/tsec-config.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + /* + * this enumeration defines the index + * of a given rmon mib counter + * in the tsec_rmon_mib array + */ +typedef enum { + /* TSEC1 Transmit and Receive Counters */ + TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ + TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ + TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ + TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ + TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ + TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ + TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ + /* TSEC1 Receive Counters */ + TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ + TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ + TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ + TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ + TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ + TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ + TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ + TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ + TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ + TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ + TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ + TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ + TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ + TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ + TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ + TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ + TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ + /* TSEC1 Transmit Counters */ + TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ + TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ + TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ + TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ + TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ + TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ + TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ + TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ + TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ + TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ + TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ + TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ + TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ + TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ + TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ + TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ + TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ + TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ + TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ + TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ + TSEC_RMON_CNT +} tsec_rmon_idx; + + /* TSEC1/2 General Control and Status Registers */ +typedef struct { + uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ + uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ + uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ + uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ + uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ + uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ + uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ + uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ + uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ + uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ + uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ + /* TSEC1 FIFO Control and Status Registers */ + uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ + uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ + uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ + uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ + uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ + uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ + /* TSEC1 Transmit Control and Status Registers */ + uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ + uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ + uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ + uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ + uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ + uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ + uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ + uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ + uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ + uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ + uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ + uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ + uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ + uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ + /* TSEC1 Receive Control and Status Registers */ + uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ + uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ + uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ + uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ + uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ + uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ + uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ + uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ + uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ + uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ + uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ + uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ + uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ + uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ + /* TSEC1 MAC Registers */ + uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ + uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ + uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ + uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ + uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ + uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ + uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ + uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ + uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ + uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ + uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ + uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ + uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ + uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ + uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ + uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ + + /* TSEC1 RMON MIB Registers */ + uint32_t rmon_mib[TSEC_RMON_CNT]; + + /* TSEC1 General Registers */ + uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ + uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ + uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ + + /* TSEC1 Hash Function Registers */ + uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ + uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ + uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ + uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ + + /* TSEC1 Attribute Registers */ + uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ + uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ + uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ + uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ +} tsec_registers; + +/* + * TSEC IEVENT/IMASK bit definitions + */ +#define TSEC_IEVENT_BABR (1<<(31- 0)) +#define TSEC_IEVENT_RXC (1<<(31- 1)) +#define TSEC_IEVENT_BSY (1<<(31- 2)) +#define TSEC_IEVENT_EBERR (1<<(31- 3)) +#define TSEC_IEVENT_MSRO (1<<(31- 5)) +#define TSEC_IEVENT_GTSC (1<<(31- 6)) +#define TSEC_IEVENT_BABT (1<<(31- 7)) +#define TSEC_IEVENT_TXC (1<<(31- 8)) +#define TSEC_IEVENT_TXE (1<<(31- 9)) +#define TSEC_IEVENT_TXB (1<<(31-10)) +#define TSEC_IEVENT_TXF (1<<(31-11)) +#define TSEC_IEVENT_LC (1<<(31-13)) +#define TSEC_IEVENT_CRL_XDA (1<<(31-14)) +#define TSEC_IEVENT_XFUN (1<<(31-15)) +#define TSEC_IEVENT_RXB (1<<(31-16)) +#define TSEC_IEVENT_MMRD (1<<(31-21)) +#define TSEC_IEVENT_MMWR (1<<(31-22)) +#define TSEC_IEVENT_GRSC (1<<(31-23)) +#define TSEC_IEVENT_RXF (1<<(31-24)) + +/* + * TSEC DMACTRL bit definitions + */ +#define TSEC_DMACTL_TDSEN (1<<(31-24)) +#define TSEC_DMACTL_TBDSEN (1<<(31-25)) +#define TSEC_DMACTL_GRS (1<<(31-27)) +#define TSEC_DMACTL_GTS (1<<(31-28)) +#define TSEC_DMACTL_WWR (1<<(31-30)) +#define TSEC_DMACTL_WOP (1<<(31-31)) + +/* + * TSEC TSTAT bit definitions + */ +#define TSEC_TSTAT_THLT (1<<(31-0)) + +/* + * TSEC RSTAT bit definitions + */ +#define TSEC_RSTAT_QHLT (1<<(31-8)) + /* + * TSEC ECNTRL bit positions + */ +#define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ +#define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ +#define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ +#define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ +#define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ +#define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ + /* + * TSEC EDIS bit positions + */ +#define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ +#define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ +#define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ +#define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ +#define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ +#define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ + + /* + * TSEC RCTRL bit positions + */ +#define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ +#define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ +#define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ + + /* + * TSEC TXIC bit positions + */ +#define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC RXIC bit positions + */ +#define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC MACCFG1 bit positions + */ +#define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ +#define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ +#define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ +#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ +#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ +#define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ +#define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ +#define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ +#define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ +#define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ +#define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ +#define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ + + /* + * TSEC MACCFG2 bit positions + */ +#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ + +#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ +#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ +#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ + +#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ +#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ +#define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ +#define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ +#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ + + /* + * TSEC MIIMADD bit positions + */ +#define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ +#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ + + /* + * TSEC MIIMCOM bit positions + */ +#define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ +#define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ + + /* + * TSEC MIIMIND bit positions + */ +#define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ +#define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ +#define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ + + /* + * TSEC ATTR bit positions + */ +#define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ +#define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ + +typedef struct { + volatile uint16_t status; + volatile uint16_t length; + volatile void *buffer; +} PQBufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define BD_EMPTY (1<<15) +#define BD_RO1 (1<<14) +#define BD_WRAP (1<<13) +#define BD_INTERRUPT (1<<12) +#define BD_LAST (1<<11) +#define BD_CONTROL_CHAR (1<<11) +#define BD_FIRST_IN_FRAME (1<<10) +#define BD_MISS (1<<8) +#define BD_BROADCAST (1<<7) +#define BD_MULTICAST (1<<6) +#define BD_LONG (1<<5) +#define BD_NONALIGNED (1<<4) +#define BD_SHORT (1<<3) +#define BD_CRC_ERROR (1<<2) +#define BD_OVERRUN (1<<1) +#define BD_COLLISION (1<<0) + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define BD_READY (1<<15) +#define BD_PAD_CRC (1<<14) +/* WRAP/Interrupt as in Rx BDs */ +#define BD_TX_CRC (1<<10) +#define BD_DEFER (1<<9) +#define BD_TO1 (1<<8) +#define BD_HFE_ (1<<7) +#define BD_LATE_COLLISION (1<<7) +#define BD_RETRY_LIMIT (1<<6) +#define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) +#define BD_UNDERRUN (1<<1) +#define BD_TXTRUNC (1<<0) + +struct rtems_bsdnet_ifconfig; + +typedef struct { + int unit_number; + char *unit_name; + volatile tsec_registers *reg_ptr; + volatile tsec_registers *mdio_ptr; + rtems_irq_number irq_num_tx; + rtems_irq_number irq_num_rx; + rtems_irq_number irq_num_err; + int phy_default; +} tsec_config; + +int tsec_driver_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_TSEC_H */ diff --git a/bsps/powerpc/include/bsp/u-boot-board-info.h b/bsps/powerpc/include/bsp/u-boot-board-info.h new file mode 100644 index 0000000000..b377705687 --- /dev/null +++ b/bsps/powerpc/include/bsp/u-boot-board-info.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __U_BOOT_H__ +#define __U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + unsigned long bi_immrbar; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_inpfreq; /* Input Freq, In MHz */ + unsigned long bi_pcifreq; /* PCI Freq, in MHz */ + unsigned long bi_pevfreq; /* PEV Freq, in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ + unsigned long bi_vcofreq; /* VCO Freq, in MHz */ +#endif + unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_MPC512X) + unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ +#endif /* CONFIG_MPC512X */ +#if defined(CONFIG_MPC5xxx) + unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif + unsigned long bi_baudrate; /* Console Baudrate */ +#if defined(CONFIG_405) || \ + defined(CONFIG_405GP) || \ + defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ + defined(CONFIG_440) + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ + unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ + unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ +#endif +#if defined(CONFIG_HYMOD) + hymod_conf_t bi_hymod_conf; /* hymod configuration information */ +#endif + +#ifdef CONFIG_HAS_ETH1 + unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH2 + unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + unsigned int bi_opbfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +#endif +#if defined(CONFIG_NX823) + unsigned char bi_sernum[8]; +#endif +#if defined(CONFIG_4xx) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#elif defined(CONFIG_405EP) || defined(CONFIG_440) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#else + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ +#endif +#endif /* defined(CONFIG_4xx) */ +} bd_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __U_BOOT_H__ */ diff --git a/bsps/powerpc/include/bsp/uart.h b/bsps/powerpc/include/bsp/uart.h new file mode 100644 index 0000000000..b7539b5b7b --- /dev/null +++ b/bsps/powerpc/include/bsp/uart.h @@ -0,0 +1,190 @@ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#include <bsp/irq.h> + +#include <sys/ioctl.h> +#include <rtems/libio.h> + +void BSP_uart_init(int uart, int baud, int hwFlow); +void BSP_uart_set_baud(int uart, int baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +ssize_t BSP_uart_termios_write_com(int minor, const char *buf, size_t len); +int BSP_uart_termios_read_com (int minor); +void BSP_uart_termios_isr_com1(void *unused); +void BSP_uart_termios_isr_com2(void *unused); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); +int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); +ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len); +int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); +int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); + +extern unsigned BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(const char val); +extern int BSPConsolePort; +extern int BSPBaseBaud; + +/* Special IOCTLS to install a lowlevel 'BREAK' handler */ + +/* pass a BSP_UartBreakCb pointer to ioctl when retrieving + * or installing break callback + */ +typedef void (*BSP_UartBreakCbProc)( + int uartMinor, + unsigned uartRBRLSRStatus, + void *termiosPrivatePtr, + void *private +); + +typedef struct BSP_UartBreakCbRec_ { + BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */ + void *private; /* closure pointer which is passed to the callback */ +} BSP_UartBreakCbRec, *BSP_UartBreakCb; + +#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec)) +#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec)) + +/* + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ + +/* Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) /* No character */ +#define BSP_UART_STATUS_NOCHAR (0) /* No character */ +#define BSP_UART_STATUS_CHAR (1) /* Character present */ +#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ + +/* PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/* + * Offsets from base + */ + +/* DLAB 0 */ +#define RBR (0) /* Rx Buffer Register (read) */ +#define THR (0) /* Tx Buffer Register (write) */ +#define IER (1) /* Interrupt Enable Register */ + +/* DLAB X */ +#define IIR (2) /* Interrupt Ident Register (read) */ +#define FCR (2) /* FIFO Control Register (write) */ +#define LCR (3) /* Line Control Register */ +#define MCR (4) /* Modem Control Register */ +#define LSR (5) /* Line Status Register */ +#define MSR (6) /* Modem Status Register */ +#define SCR (7) /* Scratch register */ + +/* DLAB 1 */ +#define DLL (0) /* Divisor Latch, LSB */ +#define DLM (1) /* Divisor Latch, MSB */ +#define AFR (2) /* Alternate Function register */ + +/* + * Interrupt source definition via IIR + */ +#define MODEM_STATUS 0 +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/* + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define MODEM_ENABLE 0x8 +#define INTERRUPT_DISABLE 0x0 + +/* + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ + +/* + * Bits definition of the MODEM Control Register (MCR) + */ +#define DTR 0x01 /* Data Terminal Ready */ +#define RTS 0x02 /* Request To Send */ +#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */ +#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */ +#define LB 0x10 /* Enable Internal Loop Back */ + +/* + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 /* Word length mask */ +#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ +#define PEN 0x08 /* Parity Enabled */ +#define EPS 0x10 /* Even Parity Select, otherwise Odd */ +#define SP 0x20 /* Stick Parity */ +#define BCB 0x40 /* Break Control Bit */ +#define DLAB 0x80 /* Enable Divisor Latch Access */ + +/* + * Bits definition of the MODEM Status Register (MSR) + */ +#define DCTS 0x01 /* Delta Clear To Send */ +#define DDSR 0x02 /* Delta Data Set Ready */ +#define TERI 0x04 /* Trailing Edge Ring Indicator */ +#define DDCD 0x08 /* Delta Carrier Detect Indicator */ +#define CTS 0x10 /* Clear To Send (when loop back is active) */ +#define DSR 0x20 /* Data Set Ready (when loop back is active) */ +#define RI 0x40 /* Ring Indicator (when loop back is active) */ +#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */ + +/* + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ +#define FIFO_EN 0x01 /* Enable the FIFO */ +#define XMIT_RESET 0x02 /* Transmit FIFO Reset */ +#define RCV_RESET 0x04 /* Receive FIFO Reset */ +#define FCR3 0x08 /* do not understand manual! */ + +#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */ +#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */ +#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */ +#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */ +#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ + +#endif /* _BSPUART_H */ diff --git a/bsps/powerpc/include/bsp/vectors.h b/bsps/powerpc/include/bsp/vectors.h new file mode 100644 index 0000000000..81526eb4b0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vectors.h @@ -0,0 +1,493 @@ +/** + * @file + * + * @ingroup ppc_exc + * @ingroup ppc_exc_frame + * + * @brief PowerPC Exceptions API. + */ + +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> + * + * Copyright (C) 2009 embedded brains GmbH. + * + * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> + * to support 603, 603e, 604, 604e exceptions + * + * Moved to "libcpu/powerpc/new-exceptions" and consolidated + * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + * to be common for all PPCs with new exceptions. + * + * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". + * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */ + +#ifndef LIBCPU_VECTORS_H +#define LIBCPU_VECTORS_H + +#include <bspopts.h> +#include <rtems/score/cpuimpl.h> +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup ppc_exc PowerPC Exceptions + * + * @brief XXX + * + * @{ + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 +#define ASM_PROT_VECTOR 0x03 +#define ASM_ISI_VECTOR 0x04 +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D + +#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR + +#define ASM_8XX_FLOATASSIST_VECTOR 0x0E +#define ASM_8XX_SOFTEMUL_VECTOR 0x10 +#define ASM_8XX_ITLBMISS_VECTOR 0x11 +#define ASM_8XX_DTLBMISS_VECTOR 0x12 +#define ASM_8XX_ITLBERROR_VECTOR 0x13 +#define ASM_8XX_DTLBERROR_VECTOR 0x14 +#define ASM_8XX_DBREAK_VECTOR 0x1C +#define ASM_8XX_IBREAK_VECTOR 0x1D +#define ASM_8XX_PERIFBREAK_VECTOR 0x1E +#define ASM_8XX_DEVPORT_VECTOR 0x1F + +#define ASM_5XX_FLOATASSIST_VECTOR 0x0E +#define ASM_5XX_SOFTEMUL_VECTOR 0x10 +#define ASM_5XX_IPROT_VECTOR 0x13 +#define ASM_5XX_DPROT_VECTOR 0x14 +#define ASM_5XX_DBREAK_VECTOR 0x1C +#define ASM_5XX_IBREAK_VECTOR 0x1D +#define ASM_5XX_MEBREAK_VECTOR 0x1E +#define ASM_5XX_NMEBREAK_VECTOR 0x1F + +#define ASM_60X_VEC_VECTOR 0x0A +#define ASM_60X_PERFMON_VECTOR 0x0F +#define ASM_60X_IMISS_VECTOR 0x10 +#define ASM_60X_DLMISS_VECTOR 0x11 +#define ASM_60X_DSMISS_VECTOR 0x12 +#define ASM_60X_ADDR_VECTOR 0x13 +#define ASM_60X_SYSMGMT_VECTOR 0x14 +#define ASM_60X_VEC_ASSIST_VECTOR 0x16 +#define ASM_60X_ITM_VECTOR 0x17 + +/* Book E */ +#define ASM_BOOKE_CRIT_VECTOR 0x01 +/* We could use the std. decrementer vector # on bookE, too, + * but the bookE decrementer has slightly different semantics + * so we use a different vector (which happens to be + * the PIT vector on the 405 which is like the booke decrementer) + */ +#define ASM_BOOKE_DEC_VECTOR 0x10 +#define ASM_BOOKE_ITLBMISS_VECTOR 0x11 +#define ASM_BOOKE_DTLBMISS_VECTOR 0x12 +#define ASM_BOOKE_FIT_VECTOR 0x13 +#define ASM_BOOKE_WDOG_VECTOR 0x14 +#define ASM_BOOKE_APU_VECTOR 0x18 +#define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR + +/* e200 and e500 */ +#define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR +#define ASM_E500_EMB_FP_DATA_VECTOR 0x19 +#define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A +#define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR + +/* e300 */ +#define ASM_E300_CRIT_VECTOR 0x0A +#define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR +#define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR +#define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR + +/* + * If you change that number make sure to adjust the wrapper code in ppc_exc.S + * and that ppc_exc_handler_table will be correctly initialized. + */ +#define LAST_VALID_EXC 0x1F + +/* DO NOT USE -- this symbol is DEPRECATED + * (only used by libbsp/shared/vectors/vectors.S + * which should not be used by new BSPs). + */ +#define ASM_60X_VEC_VECTOR_OFFSET 0xf20 + +#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010 +#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020 +#define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000 + +/** @} */ + +/** + * @defgroup ppc_exc_frame PowerPC Exception Frame + * + * @brief XXX + * + * @{ + */ + +/* + * The callee (high level exception code written in C) + * will store the Link Registers (return address) at entry r1 + 4 !!!. + * So let room for it!!!. + */ +#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 + +#define EXC_GENERIC_SIZE (PPC_EXC_FRAME_SIZE + PPC_STACK_RED_ZONE_SIZE) + +#define PPC_EXC_INTERRUPT_FRAME_SIZE CPU_INTERRUPT_FRAME_SIZE + +#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) +#define EXC_VEC_OFFSET EXC_GENERIC_SIZE +#ifndef PPC_CACHE_ALIGNMENT +#error "Missing include file!" +#endif +/* 20 volatile registers + * + cache-aligned area for vcsr, vrsave + * + area for alignment + */ +#define EXC_VEC_SIZE (16*20 + 2*PPC_CACHE_ALIGNMENT) +#else +#define EXC_VEC_SIZE (0) +#endif + +/* + * maintain the EABI requested 8 bytes aligment + * As SVR4 ABI requires 16, make it 16 (as some + * exception may need more registers to be processed...) + */ +#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE) + +/** @} */ + +#ifndef ASM + +/** + * @ingroup ppc_exc_frame + * + * @{ + */ + +typedef CPU_Exception_frame BSP_Exception_frame; + +/** @} */ + +/** + * @ingroup ppc_exc + * + * @{ + */ + +/** + * @brief Global exception handler type. + */ +typedef void (*exception_handler_t)(BSP_Exception_frame*); + +/** + * @brief Default global exception handler. + */ +void C_exception_handler(BSP_Exception_frame* excPtr); + +void BSP_printStackTrace(const BSP_Exception_frame *excPtr); + +/** + * @brief Exception categories. + * + * Exceptions of different categories use different SRR registers to save the + * machine state and do different things in the prologue and epilogue. + * + * For now, the CPU descriptions assume this fits into 8 bits. + */ +typedef enum { + PPC_EXC_INVALID = 0, + PPC_EXC_ASYNC = 1, + PPC_EXC_CLASSIC = 2, + PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, + PPC_EXC_405_CRITICAL = 4, + PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_BOOKE_CRITICAL = 6, + PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_E500_MACHCHK = 8, + PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC, + PPC_EXC_NAKED = 10 +} ppc_exc_category; + +/** + * @brief Categorie set type. + */ +typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1]; + +static inline bool ppc_exc_is_valid_category(ppc_exc_category category) +{ + return (unsigned) category <= (unsigned) PPC_EXC_NAKED; +} + +/** + * @brief Returns the entry address of the vector. + * + * @param[in] vector The vector number. + * @param[in] vector_base The vector table base address. + */ +void *ppc_exc_vector_address(unsigned vector, void *vector_base); + +/** + * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if + * there is no category set available for this CPU. + */ +const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu); + +/** + * @brief Returns the category set for the current CPU, or @c NULL if there is + * no category set available for this CPU. + */ +static inline const ppc_exc_categories *ppc_exc_current_categories(void) +{ + return ppc_exc_categories_for_cpu(ppc_cpu_current()); +} + +/** + * @brief Returns the category for the vector @a vector using the category set + * @a categories. + */ +ppc_exc_category ppc_exc_category_for_vector( + const ppc_exc_categories *categories, + unsigned vector +); + +/** + * @brief Makes a minimal prologue for the vector @a vector with the category + * @a category. + * + * The minimal prologue will be copied to @a prologue. Not more than + * @a prologue_size bytes will be copied. Returns the actual minimal prologue + * size in bytes in @a prologue_size. + * + * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_INVALID_NUMBER Invalid category. + * @retval RTEMS_INVALID_SIZE Prologue size to small. + */ +rtems_status_code ppc_exc_make_prologue( + unsigned vector, + void *vector_base, + ppc_exc_category category, + uint32_t *prologue, + size_t *prologue_size +); + +static inline void ppc_exc_initialize_interrupt_stack( + uintptr_t stack_begin, + uintptr_t stack_size +) +{ + uintptr_t stack_end = stack_begin + stack_size; + uintptr_t stack_pointer = stack_end - PPC_MINIMUM_STACK_FRAME_SIZE; + + /* Ensure proper interrupt stack alignment */ + stack_pointer &= ~((uintptr_t) CPU_STACK_ALIGNMENT - 1); + + /* Tag interrupt stack bottom */ + *(uint32_t *) stack_pointer = 0; + + /* Move interrupt stack values to special purpose registers */ + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, stack_pointer); + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, stack_begin); +} + +/** + * @brief Initializes the exception handling. + * + * @see ppc_exc_initialize(). + */ +void ppc_exc_initialize_with_vector_base( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size, + void *vector_base +); + +/** + * @brief Initializes the exception handling. + * + * If the initialization fails, then this is a fatal error. The fatal error + * source is RTEMS_FATAL_SOURCE_BSP and the fatal error code is + * PPC_FATAL_EXCEPTION_INITIALIZATION. + * + * Possible error reasons are + * - no category set available for the current CPU, + * - the register r13 does not point to the small data area anchor required by + * SVR4/EABI, or + * - the minimal prologue creation failed. + */ +static inline void ppc_exc_initialize( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size +) +{ + ppc_exc_initialize_with_vector_base( + interrupt_stack_begin, + interrupt_stack_size, + NULL + ); +} + +/** + * @brief High-level exception handler type. + * + * @retval 0 The exception was handled and normal execution may resume. + * @retval -1 Reject the exception resulting in a call of the global exception + * handler. + * @retval other Reserved, do not use. + */ +typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); + +/** + * @brief Default high-level exception handler. + * + * @retval -1 Always. + */ +int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector); + +#ifndef PPC_EXC_CONFIG_BOOKE_ONLY + +/** + * @brief Bits for MSR update. + * + * Bits in MSR that are enabled during execution of exception handlers / ISRs + * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should + * be set to 0 during initialization) + * + * By default, the setting of these bits that is in effect when exception + * handling is initialized is used. + */ +extern uint32_t ppc_exc_msr_bits; + +#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ + +/** + * @brief Cache write back check flag. + * + * (See README under CAVEATS). During initialization + * a check is performed to assert that write-back + * caching is enabled for memory accesses. If a BSP + * runs entirely without any caching then it should + * set this variable to zero prior to initializing + * exceptions in order to skip the test. + * NOTE: The code does NOT support mapping memory + * with cache-attributes other than write-back + * (unless the entire cache is physically disabled) + */ +extern uint32_t ppc_exc_cache_wb_check; + +#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER + /** + * @brief High-level exception handler table. + */ + extern ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Global exception handler. + */ + extern exception_handler_t globalExceptHdl; +#else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + /** + * @brief High-level exception handler table. + */ + extern const ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Interrupt dispatch routine provided by BSP. + */ + void bsp_interrupt_dispatch(uintptr_t exception_number); +#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + +/** + * @brief Set high-level exception handler. + * + * Hook C exception handlers. + * - handlers for asynchronous exceptions run on the ISR stack + * with thread-dispatching disabled. + * - handlers for synchronous exceptions run on the task stack + * with thread-dispatching enabled. + * + * If a particular slot is NULL then the traditional 'globalExcHdl' is used. + * + * ppc_exc_set_handler() registers a handler (returning 0 on success, + * -1 if the vector argument is too big). + * + * It is legal to set a NULL handler. This leads to the globalExcHdl + * being called if an exception for 'vector' occurs. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_RESOURCE_IN_USE Handler table is read-only and handler does + * not match. + */ +rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl); + +/** + * @brief Returns the currently active high-level exception handler. + */ +ppc_exc_handler_t ppc_exc_get_handler(unsigned vector); + +/** + * @brief Function for DAR access. + * + * CPU support may store the address of a function here + * that can be used by the default exception handler to + * obtain fault-address info which is helpful. Unfortunately, + * the SPR holding this information is not uniform + * across PPC families so we need assistance from + * CPU support + */ +extern uint32_t (*ppc_exc_get_DAR)(void); + +void +ppc_exc_wrapup(BSP_Exception_frame *f); + +/** + * @brief Standard aligment handler. + * + * @retval 0 Performed a dcbz instruction. + * @retval -1 Otherwise. + */ +int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum); + +/** @} */ + +/* + * Compatibility with pc386 + */ +typedef exception_handler_t cpuExcHandlerType; + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBCPU_VECTORS_H */ diff --git a/bsps/powerpc/include/bsp/vpd.h b/bsps/powerpc/include/bsp/vpd.h new file mode 100644 index 0000000000..23e49ac9f0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vpd.h @@ -0,0 +1,143 @@ +#ifndef PPC_MOTLOAD_VPD_H +#define PPC_MOTLOAD_VPD_H + +/* MotLoad VPD format */ + +/* Till Straumann, 2005; see copyright notice at the end of this file */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* +VPD = "MOTOROLA" , { field } + +field = type_byte, length_byte, { data } +*/ + +/* Known fields so far */ +typedef enum { + ProductIdent = 0x01, /* String */ + AssemblyNumber = 0x02, /* String */ + SerialNumber = 0x03, /* String */ + CpuClockHz = 0x05, /* binary (5bytes), 0x01 byte appended to unsigned int */ + BusClockHz = 0x06, /* binary (5bytes), 0x01 byte appended to unsigned int */ + EthernetAddr = 0x08, /* binary (7bytes), 0x00 byte appended, 2nd has 0x01 appended */ + CpuType = 0x09, /* String */ + EEpromCrc = 0x0a, /* binary (4bytes) */ + FlashConfig = 0x0b, /* binary */ + L2CacheConfig = 0x0e, /* binary */ + VPDRevision = 0x0f, /* binary (4bytes) */ + L3CacheConfig = 0x19, /* binary */ + End = 0xff +} VpdKey; + +typedef struct { + VpdKey key; /* key for the data item to be read into 'buf' */ + char instance; /* instance # (starting with 0) - some keys are present more than one time */ + void *buf; /* pointer to area where the data item is to be stored */ + int buflen; /* available space in the buffer */ + char found; /* set by BSP_vpdRetrieveFields() to the original length as found in the PROM */ +} VpdBufRec, *VpdBuf; + + +#define VPD_END { key:End, } + + +/* Scan the VPD EEPROM for a number of fields + * + * Pass an array of VpdBufRec items. The routine + * fills the 'buf'fers for all keys that are found + * and sets the 'found' field to the original length + * of the data (i.e., as found in the PROM) so that + * the routine could be called again with a larger + * buffer. + * + * NOTE: - the array must be terminated by a VPD_END record! + * - no CRC check is performed. + * - INTERRUPT MANAGEMENT MUST BE FUNCTIONAL + * + * RETURNS: 0 on success, -1 if any read errors were + * encountered or if the "MOTOROLA" header + * was not found. + */ +int +BSP_vpdRetrieveFields(VpdBuf data); + +/* Example: + * Read 2nd ethernet address: + * + * char enet_addr_2[6]; + * + * VpdBufRec enetVpd [] = { + * { key: EthernetAddr, instance: 1, buf: enet_addr_2, buflen: 2}, + * VPD_END + * }; + * + * if ( BSP_vpdRetrieveFields(enetVpd) ) { + * error("ethernet address couldn't be read\n"); + * } else if ( enetVpd[0].found < 6 ) { + * error("2nd ethernet address not found in VPD\n"); + * } else { + * use_it(enet_addr_2); + * } + */ + + +/* Simple wrapper if only one field is needed + * + * RETURNS: original length if key is found, -1 on error or if key is not found + */ +int +BSP_vpdRetrieveKey(VpdKey k, void *buf, int buflen, int instance); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif |