diff options
Diffstat (limited to 'bsps/powerpc/haleakala/include')
| -rw-r--r-- | bsps/powerpc/haleakala/include/bsp.h | 87 | ||||
| -rw-r--r-- | bsps/powerpc/haleakala/include/bsp/irq.h | 166 | ||||
| -rw-r--r-- | bsps/powerpc/haleakala/include/mmu_405.h | 77 | ||||
| -rw-r--r-- | bsps/powerpc/haleakala/include/tm27.h | 1 |
4 files changed, 331 insertions, 0 deletions
diff --git a/bsps/powerpc/haleakala/include/bsp.h b/bsps/powerpc/haleakala/include/bsp.h new file mode 100644 index 0000000000..b26e739e60 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp.h @@ -0,0 +1,87 @@ +/* bsp.h + * + * Generic 405EX bsp.h + * derived from virtex/include/bsp.h + * by Michael Hamel ADInstruments Ltd 2008 + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * + */ + +#ifndef LIBBSP_POWERPC_HALEAKALA_BSP_H +#define LIBBSP_POWERPC_HALEAKALA_BSP_H + +#include <bspopts.h> + +#ifdef ASM + + + /* Definition of where to store registers in alignment handler */ + #define ALIGN_REGS 0x0140 + +#else + + #include <rtems.h> + #include <libcpu/io.h> + #include <bsp/irq.h> + #include <bsp/vectors.h> + #include <bsp/default-initial-extension.h> + + #ifdef __cplusplus + extern "C" { + #endif + + /* Network Defines */ + #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + + struct rtems_bsdnet_ifconfig; + int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching); + #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach + + #define BSP_UART_IOBASE_COM1 0xEF600200 /* PPC405EX */ + #define BSP_UART_IOBASE_COM2 0xEF600300 + + #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ + + #define BSP_UART_BAUD_BASE (11059200 / 16) /* Kilauea ext clock, max speed */ + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* BSP_H */ diff --git a/bsps/powerpc/haleakala/include/bsp/irq.h b/bsps/powerpc/haleakala/include/bsp/irq.h new file mode 100644 index 0000000000..c413ec3172 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp/irq.h @@ -0,0 +1,166 @@ +/*===============================================================*\ +| Project: RTEMS Haleakala BSP | +| by Michael Hamel ADInstruments Ltd 2008 | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | +\*===============================================================*/ + + +#ifndef Haleakala_IRQ_IRQ_H +#define Haleakala_IRQ_IRQ_H + +/* Implemented for us in bsp_irq_dispatch_list */ +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#include <rtems/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. + These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ + + /* + + #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC_IRQ_NUMBER (32) + + */ + /* PPC405EX interrupt vectors */ + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) + #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) + + #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) + #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) + + #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) + + #define BSP_UIC_IRQ_NUMBER (95) + + + #define BSP_UIC_IRQ_LOWEST_OFFSET 0 + #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) + + #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ + #define BSP_UART_COM2_IRQ BSP_UIC_UART1 + + /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */ + + #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ + #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 + #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + + #define BSP_PROCESSOR_IRQ_NUMBER (3) + #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) + #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* Summary and totals */ + + #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) + #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) + #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c + #include <bsp/irq_supp.h> + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* Haleakala_IRQ_IRQ_H */ diff --git a/bsps/powerpc/haleakala/include/mmu_405.h b/bsps/powerpc/haleakala/include/mmu_405.h new file mode 100644 index 0000000000..e11cfa7738 --- /dev/null +++ b/bsps/powerpc/haleakala/include/mmu_405.h @@ -0,0 +1,77 @@ +#ifndef _mmu_405_h +#define _mmu_405_h + +/* + Simple interface to the PowerPC 405 MMU + + The intention here is just to allow the MMU to be used to define cacheability and + read/write/execute permissions in a simple enough way to fit entirely into the + 64-entry TLB cache. + + This code does not do address relocation and does not generate any MMU-related interrupts. + + The process ID support is there for a possible future extension where RTEMS supports + setting the process ID on task switches, which allows per-process stack protection + + This code will call fatal_error() if your add_space() calls overrun the 64 entries + + Michael Hamel ADInstruments 2008 + +*/ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" + +enum { + kAllProcessIDs = 0 +}; + +typedef enum MMUAccessType { + executable, + readOnlyData, + readOnlyNoCache, + readWriteData, + readWriteNoCache, + readWriteExecutable +} MMUAccessType; + +/* Initialise and clear the MMU */ +void mmu_initialise(); + +/* Turn on/off data access translation */ +bool mmu_enable_data(bool enable); + +/* Turn on instruction translation */ +bool mmu_enable_code(bool enable); + +/* Define properties for an area of memory (must be 1K-aligned) */ +void mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID); + +/* Delete a memory property definition */ +void mmu_remove_space(uint32_t startAddr, uint32_t endAddr); + +/* Return number of TLB entries out of total in use */ +int mmu_get_tlb_count(); + +/* Allocate a new process ID and return it */ +uint8_t mmu_new_processID(); + +/* Free a process ID that has been in use */ +void mmu_free_processID(uint8_t freeThis); + +/* Return the current process ID */ +uint8_t mmu_current_processID(); + +/* Change the process ID to ID and return the old value */ +uint8_t mmu_set_processID(uint8_t toID); + + +#ifdef __cplusplus +} +#endif + +#endif //_mmu_405.h
\ No newline at end of file diff --git a/bsps/powerpc/haleakala/include/tm27.h b/bsps/powerpc/haleakala/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/haleakala/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> |