diff options
Diffstat (limited to 'bsps/powerpc/beatnik/net/if_gfe')
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/gtethreg.h | 854 | ||||
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/gtvar.h | 170 | ||||
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/if_gfe.c | 2648 | ||||
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/if_gfe_rtems.c | 129 | ||||
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/if_gfevar.h | 225 | ||||
| -rw-r--r-- | bsps/powerpc/beatnik/net/if_gfe/rtemscompat_defs.h | 161 |
6 files changed, 0 insertions, 4187 deletions
diff --git a/bsps/powerpc/beatnik/net/if_gfe/gtethreg.h b/bsps/powerpc/beatnik/net/if_gfe/gtethreg.h deleted file mode 100644 index d571eecd34..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/gtethreg.h +++ /dev/null @@ -1,854 +0,0 @@ -/* $NetBSD: gtethreg.h,v 1.2.10.1 2005/04/29 11:28:55 kent Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _DEV_GTETHREG_H_ -#define _DEV_GTETHREG_H_ - -#define ETH__BIT(bit) (1U << (bit)) -#define ETH__LLBIT(bit) (1LLU << (bit)) -#define ETH__MASK(bit) (ETH__BIT(bit) - 1) -#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) -#define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off)) -#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) -#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) -#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) -#define ETH__INS(new, bit) ((new) << (bit)) -#define ETH__LLINS(new, bit) ((uint64_t)(new) << (bit)) - -/* - * Descriptors used for both receive & transmit data. Note that the descriptor - * must start on a 4LW boundary. Since the GT accesses the descriptor as - * two 64-bit quantities, we must present them 32bit quantities in the right - * order based on endianess. - */ - -struct gt_eth_desc { -#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN - u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ - u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ - u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ - u_int32_t ed_bufptr; /* pointer to packet buffer */ -#endif -#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN - u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ - u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ - u_int32_t ed_bufptr; /* pointer to packet buffer */ - u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ -#endif -}; - -/* Table 578: Ethernet TX Descriptor - Command/Status word - * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, - * otherwise should be 0 (tx). - */ -#define TX_STS_LC ETH__BIT(5) /* Late Collision */ -#define TX_STS_UR ETH__BIT(6) /* Underrun error */ -#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ -#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ -#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ -#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ -#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ -#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ -#define TX_CMD_P ETH__BIT(18) /* Pad Packet */ -#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ -#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ -#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ -#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ - -#define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) -#define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) - -/* Table 582: Ethernet RX Descriptor - Command/Status Word - * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, - * otherwise should be ignored (rx). - */ -#define RX_STS_CE ETH__BIT(0) /* CRC Error */ -#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ -#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ -#define RX_STS_OR ETH__BIT(6) /* Overrun Error */ -#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ -#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ -#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ -#define RX_STS_M ETH__BIT(12) /* Missed Frame */ -#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ -#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ -#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ -#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ -#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ -#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ -#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ -#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ - -/* Table 586: Hash Table Entry Fields - */ -#define HSH_V ETH__LLBIT(0) /* Entry is valid */ -#define HSH_S ETH__LLBIT(1) /* Skip this entry */ -#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ -#define HSH_R ETH__LLBIT(2) /* Receive(1) */ -#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) -#define HSH_PRIO_INS(v) ETH__LLINS(v, 51) -#define HSH_ADDR_MASK 0x7fffff8LLU -#define HSH_LIMIT 12 - - -#define ETH_EPAR 0x2000 /* PHY Address Register */ -#define ETH_ESMIR 0x2010 /* SMI Register */ - -#define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */ -#define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */ -#define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */ -#define ETH_SIZE 0x0400 /* Register Space */ - -#define ETH__EBASE 0x0000 /* Base of Registers */ -#define ETH__EPCR 0x0000 /* Port Config. Register */ -#define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */ -#define ETH__EPCMR 0x0010 /* Port Command Register */ -#define ETH__EPSR 0x0018 /* Port Status Register */ -#define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */ -#define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/ -#define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */ -#define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */ -#define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */ -#define ETH__ESDCMR 0x0048 /* SDMA Command Register */ -#define ETH__EICR 0x0050 /* Interrupt Cause Register */ -#define ETH__EIMR 0x0058 /* Interrupt Mask Register */ -#define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */ -#define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */ -#define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */ -#define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */ -#define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */ -#define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */ -#define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */ -#define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */ -#define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */ -#define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */ -#define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services - CodePoint to Priority0 low */ -#define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services - CodePoint to Priority0 high*/ -#define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services - CodePoint to Priority1 low */ -#define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services - CodePoint to Priority1 high*/ -#define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */ -#define ETH__EMIBCTRS 0x0100 /* MIB Counters */ - -#define ETH_BASE(n) ETH__GEN(n, EBASE) -#define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */ -#define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */ -#define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */ -#define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */ -#define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */ -#define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/ -#define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */ -#define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */ -#define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */ -#define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */ -#define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */ -#define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */ -#define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */ -#define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */ -#define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */ -#define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */ -#define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */ -#define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */ -#define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */ -#define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */ -#define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */ -#define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */ -#define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services - CodePoint to Priority0 low */ -#define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services - CodePoint to Priority0 high*/ -#define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services - CodePoint to Priority1 low */ -#define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services - CodePoint to Priority1 high*/ -#define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */ -#define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */ - -#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) - -#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ - ETH__INS(reg, 21)|\ - ETH_ESMIR_ReadOpcode) -#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ - ETH__INS(reg, 21)|\ - ETH__INS(val, 0)|\ - ETH_ESMIR_WriteOpcode) -#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) -#define ETH_ESMIR_WriteOpcode 0 -#define ETH_ESMIR_ReadOpcode ETH__BIT(26) -#define ETH_ESMIR_ReadValid ETH__BIT(27) -#define ETH_ESMIR_Busy ETH__BIT(28) - -/* - * Table 597: Port Configuration Register (PCR) - * 00:00 PM Promiscuous mode - * 0: Normal mode (Frames are only received if the - * destination address is found in the hash - * table) - * 1: Promiscuous mode (Frames are received - * regardless of their destination address. - * Errored frames are discarded unless the Port - * Configuration register's PBF bit is set) - * 01:01 RBM Reject Broadcast Mode - * 0: Receive broadcast address - * 1: Reject frames with broadcast address - * Overridden by the promiscuous mode. - * 02:02 PBF Pass Bad Frames - * (0: Normal mode, 1: Pass bad Frames) - * The Ethernet receiver passes to the CPU errored - * frames (like fragments and collided packets) - * that are normally rejected. - * NOTE: Frames are only passed if they - * successfully pass address filtering. - * 06:03 Reserved - * 07:07 EN Enable (0: Disabled, 1: Enable) - * When enabled, the ethernet port is ready to - * transmit/receive. - * 09:08 LPBK Loop Back Mode - * 00: Normal mode - * 01: Internal loop back mode (TX data is looped - * back to the RX lines. No transition is seen - * on the interface pins) - * 10: External loop back mode (TX data is looped - * back to the RX lines and also transmitted - * out to the MII interface pins) - * 11: Reserved - * 10:10 FC Force Collision - * 0: Normal mode. - * 1: Force Collision on any TX frame. - * For RXM test (in Loopback mode). - * 11:11 Reserved. - * 12:12 HS Hash Size - * 0: 8K address filtering - * (256KB of memory space required). - * 1: 512 address filtering - * ( 16KB of memory space required). - * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) - * 14:14 HDM Hash Default Mode - * 0: Discard addresses not found in address table - * 1: Pass addresses not found in address table - * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) - * NOTE: Valid only when auto-negotiation for - * duplex mode is disabled. - * 30:16 Reserved - * 31:31 ACCS Accelerate Slot Time - * (0: Normal mode, 1: Reserved) - */ -#define ETH_EPCR_PM ETH__BIT(0) -#define ETH_EPCR_RBM ETH__BIT(1) -#define ETH_EPCR_PBF ETH__BIT(2) -#define ETH_EPCR_EN ETH__BIT(7) -#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) -#define ETH_EPCR_LPBK_Normal 0 -#define ETH_EPCR_LPBK_Internal 1 -#define ETH_EPCR_LPBK_External 2 -#define ETH_EPCR_FC ETH__BIT(10) - -#define ETH_EPCR_HS ETH__BIT(12) -#define ETH_EPCR_HS_8K 0 -#define ETH_EPCR_HS_512 ETH_EPCR_HS - -#define ETH_EPCR_HM ETH__BIT(13) -#define ETH_EPCR_HM_0 0 -#define ETH_EPCR_HM_1 ETH_EPCR_HM - -#define ETH_EPCR_HDM ETH__BIT(14) -#define ETH_EPCR_HDM_Discard 0 -#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM - -#define ETH_EPCR_HD_Half 0 -#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full - -#define ETH_EPCR_ACCS ETH__BIT(31) - - - -/* - * Table 598: Port Configuration Extend Register (PCXR) - * 00:00 IGMP IGMP Packets Capture Enable - * 0: IGMP packets are treated as normal Multicast - * packets. - * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 - * are trapped and sent to high priority RX - * queue. - * 01:01 SPAN Spanning Tree Packets Capture Enable - * 0: BPDU (Bridge Protocol Data Unit) packets are - * treated as normal Multicast packets. - * 1: BPDU packets are trapped and sent to high - * priority RX queue. - * 02:02 PAR Partition Enable (0: Normal, 1: Partition) - * When more than 61 collisions occur while - * transmitting, the port enters Partition mode. - * It waits for the first good packet from the - * wire and then goes back to Normal mode. Under - * Partition mode it continues transmitting, but - * it does not receive. - * 05:03 PRIOtx Priority weight in the round-robin between high - * and low priority TX queues. - * 000: 1 pkt from HIGH, 1 pkt from LOW. - * 001: 2 pkt from HIGH, 1 pkt from LOW. - * 010: 4 pkt from HIGH, 1 pkt from LOW. - * 011: 6 pkt from HIGH, 1 pkt from LOW. - * 100: 8 pkt from HIGH, 1 pkt from LOW. - * 101: 10 pkt from HIGH, 1 pkt from LOW. - * 110: 12 pkt from HIGH, 1 pkt from LOW. - * 111: All pkt from HIGH, 0 pkt from LOW. LOW is - * served only if HIGH is empty. - * NOTE: If the HIGH queue is emptied before - * finishing the count, the count is reset - * until the next first HIGH comes in. - * 07:06 PRIOrx Default Priority for Packets Received on this - * Port (00: Lowest priority, 11: Highest priority) - * 08:08 PRIOrx_Override Override Priority for Packets Received on this - * Port (0: Do not override, 1: Override with - * <PRIOrx> field) - * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode - * (0: Enable, 1: Disable) - * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control - * 0: Enable; When enabled, 1 is written (through - * SMI access) to the PHY's register 4 bit 10 - * to advertise flow-control capability. - * 1: Disable; Only enables flow control after the - * PHY address is set by the CPU. When changing - * the PHY address the flow control - * auto-negotiation must be disabled. - * 11:11 FLP Force Link Pass - * (0: Force Link Pass, 1: Do NOT Force Link pass) - * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) - * NOTE: Only valid when auto negotiation for flow - * control is disabled. - * 13:13 Reserved - * 15:14 MFL Max Frame Length - * Maximum packet allowed for reception (including - * CRC): 00: 1518 bytes, 01: 1536 bytes, - * 10: 2048 bytes, 11: 64K bytes - * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) - * 17:17 MIBctrMode Reserved. (MBZ) - * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) - * NOTE: Only valid if SpeedEn bit is set. - * 19:19 SpeedEn Enable Auto-negotiation for Speed - * (0: Enable, 1: Disable) - * 20:20 RMIIen RMII enable - * 0: Port functions as MII port - * 1: Port functions as RMII port - * 21:21 DSCPen DSCP enable - * 0: IP DSCP field decoding is disabled. - * 1: IP DSCP field decoding is enabled. - * 31:22 Reserved - */ -#define ETH_EPCXR_IGMP ETH__BIT(0) -#define ETH_EPCXR_SPAN ETH__BIT(1) -#define ETH_EPCXR_PAR ETH__BIT(2) -#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) -#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) -#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) -#define ETH_EPCXR_DLPXen ETH__BIT(9) -#define ETH_EPCXR_FCTLen ETH__BIT(10) -#define ETH_EPCXR_FLP ETH__BIT(11) -#define ETH_EPCXR_FCTL ETH__BIT(12) -#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) -#define ETH_EPCXR_MFL_1518 0 -#define ETH_EPCXR_MFL_1536 1 -#define ETH_EPCXR_MFL_2084 2 -#define ETH_EPCXR_MFL_64K 3 -#define ETH_EPCXR_MIBclrMode ETH__BIT(16) -#define ETH_EPCXR_MIBctrMode ETH__BIT(17) -#define ETH_EPCXR_Speed ETH__BIT(18) -#define ETH_EPCXR_SpeedEn ETH__BIT(19) -#define ETH_EPCXR_RMIIEn ETH__BIT(20) -#define ETH_EPCXR_DSCPEn ETH__BIT(21) - - - -/* - * Table 599: Port Command Register (PCMR) - * 14:00 Reserved - * 15:15 FJ Force Jam / Flow Control - * When in half-duplex mode, the CPU uses this bit - * to force collisions on the Ethernet segment. - * When the CPU recognizes that it is going to run - * out of receive buffers, it can force the - * transmitter to send jam frames, forcing - * collisions on the wire. To allow transmission - * on the Ethernet segment, the CPU must clear the - * FJ bit when more resources are available. When - * in full-duplex and flow-control is enabled, this - * bit causes the port's transmitter to send - * flow-control PAUSE packets. The CPU must reset - * this bit when more resources are available. - * 31:16 Reserved - */ - -#define ETH_EPCMR_FJ ETH__BIT(15) - - -/* - * Table 600: Port Status Register (PSR) -- Read Only - * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) - * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) - * 02:02 Fctl Indicates Flow-control Mode - * (0: enabled, 1: disabled) - * 03:03 Link Indicates Link Status (0: down, 1: up) - * 04:04 Pause Indicates that the port is in flow-control - * disabled state. This bit is set when an IEEE - * 802.3x flow-control PAUSE (XOFF) packet is - * received (assuming that flow-control is - * enabled and the port is in full-duplex mode). - * Reset when XON is received, or when the XOFF - * timer has expired. - * 05:05 TxLow Tx Low Priority Status - * Indicates the status of the low priority - * transmit queue: (0: Stopped, 1: Running) - * 06:06 TxHigh Tx High Priority Status - * Indicates the status of the high priority - * transmit queue: (0: Stopped, 1: Running) - * 07:07 TXinProg TX in Progress - * Indicates that the port's transmitter is in an - * active transmission state. - * 31:08 Reserved - */ -#define ETH_EPSR_Speed ETH__BIT(0) -#define ETH_EPSR_Duplex ETH__BIT(1) -#define ETH_EPSR_Fctl ETH__BIT(2) -#define ETH_EPSR_Link ETH__BIT(3) -#define ETH_EPSR_Pause ETH__BIT(4) -#define ETH_EPSR_TxLow ETH__BIT(5) -#define ETH_EPSR_TxHigh ETH__BIT(6) -#define ETH_EPSR_TXinProg ETH__BIT(7) - - -/* - * Table 601: Serial Parameters Register (SPR) - * 01:00 JAM_LENGTH Two bits to determine the JAM Length - * (in Backpressure) as follows: - * 00 = 12K bit-times - * 01 = 24K bit-times - * 10 = 32K bit-times - * 11 = 48K bit-times - * 06:02 JAM_IPG Five bits to determine the JAM IPG. - * The step is four bit-times. The value may vary - * between 4 bit time to 124. - * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. - * The step is four bit-times. The value may vary - * between 4 bit time to 124. - * 16:12 IPG_DATA Inter-Packet Gap (IPG) - * The step is four bit-times. The value may vary - * between 12 bit time to 124. - * NOTE: These bits may be changed only when the - * Ethernet ports is disabled. - * 21:17 Data_Blind Data Blinder - * The number of nibbles from the beginning of the - * IPG, in which the IPG counter is restarted when - * detecting a carrier activity. Following this - * value, the port enters the Data Blinder zone and - * does not reset the IPG counter. This ensures - * fair access to the medium. - * The default is 10 hex (64 bit times - 2/3 of the - * default IPG). The step is 4 bit-times. Valid - * range is 3 to 1F hex nibbles. - * NOTE: These bits may be only changed when the - * Ethernet port is disabled. - * 22:22 Limit4 The number of consecutive packet collisions that - * occur before the collision counter is reset. - * 0: The port resets its collision counter after - * 16 consecutive retransmit trials and - * restarts the Backoff algorithm. - * 1: The port resets its collision counter and - * restarts the Backoff algorithm after 4 - * consecutive transmit trials. - * 31:23 Reserved - */ -#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) -#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) -#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) -#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) -#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) -#define ETH_ESPR_Limit4(v) ETH__BIT(22) - -/* - * Table 602: Hash Table Pointer Register (HTPR) - * 31:00 HTP 32-bit pointer to the address table. - * Bits [2:0] must be set to zero. - */ - -/* - * Table 603: Flow Control Source Address Low (FCSAL) - * 15:0 SA[15:0] Source Address - * The least significant bits of the source - * address for the port. This address is used for - * Flow Control. - * 31:16 Reserved - */ - -/* - * Table 604: Flow Control Source Address High (FCSAH) - * 31:0 SA[47:16] Source Address - * The most significant bits of the source address - * for the port. This address is used for Flow - * Control. - */ - - -/* - * Table 605: SDMA Configuration Register (SDCR) - * 01:00 Reserved - * 05:02 RC Retransmit Count - * Sets the maximum number of retransmits per - * packet. After executing retransmit for RC - * times, the TX SDMA closes the descriptor with a - * Retransmit Limit error indication and processes - * the next packet. When RC is set to 0, the - * number of retransmits is unlimited. In this - * case, the retransmit process is only terminated - * if CPU issues an Abort command. - * 06:06 BLMR Big/Little Endian Receive Mode - * The DMA supports Big or Little Endian - * configurations on a per channel basis. The BLMR - * bit only affects data transfer to memory. - * 0: Big Endian - * 1: Little Endian - * 07:07 BLMT Big/Little Endian Transmit Mode - * The DMA supports Big or Little Endian - * configurations on a per channel basis. The BLMT - * bit only affects data transfer from memory. - * 0: Big Endian - * 1: Little Endian - * 08:08 POVR PCI Override - * When set, causes the SDMA to direct all its - * accesses in PCI_0 direction and overrides - * normal address decoding process. - * 09:09 RIFB Receive Interrupt on Frame Boundaries - * When set, the SDMA Rx generates interrupts only - * on frame boundaries (i.e. after writing the - * frame status to the descriptor). - * 11:10 Reserved - * 13:12 BSZ Burst Size - * Sets the maximum burst size for SDMA - * transactions: - * 00: Burst is limited to 1 64bit words. - * 01: Burst is limited to 2 64bit words. - * 10: Burst is limited to 4 64bit words. - * 11: Burst is limited to 8 64bit words. - * 31:14 Reserved - */ -#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) -#define ETH_ESDCR_BLMR ETH__BIT(6) -#define ETH_ESDCR_BLMT ETH__BIT(7) -#define ETH_ESDCR_POVR ETH__BIT(8) -#define ETH_ESDCR_RIFB ETH__BIT(9) -#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) -#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ - (v) |= ETH__INS(n, 12)) -#define ETH_ESDCR_BSZ_1 0 -#define ETH_ESDCR_BSZ_2 1 -#define ETH_ESDCR_BSZ_4 2 -#define ETH_ESDCR_BSZ_8 3 - -#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ - "4 64-bit words", "8 64-bit words" } - -/* - * Table 606: SDMA Command Register (SDCMR) - * 06:00 Reserved - * 07:07 ERD Enable RX DMA. - * Set to 1 by the CPU to cause the SDMA to start - * a receive process. Cleared when the CPU issues - * an Abort Receive command. - * 14:08 Reserved - * 15:15 AR Abort Receive - * Set to 1 by the CPU to abort a receive SDMA - * operation. When the AR bit is set, the SDMA - * aborts its current operation and moves to IDLE. - * No descriptor is closed. The AR bit is cleared - * upon entering IDLE. After setting the AR bit, - * the CPU must poll the bit to verify that the - * abort sequence is completed. - * 16:16 STDH Stop TX High - * Set to 1 by the CPU to stop the transmission - * process from the high priority queue at the end - * of the current frame. An interrupt is generated - * when the stop command has been executed. - * Writing 1 to STDH resets TXDH bit. - * Writing 0 to this bit has no effect. - * 17:17 STDL Stop TX Low - * Set to 1 by the CPU to stop the transmission - * process from the low priority queue at the end - * of the current frame. An interrupt is generated - * when the stop command has been executed. - * Writing 1 to STDL resets TXDL bit. - * Writing 0 to this bit has no effect. - * 22:18 Reserved - * 23:23 TXDH Start Tx High - * Set to 1 by the CPU to cause the SDMA to fetch - * the first descriptor and start a transmit - * process from the high priority Tx queue. - * Writing 1 to TXDH resets STDH bit. - * Writing 0 to this bit has no effect. - * 24:24 TXDL Start Tx Low - * Set to 1 by the CPU to cause the SDMA to fetch - * the first descriptor and start a transmit - * process from the low priority Tx queue. - * Writing 1 to TXDL resets STDL bit. - * Writing 0 to this bit has no effect. - * 30:25 Reserved - * 31:31 AT Abort Transmit - * Set to 1 by the CPU to abort a transmit DMA - * operation. When the AT bit is set, the SDMA - * aborts its current operation and moves to IDLE. - * No descriptor is closed. Cleared upon entering - * IDLE. After setting AT bit, the CPU must poll - * it in order to verify that the abort sequence - * is completed. - */ -#define ETH_ESDCMR_ERD ETH__BIT(7) -#define ETH_ESDCMR_AR ETH__BIT(15) -#define ETH_ESDCMR_STDH ETH__BIT(16) -#define ETH_ESDCMR_STDL ETH__BIT(17) -#define ETH_ESDCMR_TXDH ETH__BIT(23) -#define ETH_ESDCMR_TXDL ETH__BIT(24) -#define ETH_ESDCMR_AT ETH__BIT(31) - -/* - * Table 607: Interrupt Cause Register (ICR) - * 00:00 RxBuffer Rx Buffer Return - * Indicates an Rx buffer returned to CPU ownership - * or that the port finished reception of a Rx - * frame in either priority queues. - * NOTE: In order to get a Rx Buffer return per - * priority queue, use bit 19:16. This bit is - * set upon closing any Rx descriptor which - * has its EI bit set. To limit the - * interrupts to frame (rather than buffer) - * boundaries, the user must set SDMA - * Configuration register's RIFB bit. When - * the RIFB bit is set, an interrupt - * generates only upon closing the first - * descriptor of a received packet, if this - * descriptor has it EI bit set. - * 01:01 Reserved - * 02:02 TxBufferHigh Tx Buffer for High priority Queue - * Indicates a Tx buffer returned to CPU ownership - * or that the port finished transmission of a Tx - * frame. - * NOTE: This bit is set upon closing any Tx - * descriptor which has its EI bit set. To - * limit the interrupts to frame (rather than - * buffer) boundaries, the user must set EI - * only in the last descriptor. - * 03:03 TxBufferLow Tx Buffer for Low Priority Queue - * Indicates a Tx buffer returned to CPU ownership - * or that the port finished transmission of a Tx - * frame. - * NOTE: This bit is set upon closing any Tx - * descriptor which has its EI bit set. To - * limit the interrupts to frame (rather than - * buffer) boundaries, the user must set EI - * only in the last descriptor. - * 05:04 Reserved - * 06:06 TxEndHigh Tx End for High Priority Queue - * Indicates that the Tx DMA stopped processing the - * high priority queue after stop command, or that - * it reached the end of the high priority - * descriptor chain. - * 07:07 TxEndLow Tx End for Low Priority Queue - * Indicates that the Tx DMA stopped processing the - * low priority queue after stop command, or that - * it reached the end of the low priority - * descriptor chain. - * 08:08 RxError Rx Resource Error - * Indicates a Rx resource error event in one of - * the priority queues. - * NOTE: To get a Rx Resource Error Indication per - * priority queue, use bit 23:20. - * 09:09 Reserved - * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue - * Indicates a Tx resource error event during - * packet transmission from the high priority queue - * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue - * Indicates a Tx resource error event during - * packet transmission from the low priority queue - * 12:12 RxOVR Rx Overrun - * Indicates an overrun event that occurred during - * reception of a packet. - * 13:13 TxUdr Tx Underrun - * Indicates an underrun event that occurred during - * transmission of packet from either queue. - * 15:14 Reserved - * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] - * Indicates a Rx buffer returned to CPU ownership - * or that the port completed reception of a Rx - * frame in a receive priority queue[0] - * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] - * Indicates a Rx buffer returned to CPU ownership - * or that the port completed reception of a Rx - * frame in a receive priority queue[1]. - * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] - * Indicates a Rx buffer returned to CPU ownership - * or that the port completed reception of a Rx - * frame in a receive priority queue[2]. - * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] - * Indicates a Rx buffer returned to CPU ownership - * or that the port completed reception of a Rx - * frame in a receive priority queue[3]. - * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] - * Indicates a Rx resource error event in receive - * priority queue[0]. - * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] - * Indicates a Rx resource error event in receive - * priority queue[1]. - * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] - * Indicates a Rx resource error event in receive - * priority queue[2]. - * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] - * Indicates a Rx resource error event in receive - * priority queue[3]. - * 27:24 Reserved - * 28:29 MIIPhySTC MII PHY Status Change - * Indicates a status change reported by the PHY - * connected to this port. Set when the MII - * management interface block identifies a change - * in PHY's register 1. - * 29:29 SMIdone SMI Command Done - * Indicates that the SMI completed a MII - * management command (either read or write) that - * was initiated by the CPU writing to the SMI - * register. - * 30:30 Reserved - * 31:31 EtherIntSum Ethernet Interrupt Summary - * This bit is a logical OR of the (unmasked) bits - * [30:04] in the Interrupt Cause register. - */ - -#define ETH_IR_RxBuffer ETH__BIT(0) -#define ETH_IR_TxBufferHigh ETH__BIT(2) -#define ETH_IR_TxBufferLow ETH__BIT(3) -#define ETH_IR_TxEndHigh ETH__BIT(6) -#define ETH_IR_TxEndLow ETH__BIT(7) -#define ETH_IR_RxError ETH__BIT(8) -#define ETH_IR_TxErrorHigh ETH__BIT(10) -#define ETH_IR_TxErrorLow ETH__BIT(11) -#define ETH_IR_RxOVR ETH__BIT(12) -#define ETH_IR_TxUdr ETH__BIT(13) -#define ETH_IR_RxBuffer_0 ETH__BIT(16) -#define ETH_IR_RxBuffer_1 ETH__BIT(17) -#define ETH_IR_RxBuffer_2 ETH__BIT(18) -#define ETH_IR_RxBuffer_3 ETH__BIT(19) -#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) -#define ETH_IR_RxError_0 ETH__BIT(20) -#define ETH_IR_RxError_1 ETH__BIT(21) -#define ETH_IR_RxError_2 ETH__BIT(22) -#define ETH_IR_RxError_3 ETH__BIT(23) -#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) -#define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ - ETH_IR_RxBuffer_1|\ - ETH_IR_RxBuffer_2|\ - ETH_IR_RxBuffer_3|\ - ETH_IR_RxError_0|\ - ETH_IR_RxError_1|\ - ETH_IR_RxError_2|\ - ETH_IR_RxError_3) -#define ETH_IR_MIIPhySTC ETH__BIT(28) -#define ETH_IR_SMIdone ETH__BIT(29) -#define ETH_IR_EtherIntSum ETH__BIT(31) -#define ETH_IR_Summary ETH__BIT(31) - -/* - * Table 608: Interrupt Mask Register (IMR) - * 31:00 Various Mask bits for the Interrupt Cause register. - */ - -/* - * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), - * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. - */ - -/* - * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) - * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. - */ - -/* - * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) - * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. - */ - -/* - * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) - * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. - */ - -/* - * Table 613: VLAN Priority Tag to Priority (VPT2P) - * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] - * entries. - * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] - * entries. - * 31:16 Reserved - */ - -/* Address control registers -- these are offsets from the GT base - * and NOT from the ethernet port base. <tss> - */ -#define ETH_ACTL_0_LO 0xf200 - -/* Enable hardware cache snooping; - * Copyright Shuchen K. Feng <feng1@bnl.gov>, 2004 - */ - -/* Ethernet address control (Low) snoop bits */ -#define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/ -#define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */ -#define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */ -#define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */ - -#define ETH_ACTL_0_HI 0xf204 -/* Ethernet address control (High), snoop bits */ -#define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */ - - -#define ETH_ACTL_1_LO 0xf220 -#define ETH_ACTL_1_HI 0xf224 -#define ETH_ACTL_2_LO 0xf240 -#define ETH_ACTL_2_HI 0xf244 - - -#endif /* _DEV_GTETHREG_H_ */ diff --git a/bsps/powerpc/beatnik/net/if_gfe/gtvar.h b/bsps/powerpc/beatnik/net/if_gfe/gtvar.h deleted file mode 100644 index 00d72bfa3a..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/gtvar.h +++ /dev/null @@ -1,170 +0,0 @@ -/* $NetBSD: gtvar.h,v 1.7.4.1 2005/04/29 11:28:56 kent Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * gtvar.h -- placeholder for GT system controller driver - */ -#ifndef _DISCOVERY_DEV_GTVAR_H_ -#define _DISCOVERY_DEV_GTVAR_H_ - -#include <sys/systm.h> - -struct gt_softc { -#ifndef __rtems__ - struct device gt_dev; - bus_dma_tag_t gt_dmat; - bus_space_tag_t gt_memt; /* the GT itself */ - bus_space_tag_t gt_pci0_memt; /* PCI0 mem space */ - bus_space_tag_t gt_pci0_iot; /* PCI0 i/o space */ - boolean_t gt_pci0_host; /* We're host on PCI0 if TRUE */ - bus_space_tag_t gt_pci1_memt; /* PCI1 mem space */ - bus_space_tag_t gt_pci1_iot; /* PCI1 i/o space */ - boolean_t gt_pci1_host; /* We're host on PCI1 if TRUE */ - - bus_space_handle_t gt_memh; /* to access the GT registers */ -#else - unsigned gt_memh; -#endif - int gt_childmask; /* what children are present */ -}; - -#define GT_CHILDOK(gt, ga, cd, pos, max) \ - (((ga)->ga_unit) < (max) && \ - !((gt)->gt_childmask & (1 << (((ga)->ga_unit) + (pos)))) && \ - !strcmp((ga)->ga_name, (cd)->cd_name)) - -#define GT_MPSCOK(gt, ga, cd) GT_CHILDOK((gt), (ga), (cd), 0, 2) -#define GT_PCIOK(gt, ga, cd) GT_CHILDOK((gt), (ga), (cd), 2, 2) -#define GT_ETHEROK(gt, ga, cd) GT_CHILDOK((gt), (ga), (cd), 4, 3) -#define GT_OBIOOK(gt, ga, cd) GT_CHILDOK((gt), (ga), (cd), 7, 5) -#define GT_I2COK(gt, ga, cd) GT_CHILDOK((gt), (ga), (cd), 12, 1) - -#define GT_CHILDFOUND(gt, ga, pos) \ - ((void)(((gt)->gt_childmask |= (1 << (((ga)->ga_unit) + (pos)))))) - -#define GT_MPSCFOUND(gt, ga) GT_CHILDFOUND((gt), (ga), 0) -#define GT_PCIFOUND(gt, ga) GT_CHILDFOUND((gt), (ga), 2) -#define GT_ETHERFOUND(gt, ga) GT_CHILDFOUND((gt), (ga), 4) -#define GT_OBIOFOUND(gt, ga) GT_CHILDFOUND((gt), (ga), 7) -#define GT_I2CFOUND(gt, ga) GT_CHILDFOUND((gt), (ga), 12) - -#ifndef __rtems__ -struct gt_attach_args { - const char *ga_name; /* class name of device */ - bus_dma_tag_t ga_dmat; /* dma tag */ - bus_space_tag_t ga_memt; /* GT bus space tag */ - bus_space_handle_t ga_memh; /* GT bus space handle */ - int ga_unit; /* instance of ga_name */ -}; - -struct obio_attach_args { - const char *oa_name; /* call name of device */ - bus_space_tag_t oa_memt; /* bus space tag */ - bus_addr_t oa_offset; /* offset (absolute) to device */ - bus_size_t oa_size; /* size (strided) of device */ - int oa_irq; /* irq */ -}; -#endif - -#ifdef _KERNEL -#ifndef __rtems__ -#include "locators.h" -#endif - -#ifdef DEBUG -extern int gtpci_debug; -#endif - -/* - * Locators for GT private devices, as specified to config. - */ -#define GT_UNK_UNIT GTCF_UNIT_DEFAULT /* wcarded 'function' */ - -#define OBIO_UNK_OFFSET OBIOCF_OFFSET_DEFAULT /* wcarded 'offset' */ - -#define OBIO_UNK_SIZE OBIOCF_SIZE_DEFAULT /* wcarded 'size' */ - -#define OBIO_UNK_IRQ OBIOCF_IRQ_DEFAULT /* wcarded 'irq' */ - -void gt_attach_common(struct gt_softc *); -uint32_t gt_read_mpp(void); -int gt_cfprint(void *, const char *); - -#ifndef __rtems__ -/* int gt_bs_extent_init(struct discovery_bus_space *, char *); AKB */ -int gt_mii_read(struct device *, struct device *, int, int); -void gt_mii_write(struct device *, struct device *, int, int, int); -int gtget_macaddr(struct gt_softc *,int, char *); - -void gt_watchdog_service(void); -bus_addr_t gt_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); -bus_addr_t gt_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); - -#define gt_read(gt,o) \ - bus_space_read_4((gt)->gt_memt, (gt)->gt_memh, (o)) -#define gt_write(gt,o,v) \ - bus_space_write_4((gt)->gt_memt, (gt)->gt_memh, (o), (v)) -#else -#endif - -#if defined(__powerpc__) -static __inline volatile int -atomic_add(volatile int *p, int v) -{ - int rv; - int rtmp; - - __asm __volatile( - "1: lwarx %0,0,%3\n" - " add %1,%4,%0\n" - " stwcx. %1,0,%3\n" - " bne- 1b\n" - " sync" - : "=&r"(rv), "=&r"(rtmp), "=m"(*p) - : "r"(p), "r"(v), "m"(*p) - : "cc"); - - return rv; -} - -#endif /* __powerpc__ */ - -#endif /* _KERNEL */ - -#endif /* _DISCOVERY_DEV_GTVAR_H_ */ diff --git a/bsps/powerpc/beatnik/net/if_gfe/if_gfe.c b/bsps/powerpc/beatnik/net/if_gfe/if_gfe.c deleted file mode 100644 index 7b29717791..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/if_gfe.c +++ /dev/null @@ -1,2648 +0,0 @@ -/* $NetBSD: if_gfe.c,v 1.13.8.1 2005/04/29 11:28:56 kent Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Copyright 2004: Enable hardware cache snooping. Kate Feng <feng1@bnl.gov> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * if_gfe.c -- GT ethernet MAC driver - */ - -/* Enable hardware cache snooping; - * Copyright Shuchen K. Feng <feng1@bnl.gov>, 2004 - */ - -#ifdef __rtems__ -#include "rtemscompat_defs.h" -#include "../porting/rtemscompat.h" -#include <string.h> -#include <stdio.h> -#include <inttypes.h> -#endif - -#include <sys/cdefs.h> -#ifndef __rtems__ -__KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.13.8.1 2005/04/29 11:28:56 kent Exp $"); - -#include "opt_inet.h" -#include "bpfilter.h" -#endif - -#include <sys/param.h> -#include <sys/types.h> -#ifndef __rtems__ -#include <sys/inttypes.h> -#include <sys/queue.h> -#endif - -#ifndef __rtems__ -#include <uvm/uvm_extern.h> - -#include <sys/callout.h> -#include <sys/device.h> -#endif -#include <sys/errno.h> -#include <sys/mbuf.h> -#include <sys/socket.h> -#include <sys/sockio.h> - -#ifndef __rtems__ -#include <machine/bus.h> -#endif - -#include <net/if.h> -#include <net/if_dl.h> -#include <net/if_media.h> -#ifndef __rtems__ -#include <net/if_ether.h> -#else -#include <netinet/in.h> -#include <netinet/if_ether.h> -#include <net/ethernet.h> -#include <rtems/rtems_mii_ioctl.h> -#endif - -#ifdef INET -#include <netinet/in.h> -#ifndef __rtems__ -#include <netinet/if_inarp.h> -#endif -#endif -#if NBPFILTER > 0 -#include <net/bpf.h> -#endif - -#ifndef __rtems__ -#include <dev/mii/miivar.h> - -#include <dev/marvell/gtintrreg.h> -#include <dev/marvell/gtethreg.h> - -#include <dev/marvell/gtvar.h> -#include <dev/marvell/if_gfevar.h> -#else -#include <bsp/gtintrreg.h> -#include <bsp/gtreg.h> -#include "gtethreg.h" - -#include "gtvar.h" -#include "if_gfevar.h" -#include "../porting/rtemscompat1.h" -#define ether_sprintf ether_sprintf_macro -#endif - -#define GE_READ(sc, reg) \ - bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) -#define GE_WRITE(sc, reg, v) \ - bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) - -#define GT_READ(sc, reg) \ - bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, reg) -#define GT_WRITE(sc, reg, v) \ - bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, reg, (v)) - -#define GE_DEBUG -#if 0 -#define GE_NOHASH -#define GE_NORX -#endif - -#ifdef GE_DEBUG -#define GE_DPRINTF(sc, a) do \ - if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ - printf a; \ - while (0) -#define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) -#define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) -#else -#define GE_DPRINTF(sc, a) do { } while (0) -#define GE_FUNC_ENTER(sc, func) do { } while (0) -#define GE_FUNC_EXIT(sc, str) do { } while (0) -#endif -enum gfe_whack_op { - GE_WHACK_START, GE_WHACK_RESTART, - GE_WHACK_CHANGE, GE_WHACK_STOP -}; - -enum gfe_hash_op { - GE_HASH_ADD, GE_HASH_REMOVE, -}; - - -#if 1 -#define htogt32(a) htobe32(a) -#define gt32toh(a) be32toh(a) -#else -#define htogt32(a) htole32(a) -#define gt32toh(a) le32toh(a) -#endif - -#ifdef __rtems__ -#define htobe32 htonl -#define be32toh ntohl -#endif - -#define GE_RXDSYNC(sc, rxq, n, ops) \ - bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ - (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ - (ops)) -#define GE_RXDPRESYNC(sc, rxq, n) \ - GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define GE_RXDPOSTSYNC(sc, rxq, n) \ - GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) - -#define GE_TXDSYNC(sc, txq, n, ops) \ - bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ - (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ - (ops)) -#define GE_TXDPRESYNC(sc, txq, n) \ - GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) -#define GE_TXDPOSTSYNC(sc, txq, n) \ - GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) - -#define STATIC - -#ifndef __rtems__ -STATIC int gfe_match (struct device *, struct cfdata *, void *); -STATIC void gfe_attach (struct device *, struct device *, void *); -#else -STATIC int gfe_probe (device_t); -STATIC int gfe_attach (device_t); -STATIC void gfe_init (void*); -#endif - -STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, - size_t, int); -STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); - -#ifndef __rtems__ -STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); -#else -STATIC int gfe_ifioctl (struct ifnet *, ioctl_command_t, caddr_t); -#endif -STATIC void gfe_ifstart (struct ifnet *); -STATIC void gfe_ifwatchdog (struct ifnet *); - -#ifndef __rtems__ -STATIC int gfe_mii_mediachange (struct ifnet *); -STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); -STATIC int gfe_mii_read (struct device *, int, int); -STATIC void gfe_mii_write (struct device *, int, int, int); -STATIC void gfe_mii_statchg (struct device *); -#endif - -STATIC void gfe_tick(void *arg); - -STATIC void gfe_tx_restart(void *); -STATIC void gfe_assign_desc(volatile struct gt_eth_desc *, struct mbuf *, - uint32_t); -STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); -STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); -STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); -STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); -STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); -STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); - -STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); -STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); -STATIC int gfe_rx_prime(struct gfe_softc *); -STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); -STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); -STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); -STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); - -STATIC int gfe_intr(void *); - -STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); - -STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); -STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, - enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); -#ifndef __rtems__ -STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, - u_long); -#endif -STATIC int gfe_hash_fill(struct gfe_softc *); -STATIC int gfe_hash_alloc(struct gfe_softc *); - -#ifndef __rtems__ -/* Linkup to the rest of the kernel */ -CFATTACH_DECL(gfe, sizeof(struct gfe_softc), - gfe_match, gfe_attach, NULL, NULL); -#else -net_drv_tbl_t METHODS = { - n_probe : gfe_probe, - n_attach : gfe_attach, - n_detach : 0, - n_intr : (void (*)(void*))gfe_intr, -}; - -int -gfe_mii_read(int phy, void *arg, unsigned reg, uint32_t *pval); -int -gfe_mii_write(int phy, void *arg, unsigned reg, uint32_t val); - -struct rtems_mdio_info -gfe_mdio_access = { - mdio_r: gfe_mii_read, - mdio_w: gfe_mii_write, - has_gmii: 0 -}; - -#endif - -extern struct cfdriver gfe_cd; - -#ifndef __rtems__ -int -gfe_match(struct device *parent, struct cfdata *cf, void *aux) -{ - struct gt_softc *gt = (struct gt_softc *) parent; - struct gt_attach_args *ga = aux; - uint8_t enaddr[6]; - - if (!GT_ETHEROK(gt, ga, &gfe_cd)) - return 0; - - if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) - return 0; - - if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && - enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) - return 0; - - return 1; -} -#else -int -gfe_probe(device_t dev) -{ - switch ( BSP_getDiscoveryVersion(0) ) { - case GT_64260_A: - case GT_64260_B: - return 0; - default: - break; - } - return -1; -} - -void -gfe_init(void *arg) -{ -struct gfe_softc *sc = arg; - if ( sc->sc_ec.ec_if.if_flags & IFF_RUNNING ) - gfe_whack(sc, GE_WHACK_RESTART); - else - gfe_whack(sc, GE_WHACK_START); -} -#endif - -/* - * Attach this instance, and then all the sub-devices - */ -#ifndef __rtems__ -void -gfe_attach(struct device *parent, struct device *self, void *aux) -#else -int -gfe_attach(device_t dev) -#endif -{ -#ifndef __rtems__ - struct gt_attach_args * const ga = aux; - struct gt_softc * const gt = (struct gt_softc *) parent; - struct gfe_softc * const sc = (struct gfe_softc *) self; -#else - struct gfe_softc * const sc = device_get_softc(dev); -#endif - struct ifnet * const ifp = &sc->sc_ec.ec_if; - uint32_t data; - uint8_t enaddr[6]; - int phyaddr; - uint32_t sdcr; - int error; -#ifdef __rtems__ - SPRINTFVARDECL; -#endif - -#ifndef __rtems__ - GT_ETHERFOUND(gt, ga); - - sc->sc_gt_memt = ga->ga_memt; - sc->sc_gt_memh = ga->ga_memh; - sc->sc_dmat = ga->ga_dmat; - sc->sc_macno = ga->ga_unit; - - if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, - ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { - aprint_error(": failed to map registers\n"); - } - - callout_init(&sc->sc_co); -#else - /* sc_macno, irq_no and sc_gt_memh must be filled in by 'setup' */ - - /* make ring sizes even numbers so that we have always multiple - * cache lines (paranoia) - */ - if ( (sc->num_rxdesc = dev->d_ifconfig->rbuf_count) & 1 ) - sc->num_rxdesc++; - if ( 0 == sc->num_rxdesc ) - sc->num_rxdesc = 64; - - if ( (sc->num_txdesc = dev->d_ifconfig->xbuf_count) & 1 ) - sc->num_txdesc++; - if ( 0 == sc->num_txdesc ) - sc->num_txdesc = 256; - - /* Enable hardware cache snooping; - * Copyright Shuchen K. Feng <feng1@bnl.gov>, 2004 - */ - /* regs are eth0: 0xf200/0xf204, eth1 0xf220/0xf224, eth2: 0xf240/0xf244 */ - { - uint32_t v; - v = GT_READ(sc, ETH_ACTL_0_LO + (sc->sc_macno<<5)); - v |= RxBSnoopEn|TxBSnoopEn|RxDSnoopEn|TxDSnoopEn; - GT_WRITE(sc, ETH_ACTL_0_LO + (sc->sc_macno<<5), v); - - v = GT_READ(sc, ETH_ACTL_0_HI + (sc->sc_macno<<5)); - v |= HashSnoopEn; - GT_WRITE(sc, ETH_ACTL_0_HI + (sc->sc_macno<<5), v); - } - -#endif - - data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); -#ifdef __rtems__ - sc->sc_phyaddr = -#endif - phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); - -#ifndef __rtems__ - gtget_macaddr(gt, sc->sc_macno, enaddr); -#else - memset( enaddr, 0, ETHER_ADDR_LEN ); - if ( !memcmp(enaddr, sc->arpcom.ac_enaddr, ETHER_ADDR_LEN) ) { - aprint_error(": MAC address not set (pass to rtems_gfe_setup())\n"); - return -1; - } - /* mac address needs to be provided by 'setup' */ - memcpy(enaddr, sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); -#endif - - sc->sc_pcr = GE_READ(sc, EPCR); - sc->sc_pcxr = GE_READ(sc, EPCXR); - sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; - - aprint_normal(": address %s", ether_sprintf(enaddr)); - -#if defined(DEBUG) - aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); -#endif - - sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; -#ifndef __rtems__ - if (sc->sc_dev.dv_cfdata->cf_flags & 1) { - aprint_normal(", phy %d (rmii)", phyaddr); - sc->sc_pcxr |= ETH_EPCXR_RMIIEn; - } else -#endif - { - aprint_normal(", phy %d (mii)", phyaddr); - sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; - } -#ifndef __rtems__ - if (sc->sc_dev.dv_cfdata->cf_flags & 2) - sc->sc_flags |= GE_NOFREE; -#endif - sc->sc_pcxr &= ~(3 << 14); - sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); - - if (sc->sc_pcr & ETH_EPCR_EN) { - int tries = 1000; - /* - * Abort transmitter and receiver and wait for them to quiese - */ - GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); - do { - delay(100); - } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); - } - - sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); - -#if defined(DEBUG) - aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); -#endif - - /* - * Now turn off the GT. If it didn't quiese, too ***ing bad. - */ - GE_WRITE(sc, EPCR, sc->sc_pcr); -#ifndef __rtems__ - GE_WRITE(sc, EIMR, sc->sc_intrmask); -#else - GE_WRITE(sc, EICR, 0); - GE_WRITE(sc, EIMR, 0); -#endif - sdcr = GE_READ(sc, ESDCR); - ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); - sdcr |= ETH_ESDCR_RIFB; - GE_WRITE(sc, ESDCR, sdcr); - sc->sc_max_frame_length = 1536; - - aprint_normal("\n"); -#ifndef __rtems__ - sc->sc_mii.mii_ifp = ifp; - sc->sc_mii.mii_readreg = gfe_mii_read; - sc->sc_mii.mii_writereg = gfe_mii_write; - sc->sc_mii.mii_statchg = gfe_mii_statchg; - - ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, - gfe_mii_mediastatus); - - mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, - MII_OFFSET_ANY, MIIF_NOISOLATE); - if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { - ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); - } else { - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); - } - - strcpy(ifp->if_xname, sc->sc_dev.dv_xname); -#else - if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_mtu = ETHERMTU; - ifp->if_output = ether_output; - ifp->if_init = gfe_init; - ifp->if_snd.ifq_maxlen = GE_TXDESC_MAX - 1; - ifp->if_baudrate = 10000000; -#endif - ifp->if_softc = sc; - /* ifp->if_mowner = &sc->sc_mowner; */ - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; -#if 0 - ifp->if_flags |= IFF_DEBUG; -#endif - ifp->if_ioctl = gfe_ifioctl; - ifp->if_start = gfe_ifstart; - ifp->if_watchdog = gfe_ifwatchdog; - - if (sc->sc_flags & GE_NOFREE) { - error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); - if (!error) - error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); - if (!error) - error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); - if (!error) - error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); - if (!error) - error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); - if (!error) - error = gfe_hash_alloc(sc); - if (error) - aprint_error( - "%s: failed to allocate resources: %d\n", - ifp->if_xname, error); - } - - if_attach(ifp); -#ifndef __rtems__ - ether_ifattach(ifp, enaddr); -#else - ether_ifattach(ifp); -#endif -#if NBPFILTER > 0 - bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); -#endif -#if NRND > 0 - rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); -#endif -#ifndef __rtems__ - intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, - gfe_intr, sc); -#else - return 0; -#endif -} - -int -gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, - size_t size, int flags) -{ - int error = 0; - GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); - - KASSERT(gdm->gdm_kva == NULL); - gdm->gdm_size = size; - gdm->gdm_maxsegs = maxsegs; - -#ifndef __rtems__ - error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, - gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, - BUS_DMA_NOWAIT); - if (error) - goto fail; - - error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, - gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); - if (error) - goto fail; - - error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, - gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); - if (error) - goto fail; - - error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, - gdm->gdm_size, NULL, BUS_DMA_NOWAIT); - if (error) - goto fail; -#else - gdm->gdm_segs[0].ds_len = size; - - /* FIXME: probably we can relax the alignment */ - if ( ! ( gdm->gdm_unaligned_buf = malloc( size + PAGE_SIZE - 1, M_DEVBUF, M_NOWAIT ) ) ) - goto fail; - - gdm->gdm_map = gdm; - gdm->gdm_nsegs = 1; - gdm->gdm_kva = (caddr_t)(gdm->gdm_segs[0].ds_addr = _DO_ALIGN(gdm->gdm_unaligned_buf, PAGE_SIZE)); -#endif - - /* invalidate from cache */ - bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, - BUS_DMASYNC_PREREAD); -fail: - if (error) { - gfe_dmamem_free(sc, gdm); - GE_DPRINTF(sc, (":err=%d", error)); - } - GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%" PRIx32 "/%" PRIx32, - gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, - gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); - GE_FUNC_EXIT(sc, ""); - return error; -} - -void -gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) -{ - GE_FUNC_ENTER(sc, "gfe_dmamem_free"); -#ifndef __rtems__ - if (gdm->gdm_map) - bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); - if (gdm->gdm_kva) - bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); - if (gdm->gdm_nsegs > 0) - bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); -#else - if (gdm->gdm_nsegs > 0) - free(gdm->gdm_unaligned_buf, M_DEVBUF); -#endif - gdm->gdm_map = NULL; - gdm->gdm_kva = NULL; - gdm->gdm_nsegs = 0; - GE_FUNC_EXIT(sc, ""); -} - -#ifndef __rtems__ -int -gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) -#else -int -gfe_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data) -#endif -{ - struct gfe_softc * const sc = ifp->if_softc; - struct ifreq *ifr = (struct ifreq *) data; -#ifndef __rtems__ - struct ifaddr *ifa = (struct ifaddr *) data; -#endif - int s, error = 0; - - GE_FUNC_ENTER(sc, "gfe_ifioctl"); - s = splnet(); - - switch (cmd) { -#ifndef __rtems__ - case SIOCSIFADDR: - ifp->if_flags |= IFF_UP; - switch (ifa->ifa_addr->sa_family) { -#ifdef INET - case AF_INET: - error = gfe_whack(sc, GE_WHACK_START); - if (error == 0) - arp_ifinit(ifp, ifa); - break; -#endif - default: - error = gfe_whack(sc, GE_WHACK_START); - break; - } - break; -#endif - - case SIOCSIFFLAGS: - if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) - sc->sc_pcr &= ~ETH_EPCR_PM; - else - sc->sc_pcr |= ETH_EPCR_PM; - switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { - case IFF_UP|IFF_RUNNING:/* active->active, update */ - error = gfe_whack(sc, GE_WHACK_CHANGE); - break; - case IFF_RUNNING: /* not up, so we stop */ - error = gfe_whack(sc, GE_WHACK_STOP); - break; - case IFF_UP: /* not running, so we start */ - error = gfe_whack(sc, GE_WHACK_START); - break; - case 0: /* idle->idle: do nothing */ - break; - } - break; - - case SIOCADDMULTI: - case SIOCDELMULTI: - error = (cmd == SIOCADDMULTI) - ? ether_addmulti(ifr, &sc->sc_ec) - : ether_delmulti(ifr, &sc->sc_ec); - if (error == ENETRESET) { - if (ifp->if_flags & IFF_RUNNING) -#if !defined(__rtems__) - error = gfe_whack(sc, GE_WHACK_CHANGE); -#else - /* doing GE_WHACK_CHANGE seems wrong - that - * doesn't do anything to the hash table. - * Therefore we perform a stop/start sequence. - */ - { - error = gfe_whack(sc, GE_WHACK_STOP); - if ( error ) - break; - error = gfe_whack(sc, GE_WHACK_START); - } -#endif - else - error = 0; - } - break; - - case SIOCSIFMTU: - if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { - error = EINVAL; - break; - } - ifp->if_mtu = ifr->ifr_mtu; - break; - - case SIOCSIFMEDIA: - case SIOCGIFMEDIA: -#ifndef __rtems__ - error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); -#else - error = rtems_mii_ioctl(&gfe_mdio_access, sc, cmd, &ifr->ifr_media); -#endif - break; - - default: -#ifndef __rtems__ - error = EINVAL; -#else - error = ether_ioctl(ifp, cmd, data); -#endif - break; - } - splx(s); - GE_FUNC_EXIT(sc, ""); - return error; -} - -void -gfe_ifstart(struct ifnet *ifp) -{ - struct gfe_softc * const sc = ifp->if_softc; - struct mbuf *m; - - GE_FUNC_ENTER(sc, "gfe_ifstart"); - - if ((ifp->if_flags & IFF_RUNNING) == 0) { - GE_FUNC_EXIT(sc, "$"); - return; - } - - for (;;) { - IF_DEQUEUE(&ifp->if_snd, m); - if (m == NULL) { - ifp->if_flags &= ~IFF_OACTIVE; - GE_FUNC_EXIT(sc, ""); - return; - } - - /* - * No space in the pending queue? try later. - */ - if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) - break; - - /* - * Try to enqueue a mbuf to the device. If that fails, we - * can always try to map the next mbuf. - */ - IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); - GE_DPRINTF(sc, (">")); -#ifndef GE_NOTX - (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); -#endif - } - - /* - * Attempt to queue the mbuf for send failed. - */ - IF_PREPEND(&ifp->if_snd, m); - ifp->if_flags |= IFF_OACTIVE; - GE_FUNC_EXIT(sc, "%%"); -} - -void -gfe_ifwatchdog(struct ifnet *ifp) -{ - struct gfe_softc * const sc = ifp->if_softc; - struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; - - GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); - printf("%s: device timeout", sc->sc_dev.dv_xname); - if (ifp->if_flags & IFF_RUNNING) { - uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); - GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); - GE_TXDPOSTSYNC(sc, txq, curtxdnum); - printf(" (fi=%d(%#" PRIx32 "),lo=%d,cur=%" PRIx32 "(%#" PRIx32 "),icm=%#" PRIx32 ") ", - txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, - txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, - GE_READ(sc, EICR)); - GE_TXDPRESYNC(sc, txq, txq->txq_fi); - GE_TXDPRESYNC(sc, txq, curtxdnum); - } - printf("\n"); - ifp->if_oerrors++; - (void) gfe_whack(sc, GE_WHACK_RESTART); - GE_FUNC_EXIT(sc, ""); -} - -#ifdef __rtems__ -static struct mbuf * -gfe_newbuf(struct mbuf *m) -{ - if ( !m ) { - MGETHDR(m, M_DONTWAIT, MT_DATA); - if ( !m ) - return 0; - MCLGET(m, M_DONTWAIT); - if ( !(M_EXT & m->m_flags) ) { - m_freem(m); - return 0; - } - } else { - m->m_data = m->m_ext.ext_buf; - } - m->m_len = m->m_pkthdr.len = MCLBYTES; -#if 0 - m_adj(m, 2); /* so payload is 16-byte aligned */ -#endif - return m; -} -#endif - -int -gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) -{ - struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; - int error; - - GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); - GE_DPRINTF(sc, ("(%d)", rxprio)); - - error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, - GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); - if (error) { - GE_FUNC_EXIT(sc, "!!"); - return error; - } - -#ifndef __rtems__ - error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, - GE_RXBUF_MEMSIZE, 0); -#else - if ( ! (rxq->rxq_bufs = malloc( sizeof(*rxq->rxq_bufs) * GE_RXDESC_MAX, M_DEVBUF, M_NOWAIT ) ) ) { - error = -1; - } else { - int i; - for ( i = 0; i<GE_RXDESC_MAX; i++ ) { - if ( !(rxq->rxq_bufs[i] = gfe_newbuf(0)) ) { - fprintf(stderr,"gfe: Not enough mbuf clusters to initialize RX ring!\n"); - while (--i >=0 ) { - m_freem(rxq->rxq_bufs[i]); - } - free(rxq->rxq_bufs, M_DEVBUF); - rxq->rxq_bufs = 0; - error = -1; - break; - } - } - } -#endif - if (error) { - GE_FUNC_EXIT(sc, "!!!"); - return error; - } - GE_FUNC_EXIT(sc, ""); - return error; -} - -int -gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) -{ - struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; - volatile struct gt_eth_desc *rxd; -#ifndef __rtems__ - const bus_dma_segment_t *ds; -#endif - int idx; - bus_addr_t nxtaddr; -#ifndef __rtems__ - bus_size_t boff; -#endif - - GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); - GE_DPRINTF(sc, ("(%d)", rxprio)); - - if ((sc->sc_flags & GE_NOFREE) == 0) { - int error = gfe_rx_rxqalloc(sc, rxprio); - if (error) { - GE_FUNC_EXIT(sc, "!"); - return error; - } - } else { - KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); -#ifndef __rtems__ - KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); -#else - KASSERT(rxq->rxq_bufs != NULL); -#endif - } - - memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); - - rxq->rxq_descs = - (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; - rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; -#ifndef __rtems__ - rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; -#endif - rxq->rxq_fi = 0; - rxq->rxq_active = GE_RXDESC_MAX; - for (idx = 0, rxd = rxq->rxq_descs, -#ifndef __rtems__ - boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, -#endif - nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); - idx < GE_RXDESC_MAX; - idx++, rxd++, nxtaddr += sizeof(*rxd)) { -#ifndef __rtems__ - rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); -#else - rxd->ed_lencnt = htogt32(MCLBYTES << 16); -#endif - rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); -#ifndef __rtems__ - rxd->ed_bufptr = htogt32(ds->ds_addr + boff); -#else - rxd->ed_bufptr = htogt32(mtod(rxq->rxq_bufs[idx], uint32_t)); -#endif - /* - * update the nxtptr to point to the next txd. - */ - if (idx == GE_RXDESC_MAX - 1) - nxtaddr = rxq->rxq_desc_busaddr; - rxd->ed_nxtptr = htogt32(nxtaddr); -#ifndef __rtems__ - boff += GE_RXBUF_SIZE; - if (boff == ds->ds_len) { - ds++; - boff = 0; - } -#endif - } - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, - rxq->rxq_desc_mem.gdm_map->dm_mapsize, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); -#ifndef __rtems__ - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, - rxq->rxq_buf_mem.gdm_map->dm_mapsize, - BUS_DMASYNC_PREREAD); -#else - /* FIXME: we leave this call in here so compilation fails - * if bus_dmamap_sync() is ever fleshed-out to implement - * software cache coherency... - */ - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, - rxq->rxq_buf_mem.gdm_map->dm_mapsize, - BUS_DMASYNC_PREREAD); -#endif - - rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; - switch (rxprio) { - case GE_RXPRIO_HI: - rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; - rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); - rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); - break; - case GE_RXPRIO_MEDHI: - rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; - rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); - rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); - break; - case GE_RXPRIO_MEDLO: - rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; - rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); - rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); - break; - case GE_RXPRIO_LO: - rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; - rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); - rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); - break; - } - GE_FUNC_EXIT(sc, ""); - return 0; -} - -void -gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) -{ - struct ifnet * const ifp = &sc->sc_ec.ec_if; - struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; -#ifndef __rtems__ - struct mbuf *m = rxq->rxq_curpkt; -#else - struct mbuf *m; -#endif - - GE_FUNC_ENTER(sc, "gfe_rx_get"); - GE_DPRINTF(sc, ("(%d)", rxprio)); - - while (rxq->rxq_active > 0) { - volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; -#ifndef __rtems__ - struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; -#else - struct mbuf **rxb = &rxq->rxq_bufs[rxq->rxq_fi]; -#endif - const struct ether_header *eh; - unsigned int cmdsts; - size_t buflen; - - GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); - cmdsts = gt32toh(rxd->ed_cmdsts); - GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); - rxq->rxq_cmdsts = cmdsts; - /* - * Sometimes the GE "forgets" to reset the ownership bit. - * But if the length has been rewritten, the packet is ours - * so pretend the O bit is set. - */ - buflen = gt32toh(rxd->ed_lencnt) & 0xffff; - if ((cmdsts & RX_CMD_O) && buflen == 0) { - GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); - break; - } - - /* - * If this is not a single buffer packet with no errors - * or for some reason it's bigger than our frame size, - * ignore it and go to the next packet. - */ - if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != - (RX_CMD_F|RX_CMD_L) || - buflen > sc->sc_max_frame_length) { - GE_DPRINTF(sc, ("!")); - --rxq->rxq_active; - ifp->if_ipackets++; - ifp->if_ierrors++; - - *rxb = gfe_newbuf(*rxb); - goto give_it_back; - } - - /* CRC is included with the packet; trim it off. */ - buflen -= ETHER_CRC_LEN; - -#ifndef __rtems__ - if (m == NULL) { - MGETHDR(m, M_DONTWAIT, MT_DATA); - if (m == NULL) { - GE_DPRINTF(sc, ("?")); - break; - } - } - if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { - MCLGET(m, M_DONTWAIT); - if ((m->m_flags & M_EXT) == 0) { - GE_DPRINTF(sc, ("?")); - break; - } - } - m->m_data += 2; - m->m_len = 0; - m->m_pkthdr.len = 0; - m->m_pkthdr.rcvif = ifp; -#else - if ( ! (m=gfe_newbuf(0)) ) { - /* recycle old buffer */ - *rxb = gfe_newbuf(*rxb); - goto give_it_back; - } - /* swap mbufs */ - { - struct mbuf *tmp = *rxb; - *rxb = m; - m = tmp; - rxd->ed_bufptr = htogt32(mtod(*rxb, uint32_t)); - } -#endif - rxq->rxq_cmdsts = cmdsts; - --rxq->rxq_active; - -#ifdef __rtems__ - /* FIXME: we leave this call in here so compilation fails - * if bus_dmamap_sync() is ever fleshed-out to implement - * software cache coherency... - */ - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, - rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); -#else - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, - rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); - - KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); - memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); -#endif - - m->m_len = buflen; - m->m_pkthdr.len = buflen; - - ifp->if_ipackets++; -#if NBPFILTER > 0 - if (ifp->if_bpf != NULL) - bpf_mtap(ifp->if_bpf, m); -#endif - - eh = (const struct ether_header *) m->m_data; - if ((ifp->if_flags & IFF_PROMISC) || - (rxq->rxq_cmdsts & RX_STS_M) == 0 || - (rxq->rxq_cmdsts & RX_STS_HE) || - (eh->ether_dhost[0] & 1) != 0 || - memcmp(eh->ether_dhost, -#ifndef __rtems__ - LLADDR(ifp->if_sadl), -#else - sc->sc_ec.ac_enaddr, -#endif - ETHER_ADDR_LEN) == 0) { -#ifndef __rtems__ - (*ifp->if_input)(ifp, m); - m = NULL; -#else - DO_ETHER_INPUT_SKIPPING_ETHER_HEADER(ifp,m); -#endif - GE_DPRINTF(sc, (">")); - } else { -#ifndef __rtems__ - m->m_len = 0; - m->m_pkthdr.len = 0; -#else - m_freem(m); -#endif - GE_DPRINTF(sc, ("+")); - } - rxq->rxq_cmdsts = 0; - - give_it_back: - rxd->ed_lencnt &= ~0xffff; /* zero out length */ - rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); -#if 0 - GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", - rxq->rxq_fi, - ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], - ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); -#endif - GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); - if (++rxq->rxq_fi == GE_RXDESC_MAX) - rxq->rxq_fi = 0; - rxq->rxq_active++; - } -#ifndef __rtems__ - rxq->rxq_curpkt = m; -#endif - GE_FUNC_EXIT(sc, ""); -} - -uint32_t -gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) -{ - struct ifnet * const ifp = &sc->sc_ec.ec_if; - struct gfe_rxqueue *rxq; - uint32_t rxbits; -#define RXPRIO_DECODER 0xffffaa50 - GE_FUNC_ENTER(sc, "gfe_rx_process"); - - rxbits = ETH_IR_RxBuffer_GET(cause); - while (rxbits) { - enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; - GE_DPRINTF(sc, ("%1" PRIx32, rxbits)); - rxbits &= ~(1 << rxprio); - gfe_rx_get(sc, rxprio); - } - - rxbits = ETH_IR_RxError_GET(cause); - while (rxbits) { - enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; - uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; - int idx; - rxbits &= ~(1 << rxprio); - rxq = &sc->sc_rxq[rxprio]; - sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); - intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); - if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { - sc->sc_tickflags |= GE_TICK_RX_RESTART; - callout_reset(&sc->sc_co, 1, gfe_tick, sc); - } - ifp->if_ierrors++; - GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", - sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); - memset(masks, 0, sizeof(masks)); - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, - 0, rxq->rxq_desc_mem.gdm_size, - BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); - for (idx = 0; idx < GE_RXDESC_MAX; idx++) { - volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; - - if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) - masks[idx/32] |= 1 << (idx & 31); - } - bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, - 0, rxq->rxq_desc_mem.gdm_size, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); -#if defined(DEBUG) - printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", - sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, - rxq->rxq_cmdsts, masks[0], masks[1]); -#endif - } - if ((intrmask & ETH_IR_RxBits) == 0) - intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); - - GE_FUNC_EXIT(sc, ""); - return intrmask; -} - -int -gfe_rx_prime(struct gfe_softc *sc) -{ - struct gfe_rxqueue *rxq; - int error; - - GE_FUNC_ENTER(sc, "gfe_rx_prime"); - - error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); - if (error) - goto bail; - rxq = &sc->sc_rxq[GE_RXPRIO_HI]; - if ((sc->sc_flags & GE_RXACTIVE) == 0) { - GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); - } - sc->sc_intrmask |= rxq->rxq_intrbits; - - error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); - if (error) - goto bail; - if ((sc->sc_flags & GE_RXACTIVE) == 0) { - rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; - GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); - sc->sc_intrmask |= rxq->rxq_intrbits; - } - - error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); - if (error) - goto bail; - if ((sc->sc_flags & GE_RXACTIVE) == 0) { - rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; - GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); - sc->sc_intrmask |= rxq->rxq_intrbits; - } - - error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); - if (error) - goto bail; - if ((sc->sc_flags & GE_RXACTIVE) == 0) { - rxq = &sc->sc_rxq[GE_RXPRIO_LO]; - GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); - sc->sc_intrmask |= rxq->rxq_intrbits; - } - - bail: - GE_FUNC_EXIT(sc, ""); - return error; -} - -void -gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) -{ - struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; - GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); - if (rxq == NULL) { - GE_FUNC_EXIT(sc, ""); - return; - } - -#ifndef __rtems__ - if (rxq->rxq_curpkt) - m_freem(rxq->rxq_curpkt); -#endif - if ((sc->sc_flags & GE_NOFREE) == 0) { - gfe_dmamem_free(sc, &rxq->rxq_desc_mem); -#ifndef __rtems__ - gfe_dmamem_free(sc, &rxq->rxq_buf_mem); -#else - if ( rxq->rxq_bufs ) { - int i; - for ( i=0; i<GE_RXDESC_MAX; i++ ) { - if ( rxq->rxq_bufs[i] ) { - m_freem(rxq->rxq_bufs[i]); - } - } - free(rxq->rxq_bufs, M_DEVBUF); - } -#endif - } - GE_FUNC_EXIT(sc, ""); -} - -void -gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) -{ - GE_FUNC_ENTER(sc, "gfe_rx_stop"); - sc->sc_flags &= ~GE_RXACTIVE; - sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); - sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); - GE_WRITE(sc, EIMR, sc->sc_intrmask); - GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); - do { - delay(10); - } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); - gfe_rx_cleanup(sc, GE_RXPRIO_HI); - gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); - gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); - gfe_rx_cleanup(sc, GE_RXPRIO_LO); - GE_FUNC_EXIT(sc, ""); -} - -void -gfe_tick(void *arg) -{ - struct gfe_softc * const sc = arg; - uint32_t intrmask; - unsigned int tickflags; - int s; - - GE_FUNC_ENTER(sc, "gfe_tick"); - - s = splnet(); - - tickflags = sc->sc_tickflags; - sc->sc_tickflags = 0; - intrmask = sc->sc_intrmask; - if (tickflags & GE_TICK_TX_IFSTART) - gfe_ifstart(&sc->sc_ec.ec_if); - if (tickflags & GE_TICK_RX_RESTART) { - intrmask |= sc->sc_idlemask; - if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { - struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; - rxq->rxq_fi = 0; - GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); - } - if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { - struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; - rxq->rxq_fi = 0; - GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); - } - if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { - struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; - rxq->rxq_fi = 0; - GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); - } - if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { - struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; - rxq->rxq_fi = 0; - GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); - GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); - } - sc->sc_idlemask = 0; - } - if (intrmask != sc->sc_intrmask) { - sc->sc_intrmask = intrmask; - GE_WRITE(sc, EIMR, sc->sc_intrmask); - } - gfe_intr(sc); - splx(s); - - GE_FUNC_EXIT(sc, ""); -} - -static int -gfe_free_slots(struct gfe_softc *sc, struct gfe_txqueue *const txq) -{ - struct ifnet * const ifp = &sc->sc_ec.ec_if; -#ifndef __rtems__ - const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; -#endif - int got = 0; - int fi = txq->txq_fi; - volatile struct gt_eth_desc *txd = &txq->txq_descs[fi]; - uint32_t cmdsts; -#ifndef __rtems__ - size_t pktlen; -#endif - - GE_FUNC_ENTER(sc, "gfe_free_slots"); - -#ifdef __rtems__ - do { -#endif - GE_TXDPOSTSYNC(sc, txq, fi); - if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { - int nextin; - - if (txq->txq_nactive == 1) { - GE_TXDPRESYNC(sc, txq, fi); - GE_FUNC_EXIT(sc, ""); - return -1; - } - /* - * Sometimes the Discovery forgets to update the - * ownership bit in the descriptor. See if we own the - * descriptor after it (since we know we've turned - * that to the Discovery and if we own it now then the - * Discovery gave it back). If we do, we know the - * Discovery gave back this one but forgot to mark it - * as ours. - */ - nextin = fi + 1; - if (nextin == GE_TXDESC_MAX) - nextin = 0; - GE_TXDPOSTSYNC(sc, txq, nextin); - if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { - GE_TXDPRESYNC(sc, txq, fi); - GE_TXDPRESYNC(sc, txq, nextin); - GE_FUNC_EXIT(sc, ""); - return -1; - } -#ifdef DEBUG - printf("%s: gfe_free_slots: transmitter resynced at %d\n", - sc->sc_dev.dv_xname, fi); -#endif - } - got++; -#ifdef __rtems__ - txd++; - fi++; - } while ( ! ( TX_CMD_LAST & cmdsts ) ); - - { struct mbuf *m; - IF_DEQUEUE(&txq->txq_sentq, m); - m_freem(m); - } -#endif -#if 0 - GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", - txq->txq_lo, - ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], - ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); -#endif - GE_DPRINTF(sc, ("(%d)", fi)); - txq->txq_fi = fi; - if ( txq->txq_fi >= GE_TXDESC_MAX) - txq->txq_fi -= GE_TXDESC_MAX; -#ifndef __rtems__ - txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; - pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; - bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, - txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); - txq->txq_inptr += roundup(pktlen, dcache_line_size); -#endif - - /* statistics */ - ifp->if_opackets++; -#ifdef __rtems__ - /* FIXME: should we check errors on every fragment? */ -#endif - if (cmdsts & TX_STS_ES) - ifp->if_oerrors++; - - /* txd->ed_bufptr = 0; */ - - txq->txq_nactive -= got; - - GE_FUNC_EXIT(sc, ""); - - return got; -} - -#ifndef __rtems__ -int -gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) -{ -#ifndef __rtems__ - const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; -#else -#ifndef PPC_CACHE_ALIGNMENT -#error "Unknown cache alignment for your CPU" -#endif - const int dcache_line_size = PPC_CACHE_ALIGNMENT; -#endif - struct ifnet * const ifp = &sc->sc_ec.ec_if; - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; - uint32_t intrmask = sc->sc_intrmask; - size_t buflen; - struct mbuf *m; - - GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); - - /* - * Anything in the pending queue to enqueue? if not, punt. Likewise - * if the txq is not yet created. - * otherwise grab its dmamap. - */ - if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { - GE_FUNC_EXIT(sc, "-"); - return 0; - } - - /* - * Have we [over]consumed our limit of descriptors? - * Do we have enough free descriptors? - */ - if (GE_TXDESC_MAX == txq->txq_nactive + 2) { - if ( gfe_free_slots(sc, txq) <= 0 ) - return 0; - } - - buflen = roundup(m->m_pkthdr.len, dcache_line_size); - - /* - * If this packet would wrap around the end of the buffer, reset back - * to the beginning. - */ - if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { - txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; - txq->txq_outptr = 0; - } - - /* - * Make sure the output packet doesn't run over the beginning of - * what we've already given the GT. - */ - if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && - txq->txq_outptr + buflen > txq->txq_inptr) { - intrmask |= txq->txq_intrbits & - (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); - if (sc->sc_intrmask != intrmask) { - sc->sc_intrmask = intrmask; - GE_WRITE(sc, EIMR, sc->sc_intrmask); - } - GE_FUNC_EXIT(sc, "#"); - return 0; - } - - /* - * The end-of-list descriptor we put on last time is the starting point - * for this packet. The GT is supposed to terminate list processing on - * a NULL nxtptr but that currently is broken so a CPU-owned descriptor - * must terminate the list. - */ - intrmask = sc->sc_intrmask; - - m_copydata(m, 0, m->m_pkthdr.len, - txq->txq_buf_mem.gdm_kva + txq->txq_outptr); - bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, - txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); - txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); - txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); - GE_TXDPRESYNC(sc, txq, txq->txq_lo); - - /* - * Request a buffer interrupt every 2/3 of the way thru the transmit - * buffer. - */ - txq->txq_ei_gapcount += buflen; - if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { - txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); - txq->txq_ei_gapcount = 0; - } else { - txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); - } -#if 0 - GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, - ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], - ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); -#endif - GE_TXDPRESYNC(sc, txq, txq->txq_lo); - - txq->txq_outptr += buflen; - /* - * Tell the SDMA engine to "Fetch!" - */ - GE_WRITE(sc, ESDCMR, - txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); - - GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); - - /* - * Update the last out appropriately. - */ - txq->txq_nactive++; - if (++txq->txq_lo == GE_TXDESC_MAX) - txq->txq_lo = 0; - - /* - * Move mbuf from the pending queue to the snd queue. - */ - IF_DEQUEUE(&txq->txq_pendq, m); -#if NBPFILTER > 0 - if (ifp->if_bpf != NULL) - bpf_mtap(ifp->if_bpf, m); -#endif - m_freem(m); - ifp->if_flags &= ~IFF_OACTIVE; - - /* - * Since we have put an item into the packet queue, we now want - * an interrupt when the transmit queue finishes processing the - * list. But only update the mask if needs changing. - */ - intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); - if (sc->sc_intrmask != intrmask) { - sc->sc_intrmask = intrmask; - GE_WRITE(sc, EIMR, sc->sc_intrmask); - } - if (ifp->if_timer == 0) - ifp->if_timer = 5; - GE_FUNC_EXIT(sc, "*"); - return 1; -} - -#else - -#ifdef __PPC__ -static inline void membarrier(void) -{ - asm volatile("sync":::"memory"); -} -#else -#error "memory synchronization for your CPU not implemented" -#endif - - -void -gfe_assign_desc(volatile struct gt_eth_desc *const d, struct mbuf *m, uint32_t flags) -{ - d->ed_cmdsts = htogt32(flags | TX_CMD_GC | TX_CMD_P); - d->ed_bufptr = htogt32(mtod(m, uint32_t)); - d->ed_lencnt = htogt32(m->m_len << 16); -} - -int -gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) -{ - struct ifnet * const ifp = &sc->sc_ec.ec_if; - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; -#define NEXT_TXD(d) ((d)+1 < &txq->txq_descs[GE_TXDESC_MAX] ? (d)+1 : txq->txq_descs) - volatile struct gt_eth_desc *l,*d; - uint32_t intrmask = sc->sc_intrmask; - struct mbuf *m_head,*m,*m1; - int avail, used; - - GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); - - /* - * Anything in the pending queue to enqueue? if not, punt. Likewise - * if the txq is not yet created. - * otherwise grab its dmamap. - */ - if (txq == NULL || (m_head = txq->txq_pendq.ifq_head) == NULL) { - GE_FUNC_EXIT(sc, "-"); - return 0; - } - - /* find 1st mbuf with actual data; m_head is not NULL at this point */ - for ( m1=m_head; 0 == m1->m_len; ) { - if ( ! (m1=m1->m_next) ) { - /* nothing to send */ - IF_DEQUEUE(&txq->txq_pendq, m_head); - m_freem(m_head); - return 0; - } - } - - avail = GE_TXDESC_MAX - 1 - txq->txq_nactive; - - if ( avail < 1 && (avail += gfe_free_slots(sc, txq)) < 1 ) - return 0; - - avail--; - - l = txd; - d = NEXT_TXD(txd); - - for ( m=m1->m_next, used = 1; m; m=m->m_next ) { - if ( 0 == m->m_len ) - continue; /* skip empty mbufs */ - - if ( avail < 1 && (avail += gfe_free_slots(sc, txq)) < 1 ) { - /* not enough descriptors; cleanup */ - for ( l = NEXT_TXD(txd); l!=d; l = NEXT_TXD(l) ) { - l->ed_cmdsts = 0; - avail++; - } - avail++; - if ( used >= GE_TXDESC_MAX-1 ) - panic("mbuf chain (#%i) longer than TX ring (#%i); configuration error!", - used, GE_TXDESC_MAX-1); - return 0; - } - used++; - avail--; - - /* fill this slot */ - gfe_assign_desc(d, m, TX_CMD_O); - - bus_dmamap_sync(sc->sc_dmat, /* TODO */, - mtod(m, uint32_t), m->m_len, BUS_DMASYNC_PREWRITE); - - l = d; - d = NEXT_TXD(d); - - GE_TXDPRESYNC(sc, txq, l - txq->txq_descs); - } - - /* fill first slot */ - gfe_assign_desc(txd, m1, TX_CMD_F); - - bus_dmamap_sync(sc->sc_dmat, /* TODO */, - mtod(m1, uint32_t), m1->m_len, BUS_DMASYNC_PREWRITE); - - /* tag last slot; this covers where 1st = last */ - l->ed_cmdsts |= htonl(TX_CMD_L | TX_CMD_EI); - - GE_TXDPRESYNC(sc, txq, l - txq->txq_descs); - - /* - * The end-of-list descriptor we put on last time is the starting point - * for this packet. The GT is supposed to terminate list processing on - * a NULL nxtptr but that currently is broken so a CPU-owned descriptor - * must terminate the list. - */ - d = NEXT_TXD(l); - - out_be32((uint32_t*)&d->ed_cmdsts,0); - - GE_TXDPRESYNC(sc, txq, d - txq->txq_descs); - - membarrier(); - - /* turn over the whole chain by flipping the ownership of the first desc */ - txd->ed_cmdsts |= htonl(TX_CMD_O); - - GE_TXDPRESYNC(sc, txq, txq->txq_lo); - - - intrmask = sc->sc_intrmask; - -#if 0 - GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, - ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], - ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); -#endif - - membarrier(); - - /* - * Tell the SDMA engine to "Fetch!" - */ - GE_WRITE(sc, ESDCMR, - txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); - - GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); - - /* - * Update the last out appropriately. - */ - txq->txq_nactive += used; - txq->txq_lo += used; - if ( txq->txq_lo >= GE_TXDESC_MAX ) - txq->txq_lo -= GE_TXDESC_MAX; - - /* - * Move mbuf from the pending queue to the snd queue. - */ - IF_DEQUEUE(&txq->txq_pendq, m_head); - - IF_ENQUEUE(&txq->txq_sentq, m_head); - -#if NBPFILTER > 0 - if (ifp->if_bpf != NULL) - bpf_mtap(ifp->if_bpf, m_head); -#endif - ifp->if_flags &= ~IFF_OACTIVE; - - /* - * Since we have put an item into the packet queue, we now want - * an interrupt when the transmit queue finishes processing the - * list. But only update the mask if needs changing. - */ - intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); - if (sc->sc_intrmask != intrmask) { - sc->sc_intrmask = intrmask; - GE_WRITE(sc, EIMR, sc->sc_intrmask); - } - if (ifp->if_timer == 0) - ifp->if_timer = 5; - GE_FUNC_EXIT(sc, "*"); - return 1; -} -#endif - -uint32_t -gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) -{ - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - struct ifnet * const ifp = &sc->sc_ec.ec_if; - - GE_FUNC_ENTER(sc, "gfe_tx_done"); - - if (txq == NULL) { - GE_FUNC_EXIT(sc, ""); - return intrmask; - } - - while (txq->txq_nactive > 0) { - if ( gfe_free_slots(sc, txq) < 0 ) - return intrmask; - ifp->if_timer = 5; - } - if (txq->txq_nactive != 0) - panic("%s: transmit fifo%d empty but active count (%d) not 0!", - sc->sc_dev.dv_xname, txprio, txq->txq_nactive); - ifp->if_timer = 0; - intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); - intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); - GE_FUNC_EXIT(sc, ""); - return intrmask; -} - -int -gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) -{ - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - int error; - - GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); - - error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, - GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); - if (error) { - GE_FUNC_EXIT(sc, ""); - return error; - } -#ifndef __rtems__ - error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); - if (error) { - gfe_dmamem_free(sc, &txq->txq_desc_mem); - GE_FUNC_EXIT(sc, ""); - return error; - } -#endif - GE_FUNC_EXIT(sc, ""); - return 0; -} - -int -gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) -{ - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - volatile struct gt_eth_desc *txd; - unsigned int i; - bus_addr_t addr; - - GE_FUNC_ENTER(sc, "gfe_tx_start"); - - sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| - ETH_IR_TxEndLow |ETH_IR_TxBufferLow); - - if (sc->sc_flags & GE_NOFREE) { - KASSERT(txq->txq_desc_mem.gdm_kva != NULL); -#ifndef __rtems__ - KASSERT(txq->txq_buf_mem.gdm_kva != NULL); -#endif - } else { - int error = gfe_tx_txqalloc(sc, txprio); - if (error) { - GE_FUNC_EXIT(sc, "!"); - return error; - } - } - - txq->txq_descs = - (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; - txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; -#ifndef __rtems__ - txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; -#else - /* never used */ - memset(&txq->txq_pendq,0,sizeof(txq->txq_pendq)); - memset(&txq->txq_sentq,0,sizeof(txq->txq_sentq)); - txq->txq_sentq.ifq_maxlen = 100000; -#endif - - txq->txq_pendq.ifq_maxlen = 10; -#ifndef __rtems__ - txq->txq_ei_gapcount = 0; -#endif - txq->txq_nactive = 0; - txq->txq_fi = 0; - txq->txq_lo = 0; -#ifndef __rtems__ - txq->txq_ei_gapcount = 0; - txq->txq_inptr = GE_TXBUF_SIZE; - txq->txq_outptr = 0; -#endif - for (i = 0, txd = txq->txq_descs, - addr = txq->txq_desc_busaddr + sizeof(*txd); - i < GE_TXDESC_MAX - 1; - i++, txd++, addr += sizeof(*txd)) { - /* - * update the nxtptr to point to the next txd. - */ - txd->ed_cmdsts = 0; - txd->ed_nxtptr = htogt32(addr); - } - txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = - htogt32(txq->txq_desc_busaddr); - bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, - GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - - switch (txprio) { - case GE_TXPRIO_HI: - txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; - txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; - txq->txq_epsrbits = ETH_EPSR_TxHigh; - txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); - GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); - break; - - case GE_TXPRIO_LO: - txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; - txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; - txq->txq_epsrbits = ETH_EPSR_TxLow; - txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); - GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); - break; - - case GE_TXPRIO_NONE: - break; - } -#if 0 - GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); - gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); - GE_DPRINTF(sc, (")")); -#endif - - /* - * If we are restarting, there may be packets in the pending queue - * waiting to be enqueued. Try enqueuing packets from both priority - * queues until the pending queue is empty or there no room for them - * on the device. - */ - while (gfe_tx_enqueue(sc, txprio)) - continue; - - GE_FUNC_EXIT(sc, ""); - return 0; -} - -void -gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) -{ - struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; - - GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); - if (txq == NULL) { - GE_FUNC_EXIT(sc, ""); - return; - } - - if (!flush) { - GE_FUNC_EXIT(sc, ""); - return; - } - -#ifdef __rtems__ - /* reclaim mbufs that were never sent */ - { - struct mbuf *m; - while ( txq->txq_sentq.ifq_head ) { - IF_DEQUEUE(&txq->txq_sentq, m); - m_freem(m); - } - } -#endif - - if ((sc->sc_flags & GE_NOFREE) == 0) { - gfe_dmamem_free(sc, &txq->txq_desc_mem); -#ifndef __rtems__ - gfe_dmamem_free(sc, &txq->txq_buf_mem); -#endif - } - GE_FUNC_EXIT(sc, "-F"); -} - -void -gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) -{ - GE_FUNC_ENTER(sc, "gfe_tx_stop"); - - GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); - - sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); - sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); - sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| - ETH_IR_TxEndLow |ETH_IR_TxBufferLow); - - gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); - gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); - - sc->sc_ec.ec_if.if_timer = 0; - GE_FUNC_EXIT(sc, ""); -} - -int -gfe_intr(void *arg) -{ - struct gfe_softc * const sc = arg; - uint32_t cause; - uint32_t intrmask = sc->sc_intrmask; - int claim = 0; - int cnt; - - GE_FUNC_ENTER(sc, "gfe_intr"); - - for (cnt = 0; cnt < 4; cnt++) { - if (sc->sc_intrmask != intrmask) { - sc->sc_intrmask = intrmask; - GE_WRITE(sc, EIMR, sc->sc_intrmask); - } - cause = GE_READ(sc, EICR); - cause &= sc->sc_intrmask; - GE_DPRINTF(sc, (".%#" PRIx32, cause)); - if (cause == 0) - break; - - claim = 1; - - GE_WRITE(sc, EICR, ~cause); -#ifndef GE_NORX - if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) - intrmask = gfe_rx_process(sc, cause, intrmask); -#endif - -#ifndef GE_NOTX - if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) - intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); - if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) - intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); -#endif - if (cause & ETH_IR_MIIPhySTC) { - sc->sc_flags |= GE_PHYSTSCHG; - /* intrmask &= ~ETH_IR_MIIPhySTC; */ - } - } - - while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) - continue; - while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) - continue; - - GE_FUNC_EXIT(sc, ""); - return claim; -} - -#ifndef __rtems__ -int -gfe_mii_mediachange (struct ifnet *ifp) -{ - struct gfe_softc *sc = ifp->if_softc; - - if (ifp->if_flags & IFF_UP) - mii_mediachg(&sc->sc_mii); - - return (0); -} -void -gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) -{ - struct gfe_softc *sc = ifp->if_softc; - - if (sc->sc_flags & GE_PHYSTSCHG) { - sc->sc_flags &= ~GE_PHYSTSCHG; - mii_pollstat(&sc->sc_mii); - } - ifmr->ifm_status = sc->sc_mii.mii_media_status; - ifmr->ifm_active = sc->sc_mii.mii_media_active; -} - -int -gfe_mii_read (struct device *self, int phy, int reg) -{ - return gt_mii_read(self, self->dv_parent, phy, reg); -} - -void -gfe_mii_write (struct device *self, int phy, int reg, int value) -{ - gt_mii_write(self, self->dv_parent, phy, reg, value); -} - -void -gfe_mii_statchg (struct device *self) -{ - /* struct gfe_softc *sc = (struct gfe_softc *) self; */ - /* do nothing? */ -} - -#else -int -gfe_mii_read(int phy, void *arg, unsigned reg, uint32_t *pval) -{ - struct gfe_softc *sc = arg; - uint32_t data; - int count = 10000; - - if ( 0 != phy ) - return -1; /* invalid index */ - - phy = sc->sc_phyaddr; - - do { - DELAY(10); - data = GT_READ(sc, ETH_ESMIR); - } while ((data & ETH_ESMIR_Busy) && count-- > 0); - - if (count == 0) { - fprintf(stderr,"%s: mii read for phy %d reg %d busied out\n", - sc->sc_dev.dv_xname, phy, reg); - *pval = ETH_ESMIR_Value_GET(data); - return -1; - } - - GT_WRITE(sc, ETH_ESMIR, ETH_ESMIR_READ(phy, reg)); - - count = 10000; - do { - DELAY(10); - data = GT_READ(sc, ETH_ESMIR); - } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); - - if (count == 0) - printf("%s: mii read for phy %d reg %d timed out\n", - sc->sc_dev.dv_xname, phy, reg); -#if defined(GTMIIDEBUG) - printf("%s: mii_read(%d, %d): %#x data %#x\n", - sc->sc_dev.dv_xname, phy, reg, - data, ETH_ESMIR_Value_GET(data)); -#endif - *pval = ETH_ESMIR_Value_GET(data); - return 0; -} - -int -gfe_mii_write(int phy, void *arg, unsigned reg, uint32_t value) -{ - struct gfe_softc *sc = arg; - uint32_t data; - int count = 10000; - - if ( 0 != phy ) - return -1; /* invalid index */ - - phy = sc->sc_phyaddr; - - do { - DELAY(10); - data = GT_READ(sc, ETH_ESMIR); - } while ((data & ETH_ESMIR_Busy) && count-- > 0); - - if (count == 0) { - fprintf(stderr, "%s: mii write for phy %d reg %d busied out (busy)\n", - sc->sc_dev.dv_xname, phy, reg); - return -1; - } - - GT_WRITE(sc, ETH_ESMIR, - ETH_ESMIR_WRITE(phy, reg, value)); - - count = 10000; - do { - DELAY(10); - data = GT_READ(sc, ETH_ESMIR); - } while ((data & ETH_ESMIR_Busy) && count-- > 0); - - if (count == 0) - printf("%s: mii write for phy %d reg %d timed out\n", - sc->sc_dev.dv_xname, phy, reg); -#if defined(GTMIIDEBUG) - printf("%s: mii_write(%d, %d, %#x)\n", - sc->sc_dev.dv_xname, phy, reg, value); -#endif - return 0; -} - -#endif -int -gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) -{ - int error = 0; - GE_FUNC_ENTER(sc, "gfe_whack"); - - switch (op) { - case GE_WHACK_RESTART: -#ifndef GE_NOTX - gfe_tx_stop(sc, op); -#endif - /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ - /* FALLTHROUGH */ - case GE_WHACK_START: -#ifndef GE_NOHASH - if (error == 0 && sc->sc_hashtable == NULL) { - error = gfe_hash_alloc(sc); - if (error) - break; - } - if (op != GE_WHACK_RESTART) - gfe_hash_fill(sc); -#endif -#ifndef GE_NORX - if (op != GE_WHACK_RESTART) { - error = gfe_rx_prime(sc); - if (error) - break; - } -#endif -#ifndef GE_NOTX - error = gfe_tx_start(sc, GE_TXPRIO_HI); - if (error) - break; -#endif - sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; - GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); - GE_WRITE(sc, EPCXR, sc->sc_pcxr); - GE_WRITE(sc, EICR, 0); - GE_WRITE(sc, EIMR, sc->sc_intrmask); -#ifndef GE_NOHASH - GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); -#endif -#ifndef GE_NORX - GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); - sc->sc_flags |= GE_RXACTIVE; -#endif - /* FALLTHROUGH */ - case GE_WHACK_CHANGE: - GE_DPRINTF(sc, ("(pcr=%#" PRIx32 ",imr=%#" PRIx32 ")", - GE_READ(sc, EPCR), GE_READ(sc, EIMR))); - GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); - GE_WRITE(sc, EIMR, sc->sc_intrmask); - gfe_ifstart(&sc->sc_ec.ec_if); - GE_DPRINTF(sc, ("(ectdp0=%#" PRIx32 ", ectdp1=%#" PRIx32 ")", - GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); - GE_FUNC_EXIT(sc, ""); - return error; - case GE_WHACK_STOP: - break; - } - -#ifdef GE_DEBUG - if (error) - GE_DPRINTF(sc, (" failed: %d\n", error)); -#endif - GE_WRITE(sc, EPCR, sc->sc_pcr); - GE_WRITE(sc, EIMR, 0); - sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; -#ifndef GE_NOTX - gfe_tx_stop(sc, GE_WHACK_STOP); -#endif -#ifndef GE_NORX - gfe_rx_stop(sc, GE_WHACK_STOP); -#endif -#ifndef GE_NOHASH - if ((sc->sc_flags & GE_NOFREE) == 0) { - gfe_dmamem_free(sc, &sc->sc_hash_mem); - sc->sc_hashtable = NULL; - } -#endif - - GE_FUNC_EXIT(sc, ""); - return error; -} - -int -gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) -{ - uint32_t w0, add0, add1; - uint32_t result; -#ifdef __rtems__ - SPRINTFVARDECL; -#endif - - GE_FUNC_ENTER(sc, "gfe_hash_compute"); - add0 = ((uint32_t) eaddr[5] << 0) | - ((uint32_t) eaddr[4] << 8) | - ((uint32_t) eaddr[3] << 16); - - add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); - add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); - add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); - - add1 = ((uint32_t) eaddr[2] << 0) | - ((uint32_t) eaddr[1] << 8) | - ((uint32_t) eaddr[0] << 16); - - add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); - add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); - add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); - - GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); - /* - * hashResult is the 15 bits Hash entry address. - * ethernetADD is a 48 bit number, which is derived from the Ethernet - * MAC address, by nibble swapping in every byte (i.e MAC address - * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). - */ - - if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { - /* - * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) - * - * hashFunc0 calculates the hashResult in the following manner: - * hashResult[ 8:0] = ethernetADD[14:8,1,0] - * XOR ethernetADD[23:15] XOR ethernetADD[32:24] - */ - result = (add0 & 3) | ((add0 >> 6) & ~3); - result ^= (add0 >> 15) ^ (add1 >> 0); - result &= 0x1ff; - /* - * hashResult[14:9] = ethernetADD[7:2] - */ - result |= (add0 & ~3) << 7; /* excess bits will be masked */ - GE_DPRINTF(sc, ("0(%#"PRIx32")", result & 0x7fff)); - } else { -#define TRIBITFLIP 073516240 /* yes its in octal */ - /* - * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) - * - * hashFunc1 calculates the hashResult in the following manner: - * hashResult[08:00] = ethernetADD[06:14] - * XOR ethernetADD[15:23] XOR ethernetADD[24:32] - */ - w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; - /* - * Now bitswap those 9 bits - */ - result = 0; - result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; - result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; - result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; - - /* - * hashResult[14:09] = ethernetADD[00:05] - */ - result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; - result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; - GE_DPRINTF(sc, ("1(%#"PRIx32")", result)); - } - GE_FUNC_EXIT(sc, ""); - return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); -} - -int -gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, - enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) -{ - uint64_t he; - uint64_t *maybe_he_p = NULL; - int limit; - int hash; -#ifndef __rtems__ - int maybe_hash = 0; -#endif /* __rtems__ */ - - GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); - - hash = gfe_hash_compute(sc, eaddr); - - if (sc->sc_hashtable == NULL) { - panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, - __LINE__); - } - - /* - * Assume we are going to insert so create the hash entry we - * are going to insert. We also use it to match entries we - * will be removing. - */ - he = ((uint64_t) eaddr[5] << 43) | - ((uint64_t) eaddr[4] << 35) | - ((uint64_t) eaddr[3] << 27) | - ((uint64_t) eaddr[2] << 19) | - ((uint64_t) eaddr[1] << 11) | - ((uint64_t) eaddr[0] << 3) | - HSH_PRIO_INS(prio) | HSH_V | HSH_R; - - /* - * The GT will search upto 12 entries for a hit, so we must mimic that. - */ - hash &= sc->sc_hashmask / sizeof(he); - for (limit = HSH_LIMIT; limit > 0 ; --limit) { - /* - * Does the GT wrap at the end, stop at the, or overrun the - * end? Assume it wraps for now. Stash a copy of the - * current hash entry. - */ - uint64_t *he_p = &sc->sc_hashtable[hash]; - uint64_t thishe = *he_p; - - /* - * If the hash entry isn't valid, that break the chain. And - * this entry a good candidate for reuse. - */ - if ((thishe & HSH_V) == 0) { - maybe_he_p = he_p; - break; - } - - /* - * If the hash entry has the same address we are looking for - * then ... if we are removing and the skip bit is set, its - * already been removed. if are adding and the skip bit is - * clear, then its already added. In either return EBUSY - * indicating the op has already been done. Otherwise flip - * the skip bit and return 0. - */ - if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { - if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || - ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) - return EBUSY; - *he_p = thishe ^ HSH_S; - bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, - hash * sizeof(he), sizeof(he), - BUS_DMASYNC_PREWRITE); - GE_FUNC_EXIT(sc, "^"); - return 0; - } - - /* - * If we haven't found a slot for the entry and this entry - * is currently being skipped, return this entry. - */ - if (maybe_he_p == NULL && (thishe & HSH_S)) { - maybe_he_p = he_p; -#ifndef __rtems__ - maybe_hash = hash; -#endif /* __rtems__ */ - } - - hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); - } - - /* - * If we got here, then there was no entry to remove. - */ - if (op == GE_HASH_REMOVE) { - GE_FUNC_EXIT(sc, "?"); - return ENOENT; - } - - /* - * If we couldn't find a slot, return an error. - */ - if (maybe_he_p == NULL) { - GE_FUNC_EXIT(sc, "!"); - return ENOSPC; - } - - /* Update the entry. - */ - *maybe_he_p = he; - bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, - maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); - GE_FUNC_EXIT(sc, "+"); - return 0; -} - -#ifndef __rtems__ -int -gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) -{ - struct gfe_softc * const sc = ec->ec_if.if_softc; - int error; - enum gfe_hash_op op; - enum gfe_rxprio prio; -#ifdef __rtems__ - SPRINTFVARDECL; -#endif - - GE_FUNC_ENTER(sc, "hash_multichg"); - /* - * Is this a wildcard entry? If so and its being removed, recompute. - */ - if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { - if (cmd == SIOCDELMULTI) { - GE_FUNC_EXIT(sc, ""); - return ENETRESET; - } - - /* - * Switch in - */ - sc->sc_flags |= GE_ALLMULTI; - if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { - sc->sc_pcr |= ETH_EPCR_PM; - GE_WRITE(sc, EPCR, sc->sc_pcr); - GE_FUNC_EXIT(sc, ""); - return 0; - } - GE_FUNC_EXIT(sc, ""); - return ENETRESET; - } - - prio = GE_RXPRIO_MEDLO; - op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); - - if (sc->sc_hashtable == NULL) { - GE_FUNC_EXIT(sc, ""); - return 0; - } - - error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); - if (error == EBUSY) { - printf("%s: multichg: tried to %s %s again\n", - sc->sc_dev.dv_xname, - cmd == SIOCDELMULTI ? "remove" : "add", - ether_sprintf(enm->enm_addrlo)); - GE_FUNC_EXIT(sc, ""); - return 0; - } - - if (error == ENOENT) { - printf("%s: multichg: failed to remove %s: not in table\n", - sc->sc_dev.dv_xname, - ether_sprintf(enm->enm_addrlo)); - GE_FUNC_EXIT(sc, ""); - return 0; - } - - if (error == ENOSPC) { - printf("%s: multichg: failed to add %s: no space; regenerating table\n", - sc->sc_dev.dv_xname, - ether_sprintf(enm->enm_addrlo)); - GE_FUNC_EXIT(sc, ""); - return ENETRESET; - } - GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", - sc->sc_dev.dv_xname, - cmd == SIOCDELMULTI ? "remove" : "add", - ether_sprintf(enm->enm_addrlo))); - GE_FUNC_EXIT(sc, ""); - return 0; -} -#endif - -int -gfe_hash_fill(struct gfe_softc *sc) -{ - struct ether_multistep step; - struct ether_multi *enm; - int error; - - GE_FUNC_ENTER(sc, "gfe_hash_fill"); - -#ifndef __rtems__ - error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, - LLADDR(sc->sc_ec.ec_if.if_sadl)); -#else - error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, sc->sc_ec.ac_enaddr); -#endif - if (error) { - GE_FUNC_EXIT(sc, "!"); - return error; - } - - sc->sc_flags &= ~GE_ALLMULTI; - if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) - sc->sc_pcr &= ~ETH_EPCR_PM; - else - sc->sc_pcr |= ETH_EPCR_PM; - ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); - while (enm != NULL) { - if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { - sc->sc_flags |= GE_ALLMULTI; - sc->sc_pcr |= ETH_EPCR_PM; - } else { - error = gfe_hash_entry_op(sc, GE_HASH_ADD, - GE_RXPRIO_MEDLO, enm->enm_addrlo); - if (error == ENOSPC) - break; - } - ETHER_NEXT_MULTI(step, enm); - } - - GE_FUNC_EXIT(sc, ""); - return error; -} - -int -gfe_hash_alloc(struct gfe_softc *sc) -{ - int error; - GE_FUNC_ENTER(sc, "gfe_hash_alloc"); - sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; - error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, - BUS_DMA_NOCACHE); - if (error) { - printf("%s: failed to allocate %d bytes for hash table: %d\n", - sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); - GE_FUNC_EXIT(sc, ""); - return error; - } - sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; - memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); - bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, - 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); - GE_FUNC_EXIT(sc, ""); - return 0; -} diff --git a/bsps/powerpc/beatnik/net/if_gfe/if_gfe_rtems.c b/bsps/powerpc/beatnik/net/if_gfe/if_gfe_rtems.c deleted file mode 100644 index 9ed814eb28..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/if_gfe_rtems.c +++ /dev/null @@ -1,129 +0,0 @@ -/* Author: T. Straumann <strauman@slac.stanford.edu>; see ../../LICENSE */ -#include "rtemscompat_defs.h" -#include "../porting/rtemscompat.h" -#include "gtethreg.h" - -#include <bsp/early_enet_link_status.h> -#include <bsp/if_gfe_pub.h> -#include <bsp/irq.h> - -/* from if_gfe.c */ -#define GE_READ(sc, reg) \ - bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) -#define GE_WRITE(sc, reg, v) \ - bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) - -#define GT_READ(sc, reg) \ - bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, reg) -#define GT_WRITE(sc, reg, v) \ - bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, reg, (v)) - -#include "../porting/if_xxx_rtems.c" - -#include <bsp.h> -#include <libcpu/io.h> - -int -NET_EMBEMB(rtems_,NETDRIVER_PREFIX,_setup)( - int unit, - char *ea, - uint32_t base_addr) -{ -struct NET_SOFTC *sc; - - if ( !ea ) { - fprintf(stderr,"Station address argument missing\n"); - return 0; - } - - if ( !(sc=net_drv_check_unit(unit)) ) { - fprintf(stderr,"Bad unit number -- (not enought driver slots?)\n"); - return 0; - } - - unit--; - -#ifdef DEBUG_MODULAR - if ( !METHODSPTR ) { - fprintf(stderr,"Methods not set -- module not loaded?\n"); - return 0; - } -#endif - - if ( !base_addr ) { -#ifdef BSP_MV64x60_BASE - base_addr = BSP_MV64x60_BASE; -#else - fprintf(stderr,"Missing GT64260 base address\n"); - return 0; -#endif - } - sc->sc_gt_memh = base_addr; - /* must set this as well to indicate that the device is set up */ - sc->NET_SOFTC_BHANDLE_FIELD = base_addr + 0x2400 + (unit<<10); - sc->sc_macno = unit; - memcpy( sc->arpcom.ac_enaddr, ea, ETHER_ADDR_LEN); - - if ( 0 == METHODSPTR->n_probe(&THEDEVS[unit]) ) { - printf(NETDRIVER": Unit %i set up\n", unit + 1); - sc->irq_no = BSP_IRQ_ETH0 + unit; - return 1; - } - return 0; -} - -static int -gfe_early_init(int idx) -{ -struct gfe_softc *sc; -uint32_t d; - - if ( idx < 0 || idx >= NETDRIVER_SLOTS ) - return -1; - - sc = device_get_softc(&the_gfe_devs[idx]); - d = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); - - sc->sc_phyaddr = ETH_EPAR_PhyAD_GET(d, sc->sc_macno); - sc->sc_dev.dv_xname = NETDRIVER; - return 0; -} - -static int -gfe_early_read_phy(int idx, unsigned reg) -{ -uint32_t rval; -struct gfe_softc *sc; - - if ( idx < 0 || idx >= NETDRIVER_SLOTS ) - return -1; - - sc = device_get_softc(&the_gfe_devs[idx]); - - if ( gfe_mii_read( 0, sc, reg, &rval) ) - return -1; - return rval & 0xffff; -} - - -static int -gfe_early_write_phy(int idx, unsigned reg, unsigned val) -{ -struct gfe_softc *sc; - - if ( idx < 0 || idx >= NETDRIVER_SLOTS ) - return -1; - - sc = device_get_softc(&the_gfe_devs[idx]); - - return gfe_mii_write( 0, sc, reg, val); -} - -rtems_bsdnet_early_link_check_ops -rtems_gfe_early_link_check_ops = { - init: gfe_early_init, - read_phy: gfe_early_read_phy, - write_phy: gfe_early_write_phy, - name: NETDRIVER, - num_slots: NETDRIVER_SLOTS -}; diff --git a/bsps/powerpc/beatnik/net/if_gfe/if_gfevar.h b/bsps/powerpc/beatnik/net/if_gfe/if_gfevar.h deleted file mode 100644 index cbb9609cf8..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/if_gfevar.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef IF_GFEVAR_H -#define IF_GFEVAR_H -/* $NetBSD: if_gfevar.h,v 1.4.10.1 2005/04/29 11:28:56 kent Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* NOTE: GE_RXDESC_MAX * 16 <= GE_RXDESC_MEMSIZE */ -/* NOTE: the driver needs 4*GE_RXDESC_MAX mbuf clusters (4 queues) */ -#ifndef __rtems__ -#define GE_RXDESC_MEMSIZE (1 * PAGE_SIZE) -#define GE_RXDESC_MAX 64 -#define GE_RXBUF_SIZE 2048 -#define GE_RXBUF_MEMSIZE (GE_RXDESC_MAX*GE_RXBUF_SIZE) -#else -#define GE_RXDESC_MEMSIZE (GE_RXDESC_MAX * sizeof(struct gt_eth_desc)) -#define GE_RXDESC_MAX (sc->num_rxdesc) -#define GE_RXBUF_MEMSIZE 0 -#endif - -#define GE_RXBUF_NSEGS ((GE_RXBUF_MEMSIZE/PAGE_SIZE)+1) -#define GE_DMSEG_MAX (GE_RXBUF_NSEGS) - -struct gfe_dmamem { - bus_dmamap_t gdm_map; /* dmamem'ed memory */ -#ifdef __rtems__ - void *gdm_unaligned_buf; -#endif - caddr_t gdm_kva; /* kva of tx memory */ - int gdm_nsegs; /* # of segment in gdm_segs */ - int gdm_maxsegs; /* maximum # of segments allowed */ - size_t gdm_size; /* size of memory region */ - bus_dma_segment_t gdm_segs[GE_DMSEG_MAX]; /* dma segment of tx memory */ -}; - -/* With a 4096 page size, we get 256 descriptors per page. - */ -#ifndef __rtems__ -#define GE_TXDESC_MEMSIZE (1 * PAGE_SIZE) -#define GE_TXDESC_MAX (GE_TXDESC_MEMSIZE / 16) -#define GE_TXBUF_SIZE (4 * PAGE_SIZE) -#else -#define GE_TXDESC_MEMSIZE (sc->num_txdesc * sizeof(struct gt_eth_desc)) -#define GE_TXDESC_MAX (sc->num_txdesc) -#endif - -struct gfe_txqueue { - struct ifqueue txq_pendq; /* these are ready to go to the GT */ - struct ifqueue txq_sentq; - struct gfe_dmamem txq_desc_mem; /* transmit descriptor memory */ -#ifndef __rtems__ - struct gfe_dmamem txq_buf_mem; /* transmit buffer memory */ -#endif - unsigned int txq_lo; /* next to be given to GT */ - unsigned int txq_fi; /* next to be returned to CPU */ -#ifndef __rtems__ - unsigned int txq_ei_gapcount; /* counter until next EI */ -#endif - unsigned int txq_nactive; /* number of active descriptors */ -#ifndef __rtems__ - unsigned int txq_outptr; /* where to put next transmit packet */ - unsigned int txq_inptr; /* start of 1st queued tx packet */ -#endif - uint32_t txq_intrbits; /* bits to write to EIMR */ - uint32_t txq_esdcmrbits; /* bits to write to ESDCMR */ - uint32_t txq_epsrbits; /* bits to test with EPSR */ - volatile struct gt_eth_desc *txq_descs; /* ptr to tx descriptors */ - bus_addr_t txq_ectdp; /* offset to cur. tx desc ptr reg */ - bus_addr_t txq_desc_busaddr; /* bus addr of tx descriptors */ -#ifndef __rtems__ - bus_addr_t txq_buf_busaddr; /* bus addr of tx buffers */ -#endif -}; - -/* With a 4096 page size, we get 256 descriptors per page. We want 1024 - * which will give us about 8ms of 64 byte packets (2ms for each priority - * queue). - */ - -#ifndef __rtems__ -struct gfe_rxbuf { - uint8_t rb_data[GE_RXBUF_SIZE]; -}; -#endif - -struct gfe_rxqueue { - struct gfe_dmamem rxq_desc_mem; /* receive descriptor memory */ -#ifndef __rtems__ - struct gfe_dmamem rxq_buf_mem; /* receive buffer memory */ - struct mbuf *rxq_curpkt; /* mbuf for current packet */ -#endif - volatile struct gt_eth_desc *rxq_descs; -#ifndef __rtems__ - struct gfe_rxbuf *rxq_bufs; -#else - struct mbuf **rxq_bufs; -#endif - unsigned int rxq_fi; /* next to be returned to CPU */ - unsigned int rxq_active; /* # of descriptors given to GT */ - uint32_t rxq_intrbits; /* bits to write to EIMR */ - bus_addr_t rxq_desc_busaddr; /* bus addr of rx descriptors */ - uint32_t rxq_cmdsts; /* save cmdsts from first descriptor */ - bus_size_t rxq_efrdp; - bus_size_t rxq_ecrdp; -}; - -enum gfe_txprio { - GE_TXPRIO_HI=1, - GE_TXPRIO_LO=0, - GE_TXPRIO_NONE=2 -}; -enum gfe_rxprio { - GE_RXPRIO_HI=3, - GE_RXPRIO_MEDHI=2, - GE_RXPRIO_MEDLO=1, - GE_RXPRIO_LO=0 -}; - -#ifdef __rtems__ -#define sc_ec arpcom -#define ec_if ac_if -#define sc_dev arpcom -#define dv_xname ac_if.if_name -#endif - -struct gfe_softc { -#ifndef __rtems__ - struct device sc_dev; /* must be first */ - struct ethercom sc_ec; /* common ethernet glue */ - struct callout sc_co; /* resource recovery */ - mii_data_t sc_mii; /* mii interface */ - - /* - * - */ - bus_space_tag_t sc_gt_memt; - bus_space_handle_t sc_gt_memh; - bus_space_handle_t sc_memh; /* subregion for ethernet */ - bus_dma_tag_t sc_dmat; -#else - struct arpcom sc_ec; - unsigned sc_gt_memh; - unsigned sc_memh; - unsigned char irq_no; - rtems_id tid; - int sc_phyaddr; - int num_rxdesc, num_txdesc; -#endif - int sc_macno; /* which mac? 0, 1, or 2 */ - - unsigned int sc_tickflags; -#define GE_TICK_TX_IFSTART 0x0001 -#define GE_TICK_RX_RESTART 0x0002 - unsigned int sc_flags; -#define GE_ALLMULTI 0x0001 -#define GE_PHYSTSCHG 0x0002 -#define GE_RXACTIVE 0x0004 -#define GE_NOFREE 0x0008 /* Don't free on disable */ - uint32_t sc_pcr; /* current EPCR value */ - uint32_t sc_pcxr; /* current EPCXR value */ - uint32_t sc_intrmask; /* current EIMR value */ - uint32_t sc_idlemask; /* suspended EIMR bits */ - size_t sc_max_frame_length; /* maximum frame length */ - - /* - * Hash table related members - */ - struct gfe_dmamem sc_hash_mem; /* dma'ble hash table */ - uint64_t *sc_hashtable; - unsigned int sc_hashmask; /* 0x1ff or 0x1fff */ - - /* - * Transmit related members - */ - struct gfe_txqueue sc_txq[2]; /* High & Low transmit queues */ - - /* - * Receive related members - */ - struct gfe_rxqueue sc_rxq[4]; /* Hi/MedHi/MedLo/Lo receive queues */ -}; - -#ifdef __rtems__ -int -gfe_mii_read(int phy, void *arg, unsigned reg, uint32_t *pval); - -int -gfe_mii_write(int phy, void *arg, unsigned reg, uint32_t value); -#endif - -#endif diff --git a/bsps/powerpc/beatnik/net/if_gfe/rtemscompat_defs.h b/bsps/powerpc/beatnik/net/if_gfe/rtemscompat_defs.h deleted file mode 100644 index 971b1d3cca..0000000000 --- a/bsps/powerpc/beatnik/net/if_gfe/rtemscompat_defs.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef RTEMS_COMPAT_DEFS_H -#define RTEMS_COMPAT_DEFS_H - -#include <stdint.h> -#include <stddef.h> - -/* Number of device instances the driver should support - * - may be limited to 1 depending on IRQ API - * (braindamaged PC586 and powerpc) - */ -#define NETDRIVER_SLOTS 1 -/* String name to print with error messages */ -#define NETDRIVER "gfe" -/* Name snippet used to make global symbols unique to this driver */ -#define NETDRIVER_PREFIX gfe - -/* Define according to endianness of the *ethernet*chip* - * (not the CPU - most probably are LE) - * This must be either NET_CHIP_LE or NET_CHIP_BE - */ - -#define NET_CHIP_LE -#undef NET_CHIP_BE - -/* Define either NET_CHIP_MEM_IO or NET_CHIP_PORT_IO, - * depending whether the CPU sees it in memory address space - * or (e.g. x86) uses special I/O instructions. - */ -#define NET_CHIP_MEM_IO -#undef NET_CHIP_PORT_IO - -/* The name of the hijacked 'bus handle' field in the softc - * structure. We use this field to store the chip's base address. - */ -#define NET_SOFTC_BHANDLE_FIELD sc_memh - -/* define the names of the 'if_XXXreg.h' and 'if_XXXvar.h' headers - * (only if present, i.e., if the BSDNET driver has no respective - * header, leave this undefined). - * - */ -#undef IF_REG_HEADER -#define IF_VAR_HEADER "../if_gfe/if_gfevar.h" - -/* define if a pci device */ -/* -#define NETDRIVER_PCI <bsp/pci.h> -*/ -#undef NETDRIVER_PCI - -/* Macros to disable and enable interrupts, respectively. - * The 'disable' macro is expanded in the ISR, the 'enable' - * macro is expanded in the driver task. - * The global network semaphore usually provides mutex - * protection of the device registers. - * Special care must be taken when coding the 'disable' macro, - * however to MAKE SURE THERE ARE NO OTHER SIDE EFFECTS such - * as: - * - macro must not clear any status flags - * - macro must save/restore any context information - * (e.g., a address register pointer or a bank switch register) - * - * ARGUMENT: the macro arg is a pointer to the driver's 'softc' structure - */ - -#define NET_DISABLE_IRQS(sc) GE_WRITE(sc, EIMR, 0) -#define NET_ENABLE_IRQS(sc) GE_WRITE(sc, EIMR, sc->sc_intrmask) - -/* Driver may provide a macro/function to copy the hardware address - * from the device into 'softc.arpcom'. - * If this is undefined, the driver must to the copy itself. - * Preferrably, it should check soft.arpcom.ac_enaddr for all - * zeros and leave it alone if it is nonzero, i.e., write it - * to the hardware. -#define NET_READ_MAC_ADDR(sc) - */ - -typedef struct { - uint32_t ds_addr; - uint32_t ds_len; -} bus_dma_segment_t; - -#define dm_segs gdm_segs -#define dm_nsegs gdm_nsegs -typedef struct gfe_dmamem *bus_dmamap_t; - -typedef uint32_t bus_addr_t; -typedef uint32_t bus_size_t; - -typedef struct device blah; - -#define BUS_DMA_NOCACHE 0xdeadbeef - -#ifdef __PPC__ -#define bus_dmamap_sync(args...) do { __asm__ volatile("sync":::"memory"); } while(0) -#else -#error "Dont' know how to sync memory on your CPU" -#endif - -int ether_sprintf_r(const unsigned char *enaddr, char *buf, int len); - -/* we have it although we're not ansi */ -int snprintf(char *, size_t, const char *,...); - -#include <string.h> - -/* declare in every routine using ether_sprintf */ -#define SPRINTFVARDECL char rtems_sprintf_local_buf[3*6] /* ethernet string */ - -#define ether_sprintf_macro(a) \ - (snprintf(rtems_sprintf_local_buf, \ - sizeof(rtems_sprintf_local_buf), \ - "%02X:%02X:%02X:%02X:%02X:%02X", \ - a[0],a[1],a[2],a[3],a[4],a[5]) ? \ - rtems_sprintf_local_buf : 0 \ - ) - - -#define aprint_normal(args...) printf(args) -#define aprint_error(args...) fprintf(stderr,args) - -#define delay(arg) DELAY(arg) - -#define KASSERT(a...) do {} while (0) - -#define gfe_assign_desc _bsd_gfe_assign_desc -#define gfe_attach _bsd_gfe_attach -#define gfe_dbg_config _bsd_gfe_dbg_config -#define gfe_dmamem_alloc _bsd_gfe_dmamem_alloc -#define gfe_dmamem_free _bsd_gfe_dmamem_free -#define gfe_hash_alloc _bsd_gfe_hash_alloc -#define gfe_hash_compute _bsd_gfe_hash_compute -#define gfe_hash_entry_op _bsd_gfe_hash_entry_op -#define gfe_hash_fill _bsd_gfe_hash_fill -#define gfe_ifioctl _bsd_gfe_ifioctl -#define gfe_ifstart _bsd_gfe_ifstart -#define gfe_ifwatchdog _bsd_gfe_ifwatchdog -#define gfe_init _bsd_gfe_init -#define gfe_intr _bsd_gfe_intr -#define gfe_mdio_access _bsd_gfe_mdio_access -#define gfe_mii_read _bsd_gfe_mii_read -#define gfe_mii_write _bsd_gfe_mii_write -#define gfe_probe _bsd_gfe_probe -#define gfe_rx_cleanup _bsd_gfe_rx_cleanup -#define gfe_rx_get _bsd_gfe_rx_get -#define gfe_rx_prime _bsd_gfe_rx_prime -#define gfe_rx_process _bsd_gfe_rx_process -#define gfe_rx_rxqalloc _bsd_gfe_rx_rxqalloc -#define gfe_rx_rxqinit _bsd_gfe_rx_rxqinit -#define gfe_rx_stop _bsd_gfe_rx_stop -#define gfe_tick _bsd_gfe_tick -#define gfe_tx_cleanup _bsd_gfe_tx_cleanup -#define gfe_tx_done _bsd_gfe_tx_done -#define gfe_tx_enqueue _bsd_gfe_tx_enqueue -#define gfe_tx_start _bsd_gfe_tx_start -#define gfe_tx_stop _bsd_gfe_tx_stop -#define gfe_tx_txqalloc _bsd_gfe_tx_txqalloc -#define gfe_whack _bsd_gfe_whack -#define the_gfe_devs _bsd_the_gfe_devs - -#endif |