diff options
Diffstat (limited to 'bsps/mips/malta')
| -rw-r--r-- | bsps/mips/malta/headers.am | 11 | ||||
| -rw-r--r-- | bsps/mips/malta/include/bsp.h | 113 | ||||
| -rw-r--r-- | bsps/mips/malta/include/bsp/irq.h | 131 | ||||
| -rw-r--r-- | bsps/mips/malta/include/bsp/pci.h | 139 | ||||
| -rw-r--r-- | bsps/mips/malta/include/tm27.h | 1 |
5 files changed, 395 insertions, 0 deletions
diff --git a/bsps/mips/malta/headers.am b/bsps/mips/malta/headers.am new file mode 100644 index 0000000000..35d8bb70d0 --- /dev/null +++ b/bsps/mips/malta/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/mips/malta/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/mips/malta/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/mips/malta/include/bsp/pci.h diff --git a/bsps/mips/malta/include/bsp.h b/bsps/mips/malta/include/bsp.h new file mode 100644 index 0000000000..c1169cd0a4 --- /dev/null +++ b/bsps/mips/malta/include/bsp.h @@ -0,0 +1,113 @@ +/** + * @file + * + * This include file contains some definitions specific to the + * MIPS Malta Board. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_MALTA_BSP_H +#define LIBBSP_MIPS_MALTA_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#define REVISION_REGISTER_ADDRESS 0x1fc00010 +#define PRORV_MASK 0x0000000f /* 4 bit Product Revision */ +#define PROID_MASK 0x000000f0 /* 4 bit Product ID */ +#define CORRV_MASK 0x00000300 /* 2 bit Core Board Revision */ +#define CORID_MASK 0x0000fc00 /* 6 bit Core Board ID */ +#define FPGRV_MASK 0x00ff0000 /* 8 bit CBUS FPGA Revision */ +#define BSP_8259_BASE_ADDRESS (0x18000000UL | 0xa0000000UL) +#define BSP_PCI_BASE_ADDRESS (0x1be00000UL | 0xa0000000UL) +#define BSP_NIC_IO_BASE (0x10000000UL | 0xa0000000UL) +#define PCI0_IO_BASE (0x18000000UL | 0xa0000000UL) +#define BSP_NIC_MEM_BASE (0x00000000UL | 0xa0000000UL) + +/* functions */ +#define WRITE_PROTECTED_UINT8( _addr, _value ) \ + do { \ + volatile uint8_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define WRITE_PROTECTED_UINT16( _addr, _value ) \ + do { \ + volatile uint16_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define WRITE_PROTECTED_UINT32( _addr, _value ) \ + do { \ + volatile uint32_t *_ptr = _addr | 0x80000000; \ + *_ptr = _value; \ + } +#define READ_PROTECTED_UINT8( _addr, _value ) \ + do { \ + volatile uint8_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } +#define READ_PROTECTED_UINT16( _addr, _value ) \ + do { \ + volatile uint16_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } +#define READ_PROTECTED_UINT32( _addr, _value ) \ + do { \ + volatile uint32_t *_ptr = _addr | 0x80000000; \ + _value = *_ptr; \ + } + +#define READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile unsigned char *)(_register_))) + +#define WRITE_UINT8( _register_, _value_ ) \ + (*((volatile unsigned char *)(_register_)) = (_value_)) + +#define READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile unsigned short *)(_register_))) + +#define WRITE_UINT16( _register_, _value_ ) \ + (*((volatile unsigned short *)(_register_)) = (_value_)) + +void simple_out_32(uint32_t base, uint32_t addr, uint32_t val); +void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val); +uint8_t simple_in_8( uint32_t base, uint32_t addr ); +void simple_out_8( uint32_t base, uint32_t addr, uint8_t val ); +int16_t simple_in_le16( uint32_t base, uint32_t addr ); +int16_t simple_in_16( uint32_t base, uint32_t addr ); +uint32_t simple_in_le32( uint32_t base, uint32_t addr ); +uint32_t simple_in_32( uint32_t base, uint32_t addr ); +void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val ); +void simple_out_16( uint32_t base, uint32_t addr, uint16_t val ); + +/* + * Prototypes for methods called from .S for dependency tracking + */ +void init_tlb(void); +void resettlb(int i); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/mips/malta/include/bsp/irq.h b/bsps/mips/malta/include/bsp/irq.h new file mode 100644 index 0000000000..3ca6f964a9 --- /dev/null +++ b/bsps/mips/malta/include/bsp/irq.h @@ -0,0 +1,131 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Malta Interrupt Definitions + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MIPS_MALTA_IRQ_H +#define LIBBSP_MIPS_MALTA_IRQ_H + +#ifndef ASM + #include <rtems.h> + #include <rtems/irq.h> + #include <rtems/irq-extension.h> + #include <rtems/score/mips.h> +#endif + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +/* + * Interrupt Vector Numbers + * + * NOTE: Numbers 0-15 directly map to levels on the IRC. + * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. + */ +#define MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 +#define MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 +#define MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 +#define MALTA_CPU_INT0 MALTA_CPU_INT_START+2 +#define MALTA_CPU_INT1 MALTA_CPU_INT_START+3 +#define MALTA_CPU_INT2 MALTA_CPU_INT_START+4 +#define MALTA_CPU_INT3 MALTA_CPU_INT_START+5 +#define MALTA_CPU_INT4 MALTA_CPU_INT_START+6 +#define MALTA_CPU_INT5 MALTA_CPU_INT_START+7 +#define MALTA_CPU_INT_LAST MALTA_CPU_INT5 + +#define MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 +#define MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 +#define MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 +#define MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 +#define MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 +#define MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 +#define MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 +#define MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 +#define MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 +#define MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 +#define MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 +#define MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 +#define MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 +#define MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 +#define MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 +#define MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 +#define MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 +#define MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 + +#define MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 +#define MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 +#define MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 +#define MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 +#define MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 +#define MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 +#define MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 +#define MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 +#define MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 +#define MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 +# + +#define BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST + +/* + * Redefine interrupts with more descriptive names. + * The Generic ones above match the hardware name, + * where these match the device name. + */ +#define MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 +#define MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 +#define MALTA_INT_TTY2 MALTA_CPU_INT2 +#define MALTA_INT_COREHI MALTA_CPU_INT3 +#define MALTA_INT_CORELO MALTA_CPU_INT4 +#define MALTA_INT_TICKER MALTA_CPU_INT5 + +#define MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 +#define MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 +#define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 +#define MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 +#define MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 +#define MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 +#define MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 +#define MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 +#define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 +#define MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 +/* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */ +#define MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 +/* PCI slot 1..4 (audio, USB) */ +#define MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 +#define MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 +#define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 +#define MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 +#define MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 +#define MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 +#define MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B +#define MALTA_IRQ_AUDIO MALTA_PCI_ADP22 +#define MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 +#define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 +#define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 +#define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 +#define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 + +#ifndef ASM + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_MIPS_MALTA_IRQ_H */ diff --git a/bsps/mips/malta/include/bsp/pci.h b/bsps/mips/malta/include/bsp/pci.h new file mode 100644 index 0000000000..c5944da548 --- /dev/null +++ b/bsps/mips/malta/include/bsp/pci.h @@ -0,0 +1,139 @@ +/** + * @file + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ + +#ifndef BSP_PCI_H +#define BSP_PCI_H + +#include <rtems/pci.h> +#include <bsp.h> +#include <stdio.h> + +struct _pin_routes +{ + int pin, int_name[4]; +}; +struct _int_map +{ + int bus, slot, opts; + struct _pin_routes pin_route[5]; +}; +struct pcibridge +{ + int bus; + int slot; +}; + +/* If there's a conflict between a name in the routing table and + * what's already set on the device, reprogram the device setting + * to reflect int_name[0] for the routing table entry + */ +#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) + +void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); + +/* FIXME: This probably belongs into rtems/pci.h */ +extern unsigned char pci_bus_count(); + +int indirect_pci_read_config_byte( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint8_t *val +); + +int indirect_pci_read_config_word( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint16_t *val +); + +int indirect_pci_read_config_dword( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint32_t *val +); + +int indirect_pci_write_config_byte( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint8_t val +); + +int indirect_pci_write_config_word( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint16_t val +); + +int indirect_pci_write_config_dword( + unsigned char bus, + unsigned char slot, + unsigned char function, + unsigned char offset, + uint32_t val +); + +/* Can these be moved to the rtems pci.h? */ +int FindPCIbridge( int mybus, struct pcibridge *pb ); + +const pci_config_access_functions pci_indirect_functions; + +void pci_out_le32( uint32_t base, uint32_t addr, uint32_t val); +void pci_out_32( uint32_t base, uint32_t addr, uint32_t val); +uint8_t pci_in_8 ( uint32_t base, uint32_t addr ); +int16_t pci_in_le16 ( uint32_t base, uint32_t addr ); +uint32_t pci_in_le32 ( uint32_t base, uint32_t addr ); +int16_t pci_in_16 ( uint32_t base, uint32_t addr ); +uint32_t pci_in_32 ( uint32_t base, uint32_t addr ); +void pci_out_8 ( uint32_t base, uint32_t addr, uint8_t val ); +void pci_out_le16( uint32_t base, uint32_t addr, uint16_t val ); +void pci_out_16( uint32_t base, uint32_t addr, uint16_t val ); +void pci_out_32 ( uint32_t base, uint32_t addr, uint32_t val); + +#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define out_le32(_addr, _val) pci_out_le32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) +#define in_8(_addr) pci_in_8( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_le16(_addr) pci_in_le16( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_le32(_addr) pci_in_le32( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_16(_addr) pci_in_16( BSP_PCI_BASE_ADDRESS, _addr ) +#define in_32(_addr) pci_in_32( BSP_PCI_BASE_ADDRESS, _addr ) +#define out_8(_addr,_val) pci_out_8( BSP_PCI_BASE_ADDRESS, _addr, _val ) +#define out_le16(_addr,_val) pci_out_le16( BSP_PCI_BASE_ADDRESS, _addr, _val ) +#define out_16(_addr,_val) pci_out_16( BSP_PCI_BASE_ADDRESS, _addr, _val ) + +#endif /* BSP_PCI_H */ diff --git a/bsps/mips/malta/include/tm27.h b/bsps/mips/malta/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/mips/malta/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> |