3 files changed, 157 insertions, 0 deletions
diff --git a/bsps/mips/jmr3904/include/bsp.h b/bsps/mips/jmr3904/include/bsp.h
new file mode 100644
index 0000000000..52696b3987
--- /dev/null
+++ b/bsps/mips/jmr3904/include/bsp.h
@@ -0,0 +1,37 @@
+/**
+ *  @file
+ *  
+ *  This include file contains some definitions specific to the
+ *  JMR3904 simulator in gdb.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_JMR3904_BSP_H
+#define LIBBSP_MIPS_JMR3904_BSP_H
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+#include <libcpu/tx3904.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsps/mips/jmr3904/include/bsp/irq.h b/bsps/mips/jmr3904/include/bsp/irq.h
new file mode 100644
index 0000000000..cdb50e244e
--- /dev/null
+++ b/bsps/mips/jmr3904/include/bsp/irq.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief jmr3904 interrupt definitions.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MIPS_JMR3904_IRQ_H
+#define LIBBSP_MIPS_JMR3904_IRQ_H
+
+#ifndef ASM
+  #include <rtems.h>
+  #include <rtems/irq.h>
+  #include <rtems/irq-extension.h>
+  #include <rtems/score/mips.h>
+#endif
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+/*
+ *  Interrupt Vector Numbers
+ *
+ *  NOTE: Numbers 0-15 directly map to levels on the IRC.
+ *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
+ */
+
+  #define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
+  #define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
+  #define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
+  #define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
+  #define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
+  #define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
+  #define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
+  #define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
+  #define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
+  #define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
+  #define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
+  #define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
+  #define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
+  #define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
+  #define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
+  #define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
+  #define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
+  #define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
+  #define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
+  #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
+
+#define BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS
+
+/** @} */
+
+#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */
diff --git a/bsps/mips/jmr3904/include/tm27.h b/bsps/mips/jmr3904/include/tm27.h
new file mode 100644
index 0000000000..f73ccdea40
--- /dev/null
+++ b/bsps/mips/jmr3904/include/tm27.h
@@ -0,0 +1,52 @@
+/**
+ *  @file
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+#include <bsp/irq.h>
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+   rtems_interrupt_handler_install( \
+      TX3904_IRQ_TMR0, "benchmark", 0, \
+      (rtems_interrupt_handler)handler, NULL );
+
+#define Cause_tm27_intr() \
+  do { \
+    uint32_t   _clicks = 20; \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
+    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
+  } while(0)
+
+#define Clear_tm27_intr() \
+  do { \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
+  } while(0)
+
+#define Lower_tm27_intr() \
+  mips_enable_in_interrupt_mask( 0xff01 );
+
+#endif