diff options
Diffstat (limited to 'bsps/microblaze')
36 files changed, 5358 insertions, 0 deletions
diff --git a/bsps/microblaze/include/bsp/linker-symbols.h b/bsps/microblaze/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..da162060b5 --- /dev/null +++ b/bsps/microblaze/include/bsp/linker-symbols.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2015 Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup microblaze Linker Support + * + * @ingroup microblaze_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/microblaze/include/bsp/microblaze-fdt-support.h b/bsps/microblaze/include/bsp/microblaze-fdt-support.h new file mode 100644 index 0000000000..d4430c5a3a --- /dev/null +++ b/bsps/microblaze/include/bsp/microblaze-fdt-support.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief This header file provides support for the device tree. + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H +#define LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/** + * @brief Get the value of a property from a compatible node in the device tree. + * + * @param[in] compatible The 'compatible' string to match against. + * @param[in] prop_name The property name. + * @param[in] default_value The default value to return if no compatible node + * was found or the property was not found. + * + * @return The value of the property or the default value. + */ +uint32_t try_get_prop_from_device_tree( + const char *compatible, + const char *prop_name, + uint32_t default_value +); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_MICROBLAZE_MICROBLAZE_FDT_SUPPORT_H */ diff --git a/bsps/microblaze/include/common/xil_types.h b/bsps/microblaze/include/common/xil_types.h new file mode 100644 index 0000000000..929e83f8f0 --- /dev/null +++ b/bsps/microblaze/include/common/xil_types.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values +* 7.00 mus 01/07/19 Add cpp extern macro +* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it +* is 64-bit processor +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <stddef.h> + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include <linux/types.h> +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#if defined (__aarch64__) || defined (__arch64__) +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) +#else +#define UPPER_32_BITS(n) 0U +#endif +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/
\ No newline at end of file diff --git a/bsps/microblaze/include/dev/serial/uartlite.h b/bsps/microblaze/include/dev/serial/uartlite.h new file mode 100644 index 0000000000..f58ae92ef8 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite terminal definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_SHARED_UARTLITE_H +#define LIBBSP_MICROBLAZE_SHARED_UARTLITE_H + +#include <bspopts.h> +#include <rtems/termiostypes.h> + +#include <dev/serial/uartlite_l.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + uintptr_t address; + uint32_t initial_baud; + uint32_t enabled; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + struct rtems_termios_tty *tty; + bool transmitting; + size_t tx_queued; + uint32_t irq; +#endif +} uart_lite_context; + +extern const rtems_termios_device_handler microblaze_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_SHARED_UARTLITE_H */ diff --git a/bsps/microblaze/include/dev/serial/uartlite_l.h b/bsps/microblaze/include/dev/serial/uartlite_l.h new file mode 100644 index 0000000000..834fbb5f75 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite_l.h @@ -0,0 +1,341 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* @addtogroup uartlite_v3_5 +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b rpm 04/25/02 First release +* 1.00b rpm 07/07/03 Removed references to XUartLite_GetControlReg macro +* since the control register is write-only +* 1.12a mta 03/21/07 Updated to new coding style +* 1.13a sv 01/21/08 Updated driver to support access through DCR bus +* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been +* renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. +* </pre> +* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#ifndef __rtems__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#else +#include <common/xil_types.h> +static inline u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} +static inline void Xil_Out32(UINTPTR Addr, u32 Value) +{ + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +} +#endif /* __rtems__ */ + +/* + * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is + * accessed through a DCR bus connected to a bridge. + */ +#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0 + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#include "xio_dcr.h" +#endif + + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */ + +#else + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */ + +#endif + +/* Control Register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* Status Register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* The following constant specifies the size of the Transmit/Receive FIFOs. + * The FIFO size is fixed to 16 in the Uartlite IP and the size is not + * configurable. This constant is not used in the driver. + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* + * Define the appropriate I/O access method to memory mapped I/O or DCR. + */ +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) + +#define XUartLite_In32 XIo_DcrIn +#define XUartLite_Out32 XIo_DcrOut + +#else + +#define XUartLite_In32 Xil_In32 +#define XUartLite_Out32 Xil_Out32 + +#endif + + +/****************************************************************************/ +/** +* +* Write a value to a UartLite register. A 32 bit write is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to write to. +* @param Data is the data written to the register. +* +* @return None. +* +* @note C-style signature: +* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +****************************************************************************/ +#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \ + XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/****************************************************************************/ +/** +* +* Read a value from a UartLite register. A 32 bit read is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to read from. +* +* @return Data read from the register. +* +* @note C-style signature: +* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset) +* +****************************************************************************/ +#define XUartLite_ReadReg(BaseAddress, RegOffset) \ + XUartLite_In32((BaseAddress) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask); +* +*****************************************************************************/ +#define XUartLite_SetControlReg(BaseAddress, Mask) \ + XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note C-style Signature: +* u32 XUartLite_GetStatusReg(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_GetStatusReg(BaseAddress) \ + XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the receiver is empty, FALSE if there is data present. +* +* @note C-style Signature: +* int XUartLite_IsReceiveEmpty(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsReceiveEmpty(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \ + XUL_SR_RX_FIFO_VALID_DATA) + +#ifdef __rtems__ +/****************************************************************************/ +/** +* +* Check to see if the transmitter is empty. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the transmitter is empty, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsTransmitEmpty(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsTransmitEmpty(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_EMPTY) == \ + XUL_SR_TX_FIFO_EMPTY) +#endif /* __rtems__ */ + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the transmitter is full, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsTransmitFull(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsTransmitFull(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \ + XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the interrupt is enabled, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsIntrEnabled(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsIntrEnabled(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \ + XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. We cannot read the control register, so we +* just write the enable interrupt bit and clear all others. Since the only +* other ones are the FIFO reset bits, this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_EnableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_EnableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. We cannot read the control register, so we +* just clear all bits. Since the only other ones are the FIFO reset bits, +* this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_DisableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_DisableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), 0) + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data); +u8 XUartLite_RecvByte(UINTPTR BaseAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + + +/** @} */ diff --git a/bsps/microblaze/microblaze_fpga/clock/clock.c b/bsps/microblaze/microblaze_fpga/clock/clock.c new file mode 100644 index 0000000000..16acbaeebb --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/clock/clock.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer clock support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/fatal.h> +#include <bsp/timer.h> + +#include <rtems.h> +#include <rtems/irq-extension.h> +#include <rtems/timecounter.h> + +static rtems_timecounter_simple mblaze_tc; +static volatile Microblaze_Timer *mblaze_timer; + +static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc ) +{ + return mblaze_timer->tcr0; +} + +static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc ) +{ + return ( mblaze_timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0; +} + +static uint32_t microblaze_tc_get_timecount( struct timecounter *tc ) +{ + return rtems_timecounter_simple_downcounter_get( + tc, + microblaze_tc_get, + microblaze_tc_is_pending + ); +} + +static void microblaze_clock_initialize( void ) +{ + mblaze_timer = (volatile Microblaze_Timer *) try_get_prop_from_device_tree( + "xlnx,xps-timer-1.00.a", + "reg", + BSP_MICROBLAZE_FPGA_TIMER_BASE + ); + + /* Set load register to 0 */ + mblaze_timer->tlr0 = 0; + /* Reset the timer and interrupt */ + mblaze_timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Release the reset */ + mblaze_timer->tcsr0 = 0; + /* + * Enable interrupt, auto reload mode, external interrupt signal, + * and down counter + */ + mblaze_timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 | + MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0; + + uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); + uint32_t counter_frequency_in_hz = try_get_prop_from_device_tree( + "xlnx,xps-timer-1.00.a", + "clock-frequency", + BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY + ); + uint32_t counter_ticks_per_clock_tick = + ( counter_frequency_in_hz * us_per_tick ) / 1000000; + + /* Set a reset value for the timer counter */ + mblaze_timer->tlr0 = counter_ticks_per_clock_tick; + uint32_t control_status_reg = mblaze_timer->tcsr0; + /* Load the reset value into the counter register */ + mblaze_timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Enable the timer */ + mblaze_timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0; + + rtems_timecounter_simple_install( + &mblaze_tc, + counter_frequency_in_hz, + counter_ticks_per_clock_tick, + microblaze_tc_get_timecount + ); +} + +static void microblaze_clock_at_tick( rtems_timecounter_simple *tc ) +{ + if ( ( mblaze_timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) { + return; + } + /* Clear the interrupt */ + mblaze_timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT; +} + +static void microblaze_tc_tick( rtems_timecounter_simple *tc ) +{ + rtems_timecounter_simple_downcounter_tick( + tc, + microblaze_tc_get, + microblaze_clock_at_tick + ); +} + +static void microblaze_clock_handler_install( rtems_interrupt_handler isr ) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + uint32_t clock_irq_num = try_get_prop_from_device_tree( + "xlnx,xps-timer-1.00.a", + "interrupts", + 0 + ); + + sc = rtems_interrupt_handler_install( + clock_irq_num, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + isr, + &mblaze_tc + ); + + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal( MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL ); + } +} + +#define Clock_driver_support_initialize_hardware() microblaze_clock_initialize() +#define Clock_driver_support_install_isr( isr ) \ + microblaze_clock_handler_install( isr ) +#define Clock_driver_timecounter_tick(arg) microblaze_tc_tick(arg) + +/* Include shared source clock driver code */ +#include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c b/bsps/microblaze/microblaze_fpga/console/console-io.c new file mode 100644 index 0000000000..a07c85642f --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/console-io.c @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze console configuration + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <unistd.h> +#include <string.h> +#include <stdio.h> + +#include <sys/param.h> +#include <bsp/console-termios.h> +#include <bsp/fatal.h> +#include <bspopts.h> +#include <dev/serial/uartlite.h> + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +#include <bsp/fdt.h> +#include <libfdt.h> +#endif + +#include <rtems/console.h> + +#ifndef BSP_MICROBLAZE_FPGA_USE_FDT +static uart_lite_context uart_lite_instances[] = { + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ), + .initial_baud = 115200, + .address = BSP_MICROBLAZE_FPGA_UART_BASE, +#if BSP_MICROBLAZE_FPGA_USE_UART + .enabled = 1, +#endif +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + .irq = BSP_MICROBLAZE_FPGA_UART_IRQ +#endif + } +}; + +const console_device console_device_table[] = { + { + .device_file = "/dev/ttyS0", + .handler = µblaze_uart_fns, + .context = &uart_lite_instances[0].base + } +}; + +const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table ); +#else +static uart_lite_context uart_lite_instances[BSP_MICROBLAZE_FPGA_MAX_UARTS]; +console_device *dynamic_console_device_table; +size_t dynamic_console_device_count; + +/* Override the console_device_table and console_device_count */ +#define console_device_table dynamic_console_device_table +#define console_device_count dynamic_console_device_count +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +static int microblaze_fpga_get_stdout_node(const void *fdt) +{ + int node; + int len; + int offset; + const char *console; + const char *q; + + node = fdt_path_offset( fdt, "/chosen" ); + if ( node < 0 ) { + return 0; + } + + console = fdt_getprop( fdt, node, "stdout-path", NULL ); + if ( console == NULL ) { + return 0; + } + + q = strchr(console, ':'); + if ( !q ) { + return 0; + } + + len = q - console; + + /* Get the node specified by stdout-path */ + offset = fdt_path_offset_namelen( fdt, console, len ); + if (offset < 0) { + return 0; + } + + return offset; +} + +static void initialize_uart_arrays(uint32_t max_uarts) { + dynamic_console_device_table = calloc(max_uarts, sizeof(console_device)); + dynamic_console_device_count = max_uarts; + + for (uint32_t i = 0; i < max_uarts; i++) { + rtems_termios_device_context_initialize(&uart_lite_instances[i].base, "UARTLITE"); + uart_lite_instances[i].initial_baud = 115200; + + dynamic_console_device_table[i].device_file = malloc(11); + snprintf((char *)console_device_table[i].device_file, 11, "/dev/ttyS%u", i); + dynamic_console_device_table[i].handler = µblaze_uart_fns; + dynamic_console_device_table[i].context = &uart_lite_instances[i].base; + } +} +#endif + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + uint32_t port; + uint32_t stdout_port = BSP_MICROBLAZE_FPGA_CONSOLE_UART; + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT + initialize_uart_arrays(BSP_MICROBLAZE_FPGA_MAX_UARTS); + + const char compatible[] = "xlnx,xps-uartlite-1.00.a"; + const void *fdt = bsp_fdt_get(); + int len; + int stdout_node = microblaze_fpga_get_stdout_node(fdt); + int node = fdt_node_offset_by_compatible( fdt, -1, compatible); + + while ( node != -FDT_ERR_NOTFOUND ) { + const uint32_t *prop; + const void *status; + uint32_t disabled = 0; + port = console_device_count; + + /* check if node device status has been set to disabled */ + status = fdt_getprop( fdt, node, "status", &len ); + if ( status != NULL ) { + if ( strncmp( status, "disabled", MIN( 9, len) ) == 0 ) { + disabled = 1; + } + } + + if ( !disabled ) { + /* use port number property as the device table index */ + prop = fdt_getprop( fdt, node, "port-number", NULL ); + if ( prop != NULL ) { + port = fdt32_to_cpu( prop[0] ); + } + + if ( port < console_device_count ) { + prop = fdt_getprop( fdt, node, "reg", NULL ); + if ( prop != NULL ) { + uint32_t address = fdt32_to_cpu( prop[0] ); + uart_lite_instances[ port ].address = address; + uart_lite_instances[ port ].enabled = 1; + if ( node == stdout_node ) { + stdout_port = port; + } + } + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + prop = fdt_getprop( fdt, node, "interrupts", NULL ); + if ( prop != NULL ) { + uint32_t irq = fdt32_to_cpu( prop[0] ); + uart_lite_instances[ port ].irq = irq; + } +#endif + } + } + + node = fdt_node_offset_by_compatible( fdt, node, compatible ); + + if ( disabled || ( port >= console_device_count ) ) + continue; + } +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + + rtems_termios_initialize(); + + for ( port = 0; port < console_device_count; port++ ) { + const console_device *ctx = &console_device_table[ port ]; + rtems_status_code sc; + + if ( !uart_lite_instances[ port ].enabled ) + continue; + + sc = rtems_termios_device_install( + ctx->device_file, + ctx->handler, + ctx->flow, + ctx->context + ); + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_0 ); + } + + if ( port == stdout_port ) { + if ( link( ctx->device_file, CONSOLE_DEVICE_NAME ) != 0 ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_1 ); + } + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/microblaze/microblaze_fpga/console/debug-io.c b/bsps/microblaze/microblaze_fpga/console/debug-io.c new file mode 100644 index 0000000000..d85229ae9e --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/debug-io.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze debug IO support + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dev/serial/uartlite_l.h> +#include <rtems/bspIo.h> + +#include <bsp.h> +#include <bspopts.h> + +static uint32_t mblaze_uart_base = 0; + +static void output_char( char c ) +{ + if (mblaze_uart_base == 0 ) { + mblaze_uart_base = try_get_prop_from_device_tree( + "xlnx,xps-uartlite-1.00.a", + "reg", + BSP_MICROBLAZE_FPGA_UART_BASE + ); + } + + if ( c == '\n' ) { + XUartLite_SendByte( mblaze_uart_base, '\r' ); + } + XUartLite_SendByte( mblaze_uart_base, c ); +} + +static int xUartLite_RecvByte( int minor ) +{ + if (mblaze_uart_base == 0 ) { + mblaze_uart_base = try_get_prop_from_device_tree( + "xlnx,xps-uartlite-1.00.a", + "reg", + BSP_MICROBLAZE_FPGA_UART_BASE + ); + } + + if ( XUartLite_IsReceiveEmpty( mblaze_uart_base ) ) { + return -1; + } + + return XUartLite_ReadReg( mblaze_uart_base, XUL_RX_FIFO_OFFSET ); +} + +static int get_char( void ) +{ + return xUartLite_RecvByte( 0 ); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = get_char; diff --git a/bsps/microblaze/microblaze_fpga/dts/system.dts b/bsps/microblaze/microblaze_fpga/dts/system.dts new file mode 100644 index 0000000000..78762f8df2 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/dts/system.dts @@ -0,0 +1,452 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "xlnx,microblaze"; + model = "Xilinx MicroBlaze"; + + cpus { + #address-cells = <0x1>; + #cpus = <0x1>; + #size-cells = <0x0>; + + cpu@0 { + bus-handle = <0x1>; + clock-frequency = <0x5f5e100>; + clocks = <0x2>; + compatible = "xlnx,microblaze-11.0"; + d-cache-baseaddr = <0x80000000>; + d-cache-highaddr = <0xffffffff>; + d-cache-line-size = <0x10>; + d-cache-size = <0x8000>; + device_type = "cpu"; + i-cache-baseaddr = <0x80000000>; + i-cache-highaddr = <0xffffffff>; + i-cache-line-size = <0x20>; + i-cache-size = <0x8000>; + interrupt-handle = <0x3>; + model = "microblaze,11.0"; + reg = <0x0>; + timebase-frequency = <0x5f5e100>; + xlnx,addr-size = <0x20>; + xlnx,addr-tag-bits = <0x10>; + xlnx,allow-dcache-wr = <0x1>; + xlnx,allow-icache-wr = <0x1>; + xlnx,area-optimized = <0x0>; + xlnx,async-interrupt = <0x1>; + xlnx,async-wakeup = <0x3>; + xlnx,avoid-primitives = <0x0>; + xlnx,base-vectors = <0x0 0x0>; + xlnx,branch-target-cache-size = <0x0>; + xlnx,cache-byte-size = <0x8000>; + xlnx,d-axi = <0x1>; + xlnx,d-lmb = <0x1>; + xlnx,d-lmb-mon = <0x0>; + xlnx,d-lmb-protocol = <0x0>; + xlnx,daddr-size = <0x20>; + xlnx,data-size = <0x20>; + xlnx,dc-axi-mon = <0x0>; + xlnx,dcache-addr-tag = <0x10>; + xlnx,dcache-always-used = <0x1>; + xlnx,dcache-byte-size = <0x8000>; + xlnx,dcache-data-width = <0x0>; + xlnx,dcache-force-tag-lutram = <0x0>; + xlnx,dcache-line-len = <0x4>; + xlnx,dcache-use-writeback = <0x0>; + xlnx,dcache-victims = <0x0>; + xlnx,debug-counter-width = <0x20>; + xlnx,debug-enabled = <0x1>; + xlnx,debug-event-counters = <0x5>; + xlnx,debug-external-trace = <0x0>; + xlnx,debug-interface = <0x0>; + xlnx,debug-latency-counters = <0x1>; + xlnx,debug-profile-size = <0x0>; + xlnx,debug-trace-async-reset = <0x0>; + xlnx,debug-trace-size = <0x2000>; + xlnx,div-zero-exception = <0x1>; + xlnx,dp-axi-mon = <0x0>; + xlnx,dynamic-bus-sizing = <0x0>; + xlnx,ecc-use-ce-exception = <0x0>; + xlnx,edge-is-positive = <0x1>; + xlnx,enable-discrete-ports = <0x0>; + xlnx,endianness = <0x1>; + xlnx,fault-tolerant = <0x0>; + xlnx,fpu-exception = <0x1>; + xlnx,freq = <0x5f5e100>; + xlnx,fsl-exception = <0x0>; + xlnx,fsl-links = <0x0>; + xlnx,i-axi = <0x0>; + xlnx,i-lmb = <0x1>; + xlnx,i-lmb-mon = <0x0>; + xlnx,i-lmb-protocol = <0x0>; + xlnx,iaddr-size = <0x20>; + xlnx,ic-axi-mon = <0x0>; + xlnx,icache-always-used = <0x1>; + xlnx,icache-data-width = <0x0>; + xlnx,icache-force-tag-lutram = <0x0>; + xlnx,icache-line-len = <0x8>; + xlnx,icache-streams = <0x1>; + xlnx,icache-victims = <0x8>; + xlnx,ill-opcode-exception = <0x1>; + xlnx,imprecise-exceptions = <0x0>; + xlnx,instr-size = <0x20>; + xlnx,interconnect = <0x2>; + xlnx,interrupt-is-edge = <0x0>; + xlnx,interrupt-mon = <0x0>; + xlnx,ip-axi-mon = <0x0>; + xlnx,lmb-data-size = <0x20>; + xlnx,lockstep-master = <0x0>; + xlnx,lockstep-select = <0x0>; + xlnx,lockstep-slave = <0x0>; + xlnx,mmu-dtlb-size = <0x4>; + xlnx,mmu-itlb-size = <0x2>; + xlnx,mmu-privileged-instr = <0x0>; + xlnx,mmu-tlb-access = <0x3>; + xlnx,mmu-zones = <0x2>; + xlnx,num-sync-ff-clk = <0x2>; + xlnx,num-sync-ff-clk-debug = <0x2>; + xlnx,num-sync-ff-clk-irq = <0x1>; + xlnx,num-sync-ff-dbg-clk = <0x1>; + xlnx,num-sync-ff-dbg-trace-clk = <0x2>; + xlnx,number-of-pc-brk = <0x2>; + xlnx,number-of-rd-addr-brk = <0x1>; + xlnx,number-of-wr-addr-brk = <0x1>; + xlnx,opcode-0x0-illegal = <0x1>; + xlnx,optimization = <0x0>; + xlnx,pc-width = <0x20>; + xlnx,piaddr-size = <0x20>; + xlnx,pvr = <0x2>; + xlnx,pvr-user1 = <0x0>; + xlnx,pvr-user2 = <0x0>; + xlnx,reset-msr = <0x0>; + xlnx,reset-msr-bip = <0x0>; + xlnx,reset-msr-dce = <0x0>; + xlnx,reset-msr-ee = <0x0>; + xlnx,reset-msr-eip = <0x0>; + xlnx,reset-msr-ice = <0x0>; + xlnx,reset-msr-ie = <0x0>; + xlnx,sco = <0x0>; + xlnx,trace = <0x0>; + xlnx,unaligned-exceptions = <0x1>; + xlnx,use-barrel = <0x1>; + xlnx,use-branch-target-cache = <0x0>; + xlnx,use-config-reset = <0x0>; + xlnx,use-dcache = <0x1>; + xlnx,use-div = <0x1>; + xlnx,use-ext-brk = <0x0>; + xlnx,use-ext-nm-brk = <0x0>; + xlnx,use-extended-fsl-instr = <0x0>; + xlnx,use-fpu = <0x1>; + xlnx,use-hw-mul = <0x2>; + xlnx,use-icache = <0x1>; + xlnx,use-interrupt = <0x2>; + xlnx,use-mmu = <0x3>; + xlnx,use-msr-instr = <0x1>; + xlnx,use-non-secure = <0x0>; + xlnx,use-pcmp-instr = <0x1>; + xlnx,use-reorder-instr = <0x1>; + xlnx,use-stack-protection = <0x0>; + }; + }; + + clocks { + #address-cells = <0x1>; + #size-cells = <0x0>; + + clk_cpu@0 { + #clock-cells = <0x0>; + clock-frequency = <0x5f5e100>; + clock-output-names = "clk_cpu"; + compatible = "fixed-clock"; + reg = <0x0>; + phandle = <0x2>; + }; + + clk_bus_0@1 { + #clock-cells = <0x0>; + clock-frequency = <0x5f5e100>; + clock-output-names = "clk_bus_0"; + compatible = "fixed-clock"; + reg = <0x1>; + phandle = <0x7>; + }; + }; + + amba_pl { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + ranges; + phandle = <0x1>; + + ethernet@40c00000 { + axistream-connected = <0x4>; + axistream-control-connected = <0x4>; + clock-frequency = <0x5f5e100>; + compatible = "xlnx,axi-ethernet-7.2", "xlnx,axi-ethernet-1.00.a"; + device_type = "network"; + interrupt-names = "mac_irq", "interrupt"; + interrupt-parent = <0x3>; + interrupts = <0x4 0x0 0x5 0x2>; + local-mac-address = [00 0a 35 00 22 01]; + phy-handle = <0x5>; + phy-mode = "sgmii"; + reg = <0x40c00000 0x40000>; + xlnx = <0x0>; + xlnx,axiliteclkrate = <0x0>; + xlnx,axisclkrate = <0x0>; + xlnx,channel-ids = <0x1>; + xlnx,clockselection = <0x0>; + xlnx,enableasyncsgmii = <0x0>; + xlnx,gt-type = <0x0>; + xlnx,gtinex = <0x0>; + xlnx,gtlocation = <0x0>; + xlnx,gtrefclksrc = <0x0>; + xlnx,include-dre; + xlnx,instantiatebitslice0 = <0x0>; + xlnx,num-queues = [00 01]; + xlnx,phy-type = <0x4>; + xlnx,phyaddr = <0x1>; + xlnx,phyrst-board-interface-dummy-port = <0x0>; + xlnx,rable = <0x0>; + xlnx,rxcsum = <0x0>; + xlnx,rxlane0-placement = <0x0>; + xlnx,rxlane1-placement = <0x0>; + xlnx,rxmem = <0x1000>; + xlnx,rxnibblebitslice0used = <0x0>; + xlnx,tx-in-upper-nibble = <0x1>; + xlnx,txcsum = <0x0>; + xlnx,txlane0-placement = <0x0>; + xlnx,txlane1-placement = <0x0>; + phandle = <0x6>; + dmas = <&dma 0 + &dma 1>; + dma-names = "tx", "rx"; + memory-region = <&dma_reserved>; + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + + phy@1 { + device_type = "ethernet-phy"; + reg = <0x7>; + phandle = <0x5>; + }; + }; + }; + + dma: dma@41e00000 { + #dma-cells = <0x1>; + axistream-connected = <0x6>; + axistream-control-connected = <0x6>; + clock-frequency = <0x5f5e100>; + clock-names = "s_axi_lite_aclk"; + clocks = <0x7>; + compatible = "xlnx,eth-dma"; + interrupt-names = "mm2s_introut", "s2mm_introut"; + interrupt-parent = <0x3>; + interrupts = <0x6 0x2 0x7 0x2>; + reg = <0x41e00000 0x10000>; + xlnx,addrwidth = [20]; + xlnx,include-dre; + xlnx,num-queues = [00 01]; + phandle = <0x4>; + }; + + gpio@40000000 { + #gpio-cells = <0x3>; + clock-frequency = <0x5f5e100>; + clock-names = "s_axi_aclk"; + clocks = <0x7>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x40000000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x1>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x8>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + }; + + gpio@40010000 { + #gpio-cells = <0x3>; + clock-frequency = <0x5f5e100>; + clock-names = "s_axi_aclk"; + clocks = <0x7>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x40010000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x1>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x5>; + xlnx,gpio2-width = <0x3>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + }; + + i2c@40800000 { + #address-cells = <0x1>; + #size-cells = <0x0>; + clock-frequency = <0x5f5e100>; + clocks = <0x7>; + compatible = "xlnx,axi-iic-2.0", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <0x3>; + interrupts = <0x2 0x2>; + reg = <0x40800000 0x10000>; + + i2c-mux@75 { + compatible = "nxp,pca9544"; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x75>; + + i2c@3 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x3>; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + }; + }; + + axi_quad_spi@44a00000 { + bits-per-word = <0x8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <0x100>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <0x3>; + interrupts = <0x3 0x0>; + num-cs = <0x2>; + reg = <0x44a00000 0x10000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0x2>; + xlnx,startup-block; + #address-cells = <0x1>; + #size-cells = <0x0>; + + flash@0 { + compatible = "n25q512a"; + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + spi-tx-bus-width = <0x1>; + spi-rx-bus-width = <0x4>; + spi-max-frequency = <0x2faf080>; + + partition@0 { + label = "fpga"; + reg = <0x0 0x1000000>; + }; + + partition@1 { + label = "boot"; + reg = <0x1000000 0x180000>; + }; + + partition@2 { + label = "bootenv"; + reg = <0x1180000 0x40000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x11c0000 0xc00000>; + }; + }; + }; + + timer@41c00000 { + clock-frequency = <0x5f5e100>; + clocks = <0x7>; + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; + interrupt-names = "interrupt"; + interrupt-parent = <0x3>; + interrupts = <0x0 0x2>; + reg = <0x41c00000 0x10000>; + xlnx,count-width = <0x20>; + xlnx,gen0-assert = <0x1>; + xlnx,gen1-assert = <0x1>; + xlnx,one-timer-only = <0x0>; + xlnx,trig0-assert = <0x1>; + xlnx,trig1-assert = <0x1>; + }; + + serial@40600000 { + clock-frequency = <0x5f5e100>; + clocks = <0x7>; + compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a"; + current-speed = <0x1c200>; + device_type = "serial"; + interrupt-names = "interrupt"; + interrupt-parent = <0x3>; + interrupts = <0x1 0x0>; + port-number = <0x0>; + reg = <0x40600000 0x10000>; + xlnx,baudrate = <0x1c200>; + xlnx,data-bits = <0x8>; + xlnx,odd-parity = <0x0>; + xlnx,s-axi-aclk-freq-hz-d = "100.0"; + xlnx,use-parity = <0x0>; + }; + + ddr4@80000000 { + compatible = "xlnx,ddr4-2.2"; + reg = <0x80000000 0x80000000>; + }; + + interrupt-controller@41200000 { + #interrupt-cells = <0x2>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + reg = <0x41200000 0x10000>; + xlnx,kind-of-intr = <0x1a>; + xlnx,num-intr-inputs = <0x8>; + phandle = <0x3>; + }; + }; + + chosen { + bootargs = "console=ttyUL0,115200 earlycon root=/dev/ram0 rw"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = "/amba_pl/ethernet@40c00000"; + i2c0 = "/amba_pl/i2c@40800000"; + serial0 = "/amba_pl/serial@40600000"; + spi0 = "/amba_pl/axi_quad_spi@44a00000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + phandle = <0x8>; + }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma_reserved: buffer@10000000 { + reg = <0x10000000 0x4000000>; + }; + }; +}; diff --git a/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c new file mode 100644 index 0000000000..49859a03f1 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/fs/jffs2_qspi.c @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI QSPI JFFS2 flash driver implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <assert.h> +#include <errno.h> +#include <string.h> +#include <fcntl.h> +#include <sys/types.h> +#include <sys/stat.h> + +#include <bspopts.h> +#include <dev/spi/xilinx-axi-spi.h> +#include <linux/spi/spidev.h> +#include <rtems/jffs2.h> +#include <rtems/libio.h> + +#include <bsp.h> +#include <bsp/jffs2_qspi.h> + +#define BLOCK_SIZE (64UL * 1024UL) +#define FLASH_SIZE (32UL * BLOCK_SIZE) +#define FLASH_PAGE_SIZE 256 +#define FLASH_NUM_CS 2 +#define FLASH_DEVICE_ID 0xbb19 /* Type: 0xbb, Capacity: 0x19 */ +#define BUS_PATH "/dev/spi-0" +#define FLASH_MOUNT_POINT "/mnt" + +#define READ_WRITE_EXTRA_BYTES 4 +#define WRITE_ENABLE_BYTES 1 +#define SECTOR_ERASE_BYTES 4 + +#define COMMAND_QUAD_WRITE 0x32 +#define COMMAND_SECTOR_ERASE 0xD8 +#define COMMAND_QUAD_READ 0x6B +#define COMMAND_STATUSREG_READ 0x05 +#define COMMAND_WRITE_ENABLE 0x06 +#define FLASH_SR_IS_READY_MASK 0x01 + +typedef struct { + rtems_jffs2_flash_control super; + int fd; +} flash_control; + +static uint8_t ReadBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4]; +static uint8_t WriteBuffer[FLASH_PAGE_SIZE + READ_WRITE_EXTRA_BYTES + 4]; + +static flash_control *get_flash_control( rtems_jffs2_flash_control *super ) +{ + return (flash_control *) super; +} + +static int flash_wait_for_ready( flash_control *self ) +{ + uint8_t rv = 0; + uint8_t status = 0; + + WriteBuffer[0] = COMMAND_STATUSREG_READ; + + struct spi_ioc_transfer mesg = { + .tx_buf = WriteBuffer, + .rx_buf = ReadBuffer, + .len = 2, + .bits_per_word = 8, + .cs = 0 + }; + + do { + rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ), &mesg ); + if ( rv != 0 ) { + return -EIO; + } + + status = ReadBuffer[1]; + } while ( (status & FLASH_SR_IS_READY_MASK) != 0 ); + + return 0; +} + +static int flash_write_enable( flash_control *self ) +{ + uint8_t rv = 0; + + rv = flash_wait_for_ready( self ); + if ( rv != 0 ) { + return rv; + } + + WriteBuffer[0] = COMMAND_WRITE_ENABLE; + + struct spi_ioc_transfer mesg = { + .tx_buf = WriteBuffer, + .len = WRITE_ENABLE_BYTES, + .bits_per_word = 8, + .cs = 0 + }; + + rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ), &mesg ); + if ( rv != 0 ) { + return -EIO; + } + + return 0; +} + +static int flash_read( + rtems_jffs2_flash_control *super, + uint32_t offset, + unsigned char *buffer, + size_t size_of_buffer +) +{ + int rv = 0; + uint32_t current_offset = offset; + uint32_t bytes_left = size_of_buffer; + + flash_control *self = get_flash_control( super ); + + rv = flash_wait_for_ready( self ); + if ( rv != 0 ) { + return rv; + } + + WriteBuffer[0] = COMMAND_QUAD_READ; + + /* Read in 256-byte chunks */ + do { + uint32_t chunk_size = bytes_left > FLASH_PAGE_SIZE ? FLASH_PAGE_SIZE : bytes_left; + + struct spi_ioc_transfer mesg = { + .tx_buf = WriteBuffer, + .rx_buf = ReadBuffer, + .len = chunk_size + 8, + .bits_per_word = 8, + .cs = 0 + }; + + WriteBuffer[1] = (uint8_t) (current_offset >> 16); + WriteBuffer[2] = (uint8_t) (current_offset >> 8); + WriteBuffer[3] = (uint8_t) current_offset; + + rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ), &mesg ); + if ( rv != 0 ) { + return -EIO; + } + + memcpy( &buffer[current_offset - offset], &ReadBuffer[8], chunk_size ); + + current_offset += chunk_size; + bytes_left -= chunk_size; + } while ( bytes_left > 0 ); + + return 0; +} + +static int flash_write( + rtems_jffs2_flash_control *super, + uint32_t offset, + const unsigned char *buffer, + size_t size_of_buffer +) +{ + int rv = 0; + + flash_control *self = get_flash_control( super ); + + rv = flash_write_enable( self ); + if ( rv != 0 ) { + return rv; + } + + rv = flash_wait_for_ready( self ); + if ( rv != 0 ) { + return rv; + } + + WriteBuffer[0] = COMMAND_QUAD_WRITE; + WriteBuffer[1] = (uint8_t) (offset >> 16); + WriteBuffer[2] = (uint8_t) (offset >> 8); + WriteBuffer[3] = (uint8_t) offset; + + memcpy( &WriteBuffer[4], buffer, size_of_buffer ); + + struct spi_ioc_transfer mesg = { + .tx_buf = WriteBuffer, + .len = size_of_buffer + 4, + .bits_per_word = 8, + .cs = 0 + }; + + rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ), &mesg ); + if ( rv != 0 ) { + return -EIO; + } + + return 0; +} + +static int flash_erase( + rtems_jffs2_flash_control *super, + uint32_t offset +) +{ + int rv = 0; + + flash_control *self = get_flash_control( super ); + + rv = flash_write_enable( self ); + if ( rv != 0 ) { + return rv; + } + + rv = flash_wait_for_ready( self ); + if ( rv != 0 ) { + return rv; + } + + WriteBuffer[0] = COMMAND_SECTOR_ERASE; + WriteBuffer[1] = (uint8_t) (offset >> 16); + WriteBuffer[2] = (uint8_t) (offset >> 8); + WriteBuffer[3] = (uint8_t) offset; + + struct spi_ioc_transfer mesg = { + .tx_buf = WriteBuffer, + .len = SECTOR_ERASE_BYTES, + .bits_per_word = 8, + .cs = 0 + }; + + rv = ioctl( self->fd, SPI_IOC_MESSAGE( 1 ), &mesg ); + if ( rv != 0 ) { + return -EIO; + } + + return 0; +} + +static flash_control flash_instance = { + .super = { + .block_size = BLOCK_SIZE, + .flash_size = FLASH_SIZE, + .read = flash_read, + .write = flash_write, + .erase = flash_erase, + .device_identifier = FLASH_DEVICE_ID + } +}; + +static rtems_jffs2_mount_data mount_data = { + .flash_control = &flash_instance.super, + .compressor_control = NULL +}; + +int microblaze_jffs2_initialize( const char* mount_dir ) +{ + int rv = 0; + int fd = -1; + + uintptr_t mblaze_spi_base = try_get_prop_from_device_tree( + "xlnx,xps-spi-2.00.a", + "reg", + BSP_MICROBLAZE_FPGA_SPI_BASE + ); + + rtems_vector_number mblaze_spi_irq_num = try_get_prop_from_device_tree( + "xlnx,xps-spi-2.00.a", + "interrupts", + BSP_MICROBLAZE_FPGA_SPI_IRQ_NUM + ); + + rv = spi_bus_register_xilinx_axi( + BUS_PATH, + mblaze_spi_base, + FLASH_PAGE_SIZE, + FLASH_NUM_CS, + mblaze_spi_irq_num + ); + if ( rv != 0 ) { + return rv; + } + + fd = open( BUS_PATH, O_RDWR ); + if ( fd < 0 ) { + return -1; + } + + flash_instance.fd = fd; + + rv = mount_and_make_target_path( + NULL, + mount_dir, + RTEMS_FILESYSTEM_TYPE_JFFS2, + RTEMS_FILESYSTEM_READ_WRITE, + &mount_data + ); + if ( rv != 0 ) { + return rv; + } + + return 0; +} diff --git a/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c new file mode 100644 index 0000000000..5444052b9e --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/gpio/microblaze-gpio.c @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI GPIO implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <assert.h> + +#include <bsp/fatal.h> +#include <bsp/fdt.h> +#include <bsp/microblaze-gpio.h> + +#include <libfdt.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +rtems_status_code microblaze_gpio_init_context_from_fdt( + Microblaze_GPIO_context *context, + int index +) +{ + if ( context == NULL ) { + return RTEMS_INVALID_ADDRESS; + } + + const char* compatible = "xlnx,xps-gpio-1.00.a"; + const void *fdt = bsp_fdt_get(); + int node = fdt_node_offset_by_compatible( fdt, -1, compatible ); + if ( node < 0 ) { + return RTEMS_INVALID_NUMBER; + } + + /* Get the desired GPIO node if index is greater than zero. */ + for(int i = 0; i < index; i++) { + node = fdt_node_offset_by_compatible( fdt, node, compatible ); + if ( node < 0 ) { + return RTEMS_INVALID_NUMBER; + } + } + + const uint32_t *prop; + prop = fdt_getprop( fdt, node, "reg", NULL ); + if ( prop != NULL ) { + context->regs = (Microblaze_GPIO_registers *) fdt32_to_cpu( prop[0] ); + } else { + return RTEMS_INVALID_NUMBER; + } + + prop = fdt_getprop( fdt, node, "xlnx,is-dual", NULL ); + if ( prop != NULL ) { + context->is_dual = fdt32_to_cpu( prop[0] ) != 0 ? true : false; + } else { + return RTEMS_INVALID_NUMBER; + } + + prop = fdt_getprop( fdt, node, "xlnx,interrupt-present", NULL ); + if ( prop != NULL ) { + context->has_interrupts = fdt32_to_cpu( prop[0] ) != 0 ? true : false; + } else { + return RTEMS_INVALID_NUMBER; + } + + if ( context->has_interrupts ) { + prop = fdt_getprop( fdt, node, "interrupts", NULL ); + if ( prop != NULL ) { + context->irq = fdt32_to_cpu( prop[0] ); + } else { + return RTEMS_INVALID_NUMBER; + } + } + + return RTEMS_SUCCESSFUL; +} +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + +void microblaze_gpio_set_data_direction( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->gpio_tri = mask; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->gpio2_tri = mask; + } +} + +uint32_t microblaze_gpio_get_data_direction( + Microblaze_GPIO_context *ctx, + uint32_t channel +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + return ctx->regs->gpio_tri; + } else if ( ctx->is_dual && channel == 2 ) { + return ctx->regs->gpio2_tri; + } + + return 0; +} + +uint32_t microblaze_gpio_discrete_read( + Microblaze_GPIO_context *ctx, + uint32_t channel +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + return ctx->regs->gpio_data; + } else if ( ctx->is_dual && channel == 2 ) { + return ctx->regs->gpio2_tri; + } + + return 0; +} + +void microblaze_gpio_discrete_write( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->gpio_data = mask; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->gpio2_tri = mask; + } +} + +void microblaze_gpio_discrete_set( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->gpio_data |= mask; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->gpio2_tri |= mask; + } +} + +void microblaze_gpio_discrete_clear( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->gpio_data &= ~mask; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->gpio2_tri &= ~mask; + } +} + +rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx ) +{ + return ctx->irq; +} + +void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx ) +{ + assert( ctx->has_interrupts ); + + if ( ctx->has_interrupts ) { + ctx->regs->gier = GLOBAL_INTERRUPT_REGISTER_ENABLE; + } +} + +void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx ) +{ + assert( ctx->has_interrupts ); + + if ( ctx->has_interrupts ) { + ctx->regs->gier = 0x0; + } +} + +void microblaze_gpio_interrupt_enable( + Microblaze_GPIO_context *ctx, + uint32_t channel +) +{ + assert( ctx->has_interrupts ); + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( ctx->has_interrupts ) { + if ( channel == 1 ) { + ctx->regs->ip_ier |= CHANNEL_1_INTERRUPT_REGISTER; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->ip_ier |= CHANNEL_2_INTERRUPT_REGISTER; + } + } +} + +void microblaze_gpio_interrupt_disable( + Microblaze_GPIO_context *ctx, + uint32_t channel +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->ip_ier &= ~CHANNEL_1_INTERRUPT_REGISTER; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->ip_ier &= ~CHANNEL_2_INTERRUPT_REGISTER; + } +} + +void microblaze_gpio_interrupt_clear( + Microblaze_GPIO_context *ctx, + uint32_t channel +) +{ + assert( channel == 1 || (ctx->is_dual && channel == 2) ); + + if ( channel == 1 ) { + ctx->regs->ip_isr &= CHANNEL_1_INTERRUPT_REGISTER; + } else if ( ctx->is_dual && channel == 2 ) { + ctx->regs->ip_isr &= CHANNEL_2_INTERRUPT_REGISTER; + } +} + +uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx ) +{ + assert( ctx->has_interrupts ); + + if ( ctx->has_interrupts ) { + return ctx->regs->ip_ier; + } + + return 0; +} + +uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx ) +{ + assert( ctx->has_interrupts ); + + if ( ctx->has_interrupts ) { + return ctx->regs->ip_isr; + } + + return 0; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h b/bsps/microblaze/microblaze_fpga/include/bsp.h new file mode 100644 index 0000000000..6890f33395 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief Core BSP definitions + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H +#define LIBBSP_MICROBLAZE_FPGA_BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> +#include <bsp/microblaze-fdt-support.h> + +#include <rtems.h> + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +#define BSP_FDT_IS_SUPPORTED +#ifndef BSP_START_COPY_FDT_FROM_U_BOOT +extern const unsigned char system_dtb[]; +extern const size_t system_dtb_size; +#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */ +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + +void microblaze_enable_icache(void); +void microblaze_enable_dcache(void); +void microblaze_invalidate_icache(void); +void microblaze_invalidate_dcache(void); +void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len); + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h new file mode 100644 index 0000000000..c270c7464f --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Interrupt Controller definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H +#define LIBBSP_MICROBLAZE_FPGA_INTC_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + /* Interrupt Status Register */ + uint32_t isr; + uint32_t ipr; + /* Interrupt Enable Register */ + uint32_t ier; + /* Interrupt Acknowledge Register */ + uint32_t iar; + uint32_t sie; + uint32_t cie; + uint32_t ivr; +#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1) +#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0) + /* Master Enable Register */ + uint32_t mer; + /* Interrupt Mode Register, this is present only for Fast Interrupt */ + uint32_t imr; + /* Interrupt Level Register */ + uint32_t ilr; +} Microblaze_INTC; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/irq.h b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h new file mode 100644 index 0000000000..0a7c211fb0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP IRQ definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_IRQ_H +#define LIBBSP_MICROBLAZE_FPGA_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_COUNT 32 + +#endif /* LIBBSP_MICROBLAZE_FPGA_IRQ_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h b/bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h new file mode 100644 index 0000000000..9c071c4977 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/jffs2_qspi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI QSPI JFFS2 flash driver definitions + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_JFFS2_QSPI_H +#define LIBBSP_MICROBLAZE_FPGA_JFFS2_QSPI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Mount jffs2 filesystem. + * + * @param[in] mount_dir The directory to mount the filesystem at. + * + * @retval 0 Successful operation. Negative number otherwise. + */ +int microblaze_jffs2_initialize( const char* mount_dir ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_JFFS2_QSPI_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h new file mode 100644 index 0000000000..9a01aa8bb3 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h @@ -0,0 +1,968 @@ +/* + * Declarations for C structure representing binary file system.dtb + * + * WARNING: Automatically generated -- do not edit! + */ + +#ifndef __microblaze_dtb_h +#define __microblaze_dtb_h + +#include <rtems/score/basedefs.h> +#include <sys/types.h> + +const unsigned char system_dtb[] RTEMS_ALIGNED(8) = { + 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38, + 0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5, + 0x00, 0x00, 0x1c, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1b, + 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, + 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12, + 0x00, 0x00, 0x00, 0x26, 0x58, 0x69, 0x6c, 0x69, 0x6e, 0x78, 0x20, 0x4d, + 0x69, 0x63, 0x72, 0x6f, 0x42, 0x6c, 0x61, 0x7a, 0x65, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x32, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x3d, 0x05, 0xf5, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x02, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x1b, + 0x78, 0x6c, 0x6e, 0x78, 0x2c, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x62, 0x6c, + 0x61, 0x7a, 0x65, 0x2d, 0x31, 0x31, 0x2e, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x54, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x65, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 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0x6e, 0x65, + 0x74, 0x30, 0x00, 0x69, 0x32, 0x63, 0x30, 0x00, 0x73, 0x65, 0x72, 0x69, + 0x61, 0x6c, 0x30, 0x00, 0x73, 0x70, 0x69, 0x30, 0x00, +}; + +const size_t system_dtb_size = sizeof(system_dtb); + +#endif /* __microblaze_dtb_h */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h new file mode 100644 index 0000000000..e8f569c8fd --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-gpio.h @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI GPIO definitions + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H +#define LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H + +#include <bspopts.h> +#include <bsp/utility.h> +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + /* Channel 1 data values */ + + /* + * Used to read general purpose input ports and write to general purpose + * output ports from channel 1. + */ + volatile uint32_t gpio_data; + + /* + * The 3-state control register for channel 1 is used for the dynamic + * configuration of ports as input or output. When a bit is set to 1, the + * corresponding I/O port is an input port. When a bit is set to 0, it is an + * output port. + */ + volatile uint32_t gpio_tri; + + /* Channel 2 data values */ + + /* + * Used to read general purpose input ports and write to general purpose + * output ports from channel 2. + */ + volatile uint32_t gpio2_data; + + /* + * The 3-state control register for channel 2 is used for the dynamic + * configuration of ports as input or output. When a bit is set to 1, the + * corresponding I/O port is an input port. When a bit is set to 0, it is an + * output port. + */ + volatile uint32_t gpio2_tri; + + char _unused[272]; + + /* Only the 31st bit is used to enable interrupts globally */ +#define GLOBAL_INTERRUPT_REGISTER_ENABLE BSP_BIT32(31) + + /* + * Global Interrupt Enable Register + * + * Determines whether interrupts are enabled or disabled. + * + * 0 - Disabled + * 1 - Enabled + */ + volatile uint32_t gier; + + char _unused2[12]; + + /* Used with ip_isr and ip_ier member variables */ +#define CHANNEL_1_INTERRUPT_REGISTER BSP_BIT32(0) +#define CHANNEL_2_INTERRUPT_REGISTER BSP_BIT32(1) + + /* + * IP Status Registers + * + * Contains the status bit for each channel. + * + * 0 - Disabled + * 1 - Enabled + */ + volatile uint32_t ip_isr; + + char _unused3[4]; + + /* + * IP Interrupt Enable Register + * + * Provides the ability to independtly control whether interrupts for each + * channel are enabled or disabled. + * + * 0 - No Channel input interrupt + * 1 - Channel input interrupt + */ + volatile uint32_t ip_ier; +} Microblaze_GPIO_registers; + +typedef struct { + Microblaze_GPIO_registers *regs; + bool is_dual; + uint32_t irq; + bool has_interrupts; +} Microblaze_GPIO_context; + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +/** + * @brief Initialize GPIO context from FDT. + * + * @param[in] context the GPIO context to initialize + * @param[in] index the zero-based GPIO index in the FDT + * + * @retval RTEMS_SUCCESSFUL on success + * @retval RTEMS_INVALID_NUMBER if the index is invalid or the node is missing a + * required property + * @retval RTEMS_INVALID_ADDRESS if the context is NULL + */ +rtems_status_code microblaze_gpio_init_context_from_fdt( + Microblaze_GPIO_context *context, + int index +); +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + +/** + * @brief Set pin configuration for the specified GPIO channel. + * + * Changes the pin configuration for a channel. Bits set to 0 are output, and + * bits set to 1 are input. + * + * @param[in] ctx the GPIO context + * @param[in] channel the GPIO channel + * @param[in] mask the mask to be applied to @ channel + * + * @retval None + */ +void microblaze_gpio_set_data_direction( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +); + +/** + * @brief Get pin configuration for specified GPIO channel. + * + * Gets the current pin configuration for a specified GPIO channel. Bits set to + * 0 are output, and bits set to 1 are input. + * + * @param[in] ctx the GPIO context + * @param[in] channel the GPIO channel + * + * @retval bitmask specifiying which pins on a channel are input or output + */ +uint32_t microblaze_gpio_get_data_direction( + Microblaze_GPIO_context *ctx, + uint32_t channel +); + +/** + * @brief Reads data for specified GPIO channel. + * + * @param[in] channel the GPIO channel + * + * @retval Current values in discretes register. + */ +uint32_t microblaze_gpio_discrete_read( + Microblaze_GPIO_context *ctx, + uint32_t channel +); + +/** + * @brief Writes to data register for specified GPIO channel. + * + * @param[in] ctx the GPIO context + * @param[in] channel the GPIO channel + * @param[in] mask the mask to be applied to @ channel + * + * @retval None + */ +void microblaze_gpio_discrete_write( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +); + +/** + * @brief Set bits to 1 on specified GPIO channel. + * + * @param[in] ctx the GPIO context + * @param[in] channel the GPIO channel + * @param[in] mask the mask to be applied to @ channel + * + * @retval None + */ +void microblaze_gpio_discrete_set( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +); + +/** + * @brief Set bits to 0 on specified GPIO channel. + * + * @param[in] ctx the GPIO context + * @param[in] channel the GPIO channel + * @param[in] mask the mask to be applied to @ channel + * + * @retval None + */ +void microblaze_gpio_discrete_clear( + Microblaze_GPIO_context *ctx, + uint32_t channel, + uint32_t mask +); + +/** + * @brief Returns the vector number of the interrupt handler. + * + * @param[in] ctx the GPIO context + * + * @retval the vector number + */ +rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx ); + +/** + * @brief Turns on interrupts globally. + * + * @param[in] ctx the GPIO context + * + * @retval None + */ +void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx ); + +/** + * @brief Turns off interrupts globally. + * + * @param[in] ctx the GPIO context + * + * @retval None + */ +void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx ); + +/** + * @brief Enables interrupts on specified channel + * + * @param[in] ctx the GPIO context + * @param[in] channel the channel to enable interrupts on + * + * @retval None + */ +void microblaze_gpio_interrupt_enable( + Microblaze_GPIO_context *ctx, + uint32_t channel +); + +/** + * @brief Disables interrupts on specified channel + * + * @param[in] ctx the GPIO context + * @param[in] channel the channel to turn interrupts on for + * + * @retval None + */ +void microblaze_gpio_interrupt_disable( + Microblaze_GPIO_context *ctx, + uint32_t channel +); + +/** + * @brief Clear status of interrupt signals on a specific channel + * + * @param[in] ctx the GPIO context + * @param[in] channel the channel to clear the interrupt pending status from + * + * @retval None + */ +void microblaze_gpio_interrupt_clear( + Microblaze_GPIO_context *ctx, + uint32_t channel +); + +/** + * @brief Return a bitmask of the interrupts that are enabled + * + * @param[in] ctx the GPIO context + * + * @retval the bitmask of enabled interrupts + */ +uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx ); + +/** + * @brief Return a bitmask of the status of the interrupt signals + * + * @param[in] ctx the GPIO context + * + * @retval bitmask containing statuses of interrupt signals + */ +uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h new file mode 100644 index 0000000000..bd8661d47c --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_TIMER_H +#define LIBBSP_MICROBLAZE_FPGA_TIMER_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { +#define MICROBLAZE_TIMER_TCSR0_T0INT BSP_BIT32(8) +#define MICROBLAZE_TIMER_TCSR0_ENT0 BSP_BIT32(7) +#define MICROBLAZE_TIMER_TCSR0_ENIT0 BSP_BIT32(6) +#define MICROBLAZE_TIMER_TCSR0_LOAD0 BSP_BIT32(5) +#define MICROBLAZE_TIMER_TCSR0_ARHT0 BSP_BIT32(4) +#define MICROBLAZE_TIMER_TCSR0_GENT0 BSP_BIT32(2) +#define MICROBLAZE_TIMER_TCSR0_UDT0 BSP_BIT32(1) + /* Control/Status register */ + uint32_t tcsr0; + /* Load register */ + uint32_t tlr0; + /* Timer counter register */ + uint32_t tcr0; +} Microblaze_Timer; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_TIMER_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/tm27.h b/bsps/microblaze/microblaze_fpga/include/tm27.h new file mode 100644 index 0000000000..f2e384b534 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/tm27.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP tm27 header + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Time Test 27 cannot be implemented reliably because the AXI interrupt + * controller is not guaranteed to support software interrupts. + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif /* __tm27_h */ diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c b/bsps/microblaze/microblaze_fpga/irq/irq.c new file mode 100644 index 0000000000..f14eddc799 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/irq/irq.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze interrupt support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/intc.h> +#include <bsp/irq-generic.h> + +#include <rtems/score/cpu.h> + +static volatile Microblaze_INTC *mblaze_intc; + +static void ack_interrupt( uint8_t source ) +{ + mblaze_intc->iar = 0x1 << source; +} + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_clear = true; + attributes->cleared_by_acknowledge = true; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( pending != NULL ); + *pending = false; + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_clear( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + mblaze_intc->iar = 0x1 << vector; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_is_enabled( + rtems_vector_number vector, + bool *enabled +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( enabled != NULL ); + + uint32_t mask = 1 << vector; + + *enabled = (mblaze_intc->ier & mask) != 0; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + uint32_t mask = 1 << vector; + + mblaze_intc->ier |= mask; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + uint32_t mask = 1 << vector; + + mblaze_intc->ier &= ~mask; + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_facility_initialize( void ) +{ + /* + * Enable HW interrupts on the interrupt controller. This happens before + * interrupts are enabled on the processor. + */ + mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree( + "xlnx,xps-intc-1.00.a", + "reg", + BSP_MICROBLAZE_FPGA_INTC_BASE + ); + + mblaze_intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE; +} + +void bsp_interrupt_dispatch( uint32_t source ) +{ + uint32_t vector_number = 0; + + if ( source == 0xFF ) { + /* Read interrupt controller to get the source */ + vector_number = mblaze_intc->isr & mblaze_intc->ier; + + /* Handle and the first interrupt that is set */ + uint8_t interrupt_status = 0; + for ( int i = 0; i < 32; i++ ) { + interrupt_status = vector_number >> i & 0x1; + if ( interrupt_status != 0 ) { + /* save current ILR */ + uint32_t interrupt_levels = mblaze_intc->ilr; + /* set ILR to block out every interrupt less than or equal to priority of i */ + mblaze_intc->ilr = 0xFFFFFFFF >> (32 - i); + bsp_interrupt_handler_dispatch( i ); + ack_interrupt( i ); + /* restore ILR */ + mblaze_intc->ilr = interrupt_levels; + break; + } + } + } else { + vector_number = source; + + /* Fast interrupt mode. Handle interrupt. Ack happens automatically */ + bsp_interrupt_handler_dispatch( vector_number ); + } +} diff --git a/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S new file mode 100644 index 0000000000..872f488889 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroBlaze + * + * @brief MicroBlaze debug trap handler implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/score/cpu.h> + + .text + .globl _debug_sw_break_handler # HW Exception Handler Label + .extern _MicroBlaze_Debug_handle + .align 2 + + _debug_sw_break_handler: + /* The stack used here does not matter since debug cannot recurse */ + + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ + swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2 + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3 + swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4 + swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5 + swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6 + swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7 + swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8 + swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9 + swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10 + swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11 + swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12 + swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13 + swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14 + swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15 + swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16 + swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17 + swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18 + swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19 + swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20 + swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21 + swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22 + swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23 + swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24 + swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25 + swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26 + swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27 + swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28 + swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29 + swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30 + swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31 + + /* Retrieve and store MSR */ + mfs r3, rmsr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR + + /* Retrieve and store EAR */ + mfs r3, rear + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR + + /* Retrieve and store ESR */ + mfs r3, resr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR + + /* Retrieve and store BTR */ + mfs r3, rbtr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR + + /* Calculate and store original stack pointer */ + addik r3, r1, CPU_EXCEPTION_FRAME_SIZE + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1 + + /* set parameter 1 to CPU Exception frame */ + addi r5, r1, 0 + + /* call into the debug framework */ + braid _MicroBlaze_Debug_handle + nop diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S new file mode 100644 index 0000000000..c3c05796a4 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroBlaze + * + * @brief MicroBlaze exception handler implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/score/cpu.h> + + .text + .globl _exception_handler # Exception Handler Label + .align 2 + + _exception_handler: + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ + swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2 + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3 + swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4 + swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5 + swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6 + swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7 + swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8 + swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9 + swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10 + swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11 + swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12 + swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13 + swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14 + swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15 + swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16 + swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17 + swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18 + swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19 + swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20 + swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21 + swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22 + swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23 + swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24 + swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25 + swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26 + swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27 + swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28 + swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29 + swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30 + swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31 + + /* Retrieve and store MSR */ + mfs r3, rmsr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR + + /* Retrieve and store EAR */ + mfs r3, rear + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR + + /* Retrieve and store ESR */ + mfs r3, resr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR + + /* Retrieve and store BTR */ + mfs r3, rbtr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR + + /* Calculate and store original stack pointer */ + addik r3, r1, CPU_EXCEPTION_FRAME_SIZE + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1 + + /* set parameter 1 to CPU Exception frame */ + addi r5, r1, 0 + + /* call into the debug framework */ + braid _MicroBlaze_Exception_handle + nop diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S new file mode 100644 index 0000000000..c24807c3e0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include <rtems/score/cpuimpl.h> + + .text + .globl _interrupt_handler # Interrupt Handler Label + .align 2 + + _interrupt_handler: +#ifndef __rtems__ + rtid r14, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) + + swi r5, r1, 8 + + /* Indicate unknown interrupt source */ + addi r5, r0, 0xFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/bspreset.c b/bsps/microblaze/microblaze_fpga/start/bspreset.c new file mode 100644 index 0000000000..6a7455f522 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspreset.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Reset + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems.h> +#include <bsp/bootcard.h> + +void bsp_reset( void ) +{ + __asm__ volatile ( + "brai 0xFFFFFFFFFFFFFFFF" + ); +} diff --git a/bsps/microblaze/microblaze_fpga/start/bspstart.c b/bsps/microblaze/microblaze_fpga/start/bspstart.c new file mode 100644 index 0000000000..84524d9365 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspstart.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Startup + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/irq-generic.h> + +void bsp_start( void ) +{ + microblaze_invalidate_icache(); + microblaze_enable_icache(); + + microblaze_invalidate_dcache(); + microblaze_enable_dcache(); + + bsp_interrupt_initialize(); +} diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S b/bsps/microblaze/microblaze_fpga/start/crtinit.S new file mode 100644 index 0000000000..6c7fc3af23 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bspopts.h> + + .globl _crtinit + .align 2 + .ent _crtinit + .type _crtinit, @function +_crtinit: + addi r1, r1, -20 /* Save Link register */ + swi r15, r1, 0 + +#ifndef __rtems__ + addi r6, r0, __sbss_start /* clear SBSS */ + addi r7, r0, __sbss_end + rsub r18, r6, r7 + blei r18, .Lendsbss + +.Lloopsbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopsbss +.Lendsbss: +#endif /* __rtems__ */ + +#ifndef __rtems__ + addi r6, r0, __bss_start /* clear BSS */ + addi r7, r0, __bss_end +#else + addi r6, r0, bsp_section_bss_begin + addi r7, r0, bsp_section_bss_end +#endif /* __rtems__ */ + rsub r18, r6, r7 + blei r18, .Lendbss +.Lloopbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopbss +.Lendbss: + +#ifndef __rtems__ + brlid r15, _program_init /* Initialize the program */ + nop + + brlid r15, __init /* Invoke language initialization functions */ + nop +#endif /* __rtems__ */ +#ifdef BSP_START_COPY_FDT_FROM_U_BOOT /* Boot loaders may pass the device tree in r5 */ + brlid r15, bsp_fdt_copy /* Do not touch r5 until bsp_fdt_copy() is called */ +#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */ + addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ + addi r7, r0, 0 +#ifndef __rtems__ + brlid r15, main /* Execute the program */ +#else + mfs r3, rmsr + ori r3, r3, 0x100 /* Set Exception Enable MSR flag */ + mts rmsr, r3 + brlid r15, boot_card +#endif /* __rtems__ */ + addi r5, r0, 0 + + addik r19, r3, 0 /* Save return value */ + +#ifndef __rtems__ + brlid r15, __fini /* Invoke language cleanup functions */ + nop + + brlid r15, _program_clean /* Cleanup the program */ + nop +#endif /* __rtems__ */ + + lw r15, r1, r0 /* Return back to CRT */ + + addik r3, r19, 0 /* Restore return value */ + rtsd r15, 8 + addi r1, r1, 20 + .end _crtinit diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S new file mode 100644 index 0000000000..78babf0176 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S @@ -0,0 +1,20 @@ +/****************************************************************************** +* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + .text + .globl microblaze_enable_dcache + .ent microblaze_enable_dcache + .align 2 +microblaze_enable_dcache: + /* Read the MSR register */ + mfs r8, rmsr + /* Set the interrupt enable bit */ + ori r8, r8, 0x80 + /* Save the MSR register */ + mts rmsr, r8 + /* Return */ + rtsd r15, 8 + nop + .end microblaze_enable_dcache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S new file mode 100644 index 0000000000..7de51ac230 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S @@ -0,0 +1,20 @@ +/****************************************************************************** +* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + .text + .globl microblaze_enable_icache + .ent microblaze_enable_icache + .align 2 +microblaze_enable_icache: + /* Read the MSR register */ + mfs r8, rmsr + /* Set the interrupt enable bit */ + ori r8, r8, 0x20 + /* Save the MSR register */ + mts rmsr, r8 + /* Return */ + rtsd r15, 8 + nop + .end microblaze_enable_icache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S new file mode 100644 index 0000000000..d5bf91e626 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S @@ -0,0 +1,29 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include <bspopts.h> + + .text + .globl microblaze_invalidate_dcache + .ent microblaze_invalidate_dcache + .align 2 + +microblaze_invalidate_dcache: + addik r5, r0, BSP_MICROBLAZE_FPGA_DCACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) + addik r6, r5, BSP_MICROBLAZE_FPGA_DCACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) + +L_start: + wdc r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +L_done: + rtsd r15, 8 /* Return */ + nop + + .end microblaze_invalidate_dcache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S new file mode 100644 index 0000000000..89d5fff16b --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S @@ -0,0 +1,104 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len) +* +* Invalidate a Dcache range +* +* Parameters: +* 'cacheaddr' - address in the Dcache where invalidation begins +* 'len ' - length (in bytes) worth of Dcache to be invalidated +* +* +*******************************************************************************/ + +#include <bspopts.h> + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_USE_DCACHE +#define XPAR_MICROBLAZE_USE_DCACHE 1 +#endif + +#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR +#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#define MB_HAS_WRITEBACK_SET 0 +#else +#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#endif + + .text + .globl microblaze_invalidate_dcache_range + .ent microblaze_invalidate_dcache_range + .align 2 + +microblaze_invalidate_dcache_range: +#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1) + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + + BEQI r6, L_done /* Skip loop if size is zero */ + + ADD r6, r5, r6 /* Compute end address */ + ADDIK r6, r6, -1 + + ANDI r6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align end down to cache line */ + ANDI r5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align start down to cache line */ + +#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ + +L_start: + CMPU r18, r5, r6 /* Are we at the end? */ + BLTI r18, L_done + + wdc r5, r0 + +#if defined (__arch64__ ) + addlik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */ + breai L_start /* Branch to the beginning of the loop */ +#else + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +#endif +#else + + RSUBK r6, r5, r6 + /* r6 will now contain (count of bytes - (4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) */ +L_start: + wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */ +#if defined (__arch64__ ) + addlik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) + beagei r6, L_start +#else + bneid r6, L_start + addik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) +#endif + +#endif + +L_done: + rtsd r15, 8 +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + +#else + rtsd r15, 8 + nop +#endif + .end microblaze_invalidate_dcache_range diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S new file mode 100644 index 0000000000..d75a800560 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include <bspopts.h> + + .text + .globl microblaze_invalidate_icache + .ent microblaze_invalidate_icache + .align 2 + +microblaze_invalidate_icache: + addik r5, r0, BSP_MICROBLAZE_FPGA_ICACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, BSP_MICROBLAZE_FPGA_ICACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN)) /* Compute end */ + +L_start: + wic r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +L_done: + rtsd r15, 8 /* Return */ + nop + .end microblaze_invalidate_icache
\ No newline at end of file diff --git a/bsps/microblaze/shared/cache/cache.c b/bsps/microblaze/shared/cache/cache.c new file mode 100644 index 0000000000..472f3c04f4 --- /dev/null +++ b/bsps/microblaze/shared/cache/cache.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze cache support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../../../bsps/shared/cache/cacheimpl.h" diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c b/bsps/microblaze/shared/dev/serial/uartlite.c new file mode 100644 index 0000000000..611c339371 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/irq.h> +#include <dev/serial/uartlite.h> +#include <bspopts.h> + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static void microblaze_uart_interrupt( void *arg ) +{ + rtems_termios_tty *tty = arg; + uart_lite_context *ctx = rtems_termios_get_device_context( tty ); + + while ( !XUartLite_IsReceiveEmpty( ctx->address ) ) { + char c = (char) XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); + rtems_termios_enqueue_raw_characters( tty, &c, 1 ); + } + + if ( ctx->transmitting && XUartLite_IsTransmitEmpty( ctx->address ) ) { + size_t sent = ctx->tx_queued; + ctx->transmitting = false; + ctx->tx_queued = 0; + rtems_termios_dequeue_characters( tty, sent ); + } +} +#endif + +static bool uart_first_open( + struct rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_status_code sc; +#endif + + rtems_termios_set_initial_baud( tty, ctx->initial_baud ); + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + XUartLite_EnableIntr( ctx->address ); + + sc = rtems_interrupt_handler_install( + ctx->irq, + "UART", + RTEMS_INTERRUPT_SHARED, + microblaze_uart_interrupt, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } + + ctx->tty = tty; +#endif + + return true; +} + +static void uart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_interrupt_handler_remove( 1, microblaze_uart_interrupt, tty ); +#endif +} + +#ifndef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static int uart_read_polled( rtems_termios_device_context *base ) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + + if ( XUartLite_IsReceiveEmpty( ctx->address ) ) { + return -1; + } + + return XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); +} +#endif + +static void uart_write( + rtems_termios_device_context *base, + const char *s, + size_t n +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + if ( n > 0 ) { + size_t remaining = n; + const char *p = &s[0]; + + while (!XUartLite_IsTransmitFull( ctx->address ) && remaining > 0) { + XUartLite_SendByte( ctx->address, *p ); + p++; + remaining--; + } + + ctx->transmitting = true; + ctx->tx_queued = n - remaining; + } +#else + size_t i = 0; + + for ( i = 0; i < n; ++i ) { + XUartLite_SendByte( ctx->address, s[i] ); + } +#endif +} + +const rtems_termios_device_handler microblaze_uart_fns = { + .first_open = uart_first_open, + .last_close = uart_last_close, + .write = uart_write, +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN +#else + .poll_read = uart_read_polled, + .mode = TERMIOS_POLLED +#endif +}; diff --git a/bsps/microblaze/shared/dev/serial/uartlite_l.c b/bsps/microblaze/shared/dev/serial/uartlite_l.c new file mode 100644 index 0000000000..5acbd6c505 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite_l.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.c +* @addtogroup uartlite_v3_5 +* @{ +* +* This file contains low-level driver functions that can be used to access the +* device. The user should refer to the hardware device specification for more +* details of the device operation. + +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00b rpm 04/25/02 First release +* 1.12a rpm 07/16/07 Fixed arg type for RecvByte +* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#ifndef __rtems__ +#include "xuartlite_l.h" +#else +#include <dev/serial/uartlite_l.h> +#endif /* __rtems__ */ + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the UART. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is the base address of the device +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data) +{ + while (XUartLite_IsTransmitFull(BaseAddress)); + + XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data); +} + + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the UART. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is the base address of the device +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XUartLite_RecvByte(UINTPTR BaseAddress) +{ + while (XUartLite_IsReceiveEmpty(BaseAddress)); + + return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET); +} + +/** @} */
\ No newline at end of file diff --git a/bsps/microblaze/shared/fdt/microblaze-fdt-support.c b/bsps/microblaze/shared/fdt/microblaze-fdt-support.c new file mode 100644 index 0000000000..b1d8d186c4 --- /dev/null +++ b/bsps/microblaze/shared/fdt/microblaze-fdt-support.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bspopts.h> +#include <bsp/microblaze-fdt-support.h> +#include <bsp/fdt.h> + +#include <libfdt.h> + +#ifdef BSP_START_COPY_FDT_FROM_U_BOOT +/* use external dtb provided by u-boot */ +#include <sys/param.h> + +#ifndef BSP_FDT_BLOB_SIZE_MAX +#define BSP_FDT_BLOB_SIZE_MAX 0 +#endif + +static RTEMS_ALIGNED(8) uint32_t +system_dtb[BSP_FDT_BLOB_SIZE_MAX / sizeof(uint32_t)]; + +void bsp_fdt_copy(const void *src) +{ + const volatile uint32_t *s = (const uint32_t *) src; + uint32_t *d = RTEMS_DECONST(uint32_t *, &system_dtb[0]); + + if (s != d) { + size_t m = MIN(sizeof(system_dtb), fdt_totalsize(src)); + size_t aligned_size = roundup2(m, CPU_CACHE_LINE_BYTES); + size_t n = (m + sizeof(*d) - 1) / sizeof(*d); + size_t i; + + for (i = 0; i < n; ++i) { + d[i] = s[i]; + } + + rtems_cache_flush_multiple_data_lines(d, aligned_size); + } +} +#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */ + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT +#ifndef BSP_START_COPY_FDT_FROM_U_BOOT +/* use internal bsp dtb */ +#include BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH +#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */ + +const void *bsp_fdt_get(void) +{ + return system_dtb; +} + +uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) +{ + return intr[0]; +} +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + +uint32_t try_get_prop_from_device_tree( + const char *compatible, + const char *prop_name, + uint32_t default_value +) +{ + uint32_t value = default_value; + +#ifdef BSP_MICROBLAZE_FPGA_USE_FDT + const void *fdt = bsp_fdt_get(); + int node = fdt_node_offset_by_compatible( fdt, -1, compatible ); + if ( node < 0 ) { + return default_value; + } + + const uint32_t *prop = fdt_getprop( fdt, node, prop_name, NULL ); + if ( prop == NULL ) { + return default_value; + } + + value = fdt32_to_cpu( prop[0] ); +#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */ + + return value; +} diff --git a/bsps/microblaze/shared/start/start.S b/bsps/microblaze/shared/start/start.S new file mode 100644 index 0000000000..e9aaa706e5 --- /dev/null +++ b/bsps/microblaze/shared/start/start.S @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + + XMD load *.elf error: + MicroBlaze Vector Map for standalone executables + + Address Vector type Label + ------- ----------- ------ + + # 0x00 # (-- IMM --) + # 0x04 # Reset _start1 + + # 0x08 # (-- IMM --) + # 0x0c # Software Exception _exception_handler + + # 0x10 # (-- IMM --) + # 0x14 # Hardware Interrupt _interrupt_handler + + # 0x18 # (-- IMM --) + # 0x1C # Breakpoint Exception _debug_sw_break_handler + + # 0x20 # (-- IMM --) + # 0x24 # Hardware Exception _hw_exception_handler + +*/ + + + .globl _start + .section .vectors.reset, "ax" + .align 2 + .ent _start + .type _start, @function +_start: + brai _start1 + .end _start + + .section .vectors.sw_exception, "ax" + .align 2 +_vector_sw_exception: + brai _exception_handler + + .section .vectors.interrupt, "ax" + .align 2 +_vector_interrupt: + brai _interrupt_handler + + .section .vectors.debug_sw_break, "ax" + .align 2 +_vector_debug_sw_break: + brai _debug_sw_break_handler + + .section .vectors.hw_exception, "ax" + .align 2 +_vector_hw_exception: +/* + * Hardware and software exceptions are handled identically with the MSR[EiP] + * bit differentiating them and determining which register should be used for + * return. + */ + brai _exception_handler + + .section .text + .globl _start1 + .align 2 + .ent _start1 + .type _start1, @function +_start1: + //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ + //la r2, r0, _SDA2_BASE_ + la r1, r0, _ISR_Stack_area_end-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ + + brlid r15, _crtinit /* Initialize BSS and run program */ + nop + +#ifndef __rtems__ + brlid r15, exit /* Call exit with the return value of main */ + addik r5, r3, 0 +#endif /* __rtems__ */ + + /* Control does not reach here */ + .end _start1 + +#ifndef __rtems__ +/* + _exit + Our simple _exit +*/ + .globl _exit + .align 2 + .ent _exit + .type _exit, @function +_exit: + bri 0 + .end _exit +#endif /* __rtems__ */ |