diff options
Diffstat (limited to 'bsps/microblaze/microblaze_fpga/start')
11 files changed, 414 insertions, 93 deletions
diff --git a/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S new file mode 100644 index 0000000000..872f488889 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroBlaze + * + * @brief MicroBlaze debug trap handler implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/score/cpu.h> + + .text + .globl _debug_sw_break_handler # HW Exception Handler Label + .extern _MicroBlaze_Debug_handle + .align 2 + + _debug_sw_break_handler: + /* The stack used here does not matter since debug cannot recurse */ + + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ + swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2 + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3 + swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4 + swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5 + swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6 + swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7 + swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8 + swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9 + swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10 + swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11 + swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12 + swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13 + swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14 + swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15 + swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16 + swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17 + swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18 + swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19 + swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20 + swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21 + swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22 + swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23 + swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24 + swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25 + swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26 + swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27 + swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28 + swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29 + swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30 + swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31 + + /* Retrieve and store MSR */ + mfs r3, rmsr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR + + /* Retrieve and store EAR */ + mfs r3, rear + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR + + /* Retrieve and store ESR */ + mfs r3, resr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR + + /* Retrieve and store BTR */ + mfs r3, rbtr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR + + /* Calculate and store original stack pointer */ + addik r3, r1, CPU_EXCEPTION_FRAME_SIZE + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1 + + /* set parameter 1 to CPU Exception frame */ + addi r5, r1, 0 + + /* call into the debug framework */ + braid _MicroBlaze_Debug_handle + nop diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S index 1d96b694a7..c3c05796a4 100644 --- a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -1,52 +1,103 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ +/* SPDX-License-Identifier: BSD-2-Clause */ -/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. +/** + * @file + * + * @ingroup RTEMSBSPsMicroBlaze + * + * @brief MicroBlaze exception handler implementation + */ - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ - 1. Redistributions source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - 3. Neither the name of Xilinx nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS - IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ +#include <rtems/score/cpu.h> .text .globl _exception_handler # Exception Handler Label .align 2 _exception_handler: -#ifndef __rtems__ - rtsd r17, 0 - nop -#else /* __rtems__ */ - /* Subtract stack frame */ - addik r1, r1, -52 + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ + swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2 + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3 + swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4 + swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5 + swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6 + swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7 + swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8 + swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9 + swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10 + swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11 + swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12 + swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13 + swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14 + swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15 + swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16 + swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17 + swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18 + swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19 + swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20 + swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21 + swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22 + swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23 + swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24 + swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25 + swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26 + swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27 + swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28 + swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29 + swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30 + swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31 + + /* Retrieve and store MSR */ + mfs r3, rmsr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR + + /* Retrieve and store EAR */ + mfs r3, rear + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR + + /* Retrieve and store ESR */ + mfs r3, resr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR + + /* Retrieve and store BTR */ + mfs r3, rbtr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR - swi r5, r1, 8 + /* Calculate and store original stack pointer */ + addik r3, r1, CPU_EXCEPTION_FRAME_SIZE + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1 - addi r5, r0, 0xFFFF + /* set parameter 1 to CPU Exception frame */ + addi r5, r1, 0 - braid _ISR_Handler + /* call into the debug framework */ + braid _MicroBlaze_Exception_handle nop -#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S deleted file mode 100644 index 30436a43e9..0000000000 --- a/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: - - 1. Redistributions source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - 3. Neither the name of Xilinx nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS - IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ - - .text - .globl _hw_exception_handler # HW Exception Handler Label - .align 2 - - _hw_exception_handler: -#ifndef __rtems__ - rtsd r17, 0 - nop -#else /* __rtems__ */ - /* Subtract stack frame */ - addik r1, r1, -52 - - swi r5, r1, 8 - - addi r5, r0, 0xFFFF - - braid _ISR_Handler - nop -#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S index b817503922..c24807c3e0 100644 --- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -31,6 +31,8 @@ */ +#include <rtems/score/cpuimpl.h> + .text .globl _interrupt_handler # Interrupt Handler Label .align 2 @@ -41,7 +43,7 @@ nop #else /* __rtems__ */ /* Subtract stack frame */ - addik r1, r1, -52 + addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) swi r5, r1, 8 diff --git a/bsps/microblaze/microblaze_fpga/start/bspstart.c b/bsps/microblaze/microblaze_fpga/start/bspstart.c index 0caf385b46..84524d9365 100644 --- a/bsps/microblaze/microblaze_fpga/start/bspstart.c +++ b/bsps/microblaze/microblaze_fpga/start/bspstart.c @@ -39,5 +39,11 @@ void bsp_start( void ) { + microblaze_invalidate_icache(); + microblaze_enable_icache(); + + microblaze_invalidate_dcache(); + microblaze_enable_dcache(); + bsp_interrupt_initialize(); } diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S b/bsps/microblaze/microblaze_fpga/start/crtinit.S index a9779404b2..6c7fc3af23 100644 --- a/bsps/microblaze/microblaze_fpga/start/crtinit.S +++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S @@ -30,6 +30,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include <bspopts.h> + .globl _crtinit .align 2 .ent _crtinit @@ -75,12 +77,17 @@ _crtinit: brlid r15, __init /* Invoke language initialization functions */ nop #endif /* __rtems__ */ - +#ifdef BSP_START_COPY_FDT_FROM_U_BOOT /* Boot loaders may pass the device tree in r5 */ + brlid r15, bsp_fdt_copy /* Do not touch r5 until bsp_fdt_copy() is called */ +#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */ addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ addi r7, r0, 0 #ifndef __rtems__ brlid r15, main /* Execute the program */ #else + mfs r3, rmsr + ori r3, r3, 0x100 /* Set Exception Enable MSR flag */ + mts rmsr, r3 brlid r15, boot_card #endif /* __rtems__ */ addi r5, r0, 0 diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S new file mode 100644 index 0000000000..78babf0176 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S @@ -0,0 +1,20 @@ +/****************************************************************************** +* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + .text + .globl microblaze_enable_dcache + .ent microblaze_enable_dcache + .align 2 +microblaze_enable_dcache: + /* Read the MSR register */ + mfs r8, rmsr + /* Set the interrupt enable bit */ + ori r8, r8, 0x80 + /* Save the MSR register */ + mts rmsr, r8 + /* Return */ + rtsd r15, 8 + nop + .end microblaze_enable_dcache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S new file mode 100644 index 0000000000..7de51ac230 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S @@ -0,0 +1,20 @@ +/****************************************************************************** +* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + .text + .globl microblaze_enable_icache + .ent microblaze_enable_icache + .align 2 +microblaze_enable_icache: + /* Read the MSR register */ + mfs r8, rmsr + /* Set the interrupt enable bit */ + ori r8, r8, 0x20 + /* Save the MSR register */ + mts rmsr, r8 + /* Return */ + rtsd r15, 8 + nop + .end microblaze_enable_icache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S new file mode 100644 index 0000000000..d5bf91e626 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S @@ -0,0 +1,29 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include <bspopts.h> + + .text + .globl microblaze_invalidate_dcache + .ent microblaze_invalidate_dcache + .align 2 + +microblaze_invalidate_dcache: + addik r5, r0, BSP_MICROBLAZE_FPGA_DCACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) + addik r6, r5, BSP_MICROBLAZE_FPGA_DCACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) + +L_start: + wdc r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +L_done: + rtsd r15, 8 /* Return */ + nop + + .end microblaze_invalidate_dcache diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S new file mode 100644 index 0000000000..89d5fff16b --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S @@ -0,0 +1,104 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************** +* +* +* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len) +* +* Invalidate a Dcache range +* +* Parameters: +* 'cacheaddr' - address in the Dcache where invalidation begins +* 'len ' - length (in bytes) worth of Dcache to be invalidated +* +* +*******************************************************************************/ + +#include <bspopts.h> + +#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080 +#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002 + +#ifndef XPAR_MICROBLAZE_USE_DCACHE +#define XPAR_MICROBLAZE_USE_DCACHE 1 +#endif + +#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR +#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1 +#endif + +#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#define MB_VERSION_LT_v720 +#define MB_HAS_WRITEBACK_SET 0 +#else +#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK +#endif + + .text + .globl microblaze_invalidate_dcache_range + .ent microblaze_invalidate_dcache_range + .align 2 + +microblaze_invalidate_dcache_range: +#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1) + +#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */ + mfs r9, rmsr + andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE) + mts rmsr, r10 +#endif + + BEQI r6, L_done /* Skip loop if size is zero */ + + ADD r6, r5, r6 /* Compute end address */ + ADDIK r6, r6, -1 + + ANDI r6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align end down to cache line */ + ANDI r5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align start down to cache line */ + +#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */ + +L_start: + CMPU r18, r5, r6 /* Are we at the end? */ + BLTI r18, L_done + + wdc r5, r0 + +#if defined (__arch64__ ) + addlik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */ + breai L_start /* Branch to the beginning of the loop */ +#else + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +#endif +#else + + RSUBK r6, r5, r6 + /* r6 will now contain (count of bytes - (4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) */ +L_start: + wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */ +#if defined (__arch64__ ) + addlik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) + beagei r6, L_start +#else + bneid r6, L_start + addik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) +#endif + +#endif + +L_done: + rtsd r15, 8 +#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */ + mts rmsr, r9 +#else + nop +#endif + +#else + rtsd r15, 8 + nop +#endif + .end microblaze_invalidate_dcache_range diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S new file mode 100644 index 0000000000..d75a800560 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include <bspopts.h> + + .text + .globl microblaze_invalidate_icache + .ent microblaze_invalidate_icache + .align 2 + +microblaze_invalidate_icache: + addik r5, r0, BSP_MICROBLAZE_FPGA_ICACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN)) /* Align to cache line */ + addik r6, r5, BSP_MICROBLAZE_FPGA_ICACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN)) /* Compute end */ + +L_start: + wic r5, r0 /* Invalidate the Cache */ + + cmpu r18, r5, r6 /* Are we at the end? */ + blei r18, L_done + + brid L_start /* Branch to the beginning of the loop */ + addik r5, r5, (BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */ +L_done: + rtsd r15, 8 /* Return */ + nop + .end microblaze_invalidate_icache
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