diff options
Diffstat (limited to 'bsps/m68k')
79 files changed, 27776 insertions, 0 deletions
diff --git a/bsps/m68k/av5282/headers.am b/bsps/m68k/av5282/headers.am new file mode 100644 index 0000000000..a6a9154900 --- /dev/null +++ b/bsps/m68k/av5282/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/av5282/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/av5282/include/tm27.h diff --git a/bsps/m68k/av5282/include/bsp.h b/bsps/m68k/av5282/include/bsp.h new file mode 100644 index 0000000000..a8b32e745e --- /dev/null +++ b/bsps/m68k/av5282/include/bsp.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @ingroup m68k_av5282 + * + * @brief Global BSP definitions. + */ + +/* + * av5282 BSP header file + */ + +/** + * @defgroup m68k_av5282 AV5282 Support + * + * @ingroup bsp_m68k + * + * @brief AV5282 support. + */ + +#ifndef LIBBSP_M68K_AV5282_BSP_H +#define LIBBSP_M68K_AV5282_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* externals */ + +/* constants */ + +/* miscellaneous stuff assumed to exist */ + +/* functions */ + +uint32_t get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for methods called from .S to alow dependency tracking + */ +void Init5282(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ +#endif diff --git a/bsps/m68k/av5282/include/tm27.h b/bsps/m68k/av5282/include/tm27.h new file mode 100644 index 0000000000..1e1dc77e59 --- /dev/null +++ b/bsps/m68k/av5282/include/tm27.h @@ -0,0 +1,37 @@ +/** + * @file + * + * @ingroup m68k_av5282 + * + * @brief Time Test 27 routines. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/csb360/headers.am b/bsps/m68k/csb360/headers.am new file mode 100644 index 0000000000..5c713a234d --- /dev/null +++ b/bsps/m68k/csb360/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/csb360/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/csb360/include/tm27.h diff --git a/bsps/m68k/csb360/include/bsp.h b/bsps/m68k/csb360/include/bsp.h new file mode 100644 index 0000000000..5272e17ae2 --- /dev/null +++ b/bsps/m68k/csb360/include/bsp.h @@ -0,0 +1,189 @@ +/** + * @file + * + * @ingroup m68k_csb360 + * + * @brief Global BSP definitions. + */ + +/* + * Board Support Package for CSB360 evaluation board + * BSP definitions + * + * Copyright 2004 Cogent Computer Systems + * Author: Jay Monkman <jtm@lopingdog.com> + * + * Derived from mcf5206elite BSP: + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_CSB360_BSP_H +#define LIBBSP_M68K_CSB360_BSP_H + +#include <mcf5272/mcf5272.h> + +/** + * @defgroup m68k_csb360 CSB360 Support + * + * @ingroup bsp_m68k + * + * @brief CSB360 support. + */ + + +/*** Board resources allocation ***/ +#define BSP_MEM_ADDR_SRAM 0x20000000 +#define BSP_MEM_SIZE_SRAM 4096 + +/* Location and size of sdram. Note this includes space used by + * umon. + */ +#define BSP_MEM_ADDR_SDRAM 0x00000000 +#define BSP_MEM_MASK_SDRAM 0x01ffffff +#define BSP_MEM_SIZE_SDRAM (32 * 1024 * 1024) + +/* Address to put SIM Modules */ +#define BSP_MBAR 0x10000000 + +/* Address to put SRAM */ +#define BSP_RAMBAR BSP_MEM_ADDR_SRAM + +/* Interrupt Vectors */ +#define BSP_INTVEC_INT1 65 +#define BSP_INTVEC_INT2 66 +#define BSP_INTVEC_INT3 67 +#define BSP_INTVEC_INT4 68 +#define BSP_INTVEC_TMR0 69 +#define BSP_INTVEC_TMR1 70 +#define BSP_INTVEC_TMR2 71 +#define BSP_INTVEC_TMR3 72 +#define BSP_INTVEC_UART1 73 +#define BSP_INTVEC_UART2 74 +#define BSP_INTVEC_PLIP 75 +#define BSP_INTVEC_PLIA 76 +#define BSP_INTVEC_USB0 77 +#define BSP_INTVEC_USB1 78 +#define BSP_INTVEC_USB2 79 +#define BSP_INTVEC_USB3 80 +#define BSP_INTVEC_USB4 81 +#define BSP_INTVEC_USB5 82 +#define BSP_INTVEC_USB6 83 +#define BSP_INTVEC_USB7 84 +#define BSP_INTVEC_DMA 85 +#define BSP_INTVEC_ERX 86 +#define BSP_INTVEC_ETX 87 +#define BSP_INTVEC_ENTC 88 +#define BSP_INTVEC_QSPI 89 +#define BSP_INTVEC_INT5 90 +#define BSP_INTVEC_INT6 91 +#define BSP_INTVEC_SWTO 92 + +#define BSP_INTLVL_INT1 1 +#define BSP_INTLVL_INT2 1 +#define BSP_INTLVL_INT3 1 +#define BSP_INTLVL_INT4 1 +#define BSP_INTLVL_TMR0 1 +#define BSP_INTLVL_TMR1 1 +#define BSP_INTLVL_TMR2 1 +#define BSP_INTLVL_TMR3 1 +#define BSP_INTLVL_UART1 1 +#define BSP_INTLVL_UART2 1 +#define BSP_INTLVL_PLIP 1 +#define BSP_INTLVL_PLIA 1 +#define BSP_INTLVL_USB0 1 +#define BSP_INTLVL_USB1 1 +#define BSP_INTLVL_USB2 1 +#define BSP_INTLVL_USB3 1 +#define BSP_INTLVL_USB4 1 +#define BSP_INTLVL_USB5 1 +#define BSP_INTLVL_USB6 1 +#define BSP_INTLVL_USB7 1 +#define BSP_INTLVL_DMA 1 +#define BSP_INTLVL_ERX 1 +#define BSP_INTLVL_ETX 1 +#define BSP_INTLVL_ENTC 1 +#define BSP_INTLVL_QSPI 1 +#define BSP_INTLVL_INT5 1 +#define BSP_INTLVL_INT6 1 +#define BSP_INTLVL_SWTO 1 + + + +#ifndef ASM + +#include <bspopts.h> +#include <rtems.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +struct rtems_bsdnet_ifconfig; +extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach + +/* System frequency */ +#define BSP_SYSTEM_FREQUENCY (66 * 1000 * 1000) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { register uint32_t _delay=(microseconds); \ + register uint32_t _tmp=123; \ + __asm__ volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + +/* + * Real-Time Clock Driver Table Entry + * NOTE: put this entry to the device driver table AFTER I2C bus driver! + */ +#define RTC_DRIVER_TABLE_ENTRY \ + { rtc_initialize, NULL, NULL, NULL, NULL, NULL } +extern rtems_device_driver rtc_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +); + +/* miscellaneous stuff assumed to exist */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void init5272(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/m68k/csb360/include/tm27.h b/bsps/m68k/csb360/include/tm27.h new file mode 100644 index 0000000000..5f2fd8a383 --- /dev/null +++ b/bsps/m68k/csb360/include/tm27.h @@ -0,0 +1,39 @@ +/** + * @file + * + * @ingroup m68k_csb360 + * + * @brief Time Test 27 routines. + */ + +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/gen68340/headers.am b/bsps/m68k/gen68340/headers.am new file mode 100644 index 0000000000..ca3dba2b1e --- /dev/null +++ b/bsps/m68k/gen68340/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m340timer.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m340uart.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68340.h +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68340.inc +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/m68349.inc +include_HEADERS += ../../../../../../bsps/m68k/gen68340/include/tm27.h diff --git a/bsps/m68k/gen68340/include/bsp.h b/bsps/m68k/gen68340/include/bsp.h new file mode 100644 index 0000000000..28d86ff2f7 --- /dev/null +++ b/bsps/m68k/gen68340/include/bsp.h @@ -0,0 +1,81 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief Global BSP definitions. + */ + +/* + * Board Support Package for `Generic' Motorola MC68340 + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + */ + +/* bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_GEN68340_BSP_H +#define LIBBSP_M68K_GEN68340_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup m68k_gen68340 Motorola MC68340 Support + * + * @ingroup bsp_m68k + * + * @brief Motorola MC68340 support. + */ + +/* Constants */ + +/* Structures */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Methods used across files inside the BSP + */ +int dbug_in_char( int minor ); +void dbug_out_char( int minor, int ch ); +int dbug_char_present( int minor ); +void _dbug_dumpanic(void); + +/* + * Only called from .S but prototyped here to capture the dependecy. + */ +void _Init68340 (void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/m68k/gen68340/include/m340timer.h b/bsps/m68k/gen68340/include/m340timer.h new file mode 100644 index 0000000000..892c690e5f --- /dev/null +++ b/bsps/m68k/gen68340/include/m340timer.h @@ -0,0 +1,85 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief Time driver definitions. + */ + +/* + * Header file for timer driver + * defines for accessing M68340 timer registers + * + * Author: + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __m340timer_H__ +#define __m340timer_H__ + +extern void Fifo_Full_benchmark_timer_initialize (void); + +extern void (*Restart_Fifo_Full_A_Timer)(); +extern void (*Restart_Check_A_Timer)(); +extern void (*Restart_Fifo_Full_B_Timer)(); +extern void (*Restart_Check_B_Timer)(); + +/* CR */ +#define m340_SWR (1<<15) +#define m340_Polling_Mode (0<<12) +#define m340_TC_Enabled (1<<12) +#define m340_TG_Enabled (2<<12) +#define m340_TG_TC_Enabled (3<<12) +#define m340_TO_Enabled (4<<12) +#define m340_TO_TC_Enabled (5<<12) +#define m340_TG_TG_Enabled (6<<12) +#define m340_TO_TG_TG_Enabled (7<<12) +#define m340_TGE (1<<11) +#define m340_PSE (1<<10) +#define m340_CPE (1<<9) +#define m340_CLK (1<<8) +#define m340_Divide_by_2 (1<<5) +#define m340_Divide_by_4 (2<<5) +#define m340_Divide_by_8 (3<<5) +#define m340_Divide_by_16 (4<<5) +#define m340_Divide_by_32 (5<<5) +#define m340_Divide_by_64 (6<<5) +#define m340_Divide_by_128 (7<<5) +#define m340_Divide_by_256 (0<<5) +#define m340_ICOC (0<<2) +#define m340_SWG (1<<2) +#define m340_VDCSWG (2<<2) +#define m340_VWSSPG (3<<2) +#define m340_PWM (4<<2) +#define m340_PM (5<<2) +#define m340_EC (6<<2) +#define m340_TB (7<<2) +#define m340_Disabled 0 +#define m340_Toggle_Mode 1 +#define m340_Zero_Mode 2 +#define m340_One_Mode 3 + +/* SR */ +#define m340_IRQ (1<<15) +#define m340_TO (1<<14) +#define m340_TG (1<<13) +#define m340_TC (1<<12) +#define m340_TGL (1<<11) +#define m340_ON (1<<10) +#define m340_OUT (1<<9) +#define m340_COM (1<<8) + +#endif diff --git a/bsps/m68k/gen68340/include/m340uart.h b/bsps/m68k/gen68340/include/m340uart.h new file mode 100644 index 0000000000..619a732a14 --- /dev/null +++ b/bsps/m68k/gen68340/include/m340uart.h @@ -0,0 +1,162 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief UART console driver definitions. + */ + +/* + * Header file for console driver + * defines for accessing M68340/68349 UART registers + * + * Author: + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __m340uart_H__ +#define __m340uart_H__ + +/* UART initialisation */ +#define UART_CHANNEL_A 0 +#define UART_CHANNEL_B 1 +#define UART_NUMBER_OF_CHANNELS 2 +#define UART_CONSOLE_NAME "/dev/console" +#define UART_RAW_IO_NAME "/dev/tty1" +#define UART_FIFO_FULL 0 +#define UART_CRR 1 +#define UART_INTERRUPTS 0 +#define UART_POLLING 1 +#define UART_TERMIOS_CONSOLE 0 +#define UART_TERMIOS_RAW 1 +#define UART_TERMIOS_MIN_DEFAULT 1 +#define UART_TERMIOS_TIME_DEFAULT 0 + +void Init_UART_Table(void); + +typedef struct { + uint8_t enable; + uint16_t rx_buffer_size; /* NOT IMPLEMENTED */ + uint16_t tx_buffer_size; /* NOT IMPLEMENTED */ + } uart_termios_config; + +typedef struct { /* for one channel */ + uint8_t enable; /* use this channel */ + char name[64]; /* use UART_CONSOLE_NAME for console purpose */ + uint8_t parity_mode; /* parity mode, see MR1 section for defines */ + uint8_t bits_per_char; /* bits per character, see MR1 section for defines */ + float rx_baudrate; /* Rx baudrate */ + float tx_baudrate; /* Tx baudrate */ + uint8_t rx_mode; /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */ + uint8_t mode; /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */ + uart_termios_config termios; + } uart_channel_config; + +extern uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS]; + +typedef struct { + int set; /* number of the m340 baud speed set */ + int rcs; /* RCS for the needed baud set */ + int tcs; /* TCS for the needed baud set */ + } t_baud_speed; + +typedef struct { + t_baud_speed baud_speed_table[2]; + short nb; + } t_baud_speed_table; + +extern t_baud_speed_table +Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t enableA, + float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t enableB); + +extern rtems_isr InterruptHandler (rtems_vector_number v); + +extern int dbugRead (int minor); +extern ssize_t dbugWrite (int minor, const char *buf, size_t len); + +extern float m340_Baud_Rates_Table[16][2]; + +/* SR */ +#define m340_Rx_RDY 1 +#define m340_FFULL (1<<1) +#define m340_Tx_RDY (1<<2) +#define m340_TxEMP (1<<3) +#define m340_OE (1<<4) +#define m340_PE (1<<5) +#define m340_FE (1<<6) +#define m340_RB (1<<7) + +/* IER */ +#define m340_TxRDYA 1 +#define m340_RxRDYA (1<<1) +#define m340_TxRxRDYA 0x3 +#define m340_TxRDYB (1<<4) +#define m340_RxRDYB (1<<5) +#define m340_TxRxRDYB 0x30 + +/* CR */ +#define m340_Reset_Error_Status 0x40 +#define m340_Reset_Receiver 0x20 +#define m340_Reset_Transmitter 0x30 +#define m340_Transmitter_Enable (1<<2) +#define m340_Receiver_Enable 1 +#define m340_Transmitter_Disable (2<<2) +#define m340_Receiver_Disable 2 + +/* ACR */ +#define m340_BRG_Set1 0 +#define m340_BRG_Set2 (1<<7) + +/* OPCR */ +#define m340_OPCR_Gal 0x0 +#define m340_OPCR_Aux 0xFF + +/* ISR */ +#define m340_COS (1<<7) +#define m340_DBB (1<<6) +#define m340_XTAL_RDY (1<<3) +#define m340_DBA (1<<2) + +/* MR1 */ +#define m340_RxRTS (1<<7) +#define m340_R_F (1<<6) /* character or block mode */ +#define m340_ERR (1<<5) +#define m340_RxRTX (1<<7) +#define m340_Even_Parity 0 +#define m340_Odd_Parity (1<<2) +#define m340_Low_Parity (2<<2) +#define m340_High_Parity (3<<2) +#define m340_No_Parity (4<<2) +#define m340_Data_Character (6<<2) +#define m340_Address_Character (7<<2) +#define m340_5bpc 0x0 +#define m340_6bpc 0x1 +#define m340_7bpc 0x2 +#define m340_8bpc 0x3 + +/* MR2 */ +#define m340_normal (0<<6) +#define m340_automatic_echo (1<<6) +#define m340_local_loopback (2<<6) +#define m340_remote_loopback (3<<6) +#define m340_TxRTS (1<<5) +#define m340_TxCTS (1<<4) + +/* Baud rates for Transmitter/Receiver */ +#define SCLK 1 /* put your own SCLK value here */ + +#endif diff --git a/bsps/m68k/gen68340/include/m68340.h b/bsps/m68k/gen68340/include/m68340.h new file mode 100644 index 0000000000..37440f3098 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68340.h @@ -0,0 +1,145 @@ +/** + * @file + * + * @ingroup m68k_gen68340 + * + * @brief MC68430 definitions. + */ + +/********************************************************************** + * MC68340 C Header File * + * * + * Developed by : Motorola * + * High Performance Embedded Systems Division * + * Austin, TX * + * Rectified by : Geoffroy Montel + * g_montel@yahoo.com * + * * + **********************************************************************/ + +typedef volatile unsigned char * portb; /* 8-bit port */ +typedef volatile unsigned short * portw; /* 16-bit port */ +typedef volatile unsigned int * portl; /* 32-bit port */ + +#define MBASE 0xEFFFF000 /* Module Base Address */ + /* not EFFFF000 due to a 68349 + hardware incompatibility */ + +#define MBAR (*(portb) 0x0003FF00) /* Module Base Addr Reg */ +#define MBAR1 (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */ +#define MBAR2 (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */ + +/* System Integration Module */ + +#define SIMMCR (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg */ +#define SIMSYNCR (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */ +#define SIMAVR (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg */ +#define SIMRSR (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg */ +#define SIMPORTA (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg */ +#define SIMDDRA (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg */ +#define SIMPPRA1 (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */ +#define SIMPPRA2 (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */ +#define SIMPORTB (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg */ +#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg */ +#define SIMDDRB (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg */ +#define SIMPPARB (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg */ +#define SIMSWIV (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector */ +#define SIMSYPCR (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */ +#define SIMPICR (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */ +#define SIMPITR (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg */ +#define SIMSWSR (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */ + +#define SIMCS0AM (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk */ +#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */ +#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */ +#define SIMCS0BA (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr */ +#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */ +#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */ +#define SIMCS1AM (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */ +#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */ +#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */ +#define SIMCS1BA (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr */ +#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */ +#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */ +#define SIMCS2AM (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk */ +#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */ +#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */ +#define SIMCS2BA (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr */ +#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */ +#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */ +#define SIMCS3AM (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk */ +#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */ +#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */ +#define SIMCS3BA (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr */ +#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */ +#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */ + +/* Dynamic Memory Access (DMA) Module */ + +#define DMAMCR1 (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1 */ +#define DMAINTR1 (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1 */ +#define DMACCR1 (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1 */ +#define DMACSR1 (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */ +#define DMAFCR1 (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1 */ +#define DMASAR1 (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1 */ +#define DMADAR1 (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1 */ +#define DMABTC1 (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */ + +#define DMAMCR2 (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2 */ +#define DMAINTR2 (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2 */ +#define DMACCR2 (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2 */ +#define DMACSR2 (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */ +#define DMAFCR2 (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1 */ +#define DMASAR2 (*(portl) (MBASE+0x07AC)) /* DMA Source Addr Reg 2 */ +#define DMADAR2 (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2 */ +#define DMABTC2 (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */ + +/* Dual Serial Module */ + +#define DUMCRH (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg */ +#define DUMCRL (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg */ +#define DUILR (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level */ +#define DUIVR (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector */ +#define DUMR1A (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A */ +#define DUSRA (*(portb) (MBASE+0x0711)) /* DUART Status Reg A */ +#define DUCSRA (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A */ +#define DUCRA (*(portb) (MBASE+0x0712)) /* DUART Command Reg A */ +#define DURBA (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A */ +#define DUTBA (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */ +#define DUIPCR (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */ +#define DUACR (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */ +#define DUISR (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */ +#define DUIER (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg */ + +#define DUMR1B (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B */ +#define DUSRB (*(portb) (MBASE+0x0719)) /* DUART Status Reg B */ +#define DUCSRB (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B */ +#define DUCRB (*(portb) (MBASE+0x071A)) /* DUART Command Reg B */ +#define DURBB (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B */ +#define DUTBB (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */ +#define DUIP (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg */ +#define DUOPCR (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg */ +#define DUOPBS (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set */ +#define DUOPBR (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst */ +#define DUMR2A (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A */ +#define DUMR2B (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B */ + +/* Dual Timer Module */ + +#define TMCR1 (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */ +#define TIR1 (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1 */ +#define TCR1 (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1 */ +#define TSR1 (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1 */ +#define TCNTR1 (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1 */ +#define WPREL11 (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1 */ +#define WPREL21 (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1 */ +#define TCOM1 (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1 */ + +#define TMCR2 (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */ +#define TIR2 (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2 */ +#define TCR2 (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2 */ +#define TSR2 (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2 */ +#define TCNTR2 (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2 */ +#define WPREL12 (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2 */ +#define WPREL22 (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2 */ +#define TCOM2 (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2 */ diff --git a/bsps/m68k/gen68340/include/m68340.inc b/bsps/m68k/gen68340/include/m68340.inc new file mode 100644 index 0000000000..5c1ba36799 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68340.inc @@ -0,0 +1,148 @@ +/*---------------------------------------------------------------------------- +* file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT +* +* MC68340 BCC Board Support Package +* +* date: 1/12/1993 +* +* Copyright 1989, Ready Systems FRANCE +* +* Supports: VRTX32 and RTscope +* +* Related Board: MOTOROLA BCC M68340 +* +* Description: EQUATES FOR 68340 DEVICES +* +* Changes: +* - Geoffroy Montel (g_montel@yahoo.com) : +* changed EQU syntax for GNU as +* +*----------------------------------------------------------------------------*/ + +/************************************************ + * ATTENTION: must match defs. in C header file * + ************************************************/ + +/* -- SIM equates -- system integration module */ +.equ BASE_REG, 0x3FF00 +.equ BASE_SIM, 0xEFFFF000 +.equ SIM_MCR, 0x000 /* module configuration register */ +.equ SIM_SYNCR, 0x004 /* clock synthesizer control register */ +.equ SIM_AVR, 0x006 /* autovector register */ +.equ SIM_RSR, 0x007 /* reset status register */ + +/* -- Port A -- */ +.equ SIM_PORTA, 0x011 /* port A data */ +.equ SIM_DDRA, 0x013 /* port A direction data */ +.equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */ +.equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */ + +/* -- Port B -- */ +.equ SIM_PORTB, 0x019 /* port B data */ +.equ SIM_PORTB1, 0x01B /* port B data auxiliary */ +.equ SIM_DDRB, 0x01D /* port B direction data */ +.equ SIM_PPRB, 0x01F /* Port B pin assignement */ +.equ SIM_SWIV, 0x020 /* SW interrupt vector */ +.equ SIM_SYPCR, 0x021 /* System protection control register */ +.equ SIM_PICR, 0x022 /* Periodic interrupt control register */ +.equ SIM_PITR, 0x024 /* Periodic interrupt timing register */ +.equ SIM_SWSR, 0x027 /* Sofware service */ + +/* -- Chip select -- */ +.equ SIM_MASKH0, 0x040 /* mask register CS0 */ +.equ SIM_MASKL0, 0x042 /* mask register CS0 */ +.equ SIM_ADDRH0, 0x044 /* base address CS0 */ +.equ SIM_ADDRL0, 0x046 /* base address CS0 */ +.equ SIM_MASKH1, 0x048 /* mask register CS1 */ +.equ SIM_MASKL1, 0x04A /* mask register CS1 */ +.equ SIM_ADDRH1, 0x04C /* base address CS1 */ +.equ SIM_ADDRL1, 0x04E /* base address CS1 */ +.equ SIM_MASKH2, 0x050 /* mask register CS2 */ +.equ SIM_MASKL2, 0x052 /* mask register CS2 */ +.equ SIM_ADDRH2, 0x054 /* base address CS2 */ +.equ SIM_ADDRL2, 0x056 /* base address CS2 */ +.equ SIM_MASKH3, 0x058 /* mask register CS3 */ +.equ SIM_MASKL3, 0x05A /* mask register CS3 */ +.equ SIM_ADDRH3, 0x05C /* base address CS3 */ +.equ SIM_ADDRL3, 0x05E /* base address CS3 */ + +/* -- TIMERS equates -- */ + +/* __ TIMER 0 */ +.equ TIM_MCR0, 0x600 /* Module configuration register */ +.equ TIM_IR0, 0x604 /* interrupt register */ +.equ TIM_CR0, 0x606 /* controle register */ +.equ TIM_SR0, 0x608 /* Status/prescaler register */ +.equ TIM_CNTR0, 0x60A /* counter register */ +.equ TIM_PREL10, 0x60C /* Preload register 1 */ +.equ TIM_PREL20, 0x60E /* Preload register 2 */ +.equ TIM_COM0, 0x610 /* Compare register */ + +/* __ TIMER 1 */ + +.equ TIM_MCR1, 0x640 /* Module configuration register */ +.equ TIM_IR1, 0x644 /* interrupt register */ +.equ TIM_CR1, 0x646 /* controle register */ +.equ TIM_SR1, 0x648 /* Status/prescaler register */ +.equ TIM_CNTR1, 0x64A /* counter register */ +.equ TIM_PREL11, 0x64C /* Preload register 1 */ +.equ TIM_PREL21, 0x64E /* Preload register 2 */ +.equ TIM_COM1, 0x650 /* Compare register */ + +/* -- U.A.R.T. equates -- */ + +.equ UA_MCRH, 0x700 /* module configuration register */ +.equ UA_MCRL, 0x701 /* module configuration register */ +.equ UA_ILR, 0x704 /* Interrupt level */ +.equ UA_IVR, 0x705 /* Interrupt vector */ +.equ UA_MR1A, 0x710 /* Mode register 1 A */ +.equ UA_MR2A, 0x720 /* Mode register 2 A*/ +.equ UA_CSRA, 0x711 /* Clock_select register A */ +.equ UA_SRA, 0x711 /* status register A */ +.equ UA_CRA, 0x712 /* command register A */ +.equ UA_RBA, 0x713 /* receive buffer A */ +.equ UA_TBA, 0x713 /* transmit buffer A */ +.equ UA_IPCR, 0x714 /* input port change register */ +.equ UA_ACR, 0x714 /* auxiliary control register */ +.equ UA_ISR, 0x715 /* interrupt status register */ +.equ UA_IER, 0x715 /* interrupt enable register */ +.equ UA_MR1B, 0x718 /* Mode register 1 B */ +.equ UA_MR2B, 0x721 /* Mode register 2 B */ +.equ UA_CSRB, 0x719 /* Clock_select register B */ +.equ UA_SRB, 0x719 /* status register B */ +.equ UA_CRB, 0x71A /* command register A */ +.equ UA_RBB, 0x71B /* receive buffer A */ +.equ UA_TBB, 0x71B /* transmit buffer A */ +.equ UA_IP, 0x71D /* Input port register */ +.equ UA_OPCR, 0x71D /* output port control register */ +.equ UA_OPS, 0x71E /* output port bit set */ +.equ UA_OPR, 0x71F /* output port bit reset */ +.equ TX_A_EN, 0x01 /* Tx A irq enable */ +.equ TX_B_EN, 0x10 /* Tx B irq enable */ +.equ TX_A_DIS, 0xFE /* Tx A irq enable */ +.equ TX_B_DIS, 0xEF /* Tx B irq enable */ +.equ TX_AB_DIS, 0x22 + +/* -- DMA equates -- */ +.equ DMA_MCR0, 0x780 /* module configuration register */ +.equ DMA_IR0, 0x784 /* Interrupt register */ +.equ DMA_CCR0, 0x788 /* Channel control register */ +.equ DMA_CSR0, 0x78A /* Channel status register */ +.equ DMA_FCR0, 0x78B /* Function code register */ +.equ DMA_SARH0, 0x78C /* Source adresse register */ +.equ DMA_SARL0, 0x78E /* Source adresse register */ +.equ DMA_DARH0, 0x790 /* destination adresse register */ +.equ DMA_DARL0, 0x792 /* destination adresse register */ +.equ DMA_BTCH0, 0x794 /* byte transfer register */ +.equ DMA_BTCL0, 0x796 /* byte transfer register */ +.equ DMA_MCR1, 0x7A0 /* module configuration register */ +.equ DMA_IR1, 0x7A4 /* Interrupt register */ +.equ DMA_CCR1, 0x7A8 /* Channel control register */ +.equ DMA_CSR1, 0x7AA /* Channel status register */ +.equ DMA_FCR1, 0x7AB /* Function code register */ +.equ DMA_SARH1, 0x7AC /* Source adresse register */ +.equ DMA_SARL1, 0x7AE /* Source adresse register */ +.equ DMA_DARH1, 0x7B0 /* destination adresse register */ +.equ DMA_DARL1, 0x7B2 /* destination adresse register */ +.equ DMA_BTCH1, 0x7B4 /* byte transfer register */ +.equ DMA_BTCL1, 0x7B6 /* byte transfer register */ diff --git a/bsps/m68k/gen68340/include/m68349.inc b/bsps/m68k/gen68340/include/m68349.inc new file mode 100644 index 0000000000..4e3ce53d29 --- /dev/null +++ b/bsps/m68k/gen68340/include/m68349.inc @@ -0,0 +1,410 @@ +/*---------------------------------------------------------------------------- + * file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT + * + * MC68349 BCC Board Support Package + * + * date: 31/07/97 + * + * Description: EQUATES FOR 68349 DEVICES + * + * Modifications: + * - adapted for GNU CC by G.Montel 26/05/98 + *----------------------------------------------------------------------------*/ + +| -- SIM equates -- + +.equ BASE_REG, 0x3FF00 +.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK + +.equ SIM_MCR, 0x000 | module configuration register +.equ SIM_IDR, 0x002 | processor identification register +.equ SIM_SYNCR, 0x004 | clock synthesizer control register +.equ SIM_AVR, 0x006 | autovector register +.equ SIM_RSR, 0x007 | reset status register + +| -- Port A +.equ SIM_PORTA, 0x011 | port A data +.equ SIM_DDRA, 0x013 | port A direction data +.equ SIM_PPRA1, 0x015 | Port A pin assignement 1 +.equ SIM_PPRA2, 0x017 | Port A pin assignement 2 + +| -- Port B +.equ SIM_PORTB, 0x019 | port B data +.equ SIM_PORTB1, 0x01B | port B data auxiliary +.equ SIM_DDRB, 0x01D | port B direction data +.equ SIM_PPRB, 0x01F | Port B pin assignement + +.equ SIM_SWIV, 0x020 | SW interrupt vector +.equ SIM_SYPCR, 0x021 | System protection control register +.equ SIM_PICR, 0x022 | Periodic interrupt control register +.equ SIM_PITR, 0x024 | Periodic interrupt timing register +.equ SIM_SWSR, 0x027 | Sofware service + +| -- Chip select +.equ SIM_MASKH0, 0x040 | mask register CS0 +.equ SIM_MASKL0, 0x042 | mask register CS0 +.equ SIM_ADDRH0, 0x044 | base address CS0 +.equ SIM_ADDRL0, 0x046 | base address CS0 + +.equ SIM_MASKH1, 0x048 | mask register CS1 +.equ SIM_MASKL1, 0x04A | mask register CS1 +.equ SIM_ADDRH1, 0x04C | base address CS1 +.equ SIM_ADDRL1, 0x04E | base address CS1 + +.equ SIM_MASKH2, 0x050 | mask register CS2 +.equ SIM_MASKL2, 0x052 | mask register CS2 +.equ SIM_ADDRH2, 0x054 | base address CS2 +.equ SIM_ADDRL2, 0x056 | base address CS2 + +.equ SIM_MASKH3, 0x058 | mask register CS3 +.equ SIM_MASKL3, 0x05A | mask register CS3 +.equ SIM_ADDRH3, 0x05C | base address CS3 +.equ SIM_ADDRL3, 0x05E | base address CS3 + +| -- TIMERS equates -- + +| __ TIMER 0 + +.equ TIM_MCR0, 0x600 | Module configuration register +.equ TIM_IR0, 0x604 | interrupt register +.equ TIM_CR0, 0x606 | controle register +.equ TIM_SR0, 0x608 | Status/prescaler register +.equ TIM_CNTR0, 0x60A | counter register +.equ TIM_PREL10, 0x60C | Preload register 1 +.equ TIM_PREL20, 0x60E | Preload register 2 +.equ TIM_COM0, 0x610 | Compare register + +| __ TIMER 1 + +.equ TIM_MCR1, 0x640 | Module configuration register +.equ TIM_IR1, 0x644 | interrupt register +.equ TIM_CR1, 0x646 | controle register +.equ TIM_SR1, 0x648 | Status/prescaler register +.equ TIM_CNTR1, 0x64A | counter register +.equ TIM_PREL11, 0x64C | Preload register 1 +.equ TIM_PREL21, 0x64E | Preload register 2 +.equ TIM_COM1, 0x650 | Compare register + +| -- U.A.R.T. equates -- + +.equ UA_MCRH, 0x700 | module configuration register +.equ UA_MCRL, 0x701 | module configuration register +.equ UA_ILR, 0x704 | Interrupt level +.equ UA_IVR, 0x705 | Interrupt vector + +.equ UA_MR1A, 0x710 | Mode register 1 A +.equ UA_MR2A, 0x720 | Mode register 2 A +.equ UA_CSRA, 0x711 | Clock_select regiter A +.equ UA_SRA, 0x711 | status register A +.equ UA_CRA, 0x712 | command register A +.equ UA_RBA, 0x713 | receive buffer A +.equ UA_TBA, 0x713 | transmit buffer A + +.equ UA_IPCR, 0x714 | input port change register +.equ UA_ACR, 0x714 | auxiliary control register +.equ UA_ISR, 0x715 | interrupt status register +.equ UA_IER, 0x715 | interrupt enable register + +.equ UA_MR1B, 0x718 | Mode register 1 B +.equ UA_MR2B, 0x721 | Mode register 2 B +.equ UA_CSRB, 0x719 | Clock_select regiter B +.equ UA_SRB, 0x719 | status register B +.equ UA_CRB, 0x71A | command register A +.equ UA_RBB, 0x71B | receive buffer A +.equ UA_TBB, 0x71B | transmit buffer A + +.equ UA_IP, 0x71D | Input port register +.equ UA_OPCR, 0x71D | output port control register +.equ UA_OPS, 0x71E | output port bit set +.equ UA_OPR, 0x71F | output port bit reset +.equ TX_A_EN, 0x01 | Tx A irq enable +.equ TX_B_EN, 0x10 | Tx B irq enable +.equ TX_A_DIS, 0xFE | Tx A irq enable +.equ TX_B_DIS, 0xEF | Tx B irq enable +.equ TX_AB_DIS, 0x22 + + +| -- DMA equates +.equ DMA_MCR0, 0x780 | module configuration register +.equ DMA_IR0, 0x784 | Interrupt register +.equ DMA_CCR0, 0x788 | Channel control register +.equ DMA_CSR0, 0x78A | Channel status register +.equ DMA_FCR0, 0x78B | Function code register +.equ DMA_SARH0, 0x78C | Source adresse register +.equ DMA_SARL0, 0x78E | Source adresse register +.equ DMA_DARH0, 0x790 | destination adresse register +.equ DMA_DARL0, 0x792 | destination adresse register +.equ DMA_BTCH0, 0x794 | byte transfer register +.equ DMA_BTCL0, 0x796 | byte transfer register + +.equ DMA_MCR1, 0x7A0 | module configuration register +.equ DMA_IR1, 0x7A4 | Interrupt register +.equ DMA_CCR1, 0x7A8 | Channel control register +.equ DMA_CSR1, 0x7AA | Channel status register +.equ DMA_FCR1, 0x7AB | Function code register +.equ DMA_SARH1, 0x7AC | Source adresse register +.equ DMA_SARL1, 0x7AE | Source adresse register +.equ DMA_DARH1, 0x7B0 | destination adresse register +.equ DMA_DARL1, 0x7B2 | destination adresse register +.equ DMA_BTCH1, 0x7B4 | byte transfer register +.equ DMA_BTCL1, 0x7B6 | byte transfer register + +| -- cache equates +.equ CACHE_MCR, 0xFC0 | cache config reg. (long) + +| -- quad data memory module (QDMM) equates +.equ QDMM_MCR, 0xC00 | QDMM config reg (long) +.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long) +.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long) +.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long) +.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long) + + + +|----------------------------------------------------- +| AST68349 internal registers +|----------------------------------------------------- +.equ EPLD_SPACE, 3 | "reserved user" space +.equ CPU_SPACE, 7 | "CPU" space + +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| +| GLUE EPLD +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| + +.equ GLUE_EPLD, 0xB0000000 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of /CS0 : +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena|val|wid| ws|b31|b30|b29|b28| +| +---+---+---+---+---+---+---+---+ +| +| b[31..28] : base address for decoding /CS[3..0] +| the decoding is as follow : +| +| +----------+------------+------+ +| | a[31..28] | a[27..26] | /CS | +| +-----------+-----------+------+ +| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes +| | b[31..28] | 01 | /CS1 | +| | b[31..28] | 10 | /CS2 | +| | b[31..28] | 11 | /CS3 | +| +-----------------------+------+ +| +| after /RESET, /CS0 is validated for every cycle, until programmed +| +| ws : number of wait-states : 0 => 0 ws +| 1 => external /dsackx +| wid : width of chip-select : 0 => 16 bits +| 1 => 32 bits +| ena : enable chip-select : 0 => disabled +| 1 => enabled +| +| val : automatic validation. set after reset +| cleared when /CS0 is configured +| +.equ REG_CS0, 0 + + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of /CS1 to /CS3: +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x |wid| ws| x | x | x | x | +| +---+---+---+---+---+---+---+---+ +| +| ws : number of wait-states : 0 => 0 ws +| 1 => external /dsackx +| wid : width of chip-select : 0 => 16 bits +| 1 => 32 bits +| ena : enable chip-select : 0 => disabled +| 1 => enabled +.equ REG_CS1, 1 +.equ REG_CS2, 2 +.equ REG_CS3, 3 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| I2C register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+----+ +| | x | x | x | x | x | x |clk|data| +| +---+---+---+---+---+---+---+----+ +| bidirecionnal pin, open drain output. +| set bit to 1 to read external state of pin +| +.equ REG_I2C, 4 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| PDCS register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1| +| +---+---+---+---+---+---+---+---+ +| pd[5..1] : value read on the DRAM module +| S12, S11 and S14 : "user reserved" configuration switch +| +.equ REG_PDCS, 5 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| timer1 register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x | d1| d0| +| +---+---+---+---+---+---+---+---+ +| +| the timer clock is the 1000Hz clock of the ASTECC platform +| the timer is reloaded on each write to the register, or if the input +| TIN1 is set to 0. +| on overflow, the open drain output TOUT1 is set to 0 +| the timer must be disabled to return TOUT1 to the inactive state +| +.equ REG_TIMER1, 6 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| timer2 register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x | d1| d0| +| +---+---+---+---+---+---+---+---+ +| the timer clock is the 1000Hz clock of the ASTECC platform +| the timer is reloaded on each write to the register, or if the input +| TIN2 is set to 0. +| on overflow, the open drain output TOUT2 is set to 0 +| the timer must be disabled to return TOUT2 to the inactive state +| +.equ REG_TIMER2, 7 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| baudrate generator register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x | d2| d1| d0| +| +---+---+---+---+---+---+---+---+ +| +| d[2..0] : divider of a 3.6864 Mhz clock +| +| d[2..0] : 0 1 2 3 4 5 6 7 +| divides by : 2 4 6 8 10 12 14 16 +| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304 +| baudrate : 115200 57600 38400 28800 x 19200 x 14400 +| +.equ REG_BAUDRATE, 8 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x |io4|io3|io2|io1|io0| +| +---+---+---+---+---+---+---+---+ +| +| io[4..0] : data written to port +| +| maximum current load is about 5 mA per pin +| +.equ REG_IO, 9 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO port +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x |io4|io3|io2|io1|io0| +| +---+---+---+---+---+---+---+---+ +| +| io[4..0] : data read from port +| +.equ REG_IO_PORT, 10 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| IO direction register +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x |dr2|dr1|dr0| +| +---+---+---+---+---+---+---+---+ +| +| dr0 : 0 => io port 0 is configured as input (default after /RESET) +| 1 => io port 0 is configured as output +| +| dr1 : 0 => io port 1 is configured as input (default after /RESET) +| 1 => io port 1 is configured as output +| +| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET) +| 1 => io ports 2 to 4 are configured as output +| +.equ REG_DIR_IO, 11 + + + + +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| +| DRAM EPLD +|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| + +.equ DRAM_EPLD, 0xA0000000 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| number of wait-state for DRAM +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x | x |ws1|ws0| +| +---+---+---+---+---+---+---+---+ +| +| ws[1..0] : 0 1 2 3 +| wait states : 0 1 2 3 +| +.equ REG_WS, 0 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of refresh for DRAM +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |ena| x | x | x | x | x |rf1|rf0| +| +---+---+---+---+---+---+---+---+ +| +| rf[1..0] : 0 1 2 3 +| refresh : 5µs 10µs 15µs 20µs +| +| ena == 0 : refresh disabled +| ena == 1 : refresh enabled +| +.equ REG_REFRESH, 1 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| configuration of DRAM module size +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| | x | x | x | x | x |sz2|sz1|sz0| +| +---+---+---+---+---+---+---+---+ +| +| sz[2..0] : 0 1 2 3 4 5 6 7 +| size (Mbytes): 4 8 16 32 64 128 0 0 +| +.equ REG_CONFIG, 2 + +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| bus width of /CS0 during reset bw[1..0] : 0 1 2 3 +| bus width : 32 16 8 ext. /dsackx +| +| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) +| : sel == 1 => EPLD chip_selects (/CS[3..0]) +| +| 7 6 5 4 3 2 1 0 +| +---+---+---+---+---+---+---+---+ +| |bw1|bw0| x | x | x | x | x |sel| +| +---+---+---+---+---+---+---+---+ +| +.equ REG_BUSWIDTH, 3 + diff --git a/bsps/m68k/gen68340/include/tm27.h b/bsps/m68k/gen68340/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/m68k/gen68340/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/m68k/gen68360/headers.am b/bsps/m68k/gen68360/headers.am new file mode 100644 index 0000000000..be0ec17252 --- /dev/null +++ b/bsps/m68k/gen68360/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/gen68360/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/gen68360/include/tm27.h diff --git a/bsps/m68k/gen68360/include/bsp.h b/bsps/m68k/gen68360/include/bsp.h new file mode 100644 index 0000000000..0c6a94066c --- /dev/null +++ b/bsps/m68k/gen68360/include/bsp.h @@ -0,0 +1,111 @@ +/** + * @file + * + * @ingroup gen68360_bsp + * + * @brief Board Support Package for `Generic' Motorola MC68360 + */ + +/* + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + */ + +/* bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_GEN68360_BSP_H +#define LIBBSP_M68K_GEN68360_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gen68360_bsp Network driver + * + * @ingroup m68k_gen68360 + * + * @brief Network driver configuration + */ + +struct rtems_bsdnet_ifconfig; +extern int rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "scc1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_scc1_driver_attach + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +void M360ExecuteRISC( uint16_t command ); +void *M360AllocateBufferDescriptors( int count ); +void *M360AllocateRiscTimers( int count ); +extern char M360DefaultWatchdogFeeder; + +extern int m360_clock_rate; /* BRG clock rate, defined in console.c */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB) + */ +#define ATLASHSB_ESR 0x20010000L +#define ATLASHSB_USICR 0x20010001L +#define ATLASHSB_DSRR 0x20010002L +#define ATLASHSB_LED4 0x20010004L +#define ATLASHSB_ROM_U6 0xFF080000L /* U6 flash ROM socket */ + + +/* + * definitions for PGH360 board + */ +#if defined(PGH360) +/* + * logical SPI addresses of SPI slaves available + */ +#define PGH360_SPI_ADDR_EEPROM 0 +#define PGH360_SPI_ADDR_DISP4_DATA 1 +#define PGH360_SPI_ADDR_DISP4_CTRL 2 + +/* + * Port B bit locations of SPI slave selects + */ +#define PGH360_PB_SPI_DISP4_RS_MSK (1<<15) +#define PGH360_PB_SPI_DISP4_CE_MSK (1<<14) +#define PGH360_PB_SPI_EEP_CE_MSK (1<< 0) +#endif /* defined(PGH360) */ + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void _Init68360(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/gen68360/include/tm27.h b/bsps/m68k/gen68360/include/tm27.h new file mode 100644 index 0000000000..c71eed3897 --- /dev/null +++ b/bsps/m68k/gen68360/include/tm27.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup m68k_tm27 + * + * @brief Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup m68k_tm27 Stuff for Time Test 27 + * + * @ingroup m68k_gen68360 + * + * @brief Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/genmcf548x/headers.am b/bsps/m68k/genmcf548x/headers.am new file mode 100644 index 0000000000..80752c512e --- /dev/null +++ b/bsps/m68k/genmcf548x/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/m68k/genmcf548x/include/bsp/irq.h diff --git a/bsps/m68k/genmcf548x/include/bsp.h b/bsps/m68k/genmcf548x/include/bsp.h new file mode 100644 index 0000000000..77a7bca0e8 --- /dev/null +++ b/bsps/m68k/genmcf548x/include/bsp.h @@ -0,0 +1,134 @@ +/** + * @file + * + * @ingroup m68k_genmcf548x + * + * @brief Global BSP definitions. + */ + +/*===============================================================*\ +| Project: RTEMS generic mcf548x BSP | ++-----------------------------------------------------------------+ +| File: bsp.h | ++-----------------------------------------------------------------+ +| The file contains the BSP header of generic MCF548x BSP. | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| | +| Parts of the code has been derived from the "dBUG source code" | +| package Freescale is providing for M548X EVBs. The usage of | +| the modified or unmodified code and it's integration into the | +| generic mcf548x BSP has been done according to the Freescale | +| license terms. | +| | +| The Freescale license terms can be reviewed in the file | +| | +| Freescale_license.txt | +| | ++-----------------------------------------------------------------+ +| | +| The generic mcf548x BSP has been developed on the basic | +| structures and modules of the av5282 BSP. | +| | ++-----------------------------------------------------------------+ +| | +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| | +| date history ID | +| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | +| 12.11.07 1.0 ras | +| | +\*===============================================================*/ + +#ifndef LIBBSP_M68K_GENMCF548X_BSP_H +#define LIBBSP_M68K_GENMCF548X_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +/** + * @defgroup m68k_genmcf548x MCF548X Support + * + * @ingroup bsp_m68k + * + * @brief MCT548X support. + */ + +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf548x/mcf548x.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* Initial values for the interrupt level and priority registers (INTC_ICRn) */ +extern const uint8_t mcf548x_intc_icr_init_values[64]; + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_mcf548x_fec_driver_attach_detach(struct rtems_bsdnet_ifconfig *config,int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mcf548x_fec_driver_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec1" +#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "fec2" + +#ifdef HAS_DBUG + typedef struct { + uint32_t console_baudrate; + uint8_t server_ip [4]; + uint8_t client_ip [4]; + uint8_t gateway_ip[4]; + uint8_t netmask [4]; + uint8_t spare[4]; + uint8_t macaddr [6]; + uint32_t ethport; /* default fec port: 1 = fec1, 2 = fec2 */ + uint32_t uartport; /* default fec port: 1 = psc0, 2 = psc1... */ + } dbug_settings_t; + +#define DBUG_SETTINGS (*(const dbug_settings_t *)0xFC020000) +#endif /* HAS_DBUG */ + +void bsp_cacr_set_flags(uint32_t flags); + +void bsp_cacr_set_self_clear_flags(uint32_t flags); + +void bsp_cacr_clear_flags(uint32_t flags); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/genmcf548x/include/bsp/irq.h b/bsps/m68k/genmcf548x/include/bsp/irq.h new file mode 100644 index 0000000000..825cc0d104 --- /dev/null +++ b/bsps/m68k/genmcf548x/include/bsp/irq.h @@ -0,0 +1,96 @@ +/** + * @file + * + * @ingroup genmcf548x_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF548X_IRQ_H +#define LIBBSP_M68K_MCF548X_IRQ_H + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +/** + * @defgroup genmcf548x_interrupt Interrupt Support + * + * @ingroup m68k_genmcf548x + * + * @brief Interrupt support. + */ + + +#define MCF548X_IRQ_EPORT_EPF1 1 +#define MCF548X_IRQ_EPORT_EPF2 2 +#define MCF548X_IRQ_EPORT_EPF3 3 +#define MCF548X_IRQ_EPORT_EPF4 4 +#define MCF548X_IRQ_EPORT_EPF5 5 +#define MCF548X_IRQ_EPORT_EPF6 6 +#define MCF548X_IRQ_EPORT_EPF7 7 +#define MCF548X_IRQ_USB_EP0ISR 15 +#define MCF548X_IRQ_USB_EP1ISR 16 +#define MCF548X_IRQ_USB_EP2ISR 17 +#define MCF548X_IRQ_USB_EP3ISR 18 +#define MCF548X_IRQ_USB_EP4ISR 19 +#define MCF548X_IRQ_USB_EP5ISR 20 +#define MCF548X_IRQ_USB_EP6ISR 21 +#define MCF548X_IRQ_USB_ISR 22 +#define MCF548X_IRQ_USB_AISR 23 +#define MCF548X_IRQ_DSPI_RFOF_TFUF 25 +#define MCF548X_IRQ_DSPI_RFOF 26 +#define MCF548X_IRQ_DSPI_RFDF 27 +#define MCF548X_IRQ_DSPI_TFUF 28 +#define MCF548X_IRQ_DSPI_TCF 29 +#define MCF548X_IRQ_DSPI_TFFF 30 +#define MCF548X_IRQ_DSPI_EOQF 31 +#define MCF548X_IRQ_DSPI 25 +#define MCF548X_IRQ_PSC3 32 +#define MCF548X_IRQ_PSC2 33 +#define MCF548X_IRQ_PSC1 34 +#define MCF548X_IRQ_PSC0 35 +#define MCF548X_IRQ_PSC(i) (35 - (i)) +#define MCF548X_IRQ_COMMTIM 36 +#define MCF548X_IRQ_SEC 37 +#define MCF548X_IRQ_FEC1 38 +#define MCF548X_IRQ_FEC0 39 +#define MCF548X_IRQ_FEC(i) (39 - (i)) +#define MCF548X_IRQ_I2C 40 +#define MCF548X_IRQ_PCIARB 41 +#define MCF548X_IRQ_CBPCI 42 +#define MCF548X_IRQ_XLBPCI 43 +#define MCF548X_IRQ_XLBARB 47 +#define MCF548X_IRQ_DMA 48 +#define MCF548X_IRQ_CAN0_ERROR 49 +#define MCF548X_IRQ_CAN0_BUSOFF 50 +#define MCF548X_IRQ_CAN0_MBOR 51 +#define MCF548X_IRQ_SLT1 53 +#define MCF548X_IRQ_SLT0 54 +#define MCF548X_IRQ_CAN1_ERROR 55 +#define MCF548X_IRQ_CAN1_BUSOFF 56 +#define MCF548X_IRQ_CAN1_MBOR 57 +#define MCF548X_IRQ_GPT3 59 +#define MCF548X_IRQ_GPT2 60 +#define MCF548X_IRQ_GPT1 61 +#define MCF548X_IRQ_GPT0 62 + +#define BSP_INTERRUPT_VECTOR_MIN 1 + +#define BSP_INTERRUPT_VECTOR_MAX 63 + +#endif /* LIBBSP_M68K_MCF548X_IRQ_H */ diff --git a/bsps/m68k/genmcf548x/include/tm27.h b/bsps/m68k/genmcf548x/include/tm27.h new file mode 100644 index 0000000000..31ea8bca0c --- /dev/null +++ b/bsps/m68k/genmcf548x/include/tm27.h @@ -0,0 +1,37 @@ +/** + * @file + * + * @ingroup m68k_genmcf548x + * + * @brief Time Test 27 routines. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/headers.am b/bsps/m68k/headers.am new file mode 100644 index 0000000000..526fa7769f --- /dev/null +++ b/bsps/m68k/headers.am @@ -0,0 +1,47 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/m68k/include/mvme16x_hw.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/m68k/include/bsp/linker-symbols.h + +include_mcf5206dir = $(includedir)/mcf5206 +include_mcf5206_HEADERS = +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcf5206e.h +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcfmbus.h +include_mcf5206_HEADERS += ../../../../../bsps/m68k/include/mcf5206/mcfuart.h + +include_mcf5223xdir = $(includedir)/mcf5223x +include_mcf5223x_HEADERS = +include_mcf5223x_HEADERS += ../../../../../bsps/m68k/include/mcf5223x/mcf5223x.h + +include_mcf5225xdir = $(includedir)/mcf5225x +include_mcf5225x_HEADERS = +include_mcf5225x_HEADERS += ../../../../../bsps/m68k/include/mcf5225x/fec.h +include_mcf5225x_HEADERS += ../../../../../bsps/m68k/include/mcf5225x/mcf5225x.h + +include_mcf5235dir = $(includedir)/mcf5235 +include_mcf5235_HEADERS = +include_mcf5235_HEADERS += ../../../../../bsps/m68k/include/mcf5235/mcf5235.h + +include_mcf5272dir = $(includedir)/mcf5272 +include_mcf5272_HEADERS = +include_mcf5272_HEADERS += ../../../../../bsps/m68k/include/mcf5272/mcf5272.h + +include_mcf5282dir = $(includedir)/mcf5282 +include_mcf5282_HEADERS = +include_mcf5282_HEADERS += ../../../../../bsps/m68k/include/mcf5282/mcf5282.h + +include_mcf532xdir = $(includedir)/mcf532x +include_mcf532x_HEADERS = +include_mcf532x_HEADERS += ../../../../../bsps/m68k/include/mcf532x/mcf532x.h + +include_mcf548xdir = $(includedir)/mcf548x +include_mcf548x_HEADERS = +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_dma.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_progCheck.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/MCD_tasksInit.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/mcdma_glue.h +include_mcf548x_HEADERS += ../../../../../bsps/m68k/include/mcf548x/mcf548x.h diff --git a/bsps/m68k/include/bsp/linker-symbols.h b/bsps/m68k/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..8bf5ebfa07 --- /dev/null +++ b/bsps/m68k/include/bsp/linker-symbols.h @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup bsp_linker Linker Support + * + * @ingroup bsp_kit + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_vector0_begin) +LINKER_SYMBOL(bsp_vector0_end) +LINKER_SYMBOL(bsp_vector0_size) + +LINKER_SYMBOL(bsp_vector1_begin) +LINKER_SYMBOL(bsp_vector1_end) +LINKER_SYMBOL(bsp_vector1_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_initstack_begin) +LINKER_SYMBOL(bsp_initstack_end) +LINKER_SYMBOL(bsp_initstack_size) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/m68k/include/mcf5206/mcf5206e.h b/bsps/m68k/include/mcf5206/mcf5206e.h new file mode 100644 index 0000000000..06dadca9b1 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcf5206e.h @@ -0,0 +1,609 @@ +/* + * Coldfire MCF5206e on-chip peripherial definitions. + * Contents of this file based on information provided in + * Motorola MCF5206e User's Manual + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCF5206E_H__ +#define __MCF5206E_H__ + +#ifdef ASM +#define MCF5206E_REG8(base,ofs) (ofs+base) +#define MCF5206E_REG16(base,ofs) (ofs+base) +#define MCF5206E_REG32(base,ofs) (ofs+base) +#else +#define MCF5206E_REG8(base,ofs) \ + (volatile uint8_t*)((uint8_t*)(base) + (ofs)) +#define MCF5206E_REG16(base,ofs) \ + (volatile uint16_t*)((uint8_t*)(base) + (ofs)) +#define MCF5206E_REG32(base,ofs) \ + (volatile uint32_t*)((uint8_t*)(base) + (ofs)) +#endif + +/*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/ + +/* CACR - Cache Control Register */ +#define MCF5206E_CACR_CENB (0x80000000) /* Cache Enable */ +#define MCF5206E_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ +#define MCF5206E_CACR_CFRZ (0x08000000) /* Cache Freeze */ +#define MCF5206E_CACR_CINV (0x01000000) /* Cache Invalidate */ +#define MCF5206E_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable + instruction bursting */ +#define MCF5206E_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ +#define MCF5206E_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ +#define MCF5206E_CACR_DWP (0x00000020) /* Default Write Protection */ +#define MCF5206E_CACR_CLNF (0x00000003) /* Cache Line Fill */ + +/* ACR0, ACR1 - Access Control Registers */ +#define MCF5206E_ACR_AB (0xff000000) /* Address Base */ +#define MCF5206E_ACR_AB_S (24) +#define MCF5206E_ACR_AM (0x00ff0000) /* Address Mask */ +#define MCF5206E_ACR_AM_S (16) +#define MCF5206E_ACR_EN (0x00008000) /* Enable ACR */ +#define MCF5206E_ACR_SM (0x00006000) /* Supervisor Mode */ +#define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */ +#define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ +#define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */ +#define MCF5206E_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ +#define MCF5206E_ACR_BUFW (0x00000020) /* Buffered Write Enable */ +#define MCF5206E_ACR_WP (0x00000004) /* Write Protect */ +#define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB) +#define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM) + +/*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/ + +/* RAMBAR - SRAM Base Address Register */ +#define MCF5206E_RAMBAR_BA (0xffffe000) /* SRAM Base Address */ +#define MCF5206E_RAMBAR_WP (0x00000100) /* Write Protect */ +#define MCF5206E_RAMBAR_CI (0x00000020) /* CPU Space mask */ +#define MCF5206E_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_RAMBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_RAMBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5206E_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ + +/*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/ + +/* DMA Source Address Register */ +#define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40)) + +/* DMA Destination Address Register */ +#define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40)) + +/* DMA Byte Count Register */ +#define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40)) + +/* DMA Control Register */ +#define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40)) +#define MCF5206E_DCR_INT (0x8000) /* Interrupt on completion of transfer */ +#define MCF5206E_DCR_EEXT (0x4000) /* Enable External DMA Request */ +#define MCF5206E_DCR_CS (0x2000) /* Cycle Steal */ +#define MCF5206E_DCR_AA (0x1000) /* Auto Align */ +#define MCF5206E_DCR_BWC (0x0E00) /* Bandwidth Control: */ +#define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */ +#define MCF5206E_DCR_BWC_512 (0x0200) /* 512 bytes */ +#define MCF5206E_DCR_BWC_1024 (0x0400) /* 1024 bytes */ +#define MCF5206E_DCR_BWC_2048 (0x0600) /* 2048 bytes */ +#define MCF5206E_DCR_BWC_4096 (0x0800) /* 4096 bytes */ +#define MCF5206E_DCR_BWC_8192 (0x0A00) /* 8192 bytes */ +#define MCF5206E_DCR_BWC_16384 (0x0C00) /* 16384 bytes */ +#define MCF5206E_DCR_BWC_32768 (0x0E00) /* 32768 bytes */ +#define MCF5206E_DCR_SAA (0x0100) /* Single Address Access */ +#define MCF5206E_DCR_S_RW (0x0080) /* Single Address Access Read/Write Val */ +#define MCF5206E_DCR_SINC (0x0040) /* Source Increment */ +#define MCF5206E_DCR_SSIZE (0x0030) /* Source Size: */ +#define MCF5206E_DCR_SSIZE_LONG (0x0000) /* Longword (4 bytes) */ +#define MCF5206E_DCR_SSIZE_BYTE (0x0010) /* Byte */ +#define MCF5206E_DCR_SSIZE_WORD (0x0020) /* Word (2 bytes) */ +#define MCF5206E_DCR_SSIZE_LINE (0x0030) /* Line (16 bytes) */ +#define MCF5206E_DCR_DINC (0x0008) /* Destination Increment */ +#define MCF5206E_DCR_DSIZE (0x0006) /* Destination Size: */ +#define MCF5206E_DCR_DSIZE_LONG (0x0000) /* Longword (4 bytes) */ +#define MCF5206E_DCR_DSIZE_BYTE (0x0002) /* Byte */ +#define MCF5206E_DCR_DSIZE_WORD (0x0004) /* Word (2 bytes) */ +#define MCF5206E_DCR_DSIZE_LINE (0x0006) /* Line (16 bytes) */ +#define MCF5206E_DCR_START (0x0001) /* Start Transfer */ + +/* DMA Status Register */ +#define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40)) +#define MCF5206E_DSR_CE (0x40) /* Configuration Error has occured */ +#define MCF5206E_DSR_BES (0x20) /* Bus Error on Source */ +#define MCF5206E_DSR_BED (0x10) /* Bus Error on Destination */ +#define MCF5206E_DSR_REQ (0x04) /* Request */ +#define MCF5206E_DSR_BSY (0x02) /* Busy */ +#define MCF5206E_DSR_DONE (0x01) /* Transaction Done */ + +/* DMA Interrupt Vector Register */ +#define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40)) + + +/*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/ + +/* MBAR - Module Base Address Register */ +#define MCF5206E_MBAR_BA (0xFFFFFC00) /* Base Address */ +#define MCF5206E_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_MBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_MBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5206E_MBAR_V (0x00000001) /* Contents of MBAR are valid */ + +/* SIM Configuration Register */ +#define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003) +#define MCF5206E_SIMR_FRZ1 (0x80) /* Disable Soft Wdog Timer when FREEZE */ +#define MCF5206E_SIMR_FRZ0 (0x40) /* Disable Bus Timeout monitor when FREEZE*/ +#define MCF5206E_SIMR_BL (0x01) /* Bus Lock Enable */ + +/* Interrupt numbers assignment */ +#define MCF5206E_INTR_EXT_IRQ1 (1) /* External IRQ1 */ +#define MCF5206E_INTR_EXT_IPL1 (1) /* External IPL1 */ +#define MCF5206E_INTR_EXT_IPL2 (2) /* External IPL2 */ +#define MCF5206E_INTR_EXT_IPL3 (3) /* External IPL3 */ +#define MCF5206E_INTR_EXT_IRQ4 (4) /* External IRQ4 */ +#define MCF5206E_INTR_EXT_IPL4 (4) /* External IPL4 */ +#define MCF5206E_INTR_EXT_IPL5 (5) /* External IPL5 */ +#define MCF5206E_INTR_EXT_IPL6 (6) /* External IPL6 */ +#define MCF5206E_INTR_EXT_IRQ7 (7) /* External IRQ7 */ +#define MCF5206E_INTR_EXT_IPL7 (7) /* External IPL7 */ +#define MCF5206E_INTR_SWT (8) /* Software Watchdog Timer */ +#define MCF5206E_INTR_TIMER_1 (9) /* Timer 1 interrupt */ +#define MCF5206E_INTR_TIMER_2 (10) /* Timer 2 interrupt */ +#define MCF5206E_INTR_MBUS (11) /* MBUS interrupt */ +#define MCF5206E_INTR_UART_1 (12) /* UART 1 interrupt */ +#define MCF5206E_INTR_UART_2 (13) /* UART 2 interrupt */ +#define MCF5206E_INTR_DMA_0 (14) /* DMA channel 0 interrupt */ +#define MCF5206E_INTR_DMA_1 (15) /* DMA channel 1 interrupt */ + +#define MCF5206E_INTR_BIT(n) (1 << (n)) + +/* Interrupt Control Registers (ICR1 - ICR15) */ +#define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1) + +#define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */ +#define MCF5206E_ICR_IL (0x1c) /* Interrupt Level */ +#define MCF5206E_ICR_IL_S (2) +#define MCF5206E_ICR_IP (0x03) /* Interrupt Priority */ +#define MCF5206E_ICR_IP_S (0) + +/* Interrupt Mask Register */ +#define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036) + +/* Interrupt Pending Register */ +#define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a) + +/* Reset Status Register */ +#define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040) +#define MCF5206E_RSR_HRST (0x80) /* Hard Reset or System Reset */ +#define MCF5206E_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */ + +/* System Protection Control Register */ +#define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041) +#define MCF5206E_SYPCR_SWE (0x80) /* Software Watchdog Enable */ +#define MCF5206E_SYPCR_SWRI (0x40) /* Software Watchdog Reset/Interrupt Sel.*/ +#define MCF5206E_SYPCR_SWP (0x20) /* Software Watchdog Prescaler */ +#define MCF5206E_SYPCR_SWT (0x18) /* Software Watchdog Timing: */ +#define MCF5206E_SYPCR_SWT_S (3) +#define MCF5206E_SYPCR_SWT_9 (0x00) /* timeout = (1<<9)/sysfreq */ +#define MCF5206E_SYPCR_SWT_11 (0x08) /* timeout = (1<<11)/sysfreq */ +#define MCF5206E_SYPCR_SWT_13 (0x10) /* timeout = (1<<13)/sysfreq */ +#define MCF5206E_SYPCR_SWT_15 (0x18) /* timeout = (1<<15)/sysfreq */ +#define MCF5206E_SYPCR_SWT_18 (0x20) /* timeout = (1<<18)/sysfreq */ +#define MCF5206E_SYPCR_SWT_20 (0x28) /* timeout = (1<<20)/sysfreq */ +#define MCF5206E_SYPCR_SWT_22 (0x30) /* timeout = (1<<22)/sysfreq */ +#define MCF5206E_SYPCR_SWT_24 (0x38) /* timeout = (1<<24)/sysfreq */ +#define MCF5206E_SYPCR_BME (0x04) /* Bus Timeout Monitor Enable */ +#define MCF5206E_SYPCR_BMT (0x03) /* Bus Monitor Timing: */ +#define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */ +#define MCF5206E_SYPCR_BMT_512 (0x01) /* timeout 512 system clocks */ +#define MCF5206E_SYPCR_BMT_256 (0x02) /* timeout 256 system clocks */ +#define MCF5206E_SYPCR_BMT_128 (0x03) /* timeout 128 system clocks */ + +/* Software Watchdog Interrupt Vector Register */ +#define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042) + +/* Software Watchdog Service Register */ +#define MCF5206E_SWSR(mbar) MCF5206E_REG8(mbar,0x043) +#define MCF5206E_SWSR_KEY1 (0x55) +#define MCF5206E_SWSR_KEY2 (0xAA) + +/* Pin Assignment Register */ +#define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA) +#define MCF5206E_PAR_PAR9 (0x200) +#define MCF5206E_PAR_PAR9_TOUT (0x000) /* Timer 0 output */ +#define MCF5206E_PAR_PAR9_DREQ1 (0x200) /* DMA channel 1 request */ +#define MCF5206E_PAR_PAR8 (0x100) +#define MCF5206E_PAR_PAR8_TIN0 (0x000) /* Timer 1 input */ +#define MCF5206E_PAR_PAR8_DREQ0 (0x100) /* DMA channel 0 request */ +#define MCF5206E_PAR_PAR7 (0x080) +#define MCF5206E_PAR_PAR7_RSTO (0x000) /* Reset output */ +#define MCF5206E_PAR_PAR7_UART2 (0x080) /* UART 2 RTS output */ +#define MCF5206E_PAR_PAR6 (0x040) +#define MCF5206E_PAR_PAR6_IRQ (0x000) /* IRQ7, IRQ4, IRQ1 */ +#define MCF5206E_PAR_PAR6_IPL (0x040) /* IPL2, IPL1, IPL0 */ +#define MCF5206E_PAR_PAR5 (0x020) +#define MCF5206E_PAR_PAR5_GPIO (0x000) /* General purpose I/O PP7-PP4 */ +#define MCF5206E_PAR_PAR5_PST (0x020) /* BDM signals PST3-PST0 */ +#define MCF5206E_PAR_PAR4 (0x010) +#define MCF5206E_PAR_PAR4_GPIO (0x000) /* General purpose I/O PP3-PP0 */ +#define MCF5206E_PAR_PAR4_DDATA (0x010) /* BDM signals DDATA3-DDATA0 */ +#define MCF5206E_PAR_PAR3 (0x008) +#define MCF5206E_PAR_PAR2 (0x004) +#define MCF5206E_PAR_PAR1 (0x002) +#define MCF5206E_PAR_PAR0 (0x001) +#define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000) +#define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001) +#define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002) +#define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003) +#define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004) +#define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005) +#define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006) +#define MCF5206E_PAR_WE0_A26_A25_A24 (0x007) +#define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008) +#define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009) +#define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A) +#define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B) +#define MCF5206E_PAR_A27_A26_A25_A24 (0x00C) + +/* Bus Master Arbitration Control */ +#define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007) +#define MCF5206E_MARB_NOARB (0x08) /* Arbiter operation disable */ +#define MCF5206E_MARB_ARBCTRL (0x04) /* Arb. order: Internal DMA, Coldfire */ + +/*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/ + +/* Chip Select Address Register */ +#define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12)) + +/* Chip Select Mask Register */ +#define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12)) +#define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */ +#define MCF5206E_CSMR_BAM_S (16) +#define MCF5206E_CSMR_MASK_256M (0x0FFF0000) +#define MCF5206E_CSMR_MASK_128M (0x07FF0000) +#define MCF5206E_CSMR_MASK_64M (0x03FF0000) +#define MCF5206E_CSMR_MASK_32M (0x01FF0000) +#define MCF5206E_CSMR_MASK_16M (0x00FF0000) +#define MCF5206E_CSMR_MASK_8M (0x007F0000) +#define MCF5206E_CSMR_MASK_4M (0x003F0000) +#define MCF5206E_CSMR_MASK_2M (0x001F0000) +#define MCF5206E_CSMR_MASK_1M (0x000F0000) +#define MCF5206E_CSMR_MASK_1024K (0x000F0000) +#define MCF5206E_CSMR_MASK_512K (0x00070000) +#define MCF5206E_CSMR_MASK_256K (0x00030000) +#define MCF5206E_CSMR_MASK_128K (0x00010000) +#define MCF5206E_CSMR_MASK_64K (0x00000000) +#define MCF5206E_CSMR_CI (0x00000020) /* CPU Space Mask (CSMR1 only) */ +#define MCF5206E_CSMR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_CSMR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_CSMR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_CSMR_UD (0x00000002) /* User Data Space Mask */ + +/* Chip Select Control Register */ +#define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12)) +#define MCF5206E_CSCR_WS (0x3c00) /* Wait States */ +#define MCF5206E_CSCR_WS_S (10) +#define MCF5206E_CSCR_WS0 (0x0000) /* 0 Wait States */ +#define MCF5206E_CSCR_WS1 (0x0400) /* 1 Wait States */ +#define MCF5206E_CSCR_WS2 (0x0800) /* 2 Wait States */ +#define MCF5206E_CSCR_WS3 (0x0C00) /* 3 Wait States */ +#define MCF5206E_CSCR_WS4 (0x1000) /* 4 Wait States */ +#define MCF5206E_CSCR_WS5 (0x1400) /* 5 Wait States */ +#define MCF5206E_CSCR_WS6 (0x1800) /* 6 Wait States */ +#define MCF5206E_CSCR_WS7 (0x1C00) /* 7 Wait States */ +#define MCF5206E_CSCR_WS8 (0x2000) /* 8 Wait States */ +#define MCF5206E_CSCR_WS9 (0x2400) /* 9 Wait States */ +#define MCF5206E_CSCR_WS10 (0x2800) /* 10 Wait States */ +#define MCF5206E_CSCR_WS11 (0x2C00) /* 11 Wait States */ +#define MCF5206E_CSCR_WS12 (0x3000) /* 12 Wait States */ +#define MCF5206E_CSCR_WS13 (0x3400) /* 13 Wait States */ +#define MCF5206E_CSCR_WS14 (0x3800) /* 14 Wait States */ +#define MCF5206E_CSCR_WS15 (0x3C00) /* 15 Wait States */ +#define MCF5206E_CSCR_BRST (0x0200) /* Burst Enable */ +#define MCF5206E_CSCR_AA (0x0100) /* Coldfire Core Auto Acknowledge + Enable */ +#define MCF5206E_CSCR_PS (0x00C0) /* Port Size */ +#define MCF5206E_CSCR_PS_S (6) +#define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */ +#define MCF5206E_CSCR_PS_8 (0x0040) /* Port Size = 8 bits */ +#define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */ +#define MCF5206E_CSCR_EMAA (0x0020) /* External Master Automatic Acknowledge + Enable */ +#define MCF5206E_CSCR_ASET (0x0010) /* Address Setup Enable */ +#define MCF5206E_CSCR_WRAH (0x0008) /* Write Address Hold Enable */ +#define MCF5206E_CSCR_RDAH (0x0004) /* Read Address Hold Enable */ +#define MCF5206E_CSCR_WR (0x0002) /* Write Enable */ +#define MCF5206E_CSCR_RD (0x0001) /* Read Enable */ + +/* Default Memory Control Register */ +#define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6) + +/*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/ + +/* Port A Data Direction Register */ +#define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5) + +/* Port A Data Register */ +#define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9) + +#define MCF5206E_PP_DAT0 (0x01) +#define MCF5206E_PP_DAT1 (0x02) +#define MCF5206E_PP_DAT2 (0x04) +#define MCF5206E_PP_DAT3 (0x08) +#define MCF5206E_PP_DAT4 (0x10) +#define MCF5206E_PP_DAT5 (0x20) +#define MCF5206E_PP_DAT6 (0x40) +#define MCF5206E_PP_DAT7 (0x80) + +/*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/ + +/* DRAM Controller Refresh Register */ +#define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046) + +/* DRAM Controller Timing Register */ +#define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A) +#define MCF5206E_DCTR_DAEM (0x8000) /* Drive Multiplexed Address During + External Master DRAM Transfers */ +#define MCF5206E_DCTR_EDO (0x4000) /* Extended Data-Out Enable */ +#define MCF5206E_DCTR_RCD (0x1000) /* RAS-to-CAS Delay Time */ +#define MCF5206E_DCTR_RSH (0x0600) /* RAS Hold Time */ +#define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */ +#define MCF5206E_DCTR_RSH_1 (0x0200) +#define MCF5206E_DCTR_RSH_2 (0x0400) +#define MCF5206E_DCTR_RP (0x0060) /* RAS Precharge Time */ +#define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */ +#define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */ +#define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */ +#define MCF5206E_DCTR_CAS (0x0008) /* Column Address Strobe Time */ +#define MCF5206E_DCTR_CP (0x0002) /* CAS Precharge Time */ +#define MCF5206E_DCTR_CSR (0x0001) /* CAS Setup Time for CAS before RAS + refresh */ + +/* DRAM Controller Address Registers */ +#define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12)) + +/* DRAM Controller Mask Registers */ +#define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12)) +#define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */ +#define MCF5206E_DCMR_BAM_S (16) +#define MCF5206E_DCMR_MASK_256M (0x0FFE0000) +#define MCF5206E_DCMR_MASK_128M (0x07FE0000) +#define MCF5206E_DCMR_MASK_64M (0x03FE0000) +#define MCF5206E_DCMR_MASK_32M (0x01FE0000) +#define MCF5206E_DCMR_MASK_16M (0x00FE0000) +#define MCF5206E_DCMR_MASK_8M (0x007E0000) +#define MCF5206E_DCMR_MASK_4M (0x003E0000) +#define MCF5206E_DCMR_MASK_2M (0x001E0000) +#define MCF5206E_DCMR_MASK_1M (0x000E0000) +#define MCF5206E_DCMR_MASK_1024K (0x000E0000) +#define MCF5206E_DCMR_MASK_512K (0x00060000) +#define MCF5206E_DCMR_MASK_256K (0x00020000) +#define MCF5206E_DCMR_MASK_128K (0x00000000) +#define MCF5206E_DCMR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5206E_DCMR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5206E_DCMR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5206E_DCMR_UD (0x00000002) /* User Data Space Mask */ + +/* DRAM Controller Control Register */ +#define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12)) +#define MCF5206E_DCCR_PS (0xC0) /* Port Size */ +#define MCF5206E_DCCR_PS_32 (0x00) /* 32 bit Port Size */ +#define MCF5206E_DCCR_PS_8 (0x40) /* 8 bit Port Size */ +#define MCF5206E_DCCR_PS_16 (0x80) /* 16 bit Port Size */ +#define MCF5206E_DCCR_BPS (0x30) /* Bank Page Size */ +#define MCF5206E_DCCR_BPS_512 (0x00) /* 512 Byte Page Size */ +#define MCF5206E_DCCR_BPS_1K (0x10) /* 1 KByte Page Size */ +#define MCF5206E_DCCR_BPS_2K (0x20) /* 2 KByte Page Size */ +#define MCF5206E_DCCR_PM (0x0C) /* Page Mode Select */ +#define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */ +#define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */ +#define MCF5206E_DCCR_PM_FASTP (0x0C) /* Fast Page Mode */ +#define MCF5206E_DCCR_WR (0x02) /* Write Enable */ +#define MCF5206E_DCCR_RD (0x01) /* Read Enable */ + +/*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/ + +#define MCF5206E_UART_CHANNELS (2) +/* UART Mode Register */ +#define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40)) +#define MCF5206E_UMR1_RXRTS (0x80) /* Receiver Request-to-Send + Control */ +#define MCF5206E_UMR1_RXIRQ (0x40) /* Receiver Interrupt Select */ +#define MCF5206E_UMR1_ERR (0x20) /* Error Mode */ +#define MCF5206E_UMR1_PM (0x1C) /* Parity Mode, Parity Type */ +#define MCF5206E_UMR1_PM_EVEN (0x00) /* Even Parity */ +#define MCF5206E_UMR1_PM_ODD (0x04) /* Odd Parity */ +#define MCF5206E_UMR1_PM_FORCE_LOW (0x08) /* Force parity low */ +#define MCF5206E_UMR1_PM_FORCE_HIGH (0x0C) /* Force parity high */ +#define MCF5206E_UMR1_PM_NO_PARITY (0x10) /* No Parity */ +#define MCF5206E_UMR1_PM_MULTI_DATA (0x18) /* Multidrop mode - data char */ +#define MCF5206E_UMR1_PM_MULTI_ADDR (0x1C) /* Multidrop mode - addr char */ +#define MCF5206E_UMR1_BC (0x03) /* Bits per Character */ +#define MCF5206E_UMR1_BC_5 (0x00) /* 5 bits per character */ +#define MCF5206E_UMR1_BC_6 (0x01) /* 6 bits per character */ +#define MCF5206E_UMR1_BC_7 (0x02) /* 7 bits per character */ +#define MCF5206E_UMR1_BC_8 (0x03) /* 8 bits per character */ + +#define MCF5206E_UMR2_CM (0xC0) /* Channel Mode */ +#define MCF5206E_UMR2_CM_NORMAL (0x00) /* Normal Mode */ +#define MCF5206E_UMR2_CM_AUTO_ECHO (0x40) /* Automatic Echo Mode */ +#define MCF5206E_UMR2_CM_LOCAL_LOOP (0x80) /* Local Loopback Mode */ +#define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */ +#define MCF5206E_UMR2_TXRTS (0x20) /* Transmitter Ready-to-Send op */ +#define MCF5206E_UMR2_TXCTS (0x10) /* Transmitter Clear-to-Send op */ +#define MCF5206E_UMR2_SB (0x0F) /* Stop Bit Length */ +#define MCF5206E_UMR2_SB_1 (0x07) /* 1 Stop Bit for 6-8 bits char */ +#define MCF5206E_UMR2_SB_15 (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/ +#define MCF5206E_UMR2_SB_2 (0x0F) /* 2 Stop Bits for 6-8 bits char */ +#define MCF5206E_UMR2_SB5_1 (0x00) /* 1 Stop Bits for 5 bit char */ +#define MCF5206E_UMR2_SB5_15 (0x07) /* 1.5 Stop Bits for 5 bit char */ +#define MCF5206E_UMR2_SB5_2 (0x0F) /* 2 Stop Bits for 5 bit char */ + +/* UART Status Register (read only) */ +#define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) +#define MCF5206E_USR_RB (0x80) /* Received Break */ +#define MCF5206E_USR_FE (0x40) /* Framing Error */ +#define MCF5206E_USR_PE (0x20) /* Parity Error */ +#define MCF5206E_USR_OE (0x10) /* Overrun Error */ +#define MCF5206E_USR_TXEMP (0x08) /* Transmitter Empty */ +#define MCF5206E_USR_TXRDY (0x04) /* Transmitter Ready */ +#define MCF5206E_USR_FFULL (0x02) /* FIFO Full */ +#define MCF5206E_USR_RXRDY (0x01) /* Receiver Ready */ + +/* UART Clock Select Register (write only) */ +#define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) +#define MCF5206E_UCSR_RCS (0xF0) /* Receiver Clock Select */ +#define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */ +#define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */ +#define MCF5206E_UCSR_RCS_EXT (0xF0) /* External clk x1 */ +#define MCF5206E_UCSR_TCS (0x0F) /* Transmitter Clock Select */ +#define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */ +#define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */ +#define MCF5206E_UCSR_TCS_EXT (0x0F) /* External clk x1 */ + +/* UART Command Register (write only) */ +#define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40)) +#define MCF5206E_UCR_MISC (0x70) /* Miscellaneous Commands: */ +#define MCF5206E_UCR_MISC_NOP (0x00) /* No Command */ +#define MCF5206E_UCR_MISC_RESET_MR (0x10) /* Reset Mode Register Ptr */ +#define MCF5206E_UCR_MISC_RESET_RX (0x20) /* Reset Receiver */ +#define MCF5206E_UCR_MISC_RESET_TX (0x30) /* Reset Transmitter */ +#define MCF5206E_UCR_MISC_RESET_ERR (0x40) /* Reset Error Status */ +#define MCF5206E_UCR_MISC_RESET_BRK (0x50) /* Reset Break-Change Interrupt */ +#define MCF5206E_UCR_MISC_START_BRK (0x60) /* Start Break */ +#define MCF5206E_UCR_MISC_STOP_BRK (0x70) /* Stop Break */ +#define MCF5206E_UCR_TC (0x0C) /* Transmitter Commands: */ +#define MCF5206E_UCR_TC_NOP (0x00) /* No Action Taken */ +#define MCF5206E_UCR_TC_ENABLE (0x04) /* Transmitter Enable */ +#define MCF5206E_UCR_TC_DISABLE (0x08) /* Transmitter Disable */ +#define MCF5206E_UCR_RC (0x03) /* Receiver Commands: */ +#define MCF5206E_UCR_RC_NOP (0x00) /* No Action Taken */ +#define MCF5206E_UCR_RC_ENABLE (0x01) /* Receiver Enable */ +#define MCF5206E_UCR_RC_DISABLE (0x02) /* Receiver Disable */ + +/* UART Receive Buffer (read only) */ +#define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) + +/* UART Transmit Buffer (write only) */ +#define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) + +/* UART Input Port Change Register (read only) */ +#define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) +#define MCF5206E_UIPCR_COS (0x10) /* Change of State at CTS input */ +#define MCF5206E_UIPCR_CTS (0x01) /* Current State of CTS */ + +/* UART Auxiliary Control Register (write only) */ +#define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) +#define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt + on CTS change */ + +/* UART Interrupt Status Register (read only) */ +#define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) +#define MCF5206E_UISR_COS (0x80) /* Change of State has occured at CTS */ +#define MCF5206E_UISR_DB (0x04) /* Delta Break */ +#define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */ +#define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */ + +/* UART Interrupt Mask Register (write only) */ +#define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) +#define MCF5206E_UIMR_COS (0x80) /* Change of State interrupt enable */ +#define MCF5206E_UIMR_DB (0x04) /* Delta Break interrupt enable */ +#define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */ +#define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */ + +/* UART Baud Rate Generator Prescale MSB Register */ +#define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40)) + +/* UART Baud Rate Generator Prescale LSB Register */ +#define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40)) + +/* UART Interrupt Vector Register */ +#define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40)) + +/* UART Input Port Register (read only) */ +#define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40)) +#define MCF5206E_UIP_CTS (0x01) /* Current state of CTS input */ + +/* UART Output Port Bit Set Command (address-triggered command, write) */ +#define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40)) + +/* UART Output Port Bit Reset Command (address-triggered command, write */ +#define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40)) + +/*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/ + +/* M-Bus Address Register */ +#define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0) + +/* M-Bus Frequency Divider Register */ +#define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4) + +/* M-Bus Control Register */ +#define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8) +#define MCF5206E_MBCR_MEN (0x80) /* M-Bus Enable */ +#define MCF5206E_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ +#define MCF5206E_MBCR_MSTA (0x20) /* Master Mode Selection */ +#define MCF5206E_MBCR_MTX (0x10) /* Transmit Mode Selection */ +#define MCF5206E_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ +#define MCF5206E_MBCR_RSTA (0x04) /* Repeat Start */ + +/* M-Bus Status Register */ +#define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC) +#define MCF5206E_MBSR_MCF (0x80) /* Data Transferring Bit */ +#define MCF5206E_MBSR_MAAS (0x40) /* Addressed as a Slave Bit */ +#define MCF5206E_MBSR_MBB (0x20) /* Bus Busy Bit */ +#define MCF5206E_MBSR_MAL (0x10) /* Arbitration Lost */ +#define MCF5206E_MBSR_SRW (0x04) /* Slave Read/Write */ +#define MCF5206E_MBSR_MIF (0x02) /* MBus Interrupt pending */ +#define MCF5206E_MBSR_RXAK (0x01) /* Received Acknowledge */ + +/* M-Bus Data I/O Register */ +#define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0) + +/*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/ + +/* Timer Mode Register */ +#define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20)) +#define MCF5206E_TMR_PS (0xFF00) /* Prescaler Value */ +#define MCF5206E_TMR_PS_S (8) +#define MCF5206E_TMR_CE (0x00C0) /* Capture Edge and Enable + Interrupt */ +#define MCF5206E_TMR_CE_ANY (0x00C0) /* Capture on any edge */ +#define MCF5206E_TMR_CE_FALL (0x0080) /* Capture on falling edge only */ +#define MCF5206E_TMR_CE_RISE (0x0040) /* Capture on rising edge only */ +#define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture + event */ +#define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ +#define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt + Enable */ +#define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ +#define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */ +#define MCF5206E_TMR_ICLK_TIN (0x0006) /* TIN pin (falling edge) */ +#define MCF5206E_TMR_ICLK_DIV16 (0x0004) /* Master system clock divided + by 16 */ +#define MCF5206E_TMR_ICLK_MSCLK (0x0002) /* Master System Clock */ +#define MCF5206E_TMR_ICLK_STOP (0x0000) /* Stops counter */ +#define MCF5206E_TMR_RST (0x0001) /* Reset/Enable Timer */ + +/* Timer Reference Register */ +#define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20)) + +/* Timer Capture Register */ +#define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20)) + +/* Timer Counter Register */ +#define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20)) + +/* Timer Event Register */ +#define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20)) +#define MCF5206E_TER_REF (0x02) /* Output Reference Event */ +#define MCF5206E_TER_CAP (0x01) /* Capture Event */ + + + +#endif diff --git a/bsps/m68k/include/mcf5206/mcfmbus.h b/bsps/m68k/include/mcf5206/mcfmbus.h new file mode 100644 index 0000000000..f70a70e483 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcfmbus.h @@ -0,0 +1,129 @@ +/* + * MCF5206e MBUS module (I2C bus) driver header file + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCFBSP_MCFMBUS_H__ +#define __MCFBSP_MCFMBUS_H__ + +#include "mcf5206e.h" +#include "i2c.h" + +/* States of I2C machine */ +typedef enum mcfmbus_i2c_state { + STATE_IDLE, + STATE_ADDR_7, + STATE_ADDR_1_W, + STATE_ADDR_1_R, + STATE_SENDING, + STATE_RECEIVING +} mcfmbus_i2c_state; + +typedef struct mcfmbus { + uint32_t base; /* ColdFire internal peripherial base + address */ + enum mcfmbus_i2c_state state;/* State of I2C machine */ + i2c_message *msg; /* Pointer to the first message in transfer */ + int nmsg; /* Number of messages in transfer */ + i2c_message *cmsg; /* Current message */ + int byte; /* Byte number in current message */ + rtems_isr_entry oldisr; /* Old interrupt handler */ + rtems_id sema; /* MBUS semaphore */ + i2c_transfer_done done; /* Transfer done function */ + uintptr_t done_arg_ptr; /* Done function argument ptr */ +} mcfmbus; + +/* mcfmbus_initialize -- + * Initialize ColdFire MBUS I2C bus controller. + * + * PARAMETERS: + * i2c_bus - pointer to the bus descriptor structure + * base - ColdFire internal peripherial base address + * + * RETURNS: + * RTEMS_SUCCESSFUL, or RTEMS error code when initialization failed. + */ +rtems_status_code +mcfmbus_initialize(mcfmbus *i2c_bus, uint32_t base); + +/* mcfmbus_select_clock_divider -- + * Select divider for system clock which is used for I2C bus clock + * generation. Not each divider can be selected for I2C bus; this + * function select nearest larger or equal divider, or maximum + * possible divider, if passed value greater. + * + * PARAMETERS: + * i2c_bus - pointer to the bus descriptor structure + * divider - system frequency divider for I2C serial clock. + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, or + * RTEMS error code when failed. + */ +rtems_status_code +mcfmbus_select_clock_divider(mcfmbus *i2c_bus, int divider); + +/* mcfmbus_i2c_transfer -- + * Initiate multiple-messages transfer over I2C bus via ColdFire MBUS + * controller. + * + * PARAMETERS: + * bus - pointer to MBUS controller descriptor + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code when failed. + */ +rtems_status_code +mcfmbus_i2c_transfer(mcfmbus *bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void *done_arg_ptr); + +/* mcfmbus_i2c_done -- + * Close ColdFire MBUS I2C bus controller and release all resources. + * + * PARAMETERS: + * bus - pointer to MBUS controller descriptor + * + * RETURNS: + * RTEMS_SUCCESSFUL, if transfer initiated successfully, or error + * code when failed. + */ +rtems_status_code +mcfmbus_i2c_done(mcfmbus *i2c_bus); + +/* mcfmbus_i2c_interrupt_handler -- + * ColdFire MBUS I2C bus controller interrupt handler. This function + * called from real interrupt handler, and pointer to MBUS descriptor + * structure passed to this function. + * + * PARAMETERS: + * bus - pointert to the bus descriptor structure + * + * RETURNS: + * none + */ +void mcfmbus_i2c_interrupt_handler(mcfmbus *bus); + +/* mcfmbus_poll -- + * MBUS module poll routine; used to poll events when I2C driver + * operates in poll-driven mode. + * + * PARAMETERS: + * none + * + * RETURNS: + * none + */ +void mcfmbus_poll(mcfmbus *bus); + +#endif /* __MCFBSP_MCFMBUS_H__ */ diff --git a/bsps/m68k/include/mcf5206/mcfuart.h b/bsps/m68k/include/mcf5206/mcfuart.h new file mode 100644 index 0000000000..bd9df5bb56 --- /dev/null +++ b/bsps/m68k/include/mcf5206/mcfuart.h @@ -0,0 +1,109 @@ +/* + * Generic UART Serial driver for Motorola Coldfire processors definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCFUART_H__ +#define __MCFUART_H__ + +#include <termios.h> +#include "bsp.h" +#include "mcf5206e.h" + +/* + * The MCF5206e System Clock Frequency; 54MHz default + */ +#ifndef SYSTEM_CLOCK_FREQUENCY +#define SYSTEM_CLOCK_FREQUENCY BSP_SYSTEM_FREQUENCY +#endif + +/* + * The following structure is a descriptor of single UART channel. + * It contains the initialization information about channel and + * current operating values + */ +typedef struct mcfuart { + uint32_t chn; /* UART channel number */ + uint8_t intvec; /* UART interrupt vector number, or + 0 if polled I/O */ + void *tty; /* termios channel descriptor */ + + volatile const char *tx_buf; /* Transmit buffer from termios */ + volatile uint32_t tx_buf_len; /* Transmit buffer length */ + volatile uint32_t tx_ptr; /* Index of next char to transmit*/ + rtems_isr_entry old_handler; /* Saved interrupt handler */ + + tcflag_t c_iflag; /* termios input mode flags */ + bool parerr_mark_flag; /* Parity error processing + state */ +} mcfuart; + +/* mcfuart_init -- + * This function verifies the input parameters and perform initialization + * of the Motorola Coldfire on-chip UART descriptor structure. + * + */ +rtems_status_code +mcfuart_init(mcfuart *uart, void *tty, uint8_t intvec, + uint32_t chn); + +/* mcfuart_reset -- + * This function perform the hardware initialization of Motorola + * Coldfire processor on-chip UART controller using parameters + * filled by the mcfuart_init function. + */ +rtems_status_code +mcfuart_reset(mcfuart *uart); + +/* mcfuart_disable -- + * This function disable the operations on Motorola Coldfire UART + * controller + */ +rtems_status_code +mcfuart_disable(mcfuart *uart); + +/* mcfuart_set_attributes -- + * This function parse the termios attributes structure and perform + * the appropriate settings in hardware. + */ +int +mcfuart_set_attributes(mcfuart *mcf, const struct termios *t); + +/* mcfuart_poll_read -- + * This function tried to read character from MCF UART and perform + * error handling. + */ +int +mcfuart_poll_read(mcfuart *uart); + +/* mcfuart_interrupt_write -- + * This function initiate transmitting of the buffer in interrupt mode. + */ +ssize_t +mcfuart_interrupt_write(mcfuart *uart, const char *buf, size_t len); + +/* mcfuart_poll_write -- + * This function transmit buffer byte-by-byte in polling mode. + */ +ssize_t +mcfuart_poll_write(mcfuart *uart, const char *buf, size_t len); + +/* mcfuart_stop_remote_tx -- + * This function stop data flow from remote device. + */ +int +mcfuart_stop_remote_tx(mcfuart *uart); + +/* mcfuart_start_remote_tx -- + * This function resume data flow from remote device. + */ +int +mcfuart_start_remote_tx(mcfuart *uart); + +#endif diff --git a/bsps/m68k/include/mcf5223x/mcf5223x.h b/bsps/m68k/include/mcf5223x/mcf5223x.h new file mode 100644 index 0000000000..0886105b17 --- /dev/null +++ b/bsps/m68k/include/mcf5223x/mcf5223x.h @@ -0,0 +1,3362 @@ +/* + * File: mcf5223x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF5223x_H__ +#define __MCF5223x_H__ + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) +#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) +#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) +#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) +#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) +#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) +#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) +#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) +#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) +#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) +#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) +#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) +#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) +#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) +#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) +#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) +#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) +#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) +#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) +#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) +#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) + +/* Bit definitions and macros for MCF_SCM_IPSBAR */ +#define MCF_SCM_IPSBAR_V (0x00000001) +#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x00000200) +#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_CWDR (0x20) +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIC (0x01) +#define MCF_SCM_CWCR_CWTAVAL (0x02) +#define MCF_SCM_CWCR_CWTA (0x04) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_LPICR */ +#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_SCM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_PPMRH */ +#define MCF_SCM_PPMRH_CDPORTS (0x00000001) +#define MCF_SCM_PPMRH_CDEPORT (0x00000002) +#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) +#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) +#define MCF_SCM_PPMRH_CDADC (0x00000080) +#define MCF_SCM_PPMRH_CDGPT (0x00000100) +#define MCF_SCM_PPMRH_CDPWN (0x00000200) +#define MCF_SCM_PPMRH_CDFCAN (0x00000400) +#define MCF_SCM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_SCM_PPMRL */ +#define MCF_SCM_PPMRL_CDG (0x00000002) +#define MCF_SCM_PPMRL_CDEIM (0x00000008) +#define MCF_SCM_PPMRL_CDDMA (0x00000010) +#define MCF_SCM_PPMRL_CDUART0 (0x00000020) +#define MCF_SCM_PPMRL_CDUART1 (0x00000040) +#define MCF_SCM_PPMRL_CDUART2 (0x00000080) +#define MCF_SCM_PPMRL_CDI2C (0x00000200) +#define MCF_SCM_PPMRL_CDQSPI (0x00000400) +#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPARK_PRKLAST (0x00001000) +#define MCF_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF_SCM_MPARK_FIXED (0x00004000) +#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) +#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) +#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) +#define MCF_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF_SCM_MPARK_M2_P_EN (0x02000000) + +/* Bit definitions and macros for MCF_SCM_PPMRS */ +#define MCF_SCM_PPMRS_DISABLE_ALL (64) +#define MCF_SCM_PPMRS_DISABLE_CFM (43) +#define MCF_SCM_PPMRS_DISABLE_CAN (42) +#define MCF_SCM_PPMRS_DISABLE_PWM (41) +#define MCF_SCM_PPMRS_DISABLE_GPT (40) +#define MCF_SCM_PPMRS_DISABLE_ADC (39) +#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) +#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) +#define MCF_SCM_PPMRS_DISABLE_EPORT (33) +#define MCF_SCM_PPMRS_DISABLE_PORTS (32) +#define MCF_SCM_PPMRS_DISABLE_INTC (17) +#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) +#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) +#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) +#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) +#define MCF_SCM_PPMRS_DISABLE_QSPI (10) +#define MCF_SCM_PPMRS_DISABLE_I2C (9) +#define MCF_SCM_PPMRS_DISABLE_UART2 (7) +#define MCF_SCM_PPMRS_DISABLE_UART1 (6) +#define MCF_SCM_PPMRS_DISABLE_UART0 (5) +#define MCF_SCM_PPMRS_DISABLE_DMA (4) +#define MCF_SCM_PPMRS_SET_CDG (1) + +/* Bit definitions and macros for MCF_SCM_PPMRC */ +#define MCF_SCM_PPMRC_ENABLE_ALL (64) +#define MCF_SCM_PPMRC_ENABLE_CFM (43) +#define MCF_SCM_PPMRC_ENABLE_CAN (42) +#define MCF_SCM_PPMRC_ENABLE_PWM (41) +#define MCF_SCM_PPMRC_ENABLE_GPT (40) +#define MCF_SCM_PPMRC_ENABLE_ADC (39) +#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) +#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) +#define MCF_SCM_PPMRC_ENABLE_EPORT (33) +#define MCF_SCM_PPMRC_ENABLE_PORTS (32) +#define MCF_SCM_PPMRC_ENABLE_INTC (17) +#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) +#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) +#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) +#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) +#define MCF_SCM_PPMRC_ENABLE_QSPI (10) +#define MCF_SCM_PPMRC_ENABLE_I2C (9) +#define MCF_SCM_PPMRC_ENABLE_UART2 (7) +#define MCF_SCM_PPMRC_ENABLE_UART1 (6) +#define MCF_SCM_PPMRC_ENABLE_UART0 (5) +#define MCF_SCM_PPMRC_ENABLE_DMA (4) +#define MCF_SCM_PPMRC_CLEAR_CDG (1) + + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit definitions and macros for MCF_PMM_PPMRH */ +#define MCF_PMM_PPMRH_CDPORTS (0x00000001) +#define MCF_PMM_PPMRH_CDEPORT (0x00000002) +#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) +#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) +#define MCF_PMM_PPMRH_CDADC (0x00000080) +#define MCF_PMM_PPMRH_CDGPT (0x00000100) +#define MCF_PMM_PPMRH_CDPWM (0x00000200) +#define MCF_PMM_PPMRH_CDFCAN (0x00000400) +#define MCF_PMM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_PMM_PPMRL */ +#define MCF_PMM_PPMRL_CDG (0x00000002) +#define MCF_PMM_PPMRL_CDEIM (0x00000008) +#define MCF_PMM_PPMRL_CDDMA (0x00000010) +#define MCF_PMM_PPMRL_CDUART0 (0x00000020) +#define MCF_PMM_PPMRL_CDUART1 (0x00000040) +#define MCF_PMM_PPMRL_CDUART2 (0x00000080) +#define MCF_PMM_PPMRL_CDI2C (0x00000200) +#define MCF_PMM_PPMRL_CDQSPI (0x00000400) +#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_PMM_LPICR */ +#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_PMM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_LVDSE (0x02) +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) + + +/********************************************************************* +* +* DMA Controller Module (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) +#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) +#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) +#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) +#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) +#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) +#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) +#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) +#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) +#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) +#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) +#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) +#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) +#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) +#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) +#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) +#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) +#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) +#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) +#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) +#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) +#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) +#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) +#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) + +/* Bit definitions and macros for MCF_DMA_DMAREQC */ +#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for MCF_DMA_SAR */ +#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DAR */ +#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DSR */ +#define MCF_DMA_DSR_DONE (0x01) +#define MCF_DMA_DSR_BSY (0x02) +#define MCF_DMA_DSR_REQ (0x04) +#define MCF_DMA_DSR_BED (0x10) +#define MCF_DMA_DSR_BES (0x20) +#define MCF_DMA_DSR_CE (0x40) + +/* Bit definitions and macros for MCF_DMA_BCR */ +#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) +#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_DMA_DCR */ +#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) +#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) +#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) +#define MCF_DMA_DCR_D_REQ (0x00000080) +#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DCR_START (0x00010000) +#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) +#define MCF_DMA_DCR_DINC (0x00080000) +#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) +#define MCF_DMA_DCR_SINC (0x00400000) +#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) +#define MCF_DMA_DCR_AA (0x10000000) +#define MCF_DMA_DCR_CS (0x20000000) +#define MCF_DMA_DCR_EEXT (0x40000000) +#define MCF_DMA_DCR_INT (0x80000000) +#define MCF_DMA_DCR_BWC_16K (0x1) +#define MCF_DMA_DCR_BWC_32K (0x2) +#define MCF_DMA_DCR_BWC_64K (0x3) +#define MCF_DMA_DCR_BWC_128K (0x4) +#define MCF_DMA_DCR_BWC_256K (0x5) +#define MCF_DMA_DCR_BWC_512K (0x6) +#define MCF_DMA_DCR_BWC_1024K (0x7) +#define MCF_DMA_DCR_DMOD_DIS (0x0) +#define MCF_DMA_DCR_DMOD_16 (0x1) +#define MCF_DMA_DCR_DMOD_32 (0x2) +#define MCF_DMA_DCR_DMOD_64 (0x3) +#define MCF_DMA_DCR_DMOD_128 (0x4) +#define MCF_DMA_DCR_DMOD_256 (0x5) +#define MCF_DMA_DCR_DMOD_512 (0x6) +#define MCF_DMA_DCR_DMOD_1K (0x7) +#define MCF_DMA_DCR_DMOD_2K (0x8) +#define MCF_DMA_DCR_DMOD_4K (0x9) +#define MCF_DMA_DCR_DMOD_8K (0xA) +#define MCF_DMA_DCR_DMOD_16K (0xB) +#define MCF_DMA_DCR_DMOD_32K (0xC) +#define MCF_DMA_DCR_DMOD_64K (0xD) +#define MCF_DMA_DCR_DMOD_128K (0xE) +#define MCF_DMA_DCR_DMOD_256K (0xF) +#define MCF_DMA_DCR_SMOD_DIS (0x0) +#define MCF_DMA_DCR_SMOD_16 (0x1) +#define MCF_DMA_DCR_SMOD_32 (0x2) +#define MCF_DMA_DCR_SMOD_64 (0x3) +#define MCF_DMA_DCR_SMOD_128 (0x4) +#define MCF_DMA_DCR_SMOD_256 (0x5) +#define MCF_DMA_DCR_SMOD_512 (0x6) +#define MCF_DMA_DCR_SMOD_1K (0x7) +#define MCF_DMA_DCR_SMOD_2K (0x8) +#define MCF_DMA_DCR_SMOD_4K (0x9) +#define MCF_DMA_DCR_SMOD_8K (0xA) +#define MCF_DMA_DCR_SMOD_16K (0xB) +#define MCF_DMA_DCR_SMOD_32K (0xC) +#define MCF_DMA_DCR_SMOD_64K (0xD) +#define MCF_DMA_DCR_SMOD_128K (0xE) +#define MCF_DMA_DCR_SMOD_256K (0xF) +#define MCF_DMA_DCR_SSIZE_LONG (0x0) +#define MCF_DMA_DCR_SSIZE_BYTE (0x1) +#define MCF_DMA_DCR_SSIZE_WORD (0x2) +#define MCF_DMA_DCR_SSIZE_LINE (0x3) +#define MCF_DMA_DCR_DSIZE_LONG (0x0) +#define MCF_DMA_DCR_DSIZE_BYTE (0x1) +#define MCF_DMA_DCR_DSIZE_WORD (0x2) +#define MCF_DMA_DCR_DSIZE_LINE (0x3) +#define MCF_DMA_DCR_LCH1_CH0 (0x0) +#define MCF_DMA_DCR_LCH1_CH1 (0x1) +#define MCF_DMA_DCR_LCH1_CH2 (0x2) +#define MCF_DMA_DCR_LCH1_CH3 (0x3) +#define MCF_DMA_DCR_LCH2_CH0 (0x0) +#define MCF_DMA_DCR_LCH2_CH1 (0x1) +#define MCF_DMA_DCR_LCH2_CH2 (0x2) +#define MCF_DMA_DCR_LCH2_CH3 (0x3) + + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) +#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) +#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) +#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) +#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) +#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) +#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) +#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) +#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) +#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) +#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) +#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) +#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) +#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) +#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) +#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) +#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) +#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) +#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) +#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) +#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) +#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) +#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) +#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) +#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) +#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) +#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) +#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x01) +#define MCF_I2C_I2ICR_RE (0x02) +#define MCF_I2C_I2ICR_TE (0x04) +#define MCF_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) +#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) +#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) +#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) +#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) +#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) +#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) +#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) +#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) +#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) +#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) +#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) +#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) +#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) +#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) +#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) +#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) +#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) +#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) +#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) +#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) +#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) +#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) +#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) +#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) +#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) +#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) +#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) +#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) +#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) +#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) +#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) +#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) +#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) +#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) +#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) +#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) +#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) +#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) +#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) +#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) +#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) +#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) +#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) +#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) +#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) +#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) +#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) +#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) +#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) +#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) +#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) +#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) +#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) +#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) +#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) +#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) +#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) +#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) +#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) +#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) +#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) +#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) +#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) +#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) +#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) +#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) +#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) +#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) +#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) +#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) +#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) +#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) +#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) +#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) +#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) +#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) +#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) +#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) +#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) +#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) +#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) +#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) +#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) +#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) +#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) +#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) +#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) +#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) +#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) +#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) +#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) +#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) +#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) +#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) +#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) +#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) +#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) +#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) +#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) +#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) +#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) +#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) +#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) +#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) +#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) +#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) +#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) +#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) +#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) +#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) +#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) +#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) +#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) +#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) +#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) +#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) +#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) +#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) +#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) +#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) +#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) +#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) +#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) +#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) +#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) +#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) +#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) +#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) +#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) +#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) +#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) +#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) +#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) +#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) +#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) +#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) +#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) +#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) +#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) +#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) +#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) +#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) +#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) +#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) +#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) +#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) +#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) +#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) +#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) +#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) +#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) +#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) +#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) +#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) +#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) +#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) +#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) +#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) +#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) +#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) +#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) +#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) +#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) +#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) +#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) +#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) +#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) +#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) +#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) +#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) +#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) +#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) +#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) +#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) +#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) +#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) +#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) +#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) +#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) +#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) +#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) +#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) +#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) +#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) +#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) +#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) +#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) +#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) +#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) +#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) +#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) +#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) +#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) +#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) +#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) +#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) +#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) +#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) +#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) +#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) +#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) +#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) +#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) +#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) +#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) +#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) +#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) +#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) +#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) +#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) +#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) +#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) +#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) +#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) +#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) +#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) +#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) +#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) +#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) +#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) +#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) +#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) +#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) +#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) +#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) +#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) +#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) +#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) +#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) +#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) +#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) +#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) +#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) +#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) +#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) +#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) +#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) +#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) +#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) +#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) +#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) +#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) +#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) +#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) +#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) +#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) +#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) +#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) +#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) +#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) +#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) +#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) +#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) +#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) +#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) +#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) +#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) +#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) +#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) +#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) +#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) +#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_MASK32 (0x00000001) +#define MCF_INTC_IMRH_MASK33 (0x00000002) +#define MCF_INTC_IMRH_MASK34 (0x00000004) +#define MCF_INTC_IMRH_MASK35 (0x00000008) +#define MCF_INTC_IMRH_MASK36 (0x00000010) +#define MCF_INTC_IMRH_MASK37 (0x00000020) +#define MCF_INTC_IMRH_MASK38 (0x00000040) +#define MCF_INTC_IMRH_MASK39 (0x00000080) +#define MCF_INTC_IMRH_MASK40 (0x00000100) +#define MCF_INTC_IMRH_MASK41 (0x00000200) +#define MCF_INTC_IMRH_MASK42 (0x00000400) +#define MCF_INTC_IMRH_MASK43 (0x00000800) +#define MCF_INTC_IMRH_MASK44 (0x00001000) +#define MCF_INTC_IMRH_MASK45 (0x00002000) +#define MCF_INTC_IMRH_MASK46 (0x00004000) +#define MCF_INTC_IMRH_MASK47 (0x00008000) +#define MCF_INTC_IMRH_MASK48 (0x00010000) +#define MCF_INTC_IMRH_MASK49 (0x00020000) +#define MCF_INTC_IMRH_MASK50 (0x00040000) +#define MCF_INTC_IMRH_MASK51 (0x00080000) +#define MCF_INTC_IMRH_MASK52 (0x00100000) +#define MCF_INTC_IMRH_MASK53 (0x00200000) +#define MCF_INTC_IMRH_MASK54 (0x00400000) +#define MCF_INTC_IMRH_MASK55 (0x00800000) +#define MCF_INTC_IMRH_MASK56 (0x01000000) +#define MCF_INTC_IMRH_MASK57 (0x02000000) +#define MCF_INTC_IMRH_MASK58 (0x04000000) +#define MCF_INTC_IMRH_MASK59 (0x08000000) +#define MCF_INTC_IMRH_MASK60 (0x10000000) +#define MCF_INTC_IMRH_MASK61 (0x20000000) +#define MCF_INTC_IMRH_MASK62 (0x40000000) +#define MCF_INTC_IMRH_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x00000001) +#define MCF_INTC_IMRL_MASK1 (0x00000002) +#define MCF_INTC_IMRL_MASK2 (0x00000004) +#define MCF_INTC_IMRL_MASK3 (0x00000008) +#define MCF_INTC_IMRL_MASK4 (0x00000010) +#define MCF_INTC_IMRL_MASK5 (0x00000020) +#define MCF_INTC_IMRL_MASK6 (0x00000040) +#define MCF_INTC_IMRL_MASK7 (0x00000080) +#define MCF_INTC_IMRL_MASK8 (0x00000100) +#define MCF_INTC_IMRL_MASK9 (0x00000200) +#define MCF_INTC_IMRL_MASK10 (0x00000400) +#define MCF_INTC_IMRL_MASK11 (0x00000800) +#define MCF_INTC_IMRL_MASK12 (0x00001000) +#define MCF_INTC_IMRL_MASK13 (0x00002000) +#define MCF_INTC_IMRL_MASK14 (0x00004000) +#define MCF_INTC_IMRL_MASK15 (0x00008000) +#define MCF_INTC_IMRL_MASK16 (0x00010000) +#define MCF_INTC_IMRL_MASK17 (0x00020000) +#define MCF_INTC_IMRL_MASK18 (0x00040000) +#define MCF_INTC_IMRL_MASK19 (0x00080000) +#define MCF_INTC_IMRL_MASK20 (0x00100000) +#define MCF_INTC_IMRL_MASK21 (0x00200000) +#define MCF_INTC_IMRL_MASK22 (0x00400000) +#define MCF_INTC_IMRL_MASK23 (0x00800000) +#define MCF_INTC_IMRL_MASK24 (0x01000000) +#define MCF_INTC_IMRL_MASK25 (0x02000000) +#define MCF_INTC_IMRL_MASK26 (0x04000000) +#define MCF_INTC_IMRL_MASK27 (0x08000000) +#define MCF_INTC_IMRL_MASK28 (0x10000000) +#define MCF_INTC_IMRL_MASK29 (0x20000000) +#define MCF_INTC_IMRL_MASK30 (0x40000000) +#define MCF_INTC_IMRL_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) +#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) +#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) +#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) +#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) +#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) +#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) +#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) +#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) +#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) +#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) +#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) +#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) +#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) +#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) +#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) +#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) +#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) +#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) +#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) +#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) +#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) +#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) +#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) +#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) +#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) +#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) +#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) +#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) +#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) + +/* Bit definitions and macros for MCF_GPIO_PORTNQ */ +#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) +#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) +#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) +#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) +#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) +#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) +#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) +#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAN */ +#define MCF_GPIO_PORTAN_PORTAN0 (0x01) +#define MCF_GPIO_PORTAN_PORTAN1 (0x02) +#define MCF_GPIO_PORTAN_PORTAN2 (0x04) +#define MCF_GPIO_PORTAN_PORTAN3 (0x08) +#define MCF_GPIO_PORTAN_PORTAN4 (0x10) +#define MCF_GPIO_PORTAN_PORTAN5 (0x20) +#define MCF_GPIO_PORTAN_PORTAN6 (0x40) +#define MCF_GPIO_PORTAN_PORTAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAS */ +#define MCF_GPIO_PORTAS_PORTAS0 (0x01) +#define MCF_GPIO_PORTAS_PORTAS1 (0x02) +#define MCF_GPIO_PORTAS_PORTAS2 (0x04) +#define MCF_GPIO_PORTAS_PORTAS3 (0x08) +#define MCF_GPIO_PORTAS_PORTAS4 (0x10) +#define MCF_GPIO_PORTAS_PORTAS5 (0x20) +#define MCF_GPIO_PORTAS_PORTAS6 (0x40) +#define MCF_GPIO_PORTAS_PORTAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTQS */ +#define MCF_GPIO_PORTQS_PORTQS0 (0x01) +#define MCF_GPIO_PORTQS_PORTQS1 (0x02) +#define MCF_GPIO_PORTQS_PORTQS2 (0x04) +#define MCF_GPIO_PORTQS_PORTQS3 (0x08) +#define MCF_GPIO_PORTQS_PORTQS4 (0x10) +#define MCF_GPIO_PORTQS_PORTQS5 (0x20) +#define MCF_GPIO_PORTQS_PORTQS6 (0x40) +#define MCF_GPIO_PORTQS_PORTQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTA */ +#define MCF_GPIO_PORTTA_PORTTA0 (0x01) +#define MCF_GPIO_PORTTA_PORTTA1 (0x02) +#define MCF_GPIO_PORTTA_PORTTA2 (0x04) +#define MCF_GPIO_PORTTA_PORTTA3 (0x08) +#define MCF_GPIO_PORTTA_PORTTA4 (0x10) +#define MCF_GPIO_PORTTA_PORTTA5 (0x20) +#define MCF_GPIO_PORTTA_PORTTA6 (0x40) +#define MCF_GPIO_PORTTA_PORTTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTC */ +#define MCF_GPIO_PORTTC_PORTTC0 (0x01) +#define MCF_GPIO_PORTTC_PORTTC1 (0x02) +#define MCF_GPIO_PORTTC_PORTTC2 (0x04) +#define MCF_GPIO_PORTTC_PORTTC3 (0x08) +#define MCF_GPIO_PORTTC_PORTTC4 (0x10) +#define MCF_GPIO_PORTTC_PORTTC5 (0x20) +#define MCF_GPIO_PORTTC_PORTTC6 (0x40) +#define MCF_GPIO_PORTTC_PORTTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTD */ +#define MCF_GPIO_PORTTD_PORTTD0 (0x01) +#define MCF_GPIO_PORTTD_PORTTD1 (0x02) +#define MCF_GPIO_PORTTD_PORTTD2 (0x04) +#define MCF_GPIO_PORTTD_PORTTD3 (0x08) +#define MCF_GPIO_PORTTD_PORTTD4 (0x10) +#define MCF_GPIO_PORTTD_PORTTD5 (0x20) +#define MCF_GPIO_PORTTD_PORTTD6 (0x40) +#define MCF_GPIO_PORTTD_PORTTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUA */ +#define MCF_GPIO_PORTUA_PORTUA0 (0x01) +#define MCF_GPIO_PORTUA_PORTUA1 (0x02) +#define MCF_GPIO_PORTUA_PORTUA2 (0x04) +#define MCF_GPIO_PORTUA_PORTUA3 (0x08) +#define MCF_GPIO_PORTUA_PORTUA4 (0x10) +#define MCF_GPIO_PORTUA_PORTUA5 (0x20) +#define MCF_GPIO_PORTUA_PORTUA6 (0x40) +#define MCF_GPIO_PORTUA_PORTUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUB */ +#define MCF_GPIO_PORTUB_PORTUB0 (0x01) +#define MCF_GPIO_PORTUB_PORTUB1 (0x02) +#define MCF_GPIO_PORTUB_PORTUB2 (0x04) +#define MCF_GPIO_PORTUB_PORTUB3 (0x08) +#define MCF_GPIO_PORTUB_PORTUB4 (0x10) +#define MCF_GPIO_PORTUB_PORTUB5 (0x20) +#define MCF_GPIO_PORTUB_PORTUB6 (0x40) +#define MCF_GPIO_PORTUB_PORTUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUC */ +#define MCF_GPIO_PORTUC_PORTUC0 (0x01) +#define MCF_GPIO_PORTUC_PORTUC1 (0x02) +#define MCF_GPIO_PORTUC_PORTUC2 (0x04) +#define MCF_GPIO_PORTUC_PORTUC3 (0x08) +#define MCF_GPIO_PORTUC_PORTUC4 (0x10) +#define MCF_GPIO_PORTUC_PORTUC5 (0x20) +#define MCF_GPIO_PORTUC_PORTUC6 (0x40) +#define MCF_GPIO_PORTUC_PORTUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTDD */ +#define MCF_GPIO_PORTDD_PORTDD0 (0x01) +#define MCF_GPIO_PORTDD_PORTDD1 (0x02) +#define MCF_GPIO_PORTDD_PORTDD2 (0x04) +#define MCF_GPIO_PORTDD_PORTDD3 (0x08) +#define MCF_GPIO_PORTDD_PORTDD4 (0x10) +#define MCF_GPIO_PORTDD_PORTDD5 (0x20) +#define MCF_GPIO_PORTDD_PORTDD6 (0x40) +#define MCF_GPIO_PORTDD_PORTDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTLD */ +#define MCF_GPIO_PORTLD_PORTLD0 (0x01) +#define MCF_GPIO_PORTLD_PORTLD1 (0x02) +#define MCF_GPIO_PORTLD_PORTLD2 (0x04) +#define MCF_GPIO_PORTLD_PORTLD3 (0x08) +#define MCF_GPIO_PORTLD_PORTLD4 (0x10) +#define MCF_GPIO_PORTLD_PORTLD5 (0x20) +#define MCF_GPIO_PORTLD_PORTLD6 (0x40) +#define MCF_GPIO_PORTLD_PORTLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTGP */ +#define MCF_GPIO_PORTGP_PORTGP0 (0x01) +#define MCF_GPIO_PORTGP_PORTGP1 (0x02) +#define MCF_GPIO_PORTGP_PORTGP2 (0x04) +#define MCF_GPIO_PORTGP_PORTGP3 (0x08) +#define MCF_GPIO_PORTGP_PORTGP4 (0x10) +#define MCF_GPIO_PORTGP_PORTGP5 (0x20) +#define MCF_GPIO_PORTGP_PORTGP6 (0x40) +#define MCF_GPIO_PORTGP_PORTGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRNQ */ +#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) +#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) +#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) +#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) +#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) +#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) +#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) +#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAN */ +#define MCF_GPIO_DDRAN_DDRAN0 (0x01) +#define MCF_GPIO_DDRAN_DDRAN1 (0x02) +#define MCF_GPIO_DDRAN_DDRAN2 (0x04) +#define MCF_GPIO_DDRAN_DDRAN3 (0x08) +#define MCF_GPIO_DDRAN_DDRAN4 (0x10) +#define MCF_GPIO_DDRAN_DDRAN5 (0x20) +#define MCF_GPIO_DDRAN_DDRAN6 (0x40) +#define MCF_GPIO_DDRAN_DDRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAS */ +#define MCF_GPIO_DDRAS_DDRAS0 (0x01) +#define MCF_GPIO_DDRAS_DDRAS1 (0x02) +#define MCF_GPIO_DDRAS_DDRAS2 (0x04) +#define MCF_GPIO_DDRAS_DDRAS3 (0x08) +#define MCF_GPIO_DDRAS_DDRAS4 (0x10) +#define MCF_GPIO_DDRAS_DDRAS5 (0x20) +#define MCF_GPIO_DDRAS_DDRAS6 (0x40) +#define MCF_GPIO_DDRAS_DDRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRQS */ +#define MCF_GPIO_DDRQS_DDRQS0 (0x01) +#define MCF_GPIO_DDRQS_DDRQS1 (0x02) +#define MCF_GPIO_DDRQS_DDRQS2 (0x04) +#define MCF_GPIO_DDRQS_DDRQS3 (0x08) +#define MCF_GPIO_DDRQS_DDRQS4 (0x10) +#define MCF_GPIO_DDRQS_DDRQS5 (0x20) +#define MCF_GPIO_DDRQS_DDRQS6 (0x40) +#define MCF_GPIO_DDRQS_DDRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTA */ +#define MCF_GPIO_DDRTA_DDRTA0 (0x01) +#define MCF_GPIO_DDRTA_DDRTA1 (0x02) +#define MCF_GPIO_DDRTA_DDRTA2 (0x04) +#define MCF_GPIO_DDRTA_DDRTA3 (0x08) +#define MCF_GPIO_DDRTA_DDRTA4 (0x10) +#define MCF_GPIO_DDRTA_DDRTA5 (0x20) +#define MCF_GPIO_DDRTA_DDRTA6 (0x40) +#define MCF_GPIO_DDRTA_DDRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTC */ +#define MCF_GPIO_DDRTC_DDRTC0 (0x01) +#define MCF_GPIO_DDRTC_DDRTC1 (0x02) +#define MCF_GPIO_DDRTC_DDRTC2 (0x04) +#define MCF_GPIO_DDRTC_DDRTC3 (0x08) +#define MCF_GPIO_DDRTC_DDRTC4 (0x10) +#define MCF_GPIO_DDRTC_DDRTC5 (0x20) +#define MCF_GPIO_DDRTC_DDRTC6 (0x40) +#define MCF_GPIO_DDRTC_DDRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTD */ +#define MCF_GPIO_DDRTD_DDRTD0 (0x01) +#define MCF_GPIO_DDRTD_DDRTD1 (0x02) +#define MCF_GPIO_DDRTD_DDRTD2 (0x04) +#define MCF_GPIO_DDRTD_DDRTD3 (0x08) +#define MCF_GPIO_DDRTD_DDRTD4 (0x10) +#define MCF_GPIO_DDRTD_DDRTD5 (0x20) +#define MCF_GPIO_DDRTD_DDRTD6 (0x40) +#define MCF_GPIO_DDRTD_DDRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUA */ +#define MCF_GPIO_DDRUA_DDRUA0 (0x01) +#define MCF_GPIO_DDRUA_DDRUA1 (0x02) +#define MCF_GPIO_DDRUA_DDRUA2 (0x04) +#define MCF_GPIO_DDRUA_DDRUA3 (0x08) +#define MCF_GPIO_DDRUA_DDRUA4 (0x10) +#define MCF_GPIO_DDRUA_DDRUA5 (0x20) +#define MCF_GPIO_DDRUA_DDRUA6 (0x40) +#define MCF_GPIO_DDRUA_DDRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUB */ +#define MCF_GPIO_DDRUB_DDRUB0 (0x01) +#define MCF_GPIO_DDRUB_DDRUB1 (0x02) +#define MCF_GPIO_DDRUB_DDRUB2 (0x04) +#define MCF_GPIO_DDRUB_DDRUB3 (0x08) +#define MCF_GPIO_DDRUB_DDRUB4 (0x10) +#define MCF_GPIO_DDRUB_DDRUB5 (0x20) +#define MCF_GPIO_DDRUB_DDRUB6 (0x40) +#define MCF_GPIO_DDRUB_DDRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUC */ +#define MCF_GPIO_DDRUC_DDRUC0 (0x01) +#define MCF_GPIO_DDRUC_DDRUC1 (0x02) +#define MCF_GPIO_DDRUC_DDRUC2 (0x04) +#define MCF_GPIO_DDRUC_DDRUC3 (0x08) +#define MCF_GPIO_DDRUC_DDRUC4 (0x10) +#define MCF_GPIO_DDRUC_DDRUC5 (0x20) +#define MCF_GPIO_DDRUC_DDRUC6 (0x40) +#define MCF_GPIO_DDRUC_DDRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRDD */ +#define MCF_GPIO_DDRDD_DDRDD0 (0x01) +#define MCF_GPIO_DDRDD_DDRDD1 (0x02) +#define MCF_GPIO_DDRDD_DDRDD2 (0x04) +#define MCF_GPIO_DDRDD_DDRDD3 (0x08) +#define MCF_GPIO_DDRDD_DDRDD4 (0x10) +#define MCF_GPIO_DDRDD_DDRDD5 (0x20) +#define MCF_GPIO_DDRDD_DDRDD6 (0x40) +#define MCF_GPIO_DDRDD_DDRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRLD */ +#define MCF_GPIO_DDRLD_DDRLD0 (0x01) +#define MCF_GPIO_DDRLD_DDRLD1 (0x02) +#define MCF_GPIO_DDRLD_DDRLD2 (0x04) +#define MCF_GPIO_DDRLD_DDRLD3 (0x08) +#define MCF_GPIO_DDRLD_DDRLD4 (0x10) +#define MCF_GPIO_DDRLD_DDRLD5 (0x20) +#define MCF_GPIO_DDRLD_DDRLD6 (0x40) +#define MCF_GPIO_DDRLD_DDRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRGP */ +#define MCF_GPIO_DDRGP_DDRGP0 (0x01) +#define MCF_GPIO_DDRGP_DDRGP1 (0x02) +#define MCF_GPIO_DDRGP_DDRGP2 (0x04) +#define MCF_GPIO_DDRGP_DDRGP3 (0x08) +#define MCF_GPIO_DDRGP_DDRGP4 (0x10) +#define MCF_GPIO_DDRGP_DDRGP5 (0x20) +#define MCF_GPIO_DDRGP_DDRGP6 (0x40) +#define MCF_GPIO_DDRGP_DDRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETNQ */ +#define MCF_GPIO_SETNQ_SETNQ0 (0x01) +#define MCF_GPIO_SETNQ_SETNQ1 (0x02) +#define MCF_GPIO_SETNQ_SETNQ2 (0x04) +#define MCF_GPIO_SETNQ_SETNQ3 (0x08) +#define MCF_GPIO_SETNQ_SETNQ4 (0x10) +#define MCF_GPIO_SETNQ_SETNQ5 (0x20) +#define MCF_GPIO_SETNQ_SETNQ6 (0x40) +#define MCF_GPIO_SETNQ_SETNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAN */ +#define MCF_GPIO_SETAN_SETAN0 (0x01) +#define MCF_GPIO_SETAN_SETAN1 (0x02) +#define MCF_GPIO_SETAN_SETAN2 (0x04) +#define MCF_GPIO_SETAN_SETAN3 (0x08) +#define MCF_GPIO_SETAN_SETAN4 (0x10) +#define MCF_GPIO_SETAN_SETAN5 (0x20) +#define MCF_GPIO_SETAN_SETAN6 (0x40) +#define MCF_GPIO_SETAN_SETAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAS */ +#define MCF_GPIO_SETAS_SETAS0 (0x01) +#define MCF_GPIO_SETAS_SETAS1 (0x02) +#define MCF_GPIO_SETAS_SETAS2 (0x04) +#define MCF_GPIO_SETAS_SETAS3 (0x08) +#define MCF_GPIO_SETAS_SETAS4 (0x10) +#define MCF_GPIO_SETAS_SETAS5 (0x20) +#define MCF_GPIO_SETAS_SETAS6 (0x40) +#define MCF_GPIO_SETAS_SETAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETQS */ +#define MCF_GPIO_SETQS_SETQS0 (0x01) +#define MCF_GPIO_SETQS_SETQS1 (0x02) +#define MCF_GPIO_SETQS_SETQS2 (0x04) +#define MCF_GPIO_SETQS_SETQS3 (0x08) +#define MCF_GPIO_SETQS_SETQS4 (0x10) +#define MCF_GPIO_SETQS_SETQS5 (0x20) +#define MCF_GPIO_SETQS_SETQS6 (0x40) +#define MCF_GPIO_SETQS_SETQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTA */ +#define MCF_GPIO_SETTA_SETTA0 (0x01) +#define MCF_GPIO_SETTA_SETTA1 (0x02) +#define MCF_GPIO_SETTA_SETTA2 (0x04) +#define MCF_GPIO_SETTA_SETTA3 (0x08) +#define MCF_GPIO_SETTA_SETTA4 (0x10) +#define MCF_GPIO_SETTA_SETTA5 (0x20) +#define MCF_GPIO_SETTA_SETTA6 (0x40) +#define MCF_GPIO_SETTA_SETTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTC */ +#define MCF_GPIO_SETTC_SETTC0 (0x01) +#define MCF_GPIO_SETTC_SETTC1 (0x02) +#define MCF_GPIO_SETTC_SETTC2 (0x04) +#define MCF_GPIO_SETTC_SETTC3 (0x08) +#define MCF_GPIO_SETTC_SETTC4 (0x10) +#define MCF_GPIO_SETTC_SETTC5 (0x20) +#define MCF_GPIO_SETTC_SETTC6 (0x40) +#define MCF_GPIO_SETTC_SETTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTD */ +#define MCF_GPIO_SETTD_SETTD0 (0x01) +#define MCF_GPIO_SETTD_SETTD1 (0x02) +#define MCF_GPIO_SETTD_SETTD2 (0x04) +#define MCF_GPIO_SETTD_SETTD3 (0x08) +#define MCF_GPIO_SETTD_SETTD4 (0x10) +#define MCF_GPIO_SETTD_SETTD5 (0x20) +#define MCF_GPIO_SETTD_SETTD6 (0x40) +#define MCF_GPIO_SETTD_SETTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUA */ +#define MCF_GPIO_SETUA_SETUA0 (0x01) +#define MCF_GPIO_SETUA_SETUA1 (0x02) +#define MCF_GPIO_SETUA_SETUA2 (0x04) +#define MCF_GPIO_SETUA_SETUA3 (0x08) +#define MCF_GPIO_SETUA_SETUA4 (0x10) +#define MCF_GPIO_SETUA_SETUA5 (0x20) +#define MCF_GPIO_SETUA_SETUA6 (0x40) +#define MCF_GPIO_SETUA_SETUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUB */ +#define MCF_GPIO_SETUB_SETUB0 (0x01) +#define MCF_GPIO_SETUB_SETUB1 (0x02) +#define MCF_GPIO_SETUB_SETUB2 (0x04) +#define MCF_GPIO_SETUB_SETUB3 (0x08) +#define MCF_GPIO_SETUB_SETUB4 (0x10) +#define MCF_GPIO_SETUB_SETUB5 (0x20) +#define MCF_GPIO_SETUB_SETUB6 (0x40) +#define MCF_GPIO_SETUB_SETUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUC */ +#define MCF_GPIO_SETUC_SETUC0 (0x01) +#define MCF_GPIO_SETUC_SETUC1 (0x02) +#define MCF_GPIO_SETUC_SETUC2 (0x04) +#define MCF_GPIO_SETUC_SETUC3 (0x08) +#define MCF_GPIO_SETUC_SETUC4 (0x10) +#define MCF_GPIO_SETUC_SETUC5 (0x20) +#define MCF_GPIO_SETUC_SETUC6 (0x40) +#define MCF_GPIO_SETUC_SETUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETDD */ +#define MCF_GPIO_SETDD_SETDD0 (0x01) +#define MCF_GPIO_SETDD_SETDD1 (0x02) +#define MCF_GPIO_SETDD_SETDD2 (0x04) +#define MCF_GPIO_SETDD_SETDD3 (0x08) +#define MCF_GPIO_SETDD_SETDD4 (0x10) +#define MCF_GPIO_SETDD_SETDD5 (0x20) +#define MCF_GPIO_SETDD_SETDD6 (0x40) +#define MCF_GPIO_SETDD_SETDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETLD */ +#define MCF_GPIO_SETLD_SETLD0 (0x01) +#define MCF_GPIO_SETLD_SETLD1 (0x02) +#define MCF_GPIO_SETLD_SETLD2 (0x04) +#define MCF_GPIO_SETLD_SETLD3 (0x08) +#define MCF_GPIO_SETLD_SETLD4 (0x10) +#define MCF_GPIO_SETLD_SETLD5 (0x20) +#define MCF_GPIO_SETLD_SETLD6 (0x40) +#define MCF_GPIO_SETLD_SETLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETGP */ +#define MCF_GPIO_SETGP_SETGP0 (0x01) +#define MCF_GPIO_SETGP_SETGP1 (0x02) +#define MCF_GPIO_SETGP_SETGP2 (0x04) +#define MCF_GPIO_SETGP_SETGP3 (0x08) +#define MCF_GPIO_SETGP_SETGP4 (0x10) +#define MCF_GPIO_SETGP_SETGP5 (0x20) +#define MCF_GPIO_SETGP_SETGP6 (0x40) +#define MCF_GPIO_SETGP_SETGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRNQ */ +#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) +#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) +#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) +#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) +#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) +#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) +#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) +#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAN */ +#define MCF_GPIO_CLRAN_CLRAN0 (0x01) +#define MCF_GPIO_CLRAN_CLRAN1 (0x02) +#define MCF_GPIO_CLRAN_CLRAN2 (0x04) +#define MCF_GPIO_CLRAN_CLRAN3 (0x08) +#define MCF_GPIO_CLRAN_CLRAN4 (0x10) +#define MCF_GPIO_CLRAN_CLRAN5 (0x20) +#define MCF_GPIO_CLRAN_CLRAN6 (0x40) +#define MCF_GPIO_CLRAN_CLRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAS */ +#define MCF_GPIO_CLRAS_CLRAS0 (0x01) +#define MCF_GPIO_CLRAS_CLRAS1 (0x02) +#define MCF_GPIO_CLRAS_CLRAS2 (0x04) +#define MCF_GPIO_CLRAS_CLRAS3 (0x08) +#define MCF_GPIO_CLRAS_CLRAS4 (0x10) +#define MCF_GPIO_CLRAS_CLRAS5 (0x20) +#define MCF_GPIO_CLRAS_CLRAS6 (0x40) +#define MCF_GPIO_CLRAS_CLRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRQS */ +#define MCF_GPIO_CLRQS_CLRQS0 (0x01) +#define MCF_GPIO_CLRQS_CLRQS1 (0x02) +#define MCF_GPIO_CLRQS_CLRQS2 (0x04) +#define MCF_GPIO_CLRQS_CLRQS3 (0x08) +#define MCF_GPIO_CLRQS_CLRQS4 (0x10) +#define MCF_GPIO_CLRQS_CLRQS5 (0x20) +#define MCF_GPIO_CLRQS_CLRQS6 (0x40) +#define MCF_GPIO_CLRQS_CLRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTA */ +#define MCF_GPIO_CLRTA_CLRTA0 (0x01) +#define MCF_GPIO_CLRTA_CLRTA1 (0x02) +#define MCF_GPIO_CLRTA_CLRTA2 (0x04) +#define MCF_GPIO_CLRTA_CLRTA3 (0x08) +#define MCF_GPIO_CLRTA_CLRTA4 (0x10) +#define MCF_GPIO_CLRTA_CLRTA5 (0x20) +#define MCF_GPIO_CLRTA_CLRTA6 (0x40) +#define MCF_GPIO_CLRTA_CLRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTC */ +#define MCF_GPIO_CLRTC_CLRTC0 (0x01) +#define MCF_GPIO_CLRTC_CLRTC1 (0x02) +#define MCF_GPIO_CLRTC_CLRTC2 (0x04) +#define MCF_GPIO_CLRTC_CLRTC3 (0x08) +#define MCF_GPIO_CLRTC_CLRTC4 (0x10) +#define MCF_GPIO_CLRTC_CLRTC5 (0x20) +#define MCF_GPIO_CLRTC_CLRTC6 (0x40) +#define MCF_GPIO_CLRTC_CLRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTD */ +#define MCF_GPIO_CLRTD_CLRTD0 (0x01) +#define MCF_GPIO_CLRTD_CLRTD1 (0x02) +#define MCF_GPIO_CLRTD_CLRTD2 (0x04) +#define MCF_GPIO_CLRTD_CLRTD3 (0x08) +#define MCF_GPIO_CLRTD_CLRTD4 (0x10) +#define MCF_GPIO_CLRTD_CLRTD5 (0x20) +#define MCF_GPIO_CLRTD_CLRTD6 (0x40) +#define MCF_GPIO_CLRTD_CLRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUA */ +#define MCF_GPIO_CLRUA_CLRUA0 (0x01) +#define MCF_GPIO_CLRUA_CLRUA1 (0x02) +#define MCF_GPIO_CLRUA_CLRUA2 (0x04) +#define MCF_GPIO_CLRUA_CLRUA3 (0x08) +#define MCF_GPIO_CLRUA_CLRUA4 (0x10) +#define MCF_GPIO_CLRUA_CLRUA5 (0x20) +#define MCF_GPIO_CLRUA_CLRUA6 (0x40) +#define MCF_GPIO_CLRUA_CLRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUB */ +#define MCF_GPIO_CLRUB_CLRUB0 (0x01) +#define MCF_GPIO_CLRUB_CLRUB1 (0x02) +#define MCF_GPIO_CLRUB_CLRUB2 (0x04) +#define MCF_GPIO_CLRUB_CLRUB3 (0x08) +#define MCF_GPIO_CLRUB_CLRUB4 (0x10) +#define MCF_GPIO_CLRUB_CLRUB5 (0x20) +#define MCF_GPIO_CLRUB_CLRUB6 (0x40) +#define MCF_GPIO_CLRUB_CLRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUC */ +#define MCF_GPIO_CLRUC_CLRUC0 (0x01) +#define MCF_GPIO_CLRUC_CLRUC1 (0x02) +#define MCF_GPIO_CLRUC_CLRUC2 (0x04) +#define MCF_GPIO_CLRUC_CLRUC3 (0x08) +#define MCF_GPIO_CLRUC_CLRUC4 (0x10) +#define MCF_GPIO_CLRUC_CLRUC5 (0x20) +#define MCF_GPIO_CLRUC_CLRUC6 (0x40) +#define MCF_GPIO_CLRUC_CLRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRDD */ +#define MCF_GPIO_CLRDD_CLRDD0 (0x01) +#define MCF_GPIO_CLRDD_CLRDD1 (0x02) +#define MCF_GPIO_CLRDD_CLRDD2 (0x04) +#define MCF_GPIO_CLRDD_CLRDD3 (0x08) +#define MCF_GPIO_CLRDD_CLRDD4 (0x10) +#define MCF_GPIO_CLRDD_CLRDD5 (0x20) +#define MCF_GPIO_CLRDD_CLRDD6 (0x40) +#define MCF_GPIO_CLRDD_CLRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRLD */ +#define MCF_GPIO_CLRLD_CLRLD0 (0x01) +#define MCF_GPIO_CLRLD_CLRLD1 (0x02) +#define MCF_GPIO_CLRLD_CLRLD2 (0x04) +#define MCF_GPIO_CLRLD_CLRLD3 (0x08) +#define MCF_GPIO_CLRLD_CLRLD4 (0x10) +#define MCF_GPIO_CLRLD_CLRLD5 (0x20) +#define MCF_GPIO_CLRLD_CLRLD6 (0x40) +#define MCF_GPIO_CLRLD_CLRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRGP */ +#define MCF_GPIO_CLRGP_CLRGP0 (0x01) +#define MCF_GPIO_CLRGP_CLRGP1 (0x02) +#define MCF_GPIO_CLRGP_CLRGP2 (0x04) +#define MCF_GPIO_CLRGP_CLRGP3 (0x08) +#define MCF_GPIO_CLRGP_CLRGP4 (0x10) +#define MCF_GPIO_CLRGP_CLRGP5 (0x20) +#define MCF_GPIO_CLRGP_CLRGP6 (0x40) +#define MCF_GPIO_CLRGP_CLRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PNQPAR */ +#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) +#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) +#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) +#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) +#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) +#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) +#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) +#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) +#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) + +/* Bit definitions and macros for MCF_GPIO_PANPAR */ +#define MCF_GPIO_PANPAR_PANPAR0 (0x01) +#define MCF_GPIO_PANPAR_PANPAR1 (0x02) +#define MCF_GPIO_PANPAR_PANPAR2 (0x04) +#define MCF_GPIO_PANPAR_PANPAR3 (0x08) +#define MCF_GPIO_PANPAR_PANPAR4 (0x10) +#define MCF_GPIO_PANPAR_PANPAR5 (0x20) +#define MCF_GPIO_PANPAR_PANPAR6 (0x40) +#define MCF_GPIO_PANPAR_PANPAR7 (0x80) +#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) +#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) +#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) +#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) +#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) +#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) +#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) +#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PASPAR */ +#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PASPAR_PASPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) +#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) +#define MCF_GPIO_PASPAR_SCL_SCL (0x01) +#define MCF_GPIO_PASPAR_SDA_SDA (0x04) +#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) +#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) +#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) +#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) +#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) +#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) +#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) +#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PQSPAR */ +#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) +#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) +#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) +#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) +#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) +#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) +#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) +#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) +#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) +#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) +#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) +#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) +#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) +#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) +#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) +#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) +#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) + +/* Bit definitions and macros for MCF_GPIO_PTAPAR */ +#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) +#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) +#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) +#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) +#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) +#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) +#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) +#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTCPAR */ +#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) +#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) +#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) +#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) +#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) +#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) +#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) +#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PTDPAR */ +#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) +#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) +#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) +#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) +#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) +#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) +#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) +#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PUAPAR */ +#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) +#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) +#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) +#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) +#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) +#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) + +/* Bit definitions and macros for MCF_GPIO_PUBPAR */ +#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) +#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) +#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) +#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) +#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) +#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) +#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) +#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PUCPAR */ +#define MCF_GPIO_PUCPAR_PUCPAR0 (0x01) +#define MCF_GPIO_PUCPAR_PUCPAR1 (0x02) +#define MCF_GPIO_PUCPAR_PUCPAR2 (0x04) +#define MCF_GPIO_PUCPAR_PUCPAR3 (0x08) +#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) +#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) +#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) +#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDPAR */ +#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) +#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) +#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) +#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) +#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) +#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) +#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) +#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) +#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) +#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) +#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) +#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) +#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) +#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) +#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) +#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PLDPAR */ +#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) +#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) +#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) +#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) +#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) +#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) +#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) +#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) +#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) +#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) +#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) +#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) +#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) +#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) + +/* Bit definitions and macros for MCF_GPIO_PGPPAR */ +#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) +#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) +#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) +#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) +#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) +#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) +#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) +#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) +#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) +#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) +#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) +#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) +#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) +#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) +#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) +#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PWOR */ +#define MCF_GPIO_PWOR_PWOR0 (0x0001) +#define MCF_GPIO_PWOR_PWOR1 (0x0002) +#define MCF_GPIO_PWOR_PWOR2 (0x0004) +#define MCF_GPIO_PWOR_PWOR3 (0x0008) +#define MCF_GPIO_PWOR_PWOR4 (0x0010) +#define MCF_GPIO_PWOR_PWOR5 (0x0020) +#define MCF_GPIO_PWOR_PWOR6 (0x0040) +#define MCF_GPIO_PWOR_PWOR7 (0x0080) +#define MCF_GPIO_PWOR_PWOR8 (0x0100) +#define MCF_GPIO_PWOR_PWOR9 (0x0200) +#define MCF_GPIO_PWOR_PWOR10 (0x0400) +#define MCF_GPIO_PWOR_PWOR11 (0x0800) +#define MCF_GPIO_PWOR_PWOR12 (0x1000) +#define MCF_GPIO_PWOR_PWOR13 (0x2000) +#define MCF_GPIO_PWOR_PWOR14 (0x4000) +#define MCF_GPIO_PWOR_PWOR15 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRH */ +#define MCF_GPIO_PDSRH_PDSR32 (0x0001) +#define MCF_GPIO_PDSRH_PDSR33 (0x0002) +#define MCF_GPIO_PDSRH_PDSR34 (0x0004) +#define MCF_GPIO_PDSRH_PDSR35 (0x0008) +#define MCF_GPIO_PDSRH_PDSR36 (0x0010) +#define MCF_GPIO_PDSRH_PDSR37 (0x0020) +#define MCF_GPIO_PDSRH_PDSR38 (0x0040) +#define MCF_GPIO_PDSRH_PDSR39 (0x0080) +#define MCF_GPIO_PDSRH_PDSR40 (0x0100) +#define MCF_GPIO_PDSRH_PDSR41 (0x0200) +#define MCF_GPIO_PDSRH_PDSR42 (0x0400) +#define MCF_GPIO_PDSRH_PDSR43 (0x0800) +#define MCF_GPIO_PDSRH_PDSR44 (0x1000) +#define MCF_GPIO_PDSRH_PDSR45 (0x2000) +#define MCF_GPIO_PDSRH_PDSR46 (0x4000) +#define MCF_GPIO_PDSRH_PDSR47 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRL */ +#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) +#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) +#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) +#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) +#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) +#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) +#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) +#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) +#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) +#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) +#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) +#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) +#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) +#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) +#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) +#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) +#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) +#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) +#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) +#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) +#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) +#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) +#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) +#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) +#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) +#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) +#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) +#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) +#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) +#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) +#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) +#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) + +/********************************************************************* +* +* ColdFire Integration Module (CIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) +#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) +#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) +#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) +#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) + +/* Bit definitions and macros for MCF_CIM_RCR */ +#define MCF_CIM_RCR_LVDE (0x01) +#define MCF_CIM_RCR_LVDRE (0x04) +#define MCF_CIM_RCR_LVDIE (0x08) +#define MCF_CIM_RCR_LVDF (0x10) +#define MCF_CIM_RCR_FRCRSTOUT (0x40) +#define MCF_CIM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_CIM_RSR */ +#define MCF_CIM_RSR_LOL (0x01) +#define MCF_CIM_RSR_LOC (0x02) +#define MCF_CIM_RSR_EXT (0x04) +#define MCF_CIM_RSR_POR (0x08) +#define MCF_CIM_RSR_WDR (0x10) +#define MCF_CIM_RSR_SOFT (0x20) +#define MCF_CIM_RSR_LVD (0x40) + +/* Bit definitions and macros for MCF_CIM_CCR */ +#define MCF_CIM_CCR_LOAD (0x8000) + +/* Bit definitions and macros for MCF_CIM_LPCR */ +#define MCF_CIM_LPCR_LVDSE (0x02) +#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_CIM_LPCR_LPMD_STOP (0xC0) +#define MCF_CIM_LPCR_LPMD_WAIT (0x80) +#define MCF_CIM_LPCR_LPMD_DOZE (0x40) +#define MCF_CIM_LPCR_LPMD_RUN (0x00) + +/* Bit definitions and macros for MCF_CIM_RCON */ +#define MCF_CIM_RCON_RLOAD (0x0020) + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) +#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) +#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) +#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) +#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) + +/* Bit definitions and macros for MCF_CLOCK_SYNCR */ +#define MCF_CLOCK_SYNCR_PLLEN (0x0001) +#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) +#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) +#define MCF_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF_CLOCK_SYNCR_LOLRE (0x8000) + +/* Bit definitions and macros for MCF_CLOCK_SYNSR */ +#define MCF_CLOCK_SYNSR_LOCS (0x04) +#define MCF_CLOCK_SYNSR_LOCK (0x08) +#define MCF_CLOCK_SYNSR_LOCKS (0x10) +#define MCF_CLOCK_SYNSR_CRYOSC (0x20) +#define MCF_CLOCK_SYNSR_OCOSC (0x40) +#define MCF_CLOCK_SYNSR_EXTOSC (0x80) + +/* Bit definitions and macros for MCF_CLOCK_LPCR */ +#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_CLOCK_RTCDR */ +#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) +#define MCF_EPORT_EPPAR1 (*(vuint16*)(&__IPSBAR[0x140000])) +#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF_EPORT_EPDDR1 (*(vuint8 *)(&__IPSBAR[0x140002])) +#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF_EPORT_EPIER1 (*(vuint8 *)(&__IPSBAR[0x140003])) +#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF_EPORT_EPDR1 (*(vuint8 *)(&__IPSBAR[0x140004])) +#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF_EPORT_EPPDR1 (*(vuint8 *)(&__IPSBAR[0x140005])) +#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) +#define MCF_EPORT_EPFR1 (*(vuint8 *)(&__IPSBAR[0x140006])) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) +#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) +#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) +#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) +#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) +#define MCF_EPORT_EPDDR_EPDD8 (0x01) +#define MCF_EPORT_EPDDR_EPDD9 (0x02) +#define MCF_EPORT_EPDDR_EPDD10 (0x04) +#define MCF_EPORT_EPDDR_EPDD11 (0x08) +#define MCF_EPORT_EPDDR_EPDD12 (0x10) +#define MCF_EPORT_EPDDR_EPDD13 (0x20) +#define MCF_EPORT_EPDDR_EPDD14 (0x40) +#define MCF_EPORT_EPDDR_EPDD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) +#define MCF_EPORT_EPIER_EPIE8 (0x01) +#define MCF_EPORT_EPIER_EPIE9 (0x02) +#define MCF_EPORT_EPIER_EPIE10 (0x04) +#define MCF_EPORT_EPIER_EPIE11 (0x08) +#define MCF_EPORT_EPIER_EPIE12 (0x10) +#define MCF_EPORT_EPIER_EPIE13 (0x20) +#define MCF_EPORT_EPIER_EPIE14 (0x40) +#define MCF_EPORT_EPIER_EPIE15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) +#define MCF_EPORT_EPDR_EPD8 (0x01) +#define MCF_EPORT_EPDR_EPD9 (0x02) +#define MCF_EPORT_EPDR_EPD10 (0x04) +#define MCF_EPORT_EPDR_EPD11 (0x08) +#define MCF_EPORT_EPDR_EPD12 (0x10) +#define MCF_EPORT_EPDR_EPD13 (0x20) +#define MCF_EPORT_EPDR_EPD14 (0x40) +#define MCF_EPORT_EPDR_EPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) +#define MCF_EPORT_EPPDR_EPPD8 (0x01) +#define MCF_EPORT_EPPDR_EPPD9 (0x02) +#define MCF_EPORT_EPPDR_EPPD10 (0x04) +#define MCF_EPORT_EPPDR_EPPD11 (0x08) +#define MCF_EPORT_EPPDR_EPPD12 (0x10) +#define MCF_EPORT_EPPDR_EPPD13 (0x20) +#define MCF_EPORT_EPPDR_EPPD14 (0x40) +#define MCF_EPORT_EPPDR_EPPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) +#define MCF_EPORT_EPFR_EPF8 (0x01) +#define MCF_EPORT_EPFR_EPF9 (0x02) +#define MCF_EPORT_EPFR_EPF10 (0x04) +#define MCF_EPORT_EPFR_EPF11 (0x08) +#define MCF_EPORT_EPFR_EPF12 (0x10) +#define MCF_EPORT_EPFR_EPF13 (0x20) +#define MCF_EPORT_EPFR_EPF14 (0x40) +#define MCF_EPORT_EPFR_EPF15 (0x80) + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) +#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) +#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) +#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) +#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) +#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) +#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) +#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Analog-to-Digital Converter (ADC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) +#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) +#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) +#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) +#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) +#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) +#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) +#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) +#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) +#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) +#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) +#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) +#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) +#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) +#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) +#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) +#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) +#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) +#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) +#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) +#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) +#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) +#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) +#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) +#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) +#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) +#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) +#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) +#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) +#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) +#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) +#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) +#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) +#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) +#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) +#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) +#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) +#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) +#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) +#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) +#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) +#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) +#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) +#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) +#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) +#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) +#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) + +/* Bit definitions and macros for MCF_ADC_CTRL1 */ +#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) +#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) +#define MCF_ADC_CTRL1_HLMTIE (0x0100) +#define MCF_ADC_CTRL1_LLMTIE (0x0200) +#define MCF_ADC_CTRL1_ZCIE (0x0400) +#define MCF_ADC_CTRL1_EOSIE0 (0x0800) +#define MCF_ADC_CTRL1_SYNC0 (0x1000) +#define MCF_ADC_CTRL1_START0 (0x2000) +#define MCF_ADC_CTRL1_STOP0 (0x4000) + +/* Bit definitions and macros for MCF_ADC_CTRL2 */ +#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) +#define MCF_ADC_CTRL2_SIMULT (0x0020) +#define MCF_ADC_CTRL2_EOSIE1 (0x0800) +#define MCF_ADC_CTRL2_SYNC1 (0x1000) +#define MCF_ADC_CTRL2_START1 (0x2000) +#define MCF_ADC_CTRL2_STOP1 (0x4000) + +/* Bit definitions and macros for MCF_ADC_ADZCC */ +#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) +#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) +#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) +#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) +#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) +#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) +#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) +#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_ADC_ADLST1 */ +#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADLST2 */ +#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADSDIS */ +#define MCF_ADC_ADSDIS_DS0 (0x0001) +#define MCF_ADC_ADSDIS_DS1 (0x0002) +#define MCF_ADC_ADSDIS_DS2 (0x0004) +#define MCF_ADC_ADSDIS_DS3 (0x0008) +#define MCF_ADC_ADSDIS_DS4 (0x0010) +#define MCF_ADC_ADSDIS_DS5 (0x0020) +#define MCF_ADC_ADSDIS_DS6 (0x0040) +#define MCF_ADC_ADSDIS_DS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADSTAT */ +#define MCF_ADC_ADSTAT_RDY0 (0x0001) +#define MCF_ADC_ADSTAT_RDY1 (0x0002) +#define MCF_ADC_ADSTAT_RDY2 (0x0004) +#define MCF_ADC_ADSTAT_RDY3 (0x0008) +#define MCF_ADC_ADSTAT_RDY4 (0x0010) +#define MCF_ADC_ADSTAT_RDY5 (0x0020) +#define MCF_ADC_ADSTAT_RDY6 (0x0040) +#define MCF_ADC_ADSTAT_RDY7 (0x0080) +#define MCF_ADC_ADSTAT_HLMT (0x0100) +#define MCF_ADC_ADSTAT_LLMTI (0x0200) +#define MCF_ADC_ADSTAT_ZCI (0x0400) +#define MCF_ADC_ADSTAT_EOSI (0x0800) +#define MCF_ADC_ADSTAT_CIP (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLSTAT */ +#define MCF_ADC_ADLSTAT_LLS0 (0x0001) +#define MCF_ADC_ADLSTAT_LLS1 (0x0002) +#define MCF_ADC_ADLSTAT_LLS2 (0x0004) +#define MCF_ADC_ADLSTAT_LLS3 (0x0008) +#define MCF_ADC_ADLSTAT_LLS4 (0x0010) +#define MCF_ADC_ADLSTAT_LLS5 (0x0020) +#define MCF_ADC_ADLSTAT_LLS6 (0x0040) +#define MCF_ADC_ADLSTAT_LLS7 (0x0080) +#define MCF_ADC_ADLSTAT_HLS0 (0x0100) +#define MCF_ADC_ADLSTAT_HLS1 (0x0200) +#define MCF_ADC_ADLSTAT_HLS2 (0x0400) +#define MCF_ADC_ADLSTAT_HLS3 (0x0800) +#define MCF_ADC_ADLSTAT_HLS4 (0x1000) +#define MCF_ADC_ADLSTAT_HLS5 (0x2000) +#define MCF_ADC_ADLSTAT_HLS6 (0x4000) +#define MCF_ADC_ADLSTAT_HLS7 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ +#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) +#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) +#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) +#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) +#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) +#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) +#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) +#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADRSLT */ +#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) +#define MCF_ADC_ADRSLT_SEXT (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLLMT */ +#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADHLMT */ +#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADOFS */ +#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_POWER */ +#define MCF_ADC_POWER_PD0 (0x0001) +#define MCF_ADC_POWER_PD1 (0x0002) +#define MCF_ADC_POWER_PD2 (0x0004) +#define MCF_ADC_POWER_APD (0x0008) +#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) +#define MCF_ADC_POWER_PSTS0 (0x0400) +#define MCF_ADC_POWER_PSTS1 (0x0800) +#define MCF_ADC_POWER_PSTS2 (0x1000) +#define MCF_ADC_POWER_ASTBY (0x8000) + +/* Bit definitions and macros for MCF_ADC_CAL */ +#define MCF_ADC_CAL_CAL0 (0x0001) +#define MCF_ADC_CAL_CRS0 (0x0002) +#define MCF_ADC_CAL_CAL1 (0x0004) +#define MCF_ADC_CAL_CRS1 (0x0008) + +/********************************************************************* +* +* General Purpose Timer (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) +#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) +#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) +#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) +#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) +#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) +#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) +#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +/* Bit definitions and macros for MCF_GPT_GPTIOS */ +#define MCF_GPT_GPTIOS_IOS0 (0x01) +#define MCF_GPT_GPTIOS_IOS1 (0x02) +#define MCF_GPT_GPTIOS_IOS2 (0x04) +#define MCF_GPT_GPTIOS_IOS3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCFORC */ +#define MCF_GPT_GPTCFORC_FOC0 (0x01) +#define MCF_GPT_GPTCFORC_FOC1 (0x02) +#define MCF_GPT_GPTCFORC_FOC2 (0x04) +#define MCF_GPT_GPTCFORC_FOC3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTOC3D */ +#define MCF_GPT_GPTOC3D_OC3D0 (0x01) +#define MCF_GPT_GPTOC3D_OC3D1 (0x02) +#define MCF_GPT_GPTOC3D_OC3D2 (0x04) +#define MCF_GPT_GPTOC3D_OC3D3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ +#define MCF_GPT_GPTSCR1_TFFCA (0x10) +#define MCF_GPT_GPTSCR1_GPTEN (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTTOV */ +#define MCF_GPT_GPTTOV_TOV0 (0x01) +#define MCF_GPT_GPTTOV_TOV1 (0x02) +#define MCF_GPT_GPTTOV_TOV2 (0x04) +#define MCF_GPT_GPTTOV_TOV3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ +#define MCF_GPT_GPTCTL1_OL0 (0x01) +#define MCF_GPT_GPTCTL1_OM0 (0x02) +#define MCF_GPT_GPTCTL1_OL1 (0x04) +#define MCF_GPT_GPTCTL1_OM1 (0x08) +#define MCF_GPT_GPTCTL1_OL2 (0x10) +#define MCF_GPT_GPTCTL1_OM2 (0x20) +#define MCF_GPT_GPTCTL1_OL3 (0x40) +#define MCF_GPT_GPTCTL1_OM3 (0x80) +#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) +#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) +#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) +#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) +#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) +#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) +#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) +#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) +#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) +#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) +#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) +#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ +#define MCF_GPT_GPTCTL2_EDG0A (0x01) +#define MCF_GPT_GPTCTL2_EDG0B (0x02) +#define MCF_GPT_GPTCTL2_EDG1A (0x04) +#define MCF_GPT_GPTCTL2_EDG1B (0x08) +#define MCF_GPT_GPTCTL2_EDG2A (0x10) +#define MCF_GPT_GPTCTL2_EDG2B (0x20) +#define MCF_GPT_GPTCTL2_EDG3A (0x40) +#define MCF_GPT_GPTCTL2_EDG3B (0x80) +#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) +#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) +#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) +#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) +#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) +#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) +#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) +#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) +#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) +#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) +#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) +#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTIE */ +#define MCF_GPT_GPTIE_CI0 (0x01) +#define MCF_GPT_GPTIE_CI1 (0x02) +#define MCF_GPT_GPTIE_CI2 (0x04) +#define MCF_GPT_GPTIE_CI3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ +#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) +#define MCF_GPT_GPTSCR2_TCRE (0x08) +#define MCF_GPT_GPTSCR2_RDPT (0x10) +#define MCF_GPT_GPTSCR2_PUPT (0x20) +#define MCF_GPT_GPTSCR2_TOI (0x80) +#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) +#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) +#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) +#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) +#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) +#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) +#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) +#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) + +/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ +#define MCF_GPT_GPTFLG1_CF0 (0x01) +#define MCF_GPT_GPTFLG1_CF1 (0x02) +#define MCF_GPT_GPTFLG1_CF2 (0x04) +#define MCF_GPT_GPTFLG1_CF3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ +#define MCF_GPT_GPTFLG2_CF0 (0x01) +#define MCF_GPT_GPTFLG2_CF1 (0x02) +#define MCF_GPT_GPTFLG2_CF2 (0x04) +#define MCF_GPT_GPTFLG2_CF3 (0x08) +#define MCF_GPT_GPTFLG2_TOF (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTC */ +#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPACTL */ +#define MCF_GPT_GPTPACTL_PAI (0x01) +#define MCF_GPT_GPTPACTL_PAOVI (0x02) +#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF_GPT_GPTPACTL_PEDGE (0x10) +#define MCF_GPT_GPTPACTL_PAMOD (0x20) +#define MCF_GPT_GPTPACTL_PAE (0x40) +#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) +#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ +#define MCF_GPT_GPTPAFLG_PAIF (0x01) +#define MCF_GPT_GPTPAFLG_PAOVF (0x02) + +/* Bit definitions and macros for MCF_GPT_GPTPACNT */ +#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPORT */ +#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTDDR */ +#define MCF_GPT_GPTDDR_DDRT0 (0x01) +#define MCF_GPT_GPTDDR_DDRT1 (0x02) +#define MCF_GPT_GPTDDR_DDRT2 (0x04) +#define MCF_GPT_GPTDDR_DDRT3 (0x08) + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) +#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) +#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x01) +#define MCF_PWM_PWME_PWME1 (0x02) +#define MCF_PWM_PWME_PWME2 (0x04) +#define MCF_PWM_PWME_PWME3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x01) +#define MCF_PWM_PWMPOL_PPOL1 (0x02) +#define MCF_PWM_PWMPOL_PPOL2 (0x04) +#define MCF_PWM_PWMPOL_PPOL3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x01) +#define MCF_PWM_PWMCLK_PCLK1 (0x02) +#define MCF_PWM_PWMCLK_PCLK2 (0x04) +#define MCF_PWM_PWMCLK_PCLK3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x01) +#define MCF_PWM_PWMCAE_CAE1 (0x02) +#define MCF_PWM_PWMCAE_CAE2 (0x04) +#define MCF_PWM_PWMCAE_CAE3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x04) +#define MCF_PWM_PWMCTL_PSWAI (0x08) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x01) +#define MCF_PWM_PWMSDN_PWM7IL (0x02) +#define MCF_PWM_PWMSDN_PWM7IN (0x04) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) +#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) +#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) +#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) +#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) +#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) +#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) +#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) +#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) +#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF(x) (1<<x) + +/* Bit definitions and macros for MCF_CAN_IFLAG */ +#define MCF_CAN_IFLAG_BUF(x) (1<<x) + +/********************************************************************* +* +* ColdFire Flash Module (CFM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000])) +#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) +#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008])) +#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010])) +#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014])) +#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018])) +#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) +#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) + +/* Bit definitions and macros for MCF_CFM_CFMMCR */ +#define MCF_CFM_CFMMCR_KEYACC (0x0020) +#define MCF_CFM_CFMMCR_CCIE (0x0040) +#define MCF_CFM_CFMMCR_CBEIE (0x0080) +#define MCF_CFM_CFMMCR_AEIE (0x0100) +#define MCF_CFM_CFMMCR_PVIE (0x0200) +#define MCF_CFM_CFMMCR_LOCK (0x0400) + +/* Bit definitions and macros for MCF_CFM_CFMCLKD */ +#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) +#define MCF_CFM_CFMCLKD_PRDIV8 (0x40) +#define MCF_CFM_CFMCLKD_DIVLD (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMSEC */ +#define MCF_CFM_CFMSEC_SEC(x) (((x)&0x0000FFFF)<<0) +#define MCF_CFM_CFMSEC_SECSTAT (0x40000000) +#define MCF_CFM_CFMSEC_KEYEN (0x80000000) + +/* Bit definitions and macros for MCF_CFM_CFMUSTAT */ +#define MCF_CFM_CFMUSTAT_BLANK (0x04) +#define MCF_CFM_CFMUSTAT_ACCERR (0x10) +#define MCF_CFM_CFMUSTAT_PVIOL (0x20) +#define MCF_CFM_CFMUSTAT_CCIF (0x40) +#define MCF_CFM_CFMUSTAT_CBEIF (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMCMD */ +#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) +#define MCF_CFM_CFMCMD_RDARY1 (0x05) +#define MCF_CFM_CFMCMD_PGM (0x20) +#define MCF_CFM_CFMCMD_PGERS (0x40) +#define MCF_CFM_CFMCMD_MASERS (0x41) +#define MCF_CFM_CFMCMD_PGERSVER (0x06) + +/********************************************************************* +* +* Interrupt Controller (INTC_IACK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(&__IPSBAR[0x000FE0])) +#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(&__IPSBAR[0x000FE4])) +#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(&__IPSBAR[0x000FE8])) +#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(&__IPSBAR[0x000FEC])) +#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(&__IPSBAR[0x000FF0])) +#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(&__IPSBAR[0x000FF4])) +#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(&__IPSBAR[0x000FF8])) +#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(&__IPSBAR[0x000FFC])) +#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)])) + +/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ +#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ +#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x001004])) +#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x001008])) +#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x001010])) +#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x001014])) +#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x001024])) +#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x001040])) +#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x001044])) +#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x001064])) +#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x001084])) +#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x0010C4])) +#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x0010E4])) +#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x0010E8])) +#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x0010EC])) +#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x001118])) +#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x00111C])) +#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x001120])) +#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x001124])) +#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x001144])) +#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x00114C])) +#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x001150])) +#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x001180])) +#define MCF_FEC_ETDSR (*(vuint32*)(&__IPSBAR[0x001184])) +#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x001188])) +#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x001200])) +#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x001204])) +#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x001208])) +#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x00120C])) +#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001210])) +#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001214])) +#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001218])) +#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x00121C])) +#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x001220])) +#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x001224])) +#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x001228])) +#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x00122C])) +#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x001230])) +#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x001234])) +#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x001238])) +#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x00123C])) +#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x001240])) +#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x001244])) +#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x001248])) +#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x00124C])) +#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x001250])) +#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x001254])) +#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x001258])) +#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x00125C])) +#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x001260])) +#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x001264])) +#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x001268])) +#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x00126C])) +#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x001270])) +#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x001274])) +#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x001284])) +#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x001288])) +#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x00128C])) +#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001290])) +#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001294])) +#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001298])) +#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x00129C])) +#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x0012A0])) +#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x0012A4])) +#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x0012A8])) +#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x0012AC])) +#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x0012B0])) +#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x0012B4])) +#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(&__IPSBAR[0x0012B8])) +#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x0012C0])) +#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(&__IPSBAR[0x0012BC])) +#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x0012C4])) +#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x0012C8])) +#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x0012CC])) +#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x0012D0])) +#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x0012D4])) +#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x0012D8])) +#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x0012DC])) +#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x0012E0])) + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_UN (0x00080000) +#define MCF_FEC_EIR_RL (0x00100000) +#define MCF_FEC_EIR_LC (0x00200000) +#define MCF_FEC_EIR_EBERR (0x00400000) +#define MCF_FEC_EIR_MII (0x00800000) +#define MCF_FEC_EIR_RXB (0x01000000) +#define MCF_FEC_EIR_RXF (0x02000000) +#define MCF_FEC_EIR_TXB (0x04000000) +#define MCF_FEC_EIR_TXF (0x08000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_UN (0x00080000) +#define MCF_FEC_EIMR_RL (0x00100000) +#define MCF_FEC_EIMR_LC (0x00200000) +#define MCF_FEC_EIMR_EBERR (0x00400000) +#define MCF_FEC_EIMR_MII (0x00800000) +#define MCF_FEC_EIMR_RXB (0x01000000) +#define MCF_FEC_EIMR_RXF (0x02000000) +#define MCF_FEC_EIMR_TXB (0x04000000) +#define MCF_FEC_EIMR_TXF (0x08000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0x00000000) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_RDAR */ +#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_TDAR */ +#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF_FEC_MMFR_ST_01 (0x40000000) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x00000001) +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_MII_MODE (0x00000004) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_BC_REJ (0x00000010) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x00000001) +#define MCF_FEC_TCR_HBC (0x00000002) +#define MCF_FEC_TCR_FDEN (0x00000004) +#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAUR */ +#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_TFWR */ +#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) + +/* Bit definitions and macros for MCF_FEC_FRBR */ +#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_FRSR */ +#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_ERDSR */ +#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_ETDSR */ +#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_EMRBR */ +#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) + +/********************************************************************* +* +* Ethernet PHY (PHY) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PHY_EPHYCTL0 (*(vuint8 *)(&__IPSBAR[0x1E0000])) +#define MCF_PHY_EPHYCTL1 (*(vuint8 *)(&__IPSBAR[0x1E0001])) +#define MCF_PHY_EPHYSR (*(vuint8 *)(&__IPSBAR[0x1E0002])) + +/* Bit definitions and macros for MCF_PHY_EPHYCTL0 */ +#define MCF_PHY_EPHYCTL0_EPHYIEN (0x01) +#define MCF_PHY_EPHYCTL0_EPHYWAI (0x04) +#define MCF_PHY_EPHYCTL0_LEDEN (0x08) +#define MCF_PHY_EPHYCTL0_DIS10 (0x10) +#define MCF_PHY_EPHYCTL0_DIS100 (0x20) +#define MCF_PHY_EPHYCTL0_ANDIS (0x40) +#define MCF_PHY_EPHYCTL0_EPHYEN (0x80) + +/* Bit definitions and macros for MCF_PHY_EPHYCTL1 */ +#define MCF_PHY_EPHYCTL1_PHYADDR(x) (((x)&0x1F)<<0) + +/* Bit definitions and macros for MCF_PHY_EPHYSR */ +#define MCF_PHY_EPHYSR_EPHYIF (0x01) +#define MCF_PHY_EPHYSR_10DIS (0x10) +#define MCF_PHY_EPHYSR_100DIS (0x20) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RNG_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000])) +#define MCF_RNG_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004])) +#define MCF_RNG_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008])) +#define MCF_RNG_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C])) + +/* Bit definitions and macros for MCF_RNG_RNGCR */ +#define MCF_RNG_RNGCR_GO (0x00000001) +#define MCF_RNG_RNGCR_HA (0x00000002) +#define MCF_RNG_RNGCR_IM (0x00000004) +#define MCF_RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for MCF_RNG_RNGSR */ +#define MCF_RNG_RNGSR_SV (0x00000001) +#define MCF_RNG_RNGSR_LRS (0x00000002) +#define MCF_RNG_RNGSR_FUF (0x00000004) +#define MCF_RNG_RNGSR_EI (0x00000008) +#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_RNG_RNGER */ +#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_RNG_RNGOUT */ +#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Real-time Clock (RTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x0003C0])) +#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x0003C4])) +#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x0003C8])) +#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x0003CC])) +#define MCF_RTC_CR (*(vuint32*)(&__IPSBAR[0x0003D0])) +#define MCF_RTC_ISR (*(vuint32*)(&__IPSBAR[0x0003D4])) +#define MCF_RTC_IER (*(vuint32*)(&__IPSBAR[0x0003D8])) +#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x0003DC])) +#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x0003E0])) +#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x0003E4])) + +/* Bit definitions and macros for MCF_RTC_HOURMIN */ +#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_SECONDS */ +#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_HM */ +#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ +#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_CR */ +#define MCF_RTC_CR_SWR (0x00000001) +#define MCF_RTC_CR_XTL(x) (((x)&0x00000003)<<5) +#define MCF_RTC_CR_EN (0x00000080) +#define MCF_RTC_CR_32768 (0x0) +#define MCF_RTC_CR_32000 (0x1) +#define MCF_RTC_CR_38400 (0x2) + +/* Bit definitions and macros for MCF_RTC_ISR */ +#define MCF_RTC_ISR_SW (0x00000001) +#define MCF_RTC_ISR_MIN (0x00000002) +#define MCF_RTC_ISR_ALM (0x00000004) +#define MCF_RTC_ISR_DAY (0x00000008) +#define MCF_RTC_ISR_1HZ (0x00000010) +#define MCF_RTC_ISR_HR (0x00000020) +#define MCF_RTC_ISR_2HZ (0x00000080) +#define MCF_RTC_ISR_SAM0 (0x00000100) +#define MCF_RTC_ISR_SAM1 (0x00000200) +#define MCF_RTC_ISR_SAM2 (0x00000400) +#define MCF_RTC_ISR_SAM3 (0x00000800) +#define MCF_RTC_ISR_SAM4 (0x00001000) +#define MCF_RTC_ISR_SAM5 (0x00002000) +#define MCF_RTC_ISR_SAM6 (0x00004000) +#define MCF_RTC_ISR_SAM7 (0x00008000) + +/* Bit definitions and macros for MCF_RTC_IER */ +#define MCF_RTC_IER_SW (0x00000001) +#define MCF_RTC_IER_MIN (0x00000002) +#define MCF_RTC_IER_ALM (0x00000004) +#define MCF_RTC_IER_DAY (0x00000008) +#define MCF_RTC_IER_1HZ (0x00000010) +#define MCF_RTC_IER_HR (0x00000020) +#define MCF_RTC_IER_2HZ (0x00000080) +#define MCF_RTC_IER_SAM0 (0x00000100) +#define MCF_RTC_IER_SAM1 (0x00000200) +#define MCF_RTC_IER_SAM2 (0x00000400) +#define MCF_RTC_IER_SAM3 (0x00000800) +#define MCF_RTC_IER_SAM4 (0x00001000) +#define MCF_RTC_IER_SAM5 (0x00002000) +#define MCF_RTC_IER_SAM6 (0x00004000) +#define MCF_RTC_IER_SAM7 (0x00008000) + +/* Bit definitions and macros for MCF_RTC_STPWCH */ +#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_DAYS */ +#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ +#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) + +/********************************************************************/ + +#endif /* __MCF5223x_H__ */ diff --git a/bsps/m68k/include/mcf5225x/fec.h b/bsps/m68k/include/mcf5225x/fec.h new file mode 100644 index 0000000000..8d8d6c3763 --- /dev/null +++ b/bsps/m68k/include/mcf5225x/fec.h @@ -0,0 +1,32 @@ +#ifndef FEC_H +#define FEC_H + +#include <arch/sys_arch.h> +#include <lwip/netif.h> +#include <stdbool.h> + +struct if_config { + u8_t flags; + u8_t hwaddr_len; + u16_t mtu; + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + sys_thread_t net_task; + void(*phy_init)(void); + u8_t name[2]; +}; + +extern err_t mcf5225xif_init(struct netif *); +extern void handle_rx_frame(struct netif*); + +extern void smi_init(u32_t); +extern void smi_write(u8_t,u8_t,u16_t); +extern u16_t smi_read(u8_t,u8_t); + +#define MAX_FRAME_LEN 1518 +#define MTU_SIZE (MAX_FRAME_LEN-18) +#define MSCR_MII_SPEED(clk) ((clk/5000000+1)<<1) +#define PHY_ADDR 1 +#define PHY_REG_ID1 2 +#define PHY_REG_ID2 3 + +#endif /* FEC_H */ diff --git a/bsps/m68k/include/mcf5225x/mcf5225x.h b/bsps/m68k/include/mcf5225x/mcf5225x.h new file mode 100644 index 0000000000..ded447ffac --- /dev/null +++ b/bsps/m68k/include/mcf5225x/mcf5225x.h @@ -0,0 +1,3552 @@ +/* + * File: mcf5225x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF5225x_H__ +#define __MCF5225x_H__ + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) +#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) +#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) +#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) +#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) +#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) +#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) +#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) +#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) +#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) +#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) +#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) +#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) +#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) +#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) +#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) +#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) +#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) +#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) +#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) +#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) + +/* Bit definitions and macros for MCF_SCM_IPSBAR */ +#define MCF_SCM_IPSBAR_V (0x00000001) +#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x00000200) +#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_CWDR (0x20) +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIC (0x01) +#define MCF_SCM_CWCR_CWTAVAL (0x02) +#define MCF_SCM_CWCR_CWTA (0x04) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_LPICR */ +#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_SCM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_PPMRH */ +#define MCF_SCM_PPMRH_CDPORTS (0x00000001) +#define MCF_SCM_PPMRH_CDEPORT (0x00000002) +#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) +#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) +#define MCF_SCM_PPMRH_CDCAN (0x00000020) +#define MCF_SCM_PPMRH_CDADC (0x00000080) +#define MCF_SCM_PPMRH_CDGPT (0x00000100) +#define MCF_SCM_PPMRH_CDPWN (0x00000200) +#define MCF_SCM_PPMRH_CDFCAN (0x00000400) +#define MCF_SCM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_SCM_PPMRL */ +#define MCF_SCM_PPMRL_CDG (0x00000002) +#define MCF_SCM_PPMRL_CDEIM (0x00000008) +#define MCF_SCM_PPMRL_CDDMA (0x00000010) +#define MCF_SCM_PPMRL_CDUART0 (0x00000020) +#define MCF_SCM_PPMRL_CDUART1 (0x00000040) +#define MCF_SCM_PPMRL_CDUART2 (0x00000080) +#define MCF_SCM_PPMRL_CDI2C0 (0x00000200) +#define MCF_SCM_PPMRL_CDI2C1 (0x00000800) +#define MCF_SCM_PPMRL_CDQSPI (0x00000400) +#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) +#define MCF_SCM_PPMRL_CDINTC1 (0x00040000) +#define MCF_SCM_PPMRL_CDFEC (0x00200000) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPARK_PRKLAST (0x00001000) +#define MCF_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF_SCM_MPARK_FIXED (0x00004000) +#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) +#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) +#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) +#define MCF_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF_SCM_MPARK_M2_P_EN (0x02000000) + +/* Bit definitions and macros for MCF_SCM_PPMRS */ +#define MCF_SCM_PPMRS_DISABLE_ALL (64) +#define MCF_SCM_PPMRS_DISABLE_CFM (43) +#define MCF_SCM_PPMRS_DISABLE_CAN (42) +#define MCF_SCM_PPMRS_DISABLE_PWM (41) +#define MCF_SCM_PPMRS_DISABLE_GPT (40) +#define MCF_SCM_PPMRS_DISABLE_ADC (39) +#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) +#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) +#define MCF_SCM_PPMRS_DISABLE_EPORT (33) +#define MCF_SCM_PPMRS_DISABLE_PORTS (32) +#define MCF_SCM_PPMRS_DISABLE_INTC (17) +#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) +#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) +#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) +#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) +#define MCF_SCM_PPMRS_DISABLE_QSPI (10) +#define MCF_SCM_PPMRS_DISABLE_I2C (9) +#define MCF_SCM_PPMRS_DISABLE_UART2 (7) +#define MCF_SCM_PPMRS_DISABLE_UART1 (6) +#define MCF_SCM_PPMRS_DISABLE_UART0 (5) +#define MCF_SCM_PPMRS_DISABLE_DMA (4) +#define MCF_SCM_PPMRS_SET_CDG (1) + +/* Bit definitions and macros for MCF_SCM_PPMRC */ +#define MCF_SCM_PPMRC_ENABLE_ALL (64) +#define MCF_SCM_PPMRC_ENABLE_CFM (43) +#define MCF_SCM_PPMRC_ENABLE_CAN (42) +#define MCF_SCM_PPMRC_ENABLE_PWM (41) +#define MCF_SCM_PPMRC_ENABLE_GPT (40) +#define MCF_SCM_PPMRC_ENABLE_ADC (39) +#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) +#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) +#define MCF_SCM_PPMRC_ENABLE_EPORT (33) +#define MCF_SCM_PPMRC_ENABLE_PORTS (32) +#define MCF_SCM_PPMRC_ENABLE_INTC (17) +#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) +#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) +#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) +#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) +#define MCF_SCM_PPMRC_ENABLE_QSPI (10) +#define MCF_SCM_PPMRC_ENABLE_I2C (9) +#define MCF_SCM_PPMRC_ENABLE_UART2 (7) +#define MCF_SCM_PPMRC_ENABLE_UART1 (6) +#define MCF_SCM_PPMRC_ENABLE_UART0 (5) +#define MCF_SCM_PPMRC_ENABLE_DMA (4) +#define MCF_SCM_PPMRC_CLEAR_CDG (1) + + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) +#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) +#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit definitions and macros for MCF_PMM_PPMRH */ +#define MCF_PMM_PPMRH_CDPORTS (0x00000001) +#define MCF_PMM_PPMRH_CDEPORT (0x00000002) +#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) +#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) +#define MCF_PMM_PPMRH_CDADC (0x00000080) +#define MCF_PMM_PPMRH_CDGPT (0x00000100) +#define MCF_PMM_PPMRH_CDPWM (0x00000200) +#define MCF_PMM_PPMRH_CDFCAN (0x00000400) +#define MCF_PMM_PPMRH_CDCFM (0x00000800) + +/* Bit definitions and macros for MCF_PMM_PPMRL */ +#define MCF_PMM_PPMRL_CDG (0x00000002) +#define MCF_PMM_PPMRL_CDEIM (0x00000008) +#define MCF_PMM_PPMRL_CDDMA (0x00000010) +#define MCF_PMM_PPMRL_CDUART0 (0x00000020) +#define MCF_PMM_PPMRL_CDUART1 (0x00000040) +#define MCF_PMM_PPMRL_CDUART2 (0x00000080) +#define MCF_PMM_PPMRL_CDI2C (0x00000200) +#define MCF_PMM_PPMRL_CDQSPI (0x00000400) +#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) +#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) +#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) +#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) +#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) + +/* Bit definitions and macros for MCF_PMM_LPICR */ +#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) +#define MCF_PMM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_LVDSE (0x02) +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) + + +/********************************************************************* +* +* DMA Controller Module (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) +#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) +#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) +#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) +#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) +#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) +#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) +#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) +#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) +#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) +#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) +#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) +#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) +#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) +#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) +#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) +#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) +#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) +#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) +#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) +#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) +#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) +#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) +#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) +#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) + +/* Bit definitions and macros for MCF_DMA_DMAREQC */ +#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for MCF_DMA_SAR */ +#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DAR */ +#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DSR */ +#define MCF_DMA_DSR_DONE (0x01) +#define MCF_DMA_DSR_BSY (0x02) +#define MCF_DMA_DSR_REQ (0x04) +#define MCF_DMA_DSR_BED (0x10) +#define MCF_DMA_DSR_BES (0x20) +#define MCF_DMA_DSR_CE (0x40) + +/* Bit definitions and macros for MCF_DMA_BCR */ +#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) +#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_DMA_DCR */ +#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) +#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) +#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) +#define MCF_DMA_DCR_D_REQ (0x00000080) +#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) +#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) +#define MCF_DMA_DCR_START (0x00010000) +#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) +#define MCF_DMA_DCR_DINC (0x00080000) +#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) +#define MCF_DMA_DCR_SINC (0x00400000) +#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) +#define MCF_DMA_DCR_AA (0x10000000) +#define MCF_DMA_DCR_CS (0x20000000) +#define MCF_DMA_DCR_EEXT (0x40000000) +#define MCF_DMA_DCR_INT (0x80000000) +#define MCF_DMA_DCR_BWC_16K (0x1) +#define MCF_DMA_DCR_BWC_32K (0x2) +#define MCF_DMA_DCR_BWC_64K (0x3) +#define MCF_DMA_DCR_BWC_128K (0x4) +#define MCF_DMA_DCR_BWC_256K (0x5) +#define MCF_DMA_DCR_BWC_512K (0x6) +#define MCF_DMA_DCR_BWC_1024K (0x7) +#define MCF_DMA_DCR_DMOD_DIS (0x0) +#define MCF_DMA_DCR_DMOD_16 (0x1) +#define MCF_DMA_DCR_DMOD_32 (0x2) +#define MCF_DMA_DCR_DMOD_64 (0x3) +#define MCF_DMA_DCR_DMOD_128 (0x4) +#define MCF_DMA_DCR_DMOD_256 (0x5) +#define MCF_DMA_DCR_DMOD_512 (0x6) +#define MCF_DMA_DCR_DMOD_1K (0x7) +#define MCF_DMA_DCR_DMOD_2K (0x8) +#define MCF_DMA_DCR_DMOD_4K (0x9) +#define MCF_DMA_DCR_DMOD_8K (0xA) +#define MCF_DMA_DCR_DMOD_16K (0xB) +#define MCF_DMA_DCR_DMOD_32K (0xC) +#define MCF_DMA_DCR_DMOD_64K (0xD) +#define MCF_DMA_DCR_DMOD_128K (0xE) +#define MCF_DMA_DCR_DMOD_256K (0xF) +#define MCF_DMA_DCR_SMOD_DIS (0x0) +#define MCF_DMA_DCR_SMOD_16 (0x1) +#define MCF_DMA_DCR_SMOD_32 (0x2) +#define MCF_DMA_DCR_SMOD_64 (0x3) +#define MCF_DMA_DCR_SMOD_128 (0x4) +#define MCF_DMA_DCR_SMOD_256 (0x5) +#define MCF_DMA_DCR_SMOD_512 (0x6) +#define MCF_DMA_DCR_SMOD_1K (0x7) +#define MCF_DMA_DCR_SMOD_2K (0x8) +#define MCF_DMA_DCR_SMOD_4K (0x9) +#define MCF_DMA_DCR_SMOD_8K (0xA) +#define MCF_DMA_DCR_SMOD_16K (0xB) +#define MCF_DMA_DCR_SMOD_32K (0xC) +#define MCF_DMA_DCR_SMOD_64K (0xD) +#define MCF_DMA_DCR_SMOD_128K (0xE) +#define MCF_DMA_DCR_SMOD_256K (0xF) +#define MCF_DMA_DCR_SSIZE_LONG (0x0) +#define MCF_DMA_DCR_SSIZE_BYTE (0x1) +#define MCF_DMA_DCR_SSIZE_WORD (0x2) +#define MCF_DMA_DCR_SSIZE_LINE (0x3) +#define MCF_DMA_DCR_DSIZE_LONG (0x0) +#define MCF_DMA_DCR_DSIZE_BYTE (0x1) +#define MCF_DMA_DCR_DSIZE_WORD (0x2) +#define MCF_DMA_DCR_DSIZE_LINE (0x3) +#define MCF_DMA_DCR_LCH1_CH0 (0x0) +#define MCF_DMA_DCR_LCH1_CH1 (0x1) +#define MCF_DMA_DCR_LCH1_CH2 (0x2) +#define MCF_DMA_DCR_LCH1_CH3 (0x3) +#define MCF_DMA_DCR_LCH2_CH0 (0x0) +#define MCF_DMA_DCR_LCH2_CH1 (0x1) +#define MCF_DMA_DCR_LCH2_CH2 (0x2) +#define MCF_DMA_DCR_LCH2_CH3 (0x3) + + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) +#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) +#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) +#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) +#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) +#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) +#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) +#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) +#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) +#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) +#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) +#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) +#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) +#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) +#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) +#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) +#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) +#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) +#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) +#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) +#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) +#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) +#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) +#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) +#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) +#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) +#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) +#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) +#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) +#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) +#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) +#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) +#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) +#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) +#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) +#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) +#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) +#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) +#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) +#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x01) +#define MCF_I2C_I2ICR_RE (0x02) +#define MCF_I2C_I2ICR_TE (0x04) +#define MCF_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) +#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) +#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) +#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) +#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) +#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) +#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) +#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) +#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) +#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) +#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) +#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) +#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) +#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) +#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) +#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) +#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) +#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) +#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) +#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) +#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) +#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) +#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) +#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) +#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) +#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) +#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) +#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) +#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) +#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) +#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) +#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) +#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) +#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) +#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) +#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) +#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) +#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) +#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) +#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) +#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) +#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) +#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) +#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) +#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) +#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) +#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) +#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) +#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) +#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) +#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) +#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) +#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) +#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) +#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) +#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) +#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) +#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) +#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) +#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) +#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) +#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) +#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) +#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) +#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) +#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) +#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) +#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) +#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) +#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) +#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) +#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) +#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) +#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) +#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) +#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) +#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) +#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) +#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) +#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) +#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) +#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) +#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) +#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) +#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) +#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) +#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) +#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) +#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) +#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) +#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) +#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) +#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) +#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) +#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) +#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) +#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) +#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) +#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) +#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) +#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) +#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) +#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) +#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) +#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) +#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) +#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) +#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) +#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) +#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) +#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) +#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) +#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) +#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) +#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) +#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) +#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) +#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) +#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) +#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) +#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) +#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) +#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) +#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) +#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) +#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) +#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) +#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) +#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) +#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) +#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) +#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) +#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) +#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) +#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) +#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) +#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) +#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) +#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) +#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) +#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) +#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) +#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) +#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) +#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) +#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) +#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) +#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) +#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) +#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) +#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) +#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) +#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) +#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) +#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) +#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) +#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) +#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) +#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) +#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) +#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) +#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) +#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) +#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) +#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) +#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) +#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) +#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) +#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) +#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) +#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) +#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) +#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) +#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) +#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) +#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) +#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) +#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) +#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) +#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) +#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) +#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) +#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) +#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) +#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) +#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) +#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) +#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) +#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) +#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) +#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) +#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) +#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) +#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) +#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) +#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) +#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) +#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) +#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) +#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) +#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) +#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) +#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) +#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) +#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) +#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) +#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) +#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) +#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) +#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) +#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) +#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) +#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) +#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) +#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) +#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) +#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) +#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) +#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) +#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) +#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) +#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) +#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) +#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) +#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) +#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) +#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) +#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) +#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) +#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) +#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) +#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) +#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) +#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) +#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) +#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) +#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) +#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) +#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) +#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) +#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) +#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) +#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) +#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) +#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) +#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) +#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) +#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) +#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) +#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) +#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) +#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) +#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) +#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) +#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) +#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) +#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) +#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) +#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) +#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) +#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) +#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) +#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_MASK32 (0x00000001) +#define MCF_INTC_IMRH_MASK33 (0x00000002) +#define MCF_INTC_IMRH_MASK34 (0x00000004) +#define MCF_INTC_IMRH_MASK35 (0x00000008) +#define MCF_INTC_IMRH_MASK36 (0x00000010) +#define MCF_INTC_IMRH_MASK37 (0x00000020) +#define MCF_INTC_IMRH_MASK38 (0x00000040) +#define MCF_INTC_IMRH_MASK39 (0x00000080) +#define MCF_INTC_IMRH_MASK40 (0x00000100) +#define MCF_INTC_IMRH_MASK41 (0x00000200) +#define MCF_INTC_IMRH_MASK42 (0x00000400) +#define MCF_INTC_IMRH_MASK43 (0x00000800) +#define MCF_INTC_IMRH_MASK44 (0x00001000) +#define MCF_INTC_IMRH_MASK45 (0x00002000) +#define MCF_INTC_IMRH_MASK46 (0x00004000) +#define MCF_INTC_IMRH_MASK47 (0x00008000) +#define MCF_INTC_IMRH_MASK48 (0x00010000) +#define MCF_INTC_IMRH_MASK49 (0x00020000) +#define MCF_INTC_IMRH_MASK50 (0x00040000) +#define MCF_INTC_IMRH_MASK51 (0x00080000) +#define MCF_INTC_IMRH_MASK52 (0x00100000) +#define MCF_INTC_IMRH_MASK53 (0x00200000) +#define MCF_INTC_IMRH_MASK54 (0x00400000) +#define MCF_INTC_IMRH_MASK55 (0x00800000) +#define MCF_INTC_IMRH_MASK56 (0x01000000) +#define MCF_INTC_IMRH_MASK57 (0x02000000) +#define MCF_INTC_IMRH_MASK58 (0x04000000) +#define MCF_INTC_IMRH_MASK59 (0x08000000) +#define MCF_INTC_IMRH_MASK60 (0x10000000) +#define MCF_INTC_IMRH_MASK61 (0x20000000) +#define MCF_INTC_IMRH_MASK62 (0x40000000) +#define MCF_INTC_IMRH_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x00000001) +#define MCF_INTC_IMRL_MASK1 (0x00000002) +#define MCF_INTC_IMRL_MASK2 (0x00000004) +#define MCF_INTC_IMRL_MASK3 (0x00000008) +#define MCF_INTC_IMRL_MASK4 (0x00000010) +#define MCF_INTC_IMRL_MASK5 (0x00000020) +#define MCF_INTC_IMRL_MASK6 (0x00000040) +#define MCF_INTC_IMRL_MASK7 (0x00000080) +#define MCF_INTC_IMRL_MASK8 (0x00000100) +#define MCF_INTC_IMRL_MASK9 (0x00000200) +#define MCF_INTC_IMRL_MASK10 (0x00000400) +#define MCF_INTC_IMRL_MASK11 (0x00000800) +#define MCF_INTC_IMRL_MASK12 (0x00001000) +#define MCF_INTC_IMRL_MASK13 (0x00002000) +#define MCF_INTC_IMRL_MASK14 (0x00004000) +#define MCF_INTC_IMRL_MASK15 (0x00008000) +#define MCF_INTC_IMRL_MASK16 (0x00010000) +#define MCF_INTC_IMRL_MASK17 (0x00020000) +#define MCF_INTC_IMRL_MASK18 (0x00040000) +#define MCF_INTC_IMRL_MASK19 (0x00080000) +#define MCF_INTC_IMRL_MASK20 (0x00100000) +#define MCF_INTC_IMRL_MASK21 (0x00200000) +#define MCF_INTC_IMRL_MASK22 (0x00400000) +#define MCF_INTC_IMRL_MASK23 (0x00800000) +#define MCF_INTC_IMRL_MASK24 (0x01000000) +#define MCF_INTC_IMRL_MASK25 (0x02000000) +#define MCF_INTC_IMRL_MASK26 (0x04000000) +#define MCF_INTC_IMRL_MASK27 (0x08000000) +#define MCF_INTC_IMRL_MASK28 (0x10000000) +#define MCF_INTC_IMRL_MASK29 (0x20000000) +#define MCF_INTC_IMRL_MASK30 (0x40000000) +#define MCF_INTC_IMRL_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF_GPIO_PORTTE (*(vuint8 *)(&__IPSBAR[0x100000])) +#define MCF_GPIO_PORTTF (*(vuint8 *)(&__IPSBAR[0x100001])) +#define MCF_GPIO_PORTTG (*(vuint8 *)(&__IPSBAR[0x100002])) +#define MCF_GPIO_PORTTH (*(vuint8 *)(&__IPSBAR[0x100003])) +#define MCF_GPIO_PORTTI (*(vuint8 *)(&__IPSBAR[0x100004])) +#define MCF_GPIO_PORTTJ (*(vuint8 *)(&__IPSBAR[0x100006])) +#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) +#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) +#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) +#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) +#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) +#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF_GPIO_DDRTE (*(vuint8 *)(&__IPSBAR[0x100018])) +#define MCF_GPIO_DDRTF (*(vuint8 *)(&__IPSBAR[0x100019])) +#define MCF_GPIO_DDRTG (*(vuint8 *)(&__IPSBAR[0x10001A])) +#define MCF_GPIO_DDRTH (*(vuint8 *)(&__IPSBAR[0x10001B])) +#define MCF_GPIO_DDRTI (*(vuint8 *)(&__IPSBAR[0x10001C])) +#define MCF_GPIO_DDRTJ (*(vuint8 *)(&__IPSBAR[0x10001E])) +#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) +#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) +#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) +#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) +#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) +#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) +#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) +#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) +#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) +#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) +#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) +#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) +#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) +#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) +#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) +#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) +#define MCF_GPIO_PTEPAR (*(vuint8 *)(&__IPSBAR[0x100060])) +#define MCF_GPIO_PTFPAR (*(vuint8 *)(&__IPSBAR[0x100061])) +#define MCF_GPIO_PTGPAR (*(vuint8 *)(&__IPSBAR[0x100062])) +#define MCF_GPIO_PTHPAR (*(vuint8 *)(&__IPSBAR[0x100090])) +#define MCF_GPIO_PTIPAR (*(vuint8*)(&__IPSBAR[0x100064])) +#define MCF_GPIO_PTJPAR (*(vuint8*)(&__IPSBAR[0x100066])) +#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) +#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) +#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) +#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) +#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) +#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) +#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) +#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) +#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) + +/* Bit definitions and macros for MCF_GPIO_PORTNQ */ +#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) +#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) +#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) +#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) +#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) +#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) +#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) +#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAN */ +#define MCF_GPIO_PORTAN_PORTAN0 (0x01) +#define MCF_GPIO_PORTAN_PORTAN1 (0x02) +#define MCF_GPIO_PORTAN_PORTAN2 (0x04) +#define MCF_GPIO_PORTAN_PORTAN3 (0x08) +#define MCF_GPIO_PORTAN_PORTAN4 (0x10) +#define MCF_GPIO_PORTAN_PORTAN5 (0x20) +#define MCF_GPIO_PORTAN_PORTAN6 (0x40) +#define MCF_GPIO_PORTAN_PORTAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTAS */ +#define MCF_GPIO_PORTAS_PORTAS0 (0x01) +#define MCF_GPIO_PORTAS_PORTAS1 (0x02) +#define MCF_GPIO_PORTAS_PORTAS2 (0x04) +#define MCF_GPIO_PORTAS_PORTAS3 (0x08) +#define MCF_GPIO_PORTAS_PORTAS4 (0x10) +#define MCF_GPIO_PORTAS_PORTAS5 (0x20) +#define MCF_GPIO_PORTAS_PORTAS6 (0x40) +#define MCF_GPIO_PORTAS_PORTAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTQS */ +#define MCF_GPIO_PORTQS_PORTQS0 (0x01) +#define MCF_GPIO_PORTQS_PORTQS1 (0x02) +#define MCF_GPIO_PORTQS_PORTQS2 (0x04) +#define MCF_GPIO_PORTQS_PORTQS3 (0x08) +#define MCF_GPIO_PORTQS_PORTQS4 (0x10) +#define MCF_GPIO_PORTQS_PORTQS5 (0x20) +#define MCF_GPIO_PORTQS_PORTQS6 (0x40) +#define MCF_GPIO_PORTQS_PORTQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTA */ +#define MCF_GPIO_PORTTA_PORTTA0 (0x01) +#define MCF_GPIO_PORTTA_PORTTA1 (0x02) +#define MCF_GPIO_PORTTA_PORTTA2 (0x04) +#define MCF_GPIO_PORTTA_PORTTA3 (0x08) +#define MCF_GPIO_PORTTA_PORTTA4 (0x10) +#define MCF_GPIO_PORTTA_PORTTA5 (0x20) +#define MCF_GPIO_PORTTA_PORTTA6 (0x40) +#define MCF_GPIO_PORTTA_PORTTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTC */ +#define MCF_GPIO_PORTTC_PORTTC0 (0x01) +#define MCF_GPIO_PORTTC_PORTTC1 (0x02) +#define MCF_GPIO_PORTTC_PORTTC2 (0x04) +#define MCF_GPIO_PORTTC_PORTTC3 (0x08) +#define MCF_GPIO_PORTTC_PORTTC4 (0x10) +#define MCF_GPIO_PORTTC_PORTTC5 (0x20) +#define MCF_GPIO_PORTTC_PORTTC6 (0x40) +#define MCF_GPIO_PORTTC_PORTTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTD */ +#define MCF_GPIO_PORTTD_PORTTD0 (0x01) +#define MCF_GPIO_PORTTD_PORTTD1 (0x02) +#define MCF_GPIO_PORTTD_PORTTD2 (0x04) +#define MCF_GPIO_PORTTD_PORTTD3 (0x08) +#define MCF_GPIO_PORTTD_PORTTD4 (0x10) +#define MCF_GPIO_PORTTD_PORTTD5 (0x20) +#define MCF_GPIO_PORTTD_PORTTD6 (0x40) +#define MCF_GPIO_PORTTD_PORTTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTE */ +#define MCF_GPIO_PORTTE_PORTTE0 (0x01) +#define MCF_GPIO_PORTTE_PORTTE1 (0x02) +#define MCF_GPIO_PORTTE_PORTTE2 (0x04) +#define MCF_GPIO_PORTTE_PORTTE3 (0x08) +#define MCF_GPIO_PORTTE_PORTTE4 (0x10) +#define MCF_GPIO_PORTTE_PORTTE5 (0x20) +#define MCF_GPIO_PORTTE_PORTTE6 (0x40) +#define MCF_GPIO_PORTTE_PORTTE7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTF */ +#define MCF_GPIO_PORTTF_PORTTF0 (0x01) +#define MCF_GPIO_PORTTF_PORTTF1 (0x02) +#define MCF_GPIO_PORTTF_PORTTF2 (0x04) +#define MCF_GPIO_PORTTF_PORTTF3 (0x08) +#define MCF_GPIO_PORTTF_PORTTF4 (0x10) +#define MCF_GPIO_PORTTF_PORTTF5 (0x20) +#define MCF_GPIO_PORTTF_PORTTF6 (0x40) +#define MCF_GPIO_PORTTF_PORTTF7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTG */ +#define MCF_GPIO_PORTTG_PORTTG0 (0x01) +#define MCF_GPIO_PORTTG_PORTTG1 (0x02) +#define MCF_GPIO_PORTTG_PORTTG2 (0x04) +#define MCF_GPIO_PORTTG_PORTTG3 (0x08) +#define MCF_GPIO_PORTTG_PORTTG4 (0x10) +#define MCF_GPIO_PORTTG_PORTTG5 (0x20) +#define MCF_GPIO_PORTTG_PORTTG6 (0x40) +#define MCF_GPIO_PORTTG_PORTTG7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTH */ +#define MCF_GPIO_PORTTH_PORTTH0 (0x01) +#define MCF_GPIO_PORTTH_PORTTH1 (0x02) +#define MCF_GPIO_PORTTH_PORTTH2 (0x04) +#define MCF_GPIO_PORTTH_PORTTH3 (0x08) +#define MCF_GPIO_PORTTH_PORTTH4 (0x10) +#define MCF_GPIO_PORTTH_PORTTH5 (0x20) +#define MCF_GPIO_PORTTH_PORTTH6 (0x40) +#define MCF_GPIO_PORTTH_PORTTH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTTI */ +#define MCF_GPIO_PORTTI_PORTTI0 (0x01) +#define MCF_GPIO_PORTTI_PORTTI1 (0x02) +#define MCF_GPIO_PORTTI_PORTTI2 (0x04) +#define MCF_GPIO_PORTTI_PORTTI3 (0x08) +#define MCF_GPIO_PORTTI_PORTTI4 (0x10) +#define MCF_GPIO_PORTTI_PORTTI5 (0x20) +#define MCF_GPIO_PORTTI_PORTTI6 (0x40) +#define MCF_GPIO_PORTTI_PORTTI7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUA */ +#define MCF_GPIO_PORTUA_PORTUA0 (0x01) +#define MCF_GPIO_PORTUA_PORTUA1 (0x02) +#define MCF_GPIO_PORTUA_PORTUA2 (0x04) +#define MCF_GPIO_PORTUA_PORTUA3 (0x08) +#define MCF_GPIO_PORTUA_PORTUA4 (0x10) +#define MCF_GPIO_PORTUA_PORTUA5 (0x20) +#define MCF_GPIO_PORTUA_PORTUA6 (0x40) +#define MCF_GPIO_PORTUA_PORTUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUB */ +#define MCF_GPIO_PORTUB_PORTUB0 (0x01) +#define MCF_GPIO_PORTUB_PORTUB1 (0x02) +#define MCF_GPIO_PORTUB_PORTUB2 (0x04) +#define MCF_GPIO_PORTUB_PORTUB3 (0x08) +#define MCF_GPIO_PORTUB_PORTUB4 (0x10) +#define MCF_GPIO_PORTUB_PORTUB5 (0x20) +#define MCF_GPIO_PORTUB_PORTUB6 (0x40) +#define MCF_GPIO_PORTUB_PORTUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTUC */ +#define MCF_GPIO_PORTUC_PORTUC0 (0x01) +#define MCF_GPIO_PORTUC_PORTUC1 (0x02) +#define MCF_GPIO_PORTUC_PORTUC2 (0x04) +#define MCF_GPIO_PORTUC_PORTUC3 (0x08) +#define MCF_GPIO_PORTUC_PORTUC4 (0x10) +#define MCF_GPIO_PORTUC_PORTUC5 (0x20) +#define MCF_GPIO_PORTUC_PORTUC6 (0x40) +#define MCF_GPIO_PORTUC_PORTUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTDD */ +#define MCF_GPIO_PORTDD_PORTDD0 (0x01) +#define MCF_GPIO_PORTDD_PORTDD1 (0x02) +#define MCF_GPIO_PORTDD_PORTDD2 (0x04) +#define MCF_GPIO_PORTDD_PORTDD3 (0x08) +#define MCF_GPIO_PORTDD_PORTDD4 (0x10) +#define MCF_GPIO_PORTDD_PORTDD5 (0x20) +#define MCF_GPIO_PORTDD_PORTDD6 (0x40) +#define MCF_GPIO_PORTDD_PORTDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTLD */ +#define MCF_GPIO_PORTLD_PORTLD0 (0x01) +#define MCF_GPIO_PORTLD_PORTLD1 (0x02) +#define MCF_GPIO_PORTLD_PORTLD2 (0x04) +#define MCF_GPIO_PORTLD_PORTLD3 (0x08) +#define MCF_GPIO_PORTLD_PORTLD4 (0x10) +#define MCF_GPIO_PORTLD_PORTLD5 (0x20) +#define MCF_GPIO_PORTLD_PORTLD6 (0x40) +#define MCF_GPIO_PORTLD_PORTLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PORTGP */ +#define MCF_GPIO_PORTGP_PORTGP0 (0x01) +#define MCF_GPIO_PORTGP_PORTGP1 (0x02) +#define MCF_GPIO_PORTGP_PORTGP2 (0x04) +#define MCF_GPIO_PORTGP_PORTGP3 (0x08) +#define MCF_GPIO_PORTGP_PORTGP4 (0x10) +#define MCF_GPIO_PORTGP_PORTGP5 (0x20) +#define MCF_GPIO_PORTGP_PORTGP6 (0x40) +#define MCF_GPIO_PORTGP_PORTGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRNQ */ +#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) +#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) +#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) +#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) +#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) +#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) +#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) +#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAN */ +#define MCF_GPIO_DDRAN_DDRAN0 (0x01) +#define MCF_GPIO_DDRAN_DDRAN1 (0x02) +#define MCF_GPIO_DDRAN_DDRAN2 (0x04) +#define MCF_GPIO_DDRAN_DDRAN3 (0x08) +#define MCF_GPIO_DDRAN_DDRAN4 (0x10) +#define MCF_GPIO_DDRAN_DDRAN5 (0x20) +#define MCF_GPIO_DDRAN_DDRAN6 (0x40) +#define MCF_GPIO_DDRAN_DDRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRAS */ +#define MCF_GPIO_DDRAS_DDRAS0 (0x01) +#define MCF_GPIO_DDRAS_DDRAS1 (0x02) +#define MCF_GPIO_DDRAS_DDRAS2 (0x04) +#define MCF_GPIO_DDRAS_DDRAS3 (0x08) +#define MCF_GPIO_DDRAS_DDRAS4 (0x10) +#define MCF_GPIO_DDRAS_DDRAS5 (0x20) +#define MCF_GPIO_DDRAS_DDRAS6 (0x40) +#define MCF_GPIO_DDRAS_DDRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRQS */ +#define MCF_GPIO_DDRQS_DDRQS0 (0x01) +#define MCF_GPIO_DDRQS_DDRQS1 (0x02) +#define MCF_GPIO_DDRQS_DDRQS2 (0x04) +#define MCF_GPIO_DDRQS_DDRQS3 (0x08) +#define MCF_GPIO_DDRQS_DDRQS4 (0x10) +#define MCF_GPIO_DDRQS_DDRQS5 (0x20) +#define MCF_GPIO_DDRQS_DDRQS6 (0x40) +#define MCF_GPIO_DDRQS_DDRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTA */ +#define MCF_GPIO_DDRTA_DDRTA0 (0x01) +#define MCF_GPIO_DDRTA_DDRTA1 (0x02) +#define MCF_GPIO_DDRTA_DDRTA2 (0x04) +#define MCF_GPIO_DDRTA_DDRTA3 (0x08) +#define MCF_GPIO_DDRTA_DDRTA4 (0x10) +#define MCF_GPIO_DDRTA_DDRTA5 (0x20) +#define MCF_GPIO_DDRTA_DDRTA6 (0x40) +#define MCF_GPIO_DDRTA_DDRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTC */ +#define MCF_GPIO_DDRTC_DDRTC0 (0x01) +#define MCF_GPIO_DDRTC_DDRTC1 (0x02) +#define MCF_GPIO_DDRTC_DDRTC2 (0x04) +#define MCF_GPIO_DDRTC_DDRTC3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_DDRTD */ +#define MCF_GPIO_DDRTD_DDRTD0 (0x01) +#define MCF_GPIO_DDRTD_DDRTD1 (0x02) +#define MCF_GPIO_DDRTD_DDRTD2 (0x04) +#define MCF_GPIO_DDRTD_DDRTD3 (0x08) +#define MCF_GPIO_DDRTD_DDRTD4 (0x10) +#define MCF_GPIO_DDRTD_DDRTD5 (0x20) +#define MCF_GPIO_DDRTD_DDRTD6 (0x40) +#define MCF_GPIO_DDRTD_DDRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTE */ +#define MCF_GPIO_DDRTE_DDRTE0 (0x01) +#define MCF_GPIO_DDRTE_DDRTE1 (0x02) +#define MCF_GPIO_DDRTE_DDRTE2 (0x04) +#define MCF_GPIO_DDRTE_DDRTE3 (0x08) +#define MCF_GPIO_DDRTE_DDRTE4 (0x10) +#define MCF_GPIO_DDRTE_DDRTE5 (0x20) +#define MCF_GPIO_DDRTE_DDRTE6 (0x40) +#define MCF_GPIO_DDRTE_DDRTE7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTF */ +#define MCF_GPIO_DDRTF_DDRTF0 (0x01) +#define MCF_GPIO_DDRTF_DDRTF1 (0x02) +#define MCF_GPIO_DDRTF_DDRTF2 (0x04) +#define MCF_GPIO_DDRTF_DDRTF3 (0x08) +#define MCF_GPIO_DDRTF_DDRTF4 (0x10) +#define MCF_GPIO_DDRTF_DDRTF5 (0x20) +#define MCF_GPIO_DDRTF_DDRTF6 (0x40) +#define MCF_GPIO_DDRTF_DDRTF7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTG */ +#define MCF_GPIO_DDRTG_DDRTG0 (0x01) +#define MCF_GPIO_DDRTG_DDRTG1 (0x02) +#define MCF_GPIO_DDRTG_DDRTG2 (0x04) +#define MCF_GPIO_DDRTG_DDRTG3 (0x08) +#define MCF_GPIO_DDRTG_DDRTG4 (0x10) +#define MCF_GPIO_DDRTG_DDRTG5 (0x20) +#define MCF_GPIO_DDRTG_DDRTG6 (0x40) +#define MCF_GPIO_DDRTG_DDRTG7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTH */ +#define MCF_GPIO_DDRTH_DDRTH0 (0x01) +#define MCF_GPIO_DDRTH_DDRTH1 (0x02) +#define MCF_GPIO_DDRTH_DDRTH2 (0x04) +#define MCF_GPIO_DDRTH_DDRTH3 (0x08) +#define MCF_GPIO_DDRTH_DDRTH4 (0x10) +#define MCF_GPIO_DDRTH_DDRTH5 (0x20) +#define MCF_GPIO_DDRTH_DDRTH6 (0x40) +#define MCF_GPIO_DDRTH_DDRTH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRTI */ +#define MCF_GPIO_DDRTI_DDRTI0 (0x01) +#define MCF_GPIO_DDRTI_DDRTI1 (0x02) +#define MCF_GPIO_DDRTI_DDRTI2 (0x04) +#define MCF_GPIO_DDRTI_DDRTI3 (0x08) +#define MCF_GPIO_DDRTI_DDRTI4 (0x10) +#define MCF_GPIO_DDRTI_DDRTI5 (0x20) +#define MCF_GPIO_DDRTI_DDRTI6 (0x40) +#define MCF_GPIO_DDRTI_DDRTI7 (0x80) + +/* Bit definiTJons and macros for MCF_GPIO_DDRTJ */ +#define MCF_GPIO_DDRTJ_DDRTJ0 (0x01) +#define MCF_GPIO_DDRTJ_DDRTJ1 (0x02) +#define MCF_GPIO_DDRTJ_DDRTJ2 (0x04) +#define MCF_GPIO_DDRTJ_DDRTJ3 (0x08) +#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10) +#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20) +#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40) +#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUA */ +#define MCF_GPIO_DDRUA_DDRUA0 (0x01) +#define MCF_GPIO_DDRUA_DDRUA1 (0x02) +#define MCF_GPIO_DDRUA_DDRUA2 (0x04) +#define MCF_GPIO_DDRUA_DDRUA3 (0x08) +#define MCF_GPIO_DDRUA_DDRUA4 (0x10) +#define MCF_GPIO_DDRUA_DDRUA5 (0x20) +#define MCF_GPIO_DDRUA_DDRUA6 (0x40) +#define MCF_GPIO_DDRUA_DDRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUB */ +#define MCF_GPIO_DDRUB_DDRUB0 (0x01) +#define MCF_GPIO_DDRUB_DDRUB1 (0x02) +#define MCF_GPIO_DDRUB_DDRUB2 (0x04) +#define MCF_GPIO_DDRUB_DDRUB3 (0x08) +#define MCF_GPIO_DDRUB_DDRUB4 (0x10) +#define MCF_GPIO_DDRUB_DDRUB5 (0x20) +#define MCF_GPIO_DDRUB_DDRUB6 (0x40) +#define MCF_GPIO_DDRUB_DDRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRUC */ +#define MCF_GPIO_DDRUC_DDRUC0 (0x01) +#define MCF_GPIO_DDRUC_DDRUC1 (0x02) +#define MCF_GPIO_DDRUC_DDRUC2 (0x04) +#define MCF_GPIO_DDRUC_DDRUC3 (0x08) +#define MCF_GPIO_DDRUC_DDRUC4 (0x10) +#define MCF_GPIO_DDRUC_DDRUC5 (0x20) +#define MCF_GPIO_DDRUC_DDRUC6 (0x40) +#define MCF_GPIO_DDRUC_DDRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRDD */ +#define MCF_GPIO_DDRDD_DDRDD0 (0x01) +#define MCF_GPIO_DDRDD_DDRDD1 (0x02) +#define MCF_GPIO_DDRDD_DDRDD2 (0x04) +#define MCF_GPIO_DDRDD_DDRDD3 (0x08) +#define MCF_GPIO_DDRDD_DDRDD4 (0x10) +#define MCF_GPIO_DDRDD_DDRDD5 (0x20) +#define MCF_GPIO_DDRDD_DDRDD6 (0x40) +#define MCF_GPIO_DDRDD_DDRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRLD */ +#define MCF_GPIO_DDRLD_DDRLD0 (0x01) +#define MCF_GPIO_DDRLD_DDRLD1 (0x02) +#define MCF_GPIO_DDRLD_DDRLD2 (0x04) +#define MCF_GPIO_DDRLD_DDRLD3 (0x08) +#define MCF_GPIO_DDRLD_DDRLD4 (0x10) +#define MCF_GPIO_DDRLD_DDRLD5 (0x20) +#define MCF_GPIO_DDRLD_DDRLD6 (0x40) +#define MCF_GPIO_DDRLD_DDRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_DDRGP */ +#define MCF_GPIO_DDRGP_DDRGP0 (0x01) +#define MCF_GPIO_DDRGP_DDRGP1 (0x02) +#define MCF_GPIO_DDRGP_DDRGP2 (0x04) +#define MCF_GPIO_DDRGP_DDRGP3 (0x08) +#define MCF_GPIO_DDRGP_DDRGP4 (0x10) +#define MCF_GPIO_DDRGP_DDRGP5 (0x20) +#define MCF_GPIO_DDRGP_DDRGP6 (0x40) +#define MCF_GPIO_DDRGP_DDRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETNQ */ +#define MCF_GPIO_SETNQ_SETNQ0 (0x01) +#define MCF_GPIO_SETNQ_SETNQ1 (0x02) +#define MCF_GPIO_SETNQ_SETNQ2 (0x04) +#define MCF_GPIO_SETNQ_SETNQ3 (0x08) +#define MCF_GPIO_SETNQ_SETNQ4 (0x10) +#define MCF_GPIO_SETNQ_SETNQ5 (0x20) +#define MCF_GPIO_SETNQ_SETNQ6 (0x40) +#define MCF_GPIO_SETNQ_SETNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAN */ +#define MCF_GPIO_SETAN_SETAN0 (0x01) +#define MCF_GPIO_SETAN_SETAN1 (0x02) +#define MCF_GPIO_SETAN_SETAN2 (0x04) +#define MCF_GPIO_SETAN_SETAN3 (0x08) +#define MCF_GPIO_SETAN_SETAN4 (0x10) +#define MCF_GPIO_SETAN_SETAN5 (0x20) +#define MCF_GPIO_SETAN_SETAN6 (0x40) +#define MCF_GPIO_SETAN_SETAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETAS */ +#define MCF_GPIO_SETAS_SETAS0 (0x01) +#define MCF_GPIO_SETAS_SETAS1 (0x02) +#define MCF_GPIO_SETAS_SETAS2 (0x04) +#define MCF_GPIO_SETAS_SETAS3 (0x08) +#define MCF_GPIO_SETAS_SETAS4 (0x10) +#define MCF_GPIO_SETAS_SETAS5 (0x20) +#define MCF_GPIO_SETAS_SETAS6 (0x40) +#define MCF_GPIO_SETAS_SETAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETQS */ +#define MCF_GPIO_SETQS_SETQS0 (0x01) +#define MCF_GPIO_SETQS_SETQS1 (0x02) +#define MCF_GPIO_SETQS_SETQS2 (0x04) +#define MCF_GPIO_SETQS_SETQS3 (0x08) +#define MCF_GPIO_SETQS_SETQS4 (0x10) +#define MCF_GPIO_SETQS_SETQS5 (0x20) +#define MCF_GPIO_SETQS_SETQS6 (0x40) +#define MCF_GPIO_SETQS_SETQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTA */ +#define MCF_GPIO_SETTA_SETTA0 (0x01) +#define MCF_GPIO_SETTA_SETTA1 (0x02) +#define MCF_GPIO_SETTA_SETTA2 (0x04) +#define MCF_GPIO_SETTA_SETTA3 (0x08) +#define MCF_GPIO_SETTA_SETTA4 (0x10) +#define MCF_GPIO_SETTA_SETTA5 (0x20) +#define MCF_GPIO_SETTA_SETTA6 (0x40) +#define MCF_GPIO_SETTA_SETTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTC */ +#define MCF_GPIO_SETTC_SETTC0 (0x01) +#define MCF_GPIO_SETTC_SETTC1 (0x02) +#define MCF_GPIO_SETTC_SETTC2 (0x04) +#define MCF_GPIO_SETTC_SETTC3 (0x08) +#define MCF_GPIO_SETTC_SETTC4 (0x10) +#define MCF_GPIO_SETTC_SETTC5 (0x20) +#define MCF_GPIO_SETTC_SETTC6 (0x40) +#define MCF_GPIO_SETTC_SETTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETTD */ +#define MCF_GPIO_SETTD_SETTD0 (0x01) +#define MCF_GPIO_SETTD_SETTD1 (0x02) +#define MCF_GPIO_SETTD_SETTD2 (0x04) +#define MCF_GPIO_SETTD_SETTD3 (0x08) +#define MCF_GPIO_SETTD_SETTD4 (0x10) +#define MCF_GPIO_SETTD_SETTD5 (0x20) +#define MCF_GPIO_SETTD_SETTD6 (0x40) +#define MCF_GPIO_SETTD_SETTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUA */ +#define MCF_GPIO_SETUA_SETUA0 (0x01) +#define MCF_GPIO_SETUA_SETUA1 (0x02) +#define MCF_GPIO_SETUA_SETUA2 (0x04) +#define MCF_GPIO_SETUA_SETUA3 (0x08) +#define MCF_GPIO_SETUA_SETUA4 (0x10) +#define MCF_GPIO_SETUA_SETUA5 (0x20) +#define MCF_GPIO_SETUA_SETUA6 (0x40) +#define MCF_GPIO_SETUA_SETUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUB */ +#define MCF_GPIO_SETUB_SETUB0 (0x01) +#define MCF_GPIO_SETUB_SETUB1 (0x02) +#define MCF_GPIO_SETUB_SETUB2 (0x04) +#define MCF_GPIO_SETUB_SETUB3 (0x08) +#define MCF_GPIO_SETUB_SETUB4 (0x10) +#define MCF_GPIO_SETUB_SETUB5 (0x20) +#define MCF_GPIO_SETUB_SETUB6 (0x40) +#define MCF_GPIO_SETUB_SETUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETUC */ +#define MCF_GPIO_SETUC_SETUC0 (0x01) +#define MCF_GPIO_SETUC_SETUC1 (0x02) +#define MCF_GPIO_SETUC_SETUC2 (0x04) +#define MCF_GPIO_SETUC_SETUC3 (0x08) +#define MCF_GPIO_SETUC_SETUC4 (0x10) +#define MCF_GPIO_SETUC_SETUC5 (0x20) +#define MCF_GPIO_SETUC_SETUC6 (0x40) +#define MCF_GPIO_SETUC_SETUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETDD */ +#define MCF_GPIO_SETDD_SETDD0 (0x01) +#define MCF_GPIO_SETDD_SETDD1 (0x02) +#define MCF_GPIO_SETDD_SETDD2 (0x04) +#define MCF_GPIO_SETDD_SETDD3 (0x08) +#define MCF_GPIO_SETDD_SETDD4 (0x10) +#define MCF_GPIO_SETDD_SETDD5 (0x20) +#define MCF_GPIO_SETDD_SETDD6 (0x40) +#define MCF_GPIO_SETDD_SETDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETLD */ +#define MCF_GPIO_SETLD_SETLD0 (0x01) +#define MCF_GPIO_SETLD_SETLD1 (0x02) +#define MCF_GPIO_SETLD_SETLD2 (0x04) +#define MCF_GPIO_SETLD_SETLD3 (0x08) +#define MCF_GPIO_SETLD_SETLD4 (0x10) +#define MCF_GPIO_SETLD_SETLD5 (0x20) +#define MCF_GPIO_SETLD_SETLD6 (0x40) +#define MCF_GPIO_SETLD_SETLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_SETGP */ +#define MCF_GPIO_SETGP_SETGP0 (0x01) +#define MCF_GPIO_SETGP_SETGP1 (0x02) +#define MCF_GPIO_SETGP_SETGP2 (0x04) +#define MCF_GPIO_SETGP_SETGP3 (0x08) +#define MCF_GPIO_SETGP_SETGP4 (0x10) +#define MCF_GPIO_SETGP_SETGP5 (0x20) +#define MCF_GPIO_SETGP_SETGP6 (0x40) +#define MCF_GPIO_SETGP_SETGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRNQ */ +#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) +#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) +#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) +#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) +#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) +#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) +#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) +#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAN */ +#define MCF_GPIO_CLRAN_CLRAN0 (0x01) +#define MCF_GPIO_CLRAN_CLRAN1 (0x02) +#define MCF_GPIO_CLRAN_CLRAN2 (0x04) +#define MCF_GPIO_CLRAN_CLRAN3 (0x08) +#define MCF_GPIO_CLRAN_CLRAN4 (0x10) +#define MCF_GPIO_CLRAN_CLRAN5 (0x20) +#define MCF_GPIO_CLRAN_CLRAN6 (0x40) +#define MCF_GPIO_CLRAN_CLRAN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRAS */ +#define MCF_GPIO_CLRAS_CLRAS0 (0x01) +#define MCF_GPIO_CLRAS_CLRAS1 (0x02) +#define MCF_GPIO_CLRAS_CLRAS2 (0x04) +#define MCF_GPIO_CLRAS_CLRAS3 (0x08) +#define MCF_GPIO_CLRAS_CLRAS4 (0x10) +#define MCF_GPIO_CLRAS_CLRAS5 (0x20) +#define MCF_GPIO_CLRAS_CLRAS6 (0x40) +#define MCF_GPIO_CLRAS_CLRAS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRQS */ +#define MCF_GPIO_CLRQS_CLRQS0 (0x01) +#define MCF_GPIO_CLRQS_CLRQS1 (0x02) +#define MCF_GPIO_CLRQS_CLRQS2 (0x04) +#define MCF_GPIO_CLRQS_CLRQS3 (0x08) +#define MCF_GPIO_CLRQS_CLRQS4 (0x10) +#define MCF_GPIO_CLRQS_CLRQS5 (0x20) +#define MCF_GPIO_CLRQS_CLRQS6 (0x40) +#define MCF_GPIO_CLRQS_CLRQS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTA */ +#define MCF_GPIO_CLRTA_CLRTA0 (0x01) +#define MCF_GPIO_CLRTA_CLRTA1 (0x02) +#define MCF_GPIO_CLRTA_CLRTA2 (0x04) +#define MCF_GPIO_CLRTA_CLRTA3 (0x08) +#define MCF_GPIO_CLRTA_CLRTA4 (0x10) +#define MCF_GPIO_CLRTA_CLRTA5 (0x20) +#define MCF_GPIO_CLRTA_CLRTA6 (0x40) +#define MCF_GPIO_CLRTA_CLRTA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTC */ +#define MCF_GPIO_CLRTC_CLRTC0 (0x01) +#define MCF_GPIO_CLRTC_CLRTC1 (0x02) +#define MCF_GPIO_CLRTC_CLRTC2 (0x04) +#define MCF_GPIO_CLRTC_CLRTC3 (0x08) +#define MCF_GPIO_CLRTC_CLRTC4 (0x10) +#define MCF_GPIO_CLRTC_CLRTC5 (0x20) +#define MCF_GPIO_CLRTC_CLRTC6 (0x40) +#define MCF_GPIO_CLRTC_CLRTC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRTD */ +#define MCF_GPIO_CLRTD_CLRTD0 (0x01) +#define MCF_GPIO_CLRTD_CLRTD1 (0x02) +#define MCF_GPIO_CLRTD_CLRTD2 (0x04) +#define MCF_GPIO_CLRTD_CLRTD3 (0x08) +#define MCF_GPIO_CLRTD_CLRTD4 (0x10) +#define MCF_GPIO_CLRTD_CLRTD5 (0x20) +#define MCF_GPIO_CLRTD_CLRTD6 (0x40) +#define MCF_GPIO_CLRTD_CLRTD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUA */ +#define MCF_GPIO_CLRUA_CLRUA0 (0x01) +#define MCF_GPIO_CLRUA_CLRUA1 (0x02) +#define MCF_GPIO_CLRUA_CLRUA2 (0x04) +#define MCF_GPIO_CLRUA_CLRUA3 (0x08) +#define MCF_GPIO_CLRUA_CLRUA4 (0x10) +#define MCF_GPIO_CLRUA_CLRUA5 (0x20) +#define MCF_GPIO_CLRUA_CLRUA6 (0x40) +#define MCF_GPIO_CLRUA_CLRUA7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUB */ +#define MCF_GPIO_CLRUB_CLRUB0 (0x01) +#define MCF_GPIO_CLRUB_CLRUB1 (0x02) +#define MCF_GPIO_CLRUB_CLRUB2 (0x04) +#define MCF_GPIO_CLRUB_CLRUB3 (0x08) +#define MCF_GPIO_CLRUB_CLRUB4 (0x10) +#define MCF_GPIO_CLRUB_CLRUB5 (0x20) +#define MCF_GPIO_CLRUB_CLRUB6 (0x40) +#define MCF_GPIO_CLRUB_CLRUB7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRUC */ +#define MCF_GPIO_CLRUC_CLRUC0 (0x01) +#define MCF_GPIO_CLRUC_CLRUC1 (0x02) +#define MCF_GPIO_CLRUC_CLRUC2 (0x04) +#define MCF_GPIO_CLRUC_CLRUC3 (0x08) +#define MCF_GPIO_CLRUC_CLRUC4 (0x10) +#define MCF_GPIO_CLRUC_CLRUC5 (0x20) +#define MCF_GPIO_CLRUC_CLRUC6 (0x40) +#define MCF_GPIO_CLRUC_CLRUC7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRDD */ +#define MCF_GPIO_CLRDD_CLRDD0 (0x01) +#define MCF_GPIO_CLRDD_CLRDD1 (0x02) +#define MCF_GPIO_CLRDD_CLRDD2 (0x04) +#define MCF_GPIO_CLRDD_CLRDD3 (0x08) +#define MCF_GPIO_CLRDD_CLRDD4 (0x10) +#define MCF_GPIO_CLRDD_CLRDD5 (0x20) +#define MCF_GPIO_CLRDD_CLRDD6 (0x40) +#define MCF_GPIO_CLRDD_CLRDD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRLD */ +#define MCF_GPIO_CLRLD_CLRLD0 (0x01) +#define MCF_GPIO_CLRLD_CLRLD1 (0x02) +#define MCF_GPIO_CLRLD_CLRLD2 (0x04) +#define MCF_GPIO_CLRLD_CLRLD3 (0x08) +#define MCF_GPIO_CLRLD_CLRLD4 (0x10) +#define MCF_GPIO_CLRLD_CLRLD5 (0x20) +#define MCF_GPIO_CLRLD_CLRLD6 (0x40) +#define MCF_GPIO_CLRLD_CLRLD7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_CLRGP */ +#define MCF_GPIO_CLRGP_CLRGP0 (0x01) +#define MCF_GPIO_CLRGP_CLRGP1 (0x02) +#define MCF_GPIO_CLRGP_CLRGP2 (0x04) +#define MCF_GPIO_CLRGP_CLRGP3 (0x08) +#define MCF_GPIO_CLRGP_CLRGP4 (0x10) +#define MCF_GPIO_CLRGP_CLRGP5 (0x20) +#define MCF_GPIO_CLRGP_CLRGP6 (0x40) +#define MCF_GPIO_CLRGP_CLRGP7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTIPAR */ +#define MCF_GPIO_PTIPAR_PTIPAR0 (0x01) +#define MCF_GPIO_PTIPAR_PTIPAR1 (0x02) +#define MCF_GPIO_PTIPAR_PTIPAR2 (0x04) +#define MCF_GPIO_PTIPAR_PTIPAR3 (0x08) +#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10) +#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20) +#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40) +#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTJPAR */ +#define MCF_GPIO_PTJPAR_PTJPAR0 (0x01) +#define MCF_GPIO_PTJPAR_PTJPAR1 (0x02) +#define MCF_GPIO_PTJPAR_PTJPAR2 (0x04) +#define MCF_GPIO_PTJPAR_PTJPAR3 (0x08) +#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10) +#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20) +#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40) +#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PNQPAR */ +#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) +#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) +#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) +#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) +#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) +#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) +#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) +#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) +#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) +#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) + +/* Bit definitions and macros for MCF_GPIO_PANPAR */ +#define MCF_GPIO_PANPAR_PANPAR0 (0x01) +#define MCF_GPIO_PANPAR_PANPAR1 (0x02) +#define MCF_GPIO_PANPAR_PANPAR2 (0x04) +#define MCF_GPIO_PANPAR_PANPAR3 (0x08) +#define MCF_GPIO_PANPAR_PANPAR4 (0x10) +#define MCF_GPIO_PANPAR_PANPAR5 (0x20) +#define MCF_GPIO_PANPAR_PANPAR6 (0x40) +#define MCF_GPIO_PANPAR_PANPAR7 (0x80) +#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) +#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) +#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) +#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) +#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) +#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) +#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) +#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) +#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PASPAR */ +#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) +#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) +#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) +#define MCF_GPIO_PASPAR_SCL_SCL (0x01) +#define MCF_GPIO_PASPAR_SDA_SDA (0x04) +#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) +#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) +#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) +#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) +#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) +#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) +#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) +#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PQSPAR */ +#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) +#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) +#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) +#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) +#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) +#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) +#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) +#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) +#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) +#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) +#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) +#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) +#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) +#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) +#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) +#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) +#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) +#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) + +/* Bit definitions and macros for MCF_GPIO_PTAPAR */ +#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) +#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) +#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) +#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) +#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) +#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) +#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) +#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) +#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTCPAR */ +#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) +#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) +#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) +#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) +#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) +#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) +#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) +#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PTDPAR */ +#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) +#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) +#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) +#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) +#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) +#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) +#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) +#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) +#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PTEPAR */ +#define MCF_GPIO_PTEPAR_PTEPAR0 (0x01) +#define MCF_GPIO_PTEPAR_PTEPAR1 (0x02) +#define MCF_GPIO_PTEPAR_PTEPAR2 (0x04) +#define MCF_GPIO_PTEPAR_PTEPAR3 (0x08) +#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10) +#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20) +#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40) +#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTFPAR */ +#define MCF_GPIO_PTFPAR_PTFPAR0 (0x01) +#define MCF_GPIO_PTFPAR_PTFPAR1 (0x02) +#define MCF_GPIO_PTFPAR_PTFPAR2 (0x04) +#define MCF_GPIO_PTFPAR_PTFPAR3 (0x08) +#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10) +#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20) +#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40) +#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTGPAR */ +#define MCF_GPIO_PTGPAR_PTGPAR0 (0x01) +#define MCF_GPIO_PTGPAR_PTGPAR1 (0x02) +#define MCF_GPIO_PTGPAR_PTGPAR2 (0x04) +#define MCF_GPIO_PTGPAR_PTGPAR3 (0x08) +#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10) +#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20) +#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40) +#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PTHPAR */ +#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x0003)<<12) + + +/* Bit definitions and macros for MCF_GPIO_PUAPAR */ +#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) +#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) +#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) +#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) +#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) +#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) +#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) + +/* Bit definitions and macros for MCF_GPIO_PUBPAR */ +#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) +#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) +#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) +#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) +#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) +#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) +#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) +#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) +#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) + +/* Bit definitions and macros for MCF_GPIO_PUCPAR */ +#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) +#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) +#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) +#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) +#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDPAR */ +#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) +#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) +#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) +#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) +#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) +#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) +#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) +#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) +#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) +#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) +#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) +#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) +#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) +#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) +#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) +#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) +#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PLDPAR */ +#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) +#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) +#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) +#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) +#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) +#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) +#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) +#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) +#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) +#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) +#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) +#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) +#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) +#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) +#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) + +/* Bit definitions and macros for MCF_GPIO_PGPPAR */ +#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) +#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) +#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) +#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) +#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) +#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) +#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) +#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) +#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) +#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) +#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) +#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) +#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) +#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) +#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) +#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) +#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PWOR */ +#define MCF_GPIO_PWOR_PWOR0 (0x0001) +#define MCF_GPIO_PWOR_PWOR1 (0x0002) +#define MCF_GPIO_PWOR_PWOR2 (0x0004) +#define MCF_GPIO_PWOR_PWOR3 (0x0008) +#define MCF_GPIO_PWOR_PWOR4 (0x0010) +#define MCF_GPIO_PWOR_PWOR5 (0x0020) +#define MCF_GPIO_PWOR_PWOR6 (0x0040) +#define MCF_GPIO_PWOR_PWOR7 (0x0080) +#define MCF_GPIO_PWOR_PWOR8 (0x0100) +#define MCF_GPIO_PWOR_PWOR9 (0x0200) +#define MCF_GPIO_PWOR_PWOR10 (0x0400) +#define MCF_GPIO_PWOR_PWOR11 (0x0800) +#define MCF_GPIO_PWOR_PWOR12 (0x1000) +#define MCF_GPIO_PWOR_PWOR13 (0x2000) +#define MCF_GPIO_PWOR_PWOR14 (0x4000) +#define MCF_GPIO_PWOR_PWOR15 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRH */ +#define MCF_GPIO_PDSRH_PDSR32 (0x0001) +#define MCF_GPIO_PDSRH_PDSR33 (0x0002) +#define MCF_GPIO_PDSRH_PDSR34 (0x0004) +#define MCF_GPIO_PDSRH_PDSR35 (0x0008) +#define MCF_GPIO_PDSRH_PDSR36 (0x0010) +#define MCF_GPIO_PDSRH_PDSR37 (0x0020) +#define MCF_GPIO_PDSRH_PDSR38 (0x0040) +#define MCF_GPIO_PDSRH_PDSR39 (0x0080) +#define MCF_GPIO_PDSRH_PDSR40 (0x0100) +#define MCF_GPIO_PDSRH_PDSR41 (0x0200) +#define MCF_GPIO_PDSRH_PDSR42 (0x0400) +#define MCF_GPIO_PDSRH_PDSR43 (0x0800) +#define MCF_GPIO_PDSRH_PDSR44 (0x1000) +#define MCF_GPIO_PDSRH_PDSR45 (0x2000) +#define MCF_GPIO_PDSRH_PDSR46 (0x4000) +#define MCF_GPIO_PDSRH_PDSR47 (0x8000) + +/* Bit definitions and macros for MCF_GPIO_PDSRL */ +#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) +#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) +#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) +#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) +#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) +#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) +#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) +#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) +#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) +#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) +#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) +#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) +#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) +#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) +#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) +#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) +#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) +#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) +#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) +#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) +#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) +#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) +#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) +#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) +#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) +#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) +#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) +#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) +#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) +#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) +#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) +#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) + +/********************************************************************* +* +* ColdFire Integration Module (CIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) +#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) +#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) +#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) +#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) + +/* Bit definitions and macros for MCF_CIM_RCR */ +#define MCF_CIM_RCR_LVDE (0x01) +#define MCF_CIM_RCR_LVDRE (0x04) +#define MCF_CIM_RCR_LVDIE (0x08) +#define MCF_CIM_RCR_LVDF (0x10) +#define MCF_CIM_RCR_FRCRSTOUT (0x40) +#define MCF_CIM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_CIM_RSR */ +#define MCF_CIM_RSR_LOL (0x01) +#define MCF_CIM_RSR_LOC (0x02) +#define MCF_CIM_RSR_EXT (0x04) +#define MCF_CIM_RSR_POR (0x08) +#define MCF_CIM_RSR_WDR (0x10) +#define MCF_CIM_RSR_SOFT (0x20) +#define MCF_CIM_RSR_LVD (0x40) + +/* Bit definitions and macros for MCF_CIM_CCR */ +#define MCF_CIM_CCR_LOAD (0x8000) +#define MCF_CIM_CCR_EZPORT (0x05) +#define MCF_CIM_CCR_SCHIP (0x06) +#define MCF_CIM_CCR_MODE(x) (((x)&0x7)<<8) + +/* Bit definitions and macros for MCF_CIM_LPCR */ +#define MCF_CIM_LPCR_LVDSE (0x02) +#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_CIM_LPCR_LPMD_STOP (0xC0) +#define MCF_CIM_LPCR_LPMD_WAIT (0x80) +#define MCF_CIM_LPCR_LPMD_DOZE (0x40) +#define MCF_CIM_LPCR_LPMD_RUN (0x00) + +/* Bit definitions and macros for MCF_CIM_RCON */ +#define MCF_CIM_RCON_RLOAD (0x0020) + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) +#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) +#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) +#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) +#define MCF_CLOCK_CCLR (*(vuint8 *)(&__IPSBAR[0x120009])) +#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) +#define MCF_CLOCK_RTCCR (*(vuint8*)(&__IPSBAR[0x120012])) + +/* Bit definitions and macros for MCF_CLOCK_SYNCR */ +#define MCF_CLOCK_SYNCR_PLLEN (0x0001) +#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) +#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) +#define MCF_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF_CLOCK_SYNCR_LOLRE (0x8000) + +/* Bit definitions and macros for MCF_CLOCK_SYNSR */ +#define MCF_CLOCK_SYNSR_LOCS (0x04) +#define MCF_CLOCK_SYNSR_LOCK (0x08) +#define MCF_CLOCK_SYNSR_LOCKS (0x10) +#define MCF_CLOCK_SYNSR_CRYOSC (0x20) +#define MCF_CLOCK_SYNSR_OCOSC (0x40) +#define MCF_CLOCK_SYNSR_EXTOSC (0x80) + +/* Bit definitions and macros for MCF_CLOCK_LPCR */ +#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_CLOCK_CCHR */ +#define MCF_CLOCK_CCLR_PRIM_OSC (0x00) +#define MCF_CLOCK_CCLR_REL_OSC (0x01) +#define MCF_CLOCK_CCLR_SEC_OSC (0x02) +#define MCF_CLOCK_CCLR_SEC1_OSC (0x03) + +/* Bit definitions and macros for MCF_CLOCK_RTCDR */ +#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CLOCK_RTCCR */ +#define MCF_CLOCK_RTCCR_RTCSEL 0x01U +#define MCF_CLOCK_RTCCR_LPEN 0x02U +#define MCF_CLOCK_RTCCR_REFS 0x04U +#define MCF_CLOCK_RTCCR_KHZEN 0x08U +#define MCF_CLOCK_RTCCR_OSCEN 0x10U +#define MCF_CLOCK_RTCCR_EXTALEN 0x40U + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) +#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) +#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) +#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) +#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) +#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) +#define MCF_EPORT_EPDDR_EPDD8 (0x01) +#define MCF_EPORT_EPDDR_EPDD9 (0x02) +#define MCF_EPORT_EPDDR_EPDD10 (0x04) +#define MCF_EPORT_EPDDR_EPDD11 (0x08) +#define MCF_EPORT_EPDDR_EPDD12 (0x10) +#define MCF_EPORT_EPDDR_EPDD13 (0x20) +#define MCF_EPORT_EPDDR_EPDD14 (0x40) +#define MCF_EPORT_EPDDR_EPDD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) +#define MCF_EPORT_EPIER_EPIE8 (0x01) +#define MCF_EPORT_EPIER_EPIE9 (0x02) +#define MCF_EPORT_EPIER_EPIE10 (0x04) +#define MCF_EPORT_EPIER_EPIE11 (0x08) +#define MCF_EPORT_EPIER_EPIE12 (0x10) +#define MCF_EPORT_EPIER_EPIE13 (0x20) +#define MCF_EPORT_EPIER_EPIE14 (0x40) +#define MCF_EPORT_EPIER_EPIE15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) +#define MCF_EPORT_EPDR_EPD8 (0x01) +#define MCF_EPORT_EPDR_EPD9 (0x02) +#define MCF_EPORT_EPDR_EPD10 (0x04) +#define MCF_EPORT_EPDR_EPD11 (0x08) +#define MCF_EPORT_EPDR_EPD12 (0x10) +#define MCF_EPORT_EPDR_EPD13 (0x20) +#define MCF_EPORT_EPDR_EPD14 (0x40) +#define MCF_EPORT_EPDR_EPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) +#define MCF_EPORT_EPPDR_EPPD8 (0x01) +#define MCF_EPORT_EPPDR_EPPD9 (0x02) +#define MCF_EPORT_EPPDR_EPPD10 (0x04) +#define MCF_EPORT_EPPDR_EPPD11 (0x08) +#define MCF_EPORT_EPPDR_EPPD12 (0x10) +#define MCF_EPORT_EPPDR_EPPD13 (0x20) +#define MCF_EPORT_EPPDR_EPPD14 (0x40) +#define MCF_EPORT_EPPDR_EPPD15 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) +#define MCF_EPORT_EPFR_EPF8 (0x01) +#define MCF_EPORT_EPFR_EPF9 (0x02) +#define MCF_EPORT_EPFR_EPF10 (0x04) +#define MCF_EPORT_EPFR_EPF11 (0x08) +#define MCF_EPORT_EPFR_EPF12 (0x10) +#define MCF_EPORT_EPFR_EPF13 (0x20) +#define MCF_EPORT_EPFR_EPF14 (0x40) +#define MCF_EPORT_EPFR_EPF15 (0x80) + + +/********************************************************************* +* +* Backup Watchdog Timer Module (BWT) +* +*********************************************************************/ + +#define MCF_BWT_WCR (*(vuint16*)(&__IPSBAR[0x140000])) +#define MCF_BWT_WMR (*(vuint16*)(&__IPSBAR[0x140002])) +#define MCF_BWT_WCNTR (*(vuint16*)(&__IPSBAR[0x140004])) +#define MCF_BWT_WSR (*(vuint16*)(&__IPSBAR[0x140006])) + +/* Bit definitions and macros for MCF_BWT_WCR */ +#define MCF_BWT_WCR_EN 0x01 +#define MCF_BWT_WCR_DOZE 0x04 +#define MCF_BWT_WCR_WAIT 0x08 +#define MCF_BWT_WCR_STOP 0x10 + +#define MCF_BWT_WSR_SEQ1 0x5555 +#define MCF_BWT_WSR_SEQ2 0xAAAA + +//MPR: TODO this Modules is new in mcf52258 vs. mcf52235 and some macros must be written first + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) +#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) +#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) +#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) +#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) +#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) +#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) +#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Analog-to-Digital Converter (ADC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) +#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) +#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) +#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) +#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) +#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) +#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) +#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) +#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) +#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) +#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) +#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) +#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) +#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) +#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) +#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) +#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) +#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) +#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) +#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) +#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) +#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) +#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) +#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) +#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) +#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) +#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) +#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) +#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) +#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) +#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) +#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) +#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) +#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) +#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) +#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) +#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) +#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) +#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) +#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) +#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) +#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) +#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) +#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) +#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) +#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) +#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) + +/* Bit definitions and macros for MCF_ADC_CTRL1 */ +#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) +#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) +#define MCF_ADC_CTRL1_HLMTIE (0x0100) +#define MCF_ADC_CTRL1_LLMTIE (0x0200) +#define MCF_ADC_CTRL1_ZCIE (0x0400) +#define MCF_ADC_CTRL1_EOSIE0 (0x0800) +#define MCF_ADC_CTRL1_SYNC0 (0x1000) +#define MCF_ADC_CTRL1_START0 (0x2000) +#define MCF_ADC_CTRL1_STOP0 (0x4000) + +/* Bit definitions and macros for MCF_ADC_CTRL2 */ +#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) +#define MCF_ADC_CTRL2_SIMULT (0x0020) +#define MCF_ADC_CTRL2_EOSIE1 (0x0800) +#define MCF_ADC_CTRL2_SYNC1 (0x1000) +#define MCF_ADC_CTRL2_START1 (0x2000) +#define MCF_ADC_CTRL2_STOP1 (0x4000) + +/* Bit definitions and macros for MCF_ADC_ADZCC */ +#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) +#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) +#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) +#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) +#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) +#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) +#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) +#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_ADC_ADLST1 */ +#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADLST2 */ +#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) +#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) +#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) +#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) + +/* Bit definitions and macros for MCF_ADC_ADSDIS */ +#define MCF_ADC_ADSDIS_DS0 (0x0001) +#define MCF_ADC_ADSDIS_DS1 (0x0002) +#define MCF_ADC_ADSDIS_DS2 (0x0004) +#define MCF_ADC_ADSDIS_DS3 (0x0008) +#define MCF_ADC_ADSDIS_DS4 (0x0010) +#define MCF_ADC_ADSDIS_DS5 (0x0020) +#define MCF_ADC_ADSDIS_DS6 (0x0040) +#define MCF_ADC_ADSDIS_DS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADSTAT */ +#define MCF_ADC_ADSTAT_RDY0 (0x0001) +#define MCF_ADC_ADSTAT_RDY1 (0x0002) +#define MCF_ADC_ADSTAT_RDY2 (0x0004) +#define MCF_ADC_ADSTAT_RDY3 (0x0008) +#define MCF_ADC_ADSTAT_RDY4 (0x0010) +#define MCF_ADC_ADSTAT_RDY5 (0x0020) +#define MCF_ADC_ADSTAT_RDY6 (0x0040) +#define MCF_ADC_ADSTAT_RDY7 (0x0080) +#define MCF_ADC_ADSTAT_HLMT (0x0100) +#define MCF_ADC_ADSTAT_LLMTI (0x0200) +#define MCF_ADC_ADSTAT_ZCI (0x0400) +#define MCF_ADC_ADSTAT_EOSI (0x0800) +#define MCF_ADC_ADSTAT_CIP (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLSTAT */ +#define MCF_ADC_ADLSTAT_LLS0 (0x0001) +#define MCF_ADC_ADLSTAT_LLS1 (0x0002) +#define MCF_ADC_ADLSTAT_LLS2 (0x0004) +#define MCF_ADC_ADLSTAT_LLS3 (0x0008) +#define MCF_ADC_ADLSTAT_LLS4 (0x0010) +#define MCF_ADC_ADLSTAT_LLS5 (0x0020) +#define MCF_ADC_ADLSTAT_LLS6 (0x0040) +#define MCF_ADC_ADLSTAT_LLS7 (0x0080) +#define MCF_ADC_ADLSTAT_HLS0 (0x0100) +#define MCF_ADC_ADLSTAT_HLS1 (0x0200) +#define MCF_ADC_ADLSTAT_HLS2 (0x0400) +#define MCF_ADC_ADLSTAT_HLS3 (0x0800) +#define MCF_ADC_ADLSTAT_HLS4 (0x1000) +#define MCF_ADC_ADLSTAT_HLS5 (0x2000) +#define MCF_ADC_ADLSTAT_HLS6 (0x4000) +#define MCF_ADC_ADLSTAT_HLS7 (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ +#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) +#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) +#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) +#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) +#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) +#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) +#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) +#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) + +/* Bit definitions and macros for MCF_ADC_ADRSLT */ +#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) +#define MCF_ADC_ADRSLT_SEXT (0x8000) + +/* Bit definitions and macros for MCF_ADC_ADLLMT */ +#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADHLMT */ +#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_ADOFS */ +#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) + +/* Bit definitions and macros for MCF_ADC_POWER */ +#define MCF_ADC_POWER_PD0 (0x0001) +#define MCF_ADC_POWER_PD1 (0x0002) +#define MCF_ADC_POWER_PD2 (0x0004) +#define MCF_ADC_POWER_APD (0x0008) +#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) +#define MCF_ADC_POWER_PSTS0 (0x0400) +#define MCF_ADC_POWER_PSTS1 (0x0800) +#define MCF_ADC_POWER_PSTS2 (0x1000) +#define MCF_ADC_POWER_ASTBY (0x8000) + +/* Bit definitions and macros for MCF_ADC_CAL */ +#define MCF_ADC_CAL_CAL0 (0x0001) +#define MCF_ADC_CAL_CRS0 (0x0002) +#define MCF_ADC_CAL_CAL1 (0x0004) +#define MCF_ADC_CAL_CRS1 (0x0008) + +/********************************************************************* +* +* General Purpose Timer (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) +#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) +#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) +#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) +#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) +#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) +#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) +#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +/* Bit definitions and macros for MCF_GPT_GPTIOS */ +#define MCF_GPT_GPTIOS_IOS0 (0x01) +#define MCF_GPT_GPTIOS_IOS1 (0x02) +#define MCF_GPT_GPTIOS_IOS2 (0x04) +#define MCF_GPT_GPTIOS_IOS3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCFORC */ +#define MCF_GPT_GPTCFORC_FOC0 (0x01) +#define MCF_GPT_GPTCFORC_FOC1 (0x02) +#define MCF_GPT_GPTCFORC_FOC2 (0x04) +#define MCF_GPT_GPTCFORC_FOC3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTOC3D */ +#define MCF_GPT_GPTOC3D_OC3D0 (0x01) +#define MCF_GPT_GPTOC3D_OC3D1 (0x02) +#define MCF_GPT_GPTOC3D_OC3D2 (0x04) +#define MCF_GPT_GPTOC3D_OC3D3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ +#define MCF_GPT_GPTSCR1_TFFCA (0x10) +#define MCF_GPT_GPTSCR1_GPTEN (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTTOV */ +#define MCF_GPT_GPTTOV_TOV0 (0x01) +#define MCF_GPT_GPTTOV_TOV1 (0x02) +#define MCF_GPT_GPTTOV_TOV2 (0x04) +#define MCF_GPT_GPTTOV_TOV3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ +#define MCF_GPT_GPTCTL1_OL0 (0x01) +#define MCF_GPT_GPTCTL1_OM0 (0x02) +#define MCF_GPT_GPTCTL1_OL1 (0x04) +#define MCF_GPT_GPTCTL1_OM1 (0x08) +#define MCF_GPT_GPTCTL1_OL2 (0x10) +#define MCF_GPT_GPTCTL1_OM2 (0x20) +#define MCF_GPT_GPTCTL1_OL3 (0x40) +#define MCF_GPT_GPTCTL1_OM3 (0x80) +#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) +#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) +#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) +#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) +#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) +#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) +#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) +#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) +#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) +#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) +#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) +#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) +#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ +#define MCF_GPT_GPTCTL2_EDG0A (0x01) +#define MCF_GPT_GPTCTL2_EDG0B (0x02) +#define MCF_GPT_GPTCTL2_EDG1A (0x04) +#define MCF_GPT_GPTCTL2_EDG1B (0x08) +#define MCF_GPT_GPTCTL2_EDG2A (0x10) +#define MCF_GPT_GPTCTL2_EDG2B (0x20) +#define MCF_GPT_GPTCTL2_EDG3A (0x40) +#define MCF_GPT_GPTCTL2_EDG3B (0x80) +#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) +#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) +#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) +#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) +#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) +#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) +#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) +#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) +#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) +#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) +#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) +#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) +#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTIE */ +#define MCF_GPT_GPTIE_CI0 (0x01) +#define MCF_GPT_GPTIE_CI1 (0x02) +#define MCF_GPT_GPTIE_CI2 (0x04) +#define MCF_GPT_GPTIE_CI3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ +#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) +#define MCF_GPT_GPTSCR2_TCRE (0x08) +#define MCF_GPT_GPTSCR2_RDPT (0x10) +#define MCF_GPT_GPTSCR2_PUPT (0x20) +#define MCF_GPT_GPTSCR2_TOI (0x80) +#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) +#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) +#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) +#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) +#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) +#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) +#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) +#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) + +/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ +#define MCF_GPT_GPTFLG1_CF0 (0x01) +#define MCF_GPT_GPTFLG1_CF1 (0x02) +#define MCF_GPT_GPTFLG1_CF2 (0x04) +#define MCF_GPT_GPTFLG1_CF3 (0x08) + +/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ +#define MCF_GPT_GPTFLG2_CF0 (0x01) +#define MCF_GPT_GPTFLG2_CF1 (0x02) +#define MCF_GPT_GPTFLG2_CF2 (0x04) +#define MCF_GPT_GPTFLG2_CF3 (0x08) +#define MCF_GPT_GPTFLG2_TOF (0x80) + +/* Bit definitions and macros for MCF_GPT_GPTC */ +#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPACTL */ +#define MCF_GPT_GPTPACTL_PAI (0x01) +#define MCF_GPT_GPTPACTL_PAOVI (0x02) +#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF_GPT_GPTPACTL_PEDGE (0x10) +#define MCF_GPT_GPTPACTL_PAMOD (0x20) +#define MCF_GPT_GPTPACTL_PAE (0x40) +#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) +#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) +#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) + +/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ +#define MCF_GPT_GPTPAFLG_PAIF (0x01) +#define MCF_GPT_GPTPAFLG_PAOVF (0x02) + +/* Bit definitions and macros for MCF_GPT_GPTPACNT */ +#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTPORT */ +#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_GPT_GPTDDR */ +#define MCF_GPT_GPTDDR_DDRT0 (0x01) +#define MCF_GPT_GPTDDR_DDRT1 (0x02) +#define MCF_GPT_GPTDDR_DDRT2 (0x04) +#define MCF_GPT_GPTDDR_DDRT3 (0x08) + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) +#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) +#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x01) +#define MCF_PWM_PWME_PWME1 (0x02) +#define MCF_PWM_PWME_PWME2 (0x04) +#define MCF_PWM_PWME_PWME3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x01) +#define MCF_PWM_PWMPOL_PPOL1 (0x02) +#define MCF_PWM_PWMPOL_PPOL2 (0x04) +#define MCF_PWM_PWMPOL_PPOL3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x01) +#define MCF_PWM_PWMCLK_PCLK1 (0x02) +#define MCF_PWM_PWMCLK_PCLK2 (0x04) +#define MCF_PWM_PWMCLK_PCLK3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x01) +#define MCF_PWM_PWMCAE_CAE1 (0x02) +#define MCF_PWM_PWMCAE_CAE2 (0x04) +#define MCF_PWM_PWMCAE_CAE3 (0x08) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x04) +#define MCF_PWM_PWMCTL_PSWAI (0x08) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x01) +#define MCF_PWM_PWMSDN_PWM7IL (0x02) +#define MCF_PWM_PWMSDN_PWM7IN (0x04) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) +#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) +#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) +#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) +#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) +#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) +#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) +#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) +#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) +#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF(x) (1<<x) + +/* Bit definitions and macros for MCF_CAN_IFLAG */ +#define MCF_CAN_IFLAG_BUF(x) (1<<x) + +/********************************************************************* +* +* ColdFire Flash Module (CFM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000])) +#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) +#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008])) +#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010])) +#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014])) +#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018])) +#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) +#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) + +/* Bit definitions and macros for MCF_CFM_CFMMCR */ +#define MCF_CFM_CFMMCR_KEYACC (0x0020) +#define MCF_CFM_CFMMCR_CCIE (0x0040) +#define MCF_CFM_CFMMCR_CBEIE (0x0080) +#define MCF_CFM_CFMMCR_AEIE (0x0100) +#define MCF_CFM_CFMMCR_PVIE (0x0200) +#define MCF_CFM_CFMMCR_LOCK (0x0400) + +/* Bit definitions and macros for MCF_CFM_CFMCLKD */ +#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) +#define MCF_CFM_CFMCLKD_PRDIV8 (0x40) +#define MCF_CFM_CFMCLKD_DIVLD (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMSEC */ +#define MCF_CFM_CFMSEC_SEC(x) (((x)&0x0000FFFF)<<0) +#define MCF_CFM_CFMSEC_SECSTAT (0x40000000) +#define MCF_CFM_CFMSEC_KEYEN (0x80000000) + +/* Bit definitions and macros for MCF_CFM_CFMUSTAT */ +#define MCF_CFM_CFMUSTAT_BLANK (0x04) +#define MCF_CFM_CFMUSTAT_ACCERR (0x10) +#define MCF_CFM_CFMUSTAT_PVIOL (0x20) +#define MCF_CFM_CFMUSTAT_CCIF (0x40) +#define MCF_CFM_CFMUSTAT_CBEIF (0x80) + +/* Bit definitions and macros for MCF_CFM_CFMCMD */ +#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) +#define MCF_CFM_CFMCMD_RDARY1 (0x05) +#define MCF_CFM_CFMCMD_PGM (0x20) +#define MCF_CFM_CFMCMD_PGERS (0x40) +#define MCF_CFM_CFMCMD_MASERS (0x41) +#define MCF_CFM_CFMCMD_PGERSVER (0x06) + +/********************************************************************* +* +* Interrupt Controller (INTC_IACK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(&__IPSBAR[0x000FE0])) +#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(&__IPSBAR[0x000FE4])) +#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(&__IPSBAR[0x000FE8])) +#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(&__IPSBAR[0x000FEC])) +#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(&__IPSBAR[0x000FF0])) +#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(&__IPSBAR[0x000FF4])) +#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(&__IPSBAR[0x000FF8])) +#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(&__IPSBAR[0x000FFC])) +#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)])) + +/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ +#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ +#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x001004])) +#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x001008])) +#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x001010])) +#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x001014])) +#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x001024])) +#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x001040])) +#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x001044])) +#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x001064])) +#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x001084])) +#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x0010C4])) +#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x0010E4])) +#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x0010E8])) +#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x0010EC])) +#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x001118])) +#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x00111C])) +#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x001120])) +#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x001124])) +#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x001144])) +#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x00114C])) +#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x001150])) +#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x001180])) +#define MCF_FEC_ETDSR (*(vuint32*)(&__IPSBAR[0x001184])) +#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x001188])) +#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x001200])) +#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x001204])) +#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x001208])) +#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x00120C])) +#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001210])) +#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001214])) +#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001218])) +#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x00121C])) +#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x001220])) +#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x001224])) +#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x001228])) +#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x00122C])) +#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x001230])) +#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x001234])) +#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x001238])) +#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x00123C])) +#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x001240])) +#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x001244])) +#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x001248])) +#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x00124C])) +#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x001250])) +#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x001254])) +#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x001258])) +#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x00125C])) +#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x001260])) +#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x001264])) +#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x001268])) +#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x00126C])) +#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x001270])) +#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x001274])) +#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x001284])) +#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x001288])) +#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x00128C])) +#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001290])) +#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001294])) +#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001298])) +#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x00129C])) +#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x0012A0])) +#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x0012A4])) +#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x0012A8])) +#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x0012AC])) +#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x0012B0])) +#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x0012B4])) +#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(&__IPSBAR[0x0012B8])) +#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x0012C0])) +#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(&__IPSBAR[0x0012BC])) +#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x0012C4])) +#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x0012C8])) +#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x0012CC])) +#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x0012D0])) +#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x0012D4])) +#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x0012D8])) +#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x0012DC])) +#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x0012E0])) + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_UN (0x00080000) +#define MCF_FEC_EIR_RL (0x00100000) +#define MCF_FEC_EIR_LC (0x00200000) +#define MCF_FEC_EIR_EBERR (0x00400000) +#define MCF_FEC_EIR_MII (0x00800000) +#define MCF_FEC_EIR_RXB (0x01000000) +#define MCF_FEC_EIR_RXF (0x02000000) +#define MCF_FEC_EIR_TXB (0x04000000) +#define MCF_FEC_EIR_TXF (0x08000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_UN (0x00080000) +#define MCF_FEC_EIMR_RL (0x00100000) +#define MCF_FEC_EIMR_LC (0x00200000) +#define MCF_FEC_EIMR_EBERR (0x00400000) +#define MCF_FEC_EIMR_MII (0x00800000) +#define MCF_FEC_EIMR_RXB (0x01000000) +#define MCF_FEC_EIMR_RXF (0x02000000) +#define MCF_FEC_EIMR_TXB (0x04000000) +#define MCF_FEC_EIMR_TXF (0x08000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0x00000000) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_RDAR */ +#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_TDAR */ +#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF_FEC_MMFR_ST_01 (0x40000000) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x00000001) +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_MII_MODE (0x00000004) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_BC_REJ (0x00000010) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x00000001) +#define MCF_FEC_TCR_HBC (0x00000002) +#define MCF_FEC_TCR_FDEN (0x00000004) +#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAUR */ +#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_TFWR */ +#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) + +/* Bit definitions and macros for MCF_FEC_FRBR */ +#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_FRSR */ +#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_ERDSR */ +#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_ETDSR */ +#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_EMRBR */ +#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) + +/* buffer descriptor fields */ +/* Tx BD fields */ +#define MCF_FEC_TXBD_R (1 << 15) +#define MCF_FEC_TXBD_W (1 << 13) +#define MCF_FEC_TXBD_L (1 << 11) +#define MCF_FEC_TXBD_TC (1 << 10) + +/* Rx BD fields */ +#define MCF_FEC_RXBD_E (1 << 15) +#define MCF_FEC_RXBD_RO1 (1 << 14) +#define MCF_FEC_RXBD_W (1 << 13) +#define MCF_FEC_RXBD_L (1 << 11) +#define MCF_FEC_RXBD_LG (1 << 5) +#define MCF_FEC_RXBD_NO (1 << 4) +#define MCF_FEC_RXBD_CR (1 << 2) +#define MCF_FEC_RXBD_OV (1 << 1) +#define MCF_FEC_RXBD_TR (1 << 0) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RNG_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000])) +#define MCF_RNG_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004])) +#define MCF_RNG_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008])) +#define MCF_RNG_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C])) + +/* Bit definitions and macros for MCF_RNG_RNGCR */ +#define MCF_RNG_RNGCR_GO (0x00000001) +#define MCF_RNG_RNGCR_HA (0x00000002) +#define MCF_RNG_RNGCR_IM (0x00000004) +#define MCF_RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for MCF_RNG_RNGSR */ +#define MCF_RNG_RNGSR_SV (0x00000001) +#define MCF_RNG_RNGSR_LRS (0x00000002) +#define MCF_RNG_RNGSR_FUF (0x00000004) +#define MCF_RNG_RNGSR_EI (0x00000008) +#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_RNG_RNGER */ +#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_RNG_RNGOUT */ +#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Real-time Clock (RTC) +* +*********************************************************************/ +/* Register read/write macros */ +#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x180000])) +#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x180004])) +#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x180008])) +#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x18000C])) +#define MCF_RTC_CR (*(vuint32*)(&__IPSBAR[0x180010])) +#define MCF_RTC_ISR (*(vuint32*)(&__IPSBAR[0x180014])) +#define MCF_RTC_IER (*(vuint32*)(&__IPSBAR[0x180018])) +#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x18001C])) +#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x180020])) +#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x180024])) +#define MCF_RTC_OSC_CNT_U (*(vuint32*)(&__IPSBAR[0x180034])) +#define MCF_RTC_OSC_CNT_L (*(vuint32*)(&__IPSBAR[0x180038])) + +/* Bit definitions and macros for MCF_RTC_HOURMIN */ +#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_SECONDS */ +#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_HM */ +#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ +#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_CR */ +#define MCF_RTC_CR_SWR (0x00000001) +#define MCF_RTC_CR_EN (0x00000080) + +/* Bit definitions and macros for MCF_RTC_ISR */ +#define MCF_RTC_ISR_SW (0x00000001) +#define MCF_RTC_ISR_MIN (0x00000002) +#define MCF_RTC_ISR_ALM (0x00000004) +#define MCF_RTC_ISR_DAY (0x00000008) +#define MCF_RTC_ISR_1HZ (0x00000010) +#define MCF_RTC_ISR_HR (0x00000020) + +/* Bit definitions and macros for MCF_RTC_IER */ +#define MCF_RTC_IER_SW (0x00000001) +#define MCF_RTC_IER_MIN (0x00000002) +#define MCF_RTC_IER_ALM (0x00000004) +#define MCF_RTC_IER_DAY (0x00000008) +#define MCF_RTC_IER_1HZ (0x00000010) +#define MCF_RTC_IER_HR (0x00000020) + +/* Bit definitions and macros for MCF_RTC_STPWCH */ +#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_DAYS */ +#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ +#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) + +#define MCF_RTC_RTCGOCNT(x) (((x)&0x0000FFFF)<<0) +/********************************************************************/ + +#endif /* __MCF5225x_H__ */ diff --git a/bsps/m68k/include/mcf5235/mcf5235.h b/bsps/m68k/include/mcf5235/mcf5235.h new file mode 100644 index 0000000000..87e0d91541 --- /dev/null +++ b/bsps/m68k/include/mcf5235/mcf5235.h @@ -0,0 +1,2998 @@ +/* + ******************************************* + * Definitions from Motorola/FreeScale * + ******************************************* + */ + +/* + * File: mcf5235.h + * Purpose: MCF5235 definitions + * + * Notes: + */ + +#ifndef _CPU_MCF5235_H +#define _CPU_MCF5235_H + +#include <stdint.h> + +/********************************************************************/ + +/* + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + * + ***********************************************************************/ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + + +/********************************************************************/ +/* + * Memory map definitions from linker command files + */ +extern char __IPSBAR[]; + +/********************************************************************* +* +* Watchdog Timer Modules (WTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_WCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140000))) +#define MCF5235_WMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140002))) +#define MCF5235_WCNTR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140004))) +#define MCF5235_WSR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140006))) + +/* Bit definitions and macros for MCF5235_WTM_WCR */ +#define MCF5235_WCR_EN (0x0001) +#define MCF5235_WCR_HALTED (0x0002) +#define MCF5235_WCR_DOZE (0x0004) +#define MCF5235_WCR_WAIT (0x0008) + +/* Bit definitions and macros for MCF5235_WTM_WMR */ +#define MCF5235_WMR_WM0 (0x0001) +#define MCF5235_WMR_WM1 (0x0002) +#define MCF5235_WMR_WM2 (0x0004) +#define MCF5235_WMR_WM3 (0x0008) +#define MCF5235_WMR_WM4 (0x0010) +#define MCF5235_WMR_WM5 (0x0020) +#define MCF5235_WMR_WM6 (0x0040) +#define MCF5235_WMR_WM7 (0x0080) +#define MCF5235_WMR_WM8 (0x0100) +#define MCF5235_WMR_WM9 (0x0200) +#define MCF5235_WMR_WM10 (0x0400) +#define MCF5235_WMR_WM11 (0x0800) +#define MCF5235_WMR_WM12 (0x1000) +#define MCF5235_WMR_WM13 (0x2000) +#define MCF5235_WMR_WM14 (0x4000) +#define MCF5235_WMR_WM15 (0x8000) + +/* Bit definitions and macros for MCF5235_WTM_WCNTR */ +#define MCF5235_WCNTR_WC0 (0x0001) +#define MCF5235_WCNTR_WC1 (0x0002) +#define MCF5235_WCNTR_WC2 (0x0004) +#define MCF5235_WCNTR_WC3 (0x0008) +#define MCF5235_WCNTR_WC4 (0x0010) +#define MCF5235_WCNTR_WC5 (0x0020) +#define MCF5235_WCNTR_WC6 (0x0040) +#define MCF5235_WCNTR_WC7 (0x0080) +#define MCF5235_WCNTR_WC8 (0x0100) +#define MCF5235_WCNTR_WC9 (0x0200) +#define MCF5235_WCNTR_WC10 (0x0400) +#define MCF5235_WCNTR_WC11 (0x0800) +#define MCF5235_WCNTR_WC12 (0x1000) +#define MCF5235_WCNTR_WC13 (0x2000) +#define MCF5235_WCNTR_WC14 (0x4000) +#define MCF5235_WCNTR_WC15 (0x8000) +#define MCF5235_WSR_WS0 (0x0001) +#define MCF5235_WSR_WS1 (0x0002) +#define MCF5235_WSR_WS2 (0x0004) +#define MCF5235_WSR_WS3 (0x0008) +#define MCF5235_WSR_WS4 (0x0010) +#define MCF5235_WSR_WS5 (0x0020) +#define MCF5235_WSR_WS6 (0x0040) +#define MCF5235_WSR_WS7 (0x0080) +#define MCF5235_WSR_WS8 (0x0100) +#define MCF5235_WSR_WS9 (0x0200) +#define MCF5235_WSR_WS10 (0x0400) +#define MCF5235_WSR_WS11 (0x0800) +#define MCF5235_WSR_WS12 (0x1000) +#define MCF5235_WSR_WS13 (0x2000) +#define MCF5235_WSR_WS14 (0x4000) +#define MCF5235_WSR_WS15 (0x8000) + +/********************************************************************/ + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_UART_UMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200))) +#define MCF5235_UART_USR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) +#define MCF5235_UART_UCSR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) +#define MCF5235_UART_UCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208))) +#define MCF5235_UART_URB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) +#define MCF5235_UART_UTB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) +#define MCF5235_UART_UIPCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) +#define MCF5235_UART_UACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) +#define MCF5235_UART_UISR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) +#define MCF5235_UART_UIMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) +#define MCF5235_UART_UBG10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218))) +#define MCF5235_UART_UBG20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C))) +#define MCF5235_UART_UIP0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234))) +#define MCF5235_UART_UOP10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238))) +#define MCF5235_UART_UOP00 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C))) +#define MCF5235_UART_UMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000240))) +#define MCF5235_UART_USR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) +#define MCF5235_UART_UCSR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) +#define MCF5235_UART_UCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000248))) +#define MCF5235_UART_URB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) +#define MCF5235_UART_UTB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) +#define MCF5235_UART_UIPCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) +#define MCF5235_UART_UACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) +#define MCF5235_UART_UISR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) +#define MCF5235_UART_UIMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) +#define MCF5235_UART_UBG11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000258))) +#define MCF5235_UART_UBG21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00025C))) +#define MCF5235_UART_UIP1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000274))) +#define MCF5235_UART_UOP11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000278))) +#define MCF5235_UART_UOP01 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00027C))) +#define MCF5235_UART_UMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000280))) +#define MCF5235_UART_USR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) +#define MCF5235_UART_UCSR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) +#define MCF5235_UART_UCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000288))) +#define MCF5235_UART_URB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) +#define MCF5235_UART_UTB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) +#define MCF5235_UART_UIPCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) +#define MCF5235_UART_UACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) +#define MCF5235_UART_UISR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) +#define MCF5235_UART_UIMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) +#define MCF5235_UART_UBG12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000298))) +#define MCF5235_UART_UBG22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00029C))) +#define MCF5235_UART_UIP2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B4))) +#define MCF5235_UART_UOP12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B8))) +#define MCF5235_UART_UOP02 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002BC))) +#define MCF5235_UART_UMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200+((x)*0x040)))) +#define MCF5235_UART_USR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) +#define MCF5235_UART_UCSR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) +#define MCF5235_UART_UCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208+((x)*0x040)))) +#define MCF5235_UART_URB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) +#define MCF5235_UART_UTB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) +#define MCF5235_UART_UIPCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) +#define MCF5235_UART_UACR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) +#define MCF5235_UART_UISR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) +#define MCF5235_UART_UIMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) +#define MCF5235_UART_UBG1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218+((x)*0x040)))) +#define MCF5235_UART_UBG2(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C+((x)*0x040)))) +#define MCF5235_UART_UIP(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234+((x)*0x040)))) +#define MCF5235_UART_UOP1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238+((x)*0x040)))) +#define MCF5235_UART_UOP0(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C+((x)*0x040)))) + +/* Bit definitions and macros for MCF5235_UART_UMR */ +#define MCF5235_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF5235_UART_UMR_PT (0x04) +#define MCF5235_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF5235_UART_UMR_ERR (0x20) +#define MCF5235_UART_UMR_RXIRQ (0x40) +#define MCF5235_UART_UMR_RXRTS (0x80) +#define MCF5235_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF5235_UART_UMR_TXCTS (0x10) +#define MCF5235_UART_UMR_TXRTS (0x20) +#define MCF5235_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF5235_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF5235_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF5235_UART_UMR_PM_NONE (0x10) +#define MCF5235_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF5235_UART_UMR_PM_FORCE_LO (0x08) +#define MCF5235_UART_UMR_PM_ODD (0x04) +#define MCF5235_UART_UMR_PM_EVEN (0x00) +#define MCF5235_UART_UMR_BC_5 (0x00) +#define MCF5235_UART_UMR_BC_6 (0x01) +#define MCF5235_UART_UMR_BC_7 (0x02) +#define MCF5235_UART_UMR_BC_8 (0x03) +#define MCF5235_UART_UMR_CM_NORMAL (0x00) +#define MCF5235_UART_UMR_CM_ECHO (0x40) +#define MCF5235_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF5235_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF5235_UART_UMR_STOP_BITS_1 (0x07) +#define MCF5235_UART_UMR_STOP_BITS_15 (0x08) +#define MCF5235_UART_UMR_STOP_BITS_2 (0x0F) +#define MCF5235_UART_USR_RXRDY (0x01) +#define MCF5235_UART_USR_FFULL (0x02) +#define MCF5235_UART_USR_TXRDY (0x04) +#define MCF5235_UART_USR_TXEMP (0x08) +#define MCF5235_UART_USR_OE (0x10) +#define MCF5235_UART_USR_PE (0x20) +#define MCF5235_UART_USR_FE (0x40) +#define MCF5235_UART_USR_RB (0x80) +#define MCF5235_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF5235_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF5235_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF5235_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF5235_UART_UCSR_RCS_CTM (0xF0) +#define MCF5235_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF5235_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF5235_UART_UCSR_TCS_CTM (0x0F) +#define MCF5235_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF5235_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF5235_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF5235_UART_UCR_NONE (0x00) +#define MCF5235_UART_UCR_STOP_BREAK (0x70) +#define MCF5235_UART_UCR_START_BREAK (0x60) +#define MCF5235_UART_UCR_BKCHGINT (0x50) +#define MCF5235_UART_UCR_RESET_ERROR (0x40) +#define MCF5235_UART_UCR_RESET_TX (0x30) +#define MCF5235_UART_UCR_RESET_RX (0x20) +#define MCF5235_UART_UCR_RESET_MR (0x10) +#define MCF5235_UART_UCR_TX_DISABLED (0x08) +#define MCF5235_UART_UCR_TX_ENABLED (0x04) +#define MCF5235_UART_UCR_RX_DISABLED (0x02) +#define MCF5235_UART_UCR_RX_ENABLED (0x01) +#define MCF5235_UART_UIPCR_CTS (0x01) +#define MCF5235_UART_UIPCR_COS (0x10) +#define MCF5235_UART_UACR_IEC (0x01) +#define MCF5235_UART_UISR_TXRDY (0x01) +#define MCF5235_UART_UISR_RXRDY (0x02) +#define MCF5235_UART_UISR_DB (0x04) +#define MCF5235_UART_UISR_RXFTO (0x08) +#define MCF5235_UART_UISR_TXFIFO (0x10) +#define MCF5235_UART_UISR_RXFIFO (0x20) +#define MCF5235_UART_UISR_COS (0x80) +#define MCF5235_UART_UIMR_TXRDY (0x01) +#define MCF5235_UART_UIMR_FFULL (0x02) +#define MCF5235_UART_UIMR_DB (0x04) +#define MCF5235_UART_UIMR_COS (0x80) +#define MCF5235_UART_UIP_CTS (0x01) +#define MCF5235_UART_UOP1_RTS (0x01) +#define MCF5235_UART_UOP0_RTS (0x01) + + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SDRAMC_DCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000040))) +#define MCF5235_SDRAMC_DACR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000048))) +#define MCF5235_SDRAMC_DMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00004C))) +#define MCF5235_SDRAMC_DACR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000050))) +#define MCF5235_SDRAMC_DMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000054))) + +/* Bit definitions and macros for MCF5235_SDRAMC_DCR */ +#define MCF5235_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) +#define MCF5235_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) +#define MCF5235_SDRAMC_DCR_IS (0x0800) +#define MCF5235_SDRAMC_DCR_COC (0x1000) +#define MCF5235_SDRAMC_DCR_NAM (0x2000) +#define MCF5235_SDRAMC_DACR0_IP (0x00000008) +#define MCF5235_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) +#define MCF5235_SDRAMC_DACR0_MRS (0x00000040) +#define MCF5235_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) +#define MCF5235_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) +#define MCF5235_SDRAMC_DACR0_RE (0x00008000) +#define MCF5235_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR0_V (0x00000001) +#define MCF5235_SDRAMC_DMR0_WP (0x00000100) +#define MCF5235_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DACR1_IP (0x00000008) +#define MCF5235_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) +#define MCF5235_SDRAMC_DACR1_MRS (0x00000040) +#define MCF5235_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) +#define MCF5235_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) +#define MCF5235_SDRAMC_DACR1_RE (0x00008000) +#define MCF5235_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR1_V (0x00000001) +#define MCF5235_SDRAMC_DMR1_WP (0x00000100) +#define MCF5235_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) +#define MCF5235_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF5235_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF5235_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF5235_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF5235_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF5235_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF5235_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF5235_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF5235_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF5235_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF5235_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF5235_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF5235_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF5235_SDRAMC_DMR_WP (0x00000100) +#define MCF5235_SDRAMC_DMR_CI (0x00000040) +#define MCF5235_SDRAMC_DMR_AM (0x00000020) +#define MCF5235_SDRAMC_DMR_SC (0x00000010) +#define MCF5235_SDRAMC_DMR_SD (0x00000008) +#define MCF5235_SDRAMC_DMR_UC (0x00000004) +#define MCF5235_SDRAMC_DMR_UD (0x00000002) +#define MCF5235_SDRAMC_DMR_V (0x00000001) + +/********************************************************************* +* +* DMA Timers (TIMER) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_TIMER_DTMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400))) +#define MCF5235_TIMER_DTXMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402))) +#define MCF5235_TIMER_DTER0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403))) +#define MCF5235_TIMER_DTRR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404))) +#define MCF5235_TIMER_DTCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408))) +#define MCF5235_TIMER_DTCN0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C))) +#define MCF5235_TIMER_DTMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000440))) +#define MCF5235_TIMER_DTXMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000442))) +#define MCF5235_TIMER_DTER1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000443))) +#define MCF5235_TIMER_DTRR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000444))) +#define MCF5235_TIMER_DTCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000448))) +#define MCF5235_TIMER_DTCN1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00044C))) +#define MCF5235_TIMER_DTMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000480))) +#define MCF5235_TIMER_DTXMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000482))) +#define MCF5235_TIMER_DTER2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000483))) +#define MCF5235_TIMER_DTRR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000484))) +#define MCF5235_TIMER_DTCR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000488))) +#define MCF5235_TIMER_DTCN2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00048C))) +#define MCF5235_TIMER3_DTMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x0004C0))) +#define MCF5235_TIMER_DTXMR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C2))) +#define MCF5235_TIMER_DTER3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C3))) +#define MCF5235_TIMER_DTRR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C4))) +#define MCF5235_TIMER_DTCR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C8))) +#define MCF5235_TIMER3_DTCN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004CC))) +#define MCF5235_TIMER_DTMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400+((x)*0x040)))) +#define MCF5235_TIMER_DTXMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402+((x)*0x040)))) +#define MCF5235_TIMER_DTER(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403+((x)*0x040)))) +#define MCF5235_TIMER_DTRR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404+((x)*0x040)))) +#define MCF5235_TIMER_DTCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408+((x)*0x040)))) +#define MCF5235_TIMER_DTCN(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C+((x)*0x040)))) + +/* Bit definitions and macros for MCF5235_TIMER_DTMR */ +#define MCF5235_TIMER_DTMR_RST (0x0001) +#define MCF5235_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF5235_TIMER_DTMR_FRR (0x0008) +#define MCF5235_TIMER_DTMR_ORRI (0x0010) +#define MCF5235_TIMER_DTMR_OM (0x0020) +#define MCF5235_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF5235_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF5235_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF5235_TIMER_DTMR_CE_FALL (0x0080) +#define MCF5235_TIMER_DTMR_CE_RISE (0x0040) +#define MCF5235_TIMER_DTMR_CE_NONE (0x0000) +#define MCF5235_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF5235_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF5235_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF5235_TIMER_DTMR_CLK_STOP (0x0000) +#define MCF5235_TIMER_DTXMR_MODE16 (0x01) +#define MCF5235_TIMER_DTXMR_DMAEN (0x80) +#define MCF5235_TIMER_DTER_CAP (0x01) +#define MCF5235_TIMER_DTER_REF (0x02) + +/********************************************************************* +* +* System SRAM (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SRAM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x20000000))) + +/* Bit definitions and macros for MCF5235_SRAM_RAMBAR */ +#define MCF5235_SRAM_RAMBAR_V (0x00000001) +#define MCF5235_SRAM_RAMBAR_UD (0x00000002) +#define MCF5235_SRAM_RAMBAR_UC (0x00000004) +#define MCF5235_SRAM_RAMBAR_SD (0x00000008) +#define MCF5235_SRAM_RAMBAR_SC (0x00000010) +#define MCF5235_SRAM_RAMBAR_CI (0x00000020) +#define MCF5235_SRAM_RAMBAR_WP (0x00000100) +#define MCF5235_SRAM_RAMBAR_SPV (0x00000200) +#define MCF5235_SRAM_RAMBAR_PRI2 (0x00000400) +#define MCF5235_SRAM_RAMBAR_PRI1 (0x00000800) +#define MCF5235_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_SCM_IPSBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000000))) +#define MCF5235_SCM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000008))) +#define MCF5235_SCM_CRSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000010))) +#define MCF5235_SCM_CWCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000011))) +#define MCF5235_SCM_LPICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000012))) +#define MCF5235_SCM_CWSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000013))) +#define MCF5235_SCM_DMAREQC (*(vuint32*)((uintptr_t)__IPSBAR + (0x000014))) +#define MCF5235_SCM_MPARK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00001C))) +#define MCF5235_SCM_MPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000020))) +#define MCF5235_SCM_PACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000024))) +#define MCF5235_SCM_PACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000025))) +#define MCF5235_SCM_PACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000026))) +#define MCF5235_SCM_PACR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000027))) +#define MCF5235_SCM_PACR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000028))) +#define MCF5235_SCM_PACR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002A))) +#define MCF5235_SCM_PACR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002B))) +#define MCF5235_SCM_PACR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002C))) +#define MCF5235_SCM_PACR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002E))) +#define MCF5235_SCM_GPACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000030))) + +/* Bit definitions */ +#define MCF5235_SCM_IPSBAR_V (0x00000001) +#define MCF5235_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) +#define MCF5235_SCM_RAMBAR_BDE (0x00000200) +#define MCF5235_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_SCM_CRSR_CWDR (0x20) +#define MCF5235_SCM_CRSR_EXT (0x80) +#define MCF5235_SCM_CWCR_CWTIC (0x01) +#define MCF5235_SCM_CWCR_CWTAVAL (0x02) +#define MCF5235_SCM_CWCR_CWTA (0x04) +#define MCF5235_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF5235_SCM_CWCR_CWRI (0x40) +#define MCF5235_SCM_CWCR_CWE (0x80) +#define MCF5235_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define MCF5235_SCM_LPICR_ENBSTOP (0x80) +#define MCF5235_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF5235_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF5235_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF5235_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) +#define MCF5235_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF5235_SCM_MPARK_PRKLAST (0x00001000) +#define MCF5235_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF5235_SCM_MPARK_FIXED (0x00004000) +#define MCF5235_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) +#define MCF5235_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) +#define MCF5235_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) +#define MCF5235_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) +#define MCF5235_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF5235_SCM_MPARK_M2_P_EN (0x02000000) +#define MCF5235_SCM_MPR_MPR(x) (((x)&0x0F)<<0) +#define MCF5235_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR0_LOCK0 (0x08) +#define MCF5235_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR0_LOCK1 (0x80) +#define MCF5235_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR1_LOCK0 (0x08) +#define MCF5235_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR1_LOCK1 (0x80) +#define MCF5235_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR2_LOCK0 (0x08) +#define MCF5235_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR2_LOCK1 (0x80) +#define MCF5235_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR3_LOCK0 (0x08) +#define MCF5235_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR3_LOCK1 (0x80) +#define MCF5235_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR4_LOCK0 (0x08) +#define MCF5235_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR4_LOCK1 (0x80) +#define MCF5235_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR5_LOCK0 (0x08) +#define MCF5235_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR5_LOCK1 (0x80) +#define MCF5235_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR6_LOCK0 (0x08) +#define MCF5235_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR6_LOCK1 (0x80) +#define MCF5235_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR7_LOCK0 (0x08) +#define MCF5235_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR7_LOCK1 (0x80) +#define MCF5235_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF5235_SCM_PACR8_LOCK0 (0x08) +#define MCF5235_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF5235_SCM_PACR8_LOCK1 (0x80) +#define MCF5235_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) +#define MCF5235_SCM_GPACR0_LOCK (0x80) + + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CAN_CANMCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000))) +#define MCF5235_CAN_CANCTRL0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004))) +#define MCF5235_CAN_TIMER0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008))) +#define MCF5235_CAN_RXGMASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010))) +#define MCF5235_CAN_RX14MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014))) +#define MCF5235_CAN_RX15MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018))) +#define MCF5235_CAN_ERRCNT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C))) +#define MCF5235_CAN_ERRSTAT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020))) +#define MCF5235_CAN_IMASK0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A))) +#define MCF5235_CAN_IFLAG0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032))) +#define MCF5235_CAN_CANMCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0000))) +#define MCF5235_CAN_CANCTRL1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0004))) +#define MCF5235_CAN_TIMER1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0008))) +#define MCF5235_CAN_RXGMASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0010))) +#define MCF5235_CAN_RX14MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0014))) +#define MCF5235_CAN_RX15MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0018))) +#define MCF5235_CAN_ERRCNT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F001C))) +#define MCF5235_CAN_ERRSTAT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0020))) +#define MCF5235_CAN_IMASK1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F002A))) +#define MCF5235_CAN_IFLAG1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F0032))) +#define MCF5235_CAN_CANMCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000+((x)*0x30000)))) +#define MCF5235_CAN_CANCTRL(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004+((x)*0x30000)))) +#define MCF5235_CAN_TIMER(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008+((x)*0x30000)))) +#define MCF5235_CAN_RXGMASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010+((x)*0x30000)))) +#define MCF5235_CAN_RX14MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014+((x)*0x30000)))) +#define MCF5235_CAN_RX15MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018+((x)*0x30000)))) +#define MCF5235_CAN_ERRCNT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C+((x)*0x30000)))) +#define MCF5235_CAN_ERRSTAT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020+((x)*0x30000)))) +#define MCF5235_CAN_IMASK(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A+((x)*0x30000)))) +#define MCF5235_CAN_IFLAG(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032+((x)*0x30000)))) + +#define MCF5235_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0080+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0082+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0084+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0089+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0090+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0092+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0094+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0099+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00ED+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F0+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F4+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F9+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FA+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FB+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FC+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FD+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FE+((x)*0x30000)))) +#define MCF5235_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FF+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0104+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0108+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0109+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0114+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0118+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0119+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0120+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0124+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0128+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0129+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0130+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0134+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0138+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0139+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0140+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0144+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0148+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0149+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0150+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0154+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0158+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0159+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0160+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0164+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0168+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0169+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0170+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0174+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0178+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0179+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017A+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017B+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017D+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017E+((x)*0x30000)))) +#define MCF5235_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017F+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) +#define MCF5235_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) +#define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) +#define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) + + +/* Bit definitions and macros for MCF5235_CAN_CANMCR */ +#define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF5235_CAN_CANMCR_SUPV (0x00800000) +#define MCF5235_CAN_CANMCR_FRZACK (0x01000000) +#define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF5235_CAN_CANMCR_HALT (0x10000000) +#define MCF5235_CAN_CANMCR_FRZ (0x40000000) +#define MCF5235_CAN_CANMCR_MDIS (0x80000000) +#define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF5235_CAN_CANCTRL_LOM (0x00000008) +#define MCF5235_CAN_CANCTRL_LBUF (0x00000010) +#define MCF5235_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF5235_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF5235_CAN_CANCTRL_SAMP (0x00000080) +#define MCF5235_CAN_CANCTRL_LPB (0x00001000) +#define MCF5235_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF5235_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF5235_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF5235_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF5235_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF5235_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF5235_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) +#define MCF5235_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +#define MCF5235_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF5235_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) +#define MCF5235_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF5235_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF5235_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF5235_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF5235_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF5235_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF5235_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF5235_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF5235_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF5235_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF5235_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF5235_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF5235_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF5235_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF5235_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF5235_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) +#define MCF5235_CAN_IMASK_BUF0M (0x0001) +#define MCF5235_CAN_IMASK_BUF1M (0x0002) +#define MCF5235_CAN_IMASK_BUF2M (0x0004) +#define MCF5235_CAN_IMASK_BUF3M (0x0008) +#define MCF5235_CAN_IMASK_BUF4M (0x0010) +#define MCF5235_CAN_IMASK_BUF5M (0x0020) +#define MCF5235_CAN_IMASK_BUF6M (0x0040) +#define MCF5235_CAN_IMASK_BUF7M (0x0080) +#define MCF5235_CAN_IMASK_BUF8M (0x0100) +#define MCF5235_CAN_IMASK_BUF9M (0x0200) +#define MCF5235_CAN_IMASK_BUF10M (0x0400) +#define MCF5235_CAN_IMASK_BUF11M (0x0800) +#define MCF5235_CAN_IMASK_BUF12M (0x1000) +#define MCF5235_CAN_IMASK_BUF13M (0x2000) +#define MCF5235_CAN_IMASK_BUF14M (0x4000) +#define MCF5235_CAN_IMASK_BUF15M (0x8000) + +/* Bit definitions and macros for MCF5235_CAN_IFLAG */ +#define MCF5235_CAN_IFLAG_BUF0I (0x0001) +#define MCF5235_CAN_IFLAG_BUF1I (0x0002) +#define MCF5235_CAN_IFLAG_BUF2I (0x0004) +#define MCF5235_CAN_IFLAG_BUF3I (0x0008) +#define MCF5235_CAN_IFLAG_BUF4I (0x0010) +#define MCF5235_CAN_IFLAG_BUF5I (0x0020) +#define MCF5235_CAN_IFLAG_BUF6I (0x0040) +#define MCF5235_CAN_IFLAG_BUF7I (0x0080) +#define MCF5235_CAN_IFLAG_BUF8I (0x0100) +#define MCF5235_CAN_IFLAG_BUF9I (0x0200) +#define MCF5235_CAN_IFLAG_BUF10I (0x0400) +#define MCF5235_CAN_IFLAG_BUF11I (0x0800) +#define MCF5235_CAN_IFLAG_BUF12I (0x1000) +#define MCF5235_CAN_IFLAG_BUF13I (0x2000) +#define MCF5235_CAN_IFLAG_BUF14I (0x4000) +#define MCF5235_CAN_IFLAG_BUF15I (0x8000) + + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CCM_CCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x110004))) +#define MCF5235_CCM_LPCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x110007))) +#define MCF5235_CCM_CIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x11000A))) +#define MCF5235_CCM_RCON (*(vuint16*)((uintptr_t)__IPSBAR + (0x110008))) + +/* Bit definitions and macros for MCF5235_CCM_CCR */ +#define MCF5235_CCM_CCR_BMT(x) (((x)&0x0007)<<0) +#define MCF5235_CCM_CCR_BME (0x0008) +#define MCF5235_CCM_CCR_SZEN (0x0040) +#define MCF5235_CCM_CCR_MODE(x) (((x)&0x0007)<<8) +#define MCF5235_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF5235_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF5235_CCM_LPCR_LPMD_STOP (0xC0) +#define MCF5235_CCM_LPCR_LPMD_WAIT (0x80) +#define MCF5235_CCM_LPCR_LPMD_DOZE (0x40) +#define MCF5235_CCM_LPCR_LPMD_RUN (0x00) +#define MCF5235_CCM_CIR_PRN(x) (((x)&0x003F)<<0) +#define MCF5235_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define MCF5235_CCM_RCON_MODE (0x0001) +#define MCF5235_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define MCF5235_CCM_RCON_RLOAD (0x0020) +#define MCF5235_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) + +/********************************************************************* +* +* Chip Selects (CS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_CS_CSAR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080))) +#define MCF5235_CS_CSMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084))) +#define MCF5235_CS_CSCR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A))) +#define MCF5235_CS_CSAR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008C))) +#define MCF5235_CS_CSMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000090))) +#define MCF5235_CS_CSCR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000096))) +#define MCF5235_CS_CSAR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000098))) +#define MCF5235_CS_CSMR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00009C))) +#define MCF5235_CS_CSCR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A2))) +#define MCF5235_CS_CSAR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A4))) +#define MCF5235_CS_CSMR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000A8))) +#define MCF5235_CS_CSCR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000AE))) +#define MCF5235_CS_CSAR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000B0))) +#define MCF5235_CS_CSMR4 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000B4))) +#define MCF5235_CS_CSCR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BA))) +#define MCF5235_CS_CSAR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BC))) +#define MCF5235_CS_CSMR5 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000C0))) +#define MCF5235_CS_CSCR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C6))) +#define MCF5235_CS_CSAR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C8))) +#define MCF5235_CS_CSMR6 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000CC))) +#define MCF5235_CS_CSCR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D2))) +#define MCF5235_CS_CSAR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D4))) +#define MCF5235_CS_CSMR7 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000D8))) +#define MCF5235_CS_CSCR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000DE))) +#define MCF5235_CS_CSAR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080+((x)*0x00C)))) +#define MCF5235_CS_CSMR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084+((x)*0x00C)))) +#define MCF5235_CS_CSCR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A+((x)*0x00C)))) + +/* Bit definitions and macros for MCF5235_CS_CSAR */ +#define MCF5235_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) +#define MCF5235_CS_CSMR_V (0x00000001) +#define MCF5235_CS_CSMR_UD (0x00000002) +#define MCF5235_CS_CSMR_UC (0x00000004) +#define MCF5235_CS_CSMR_SD (0x00000008) +#define MCF5235_CS_CSMR_SC (0x00000010) +#define MCF5235_CS_CSMR_CI (0x00000020) +#define MCF5235_CS_CSMR_AM (0x00000040) +#define MCF5235_CS_CSMR_WP (0x00000100) +#define MCF5235_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF5235_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF5235_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF5235_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF5235_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF5235_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF5235_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF5235_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF5235_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF5235_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF5235_CS_CSMR_BAM_8M (0x007F0000) +#define MCF5235_CS_CSMR_BAM_4M (0x003F0000) +#define MCF5235_CS_CSMR_BAM_2M (0x001F0000) +#define MCF5235_CS_CSMR_BAM_1M (0x000F0000) +#define MCF5235_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF5235_CS_CSMR_BAM_512K (0x00070000) +#define MCF5235_CS_CSMR_BAM_256K (0x00030000) +#define MCF5235_CS_CSMR_BAM_128K (0x00010000) +#define MCF5235_CS_CSMR_BAM_64K (0x00000000) +#define MCF5235_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) +#define MCF5235_CS_CSCR_BSTW (0x0008) +#define MCF5235_CS_CSCR_BSTR (0x0010) +#define MCF5235_CS_CSCR_BEM (0x0020) +#define MCF5235_CS_CSCR_PS(x) (((x)&0x0003)<<6) +#define MCF5235_CS_CSCR_AA (0x0100) +#define MCF5235_CS_CSCR_IWS(x) (((x)&0x000F)<<10) +#define MCF5235_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) +#define MCF5235_CS_CSCR_PS_8 (0x0040) +#define MCF5235_CS_CSCR_PS_16 (0x0080) +#define MCF5235_CS_CSCR_PS_32 (0x0000) + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_EPORT_EPPAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x130000))) +#define MCF5235_EPORT_EPDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130002))) +#define MCF5235_EPORT_EPIER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130003))) +#define MCF5235_EPORT_EPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130004))) +#define MCF5235_EPORT_EPPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130005))) +#define MCF5235_EPORT_EPFR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130006))) + +/* Bit definitions and macros for MCF5235_EPORT_EPPAR */ +#define MCF5235_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF5235_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF5235_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF5235_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF5235_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF5235_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF5235_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF5235_EPORT_EPPAR_EPPAx_LEVEL (0) +#define MCF5235_EPORT_EPPAR_EPPAx_RISING (1) +#define MCF5235_EPORT_EPPAR_EPPAx_FALLING (2) +#define MCF5235_EPORT_EPPAR_EPPAx_BOTH (3) +#define MCF5235_EPORT_EPDDR_EPDD1 (0x02) +#define MCF5235_EPORT_EPDDR_EPDD2 (0x04) +#define MCF5235_EPORT_EPDDR_EPDD3 (0x08) +#define MCF5235_EPORT_EPDDR_EPDD4 (0x10) +#define MCF5235_EPORT_EPDDR_EPDD5 (0x20) +#define MCF5235_EPORT_EPDDR_EPDD6 (0x40) +#define MCF5235_EPORT_EPDDR_EPDD7 (0x80) +#define MCF5235_EPORT_EPIER_EPIE1 (0x02) +#define MCF5235_EPORT_EPIER_EPIE2 (0x04) +#define MCF5235_EPORT_EPIER_EPIE3 (0x08) +#define MCF5235_EPORT_EPIER_EPIE4 (0x10) +#define MCF5235_EPORT_EPIER_EPIE5 (0x20) +#define MCF5235_EPORT_EPIER_EPIE6 (0x40) +#define MCF5235_EPORT_EPIER_EPIE7 (0x80) +#define MCF5235_EPORT_EPDR_EPD1 (0x02) +#define MCF5235_EPORT_EPDR_EPD2 (0x04) +#define MCF5235_EPORT_EPDR_EPD3 (0x08) +#define MCF5235_EPORT_EPDR_EPD4 (0x10) +#define MCF5235_EPORT_EPDR_EPD5 (0x20) +#define MCF5235_EPORT_EPDR_EPD6 (0x40) +#define MCF5235_EPORT_EPDR_EPD7 (0x80) +#define MCF5235_EPORT_EPPDR_EPPD1 (0x02) +#define MCF5235_EPORT_EPPDR_EPPD2 (0x04) +#define MCF5235_EPORT_EPPDR_EPPD3 (0x08) +#define MCF5235_EPORT_EPPDR_EPPD4 (0x10) +#define MCF5235_EPORT_EPPDR_EPPD5 (0x20) +#define MCF5235_EPORT_EPPDR_EPPD6 (0x40) +#define MCF5235_EPORT_EPPDR_EPPD7 (0x80) +#define MCF5235_EPORT_EPFR_EPF1 (0x02) +#define MCF5235_EPORT_EPFR_EPF2 (0x04) +#define MCF5235_EPORT_EPFR_EPF3 (0x08) +#define MCF5235_EPORT_EPFR_EPF4 (0x10) +#define MCF5235_EPORT_EPFR_EPF5 (0x20) +#define MCF5235_EPORT_EPFR_EPF6 (0x40) +#define MCF5235_EPORT_EPFR_EPF7 (0x80) + + +/********************************************************************* +* +* enhanced Time Processor Unit (ETPU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_ETPU_EMCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0000))) +#define MCF5235_ETPU_ECDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0004))) +#define MCF5235_ETPU_EMISCCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D000C))) +#define MCF5235_ETPU_ESCMODR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0010))) +#define MCF5235_ETPU_EECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0014))) +#define MCF5235_ETPU_ETBCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0020))) +#define MCF5235_ETPU_ETB1R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0024))) +#define MCF5235_ETPU_ETB2R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0028))) +#define MCF5235_ETPU_EREDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D002C))) +#define MCF5235_ETPU_ECISR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0200))) +#define MCF5235_ETPU_ECDTRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0210))) +#define MCF5235_ETPU_ECIOSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0220))) +#define MCF5235_ETPU_ECDTROSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0230))) +#define MCF5235_ETPU_ECIER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0240))) +#define MCF5235_ETPU_ECDTRER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0250))) +#define MCF5235_ETPU_ECPSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0280))) +#define MCF5235_ETPU_ECSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0290))) +#define MCF5235_ETPU_EC0SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404))) +#define MCF5235_ETPU_EC1SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0414))) +#define MCF5235_ETPU_EC2SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0424))) +#define MCF5235_ETPU_EC3SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0434))) +#define MCF5235_ETPU_EC4SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0444))) +#define MCF5235_ETPU_EC5SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0454))) +#define MCF5235_ETPU_EC6SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0464))) +#define MCF5235_ETPU_EC7SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0474))) +#define MCF5235_ETPU_EC8SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0484))) +#define MCF5235_ETPU_EC9SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0494))) +#define MCF5235_ETPU_EC10SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A4))) +#define MCF5235_ETPU_EC11SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B4))) +#define MCF5235_ETPU_EC12SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C4))) +#define MCF5235_ETPU_EC13SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D4))) +#define MCF5235_ETPU_EC14SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E4))) +#define MCF5235_ETPU_EC15SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F4))) +#define MCF5235_ETPU_EC16SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0504))) +#define MCF5235_ETPU_EC17SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0514))) +#define MCF5235_ETPU_EC18SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0524))) +#define MCF5235_ETPU_EC19SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0534))) +#define MCF5235_ETPU_EC20SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0544))) +#define MCF5235_ETPU_EC21SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0554))) +#define MCF5235_ETPU_EC22SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0564))) +#define MCF5235_ETPU_EC23SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0574))) +#define MCF5235_ETPU_EC24SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0584))) +#define MCF5235_ETPU_EC25SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0594))) +#define MCF5235_ETPU_EC26SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A4))) +#define MCF5235_ETPU_EC27SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B4))) +#define MCF5235_ETPU_EC28SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C4))) +#define MCF5235_ETPU_EC29SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D4))) +#define MCF5235_ETPU_EC30SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E4))) +#define MCF5235_ETPU_EC31SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F4))) +#define MCF5235_ETPU_ECnSCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404+((x)*0x010)))) +#define MCF5235_ETPU_EC0CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400))) +#define MCF5235_ETPU_EC1CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0410))) +#define MCF5235_ETPU_EC2CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0420))) +#define MCF5235_ETPU_EC3CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0430))) +#define MCF5235_ETPU_EC4CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0440))) +#define MCF5235_ETPU_EC5CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0450))) +#define MCF5235_ETPU_EC6CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0460))) +#define MCF5235_ETPU_EC7CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0470))) +#define MCF5235_ETPU_EC8CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0480))) +#define MCF5235_ETPU_EC9CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0490))) +#define MCF5235_ETPU_EC10CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A0))) +#define MCF5235_ETPU_EC11CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B0))) +#define MCF5235_ETPU_EC12CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C0))) +#define MCF5235_ETPU_EC13CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D0))) +#define MCF5235_ETPU_EC14CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E0))) +#define MCF5235_ETPU_EC15CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F0))) +#define MCF5235_ETPU_EC16CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0500))) +#define MCF5235_ETPU_EC17CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0510))) +#define MCF5235_ETPU_EC18CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0520))) +#define MCF5235_ETPU_EC19CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0530))) +#define MCF5235_ETPU_EC20CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0540))) +#define MCF5235_ETPU_EC21CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0550))) +#define MCF5235_ETPU_EC22CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0560))) +#define MCF5235_ETPU_EC23CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0570))) +#define MCF5235_ETPU_EC24CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0580))) +#define MCF5235_ETPU_EC25CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0590))) +#define MCF5235_ETPU_EC26CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A0))) +#define MCF5235_ETPU_EC27CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B0))) +#define MCF5235_ETPU_EC28CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C0))) +#define MCF5235_ETPU_EC29CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D0))) +#define MCF5235_ETPU_EC30CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E0))) +#define MCF5235_ETPU_EC31CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F0))) +#define MCF5235_ETPU_ECnCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400+((x)*0x010)))) +#define MCF5235_ETPU_EC0HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408))) +#define MCF5235_ETPU_EC1HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0418))) +#define MCF5235_ETPU_EC2HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0428))) +#define MCF5235_ETPU_EC3HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0438))) +#define MCF5235_ETPU_EC4HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0448))) +#define MCF5235_ETPU_EC5HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0458))) +#define MCF5235_ETPU_EC6HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0468))) +#define MCF5235_ETPU_EC7HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0478))) +#define MCF5235_ETPU_EC8HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0488))) +#define MCF5235_ETPU_EC9HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0498))) +#define MCF5235_ETPU_EC10HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A8))) +#define MCF5235_ETPU_EC11HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B8))) +#define MCF5235_ETPU_EC12HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C8))) +#define MCF5235_ETPU_EC13HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D8))) +#define MCF5235_ETPU_EC14HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E8))) +#define MCF5235_ETPU_EC15HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F8))) +#define MCF5235_ETPU_EC16HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0508))) +#define MCF5235_ETPU_EC17HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0518))) +#define MCF5235_ETPU_EC18HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0528))) +#define MCF5235_ETPU_EC19HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0538))) +#define MCF5235_ETPU_EC20HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0548))) +#define MCF5235_ETPU_EC21HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0558))) +#define MCF5235_ETPU_EC22HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0568))) +#define MCF5235_ETPU_EC23HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0578))) +#define MCF5235_ETPU_EC24HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0588))) +#define MCF5235_ETPU_EC25HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0598))) +#define MCF5235_ETPU_EC26HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A8))) +#define MCF5235_ETPU_EC27HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B8))) +#define MCF5235_ETPU_EC28HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C8))) +#define MCF5235_ETPU_EC29HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D8))) +#define MCF5235_ETPU_EC30HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E8))) +#define MCF5235_ETPU_EC31HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F8))) +#define MCF5235_ETPU_ECnHSSR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408+((x)*0x010)))) + +/* Bit definitions and macros for MCF5235_ETPU_EMCR */ +#define MCF5235_ETPU_EMCR_GTBE (0x00000001) +#define MCF5235_ETPU_EMCR_VIS (0x00000040) +#define MCF5235_ETPU_EMCR_SCMMISEN (0x00000200) +#define MCF5235_ETPU_EMCR_SCMMISF (0x00000400) +#define MCF5235_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) +#define MCF5235_ETPU_EMCR_ILF2 (0x01000000) +#define MCF5235_ETPU_EMCR_ILF1 (0x02000000) +#define MCF5235_ETPU_EMCR_MGE2 (0x04000000) +#define MCF5235_ETPU_EMCR_MGE1 (0x08000000) +#define MCF5235_ETPU_EMCR_GEC (0x80000000) +#define MCF5235_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) +#define MCF5235_ETPU_ECDCR_WR (0x00000080) +#define MCF5235_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) +#define MCF5235_ETPU_ECDCR_PWIDTH (0x00008000) +#define MCF5235_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) +#define MCF5235_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) +#define MCF5235_ETPU_ECDCR_STS (0x80000000) +#define MCF5235_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) +#define MCF5235_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) +#define MCF5235_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) +#define MCF5235_ETPU_EECR_HLTF (0x00800000) +#define MCF5235_ETPU_EECR_STF (0x10000000) +#define MCF5235_ETPU_EECR_MDIS (0x40000000) +#define MCF5235_ETPU_EECR_FEND (0x80000000) +#define MCF5235_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) +#define MCF5235_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) +#define MCF5235_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) +#define MCF5235_ETPU_ETBCR_AM (0x02000000) +#define MCF5235_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) +#define MCF5235_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) +#define MCF5235_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) +#define MCF5235_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) +#define MCF5235_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) +#define MCF5235_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) +#define MCF5235_ETPU_EREDCR_RSC2 (0x00004000) +#define MCF5235_ETPU_EREDCR_REN2 (0x00008000) +#define MCF5235_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) +#define MCF5235_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) +#define MCF5235_ETPU_EREDCR_RSC1 (0x40000000) +#define MCF5235_ETPU_EREDCR_REN1 (0x80000000) +#define MCF5235_ETPU_ECISR_CIS0 (0x00000001) +#define MCF5235_ETPU_ECISR_CIS1 (0x00000002) +#define MCF5235_ETPU_ECISR_CIS2 (0x00000004) +#define MCF5235_ETPU_ECISR_CIS3 (0x00000008) +#define MCF5235_ETPU_ECISR_CIS4 (0x00000010) +#define MCF5235_ETPU_ECISR_CIS5 (0x00000020) +#define MCF5235_ETPU_ECISR_CIS6 (0x00000040) +#define MCF5235_ETPU_ECISR_CIS7 (0x00000080) +#define MCF5235_ETPU_ECISR_CIS8 (0x00000100) +#define MCF5235_ETPU_ECISR_CIS9 (0x00000200) +#define MCF5235_ETPU_ECISR_CIS10 (0x00000400) +#define MCF5235_ETPU_ECISR_CIS11 (0x00000800) +#define MCF5235_ETPU_ECISR_CIS12 (0x00001000) +#define MCF5235_ETPU_ECISR_CIS13 (0x00002000) +#define MCF5235_ETPU_ECISR_CIS14 (0x00004000) +#define MCF5235_ETPU_ECISR_CIS15 (0x00008000) +#define MCF5235_ETPU_ECISR_CIS16 (0x00010000) +#define MCF5235_ETPU_ECISR_CIS17 (0x00020000) +#define MCF5235_ETPU_ECISR_CIS18 (0x00040000) +#define MCF5235_ETPU_ECISR_CIS19 (0x00080000) +#define MCF5235_ETPU_ECISR_CIS20 (0x00100000) +#define MCF5235_ETPU_ECISR_CIS21 (0x00200000) +#define MCF5235_ETPU_ECISR_CIS22 (0x00400000) +#define MCF5235_ETPU_ECISR_CIS23 (0x00800000) +#define MCF5235_ETPU_ECISR_CIS24 (0x01000000) +#define MCF5235_ETPU_ECISR_CIS25 (0x02000000) +#define MCF5235_ETPU_ECISR_CIS26 (0x04000000) +#define MCF5235_ETPU_ECISR_CIS27 (0x08000000) +#define MCF5235_ETPU_ECISR_CIS28 (0x10000000) +#define MCF5235_ETPU_ECISR_CIS29 (0x20000000) +#define MCF5235_ETPU_ECISR_CIS30 (0x40000000) +#define MCF5235_ETPU_ECISR_CIS31 (0x80000000) +#define MCF5235_ETPU_ECDTRSR_DTRS0 (0x00000001) +#define MCF5235_ETPU_ECDTRSR_DTRS1 (0x00000002) +#define MCF5235_ETPU_ECDTRSR_DTRS2 (0x00000004) +#define MCF5235_ETPU_ECDTRSR_DTRS3 (0x00000008) +#define MCF5235_ETPU_ECDTRSR_DTRS4 (0x00000010) +#define MCF5235_ETPU_ECDTRSR_DTRS5 (0x00000020) +#define MCF5235_ETPU_ECDTRSR_DTRS6 (0x00000040) +#define MCF5235_ETPU_ECDTRSR_DTRS7 (0x00000080) +#define MCF5235_ETPU_ECDTRSR_DTRS8 (0x00000100) +#define MCF5235_ETPU_ECDTRSR_DTRS9 (0x00000200) +#define MCF5235_ETPU_ECDTRSR_DTRS10 (0x00000400) +#define MCF5235_ETPU_ECDTRSR_DTRS11 (0x00000800) +#define MCF5235_ETPU_ECDTRSR_DTRS12 (0x00001000) +#define MCF5235_ETPU_ECDTRSR_DTRS13 (0x00002000) +#define MCF5235_ETPU_ECDTRSR_DTRS14 (0x00004000) +#define MCF5235_ETPU_ECDTRSR_DTRS15 (0x00008000) +#define MCF5235_ETPU_ECDTRSR_DTRS16 (0x00010000) +#define MCF5235_ETPU_ECDTRSR_DTRS17 (0x00020000) +#define MCF5235_ETPU_ECDTRSR_DTRS18 (0x00040000) +#define MCF5235_ETPU_ECDTRSR_DTRS19 (0x00080000) +#define MCF5235_ETPU_ECDTRSR_DTRS20 (0x00100000) +#define MCF5235_ETPU_ECDTRSR_DTRS21 (0x00200000) +#define MCF5235_ETPU_ECDTRSR_DTRS22 (0x00400000) +#define MCF5235_ETPU_ECDTRSR_DTRS23 (0x00800000) +#define MCF5235_ETPU_ECDTRSR_DTRS24 (0x01000000) +#define MCF5235_ETPU_ECDTRSR_DTRS25 (0x02000000) +#define MCF5235_ETPU_ECDTRSR_DTRS26 (0x04000000) +#define MCF5235_ETPU_ECDTRSR_DTRS27 (0x08000000) +#define MCF5235_ETPU_ECDTRSR_DTRS28 (0x10000000) +#define MCF5235_ETPU_ECDTRSR_DTRS29 (0x20000000) +#define MCF5235_ETPU_ECDTRSR_DTRS30 (0x40000000) +#define MCF5235_ETPU_ECDTRSR_DTRS31 (0x80000000) +#define MCF5235_ETPU_ECIOSR_CIOS0 (0x00000001) +#define MCF5235_ETPU_ECIOSR_CIOS1 (0x00000002) +#define MCF5235_ETPU_ECIOSR_CIOS2 (0x00000004) +#define MCF5235_ETPU_ECIOSR_CIOS3 (0x00000008) +#define MCF5235_ETPU_ECIOSR_CIOS4 (0x00000010) +#define MCF5235_ETPU_ECIOSR_CIOS5 (0x00000020) +#define MCF5235_ETPU_ECIOSR_CIOS6 (0x00000040) +#define MCF5235_ETPU_ECIOSR_CIOS7 (0x00000080) +#define MCF5235_ETPU_ECIOSR_CIOS8 (0x00000100) +#define MCF5235_ETPU_ECIOSR_CIOS9 (0x00000200) +#define MCF5235_ETPU_ECIOSR_CIOS10 (0x00000400) +#define MCF5235_ETPU_ECIOSR_CIOS11 (0x00000800) +#define MCF5235_ETPU_ECIOSR_CIOS12 (0x00001000) +#define MCF5235_ETPU_ECIOSR_CIOS13 (0x00002000) +#define MCF5235_ETPU_ECIOSR_CIOS14 (0x00004000) +#define MCF5235_ETPU_ECIOSR_CIOS15 (0x00008000) +#define MCF5235_ETPU_ECIOSR_CIOS16 (0x00010000) +#define MCF5235_ETPU_ECIOSR_CIOS17 (0x00020000) +#define MCF5235_ETPU_ECIOSR_CIOS18 (0x00040000) +#define MCF5235_ETPU_ECIOSR_CIOS19 (0x00080000) +#define MCF5235_ETPU_ECIOSR_CIOS20 (0x00100000) +#define MCF5235_ETPU_ECIOSR_CIOS21 (0x00200000) +#define MCF5235_ETPU_ECIOSR_CIOS22 (0x00400000) +#define MCF5235_ETPU_ECIOSR_CIOS23 (0x00800000) +#define MCF5235_ETPU_ECIOSR_CIOS24 (0x01000000) +#define MCF5235_ETPU_ECIOSR_CIOS25 (0x02000000) +#define MCF5235_ETPU_ECIOSR_CIOS26 (0x04000000) +#define MCF5235_ETPU_ECIOSR_CIOS27 (0x08000000) +#define MCF5235_ETPU_ECIOSR_CIOS28 (0x10000000) +#define MCF5235_ETPU_ECIOSR_CIOS29 (0x20000000) +#define MCF5235_ETPU_ECIOSR_CIOS30 (0x40000000) +#define MCF5235_ETPU_ECIOSR_CIOS31 (0x80000000) +#define MCF5235_ETPU_ECDTROSR_DTROS0 (0x00000001) +#define MCF5235_ETPU_ECDTROSR_DTROS1 (0x00000002) +#define MCF5235_ETPU_ECDTROSR_DTROS2 (0x00000004) +#define MCF5235_ETPU_ECDTROSR_DTROS3 (0x00000008) +#define MCF5235_ETPU_ECDTROSR_DTROS4 (0x00000010) +#define MCF5235_ETPU_ECDTROSR_DTROS5 (0x00000020) +#define MCF5235_ETPU_ECDTROSR_DTROS6 (0x00000040) +#define MCF5235_ETPU_ECDTROSR_DTROS7 (0x00000080) +#define MCF5235_ETPU_ECDTROSR_DTROS8 (0x00000100) +#define MCF5235_ETPU_ECDTROSR_DTROS9 (0x00000200) +#define MCF5235_ETPU_ECDTROSR_DTROS10 (0x00000400) +#define MCF5235_ETPU_ECDTROSR_DTROS11 (0x00000800) +#define MCF5235_ETPU_ECDTROSR_DTROS12 (0x00001000) +#define MCF5235_ETPU_ECDTROSR_DTROS13 (0x00002000) +#define MCF5235_ETPU_ECDTROSR_DTROS14 (0x00004000) +#define MCF5235_ETPU_ECDTROSR_DTROS15 (0x00008000) +#define MCF5235_ETPU_ECDTROSR_DTROS16 (0x00010000) +#define MCF5235_ETPU_ECDTROSR_DTROS17 (0x00020000) +#define MCF5235_ETPU_ECDTROSR_DTROS18 (0x00040000) +#define MCF5235_ETPU_ECDTROSR_DTROS19 (0x00080000) +#define MCF5235_ETPU_ECDTROSR_DTROS20 (0x00100000) +#define MCF5235_ETPU_ECDTROSR_DTROS21 (0x00200000) +#define MCF5235_ETPU_ECDTROSR_DTROS22 (0x00400000) +#define MCF5235_ETPU_ECDTROSR_DTROS23 (0x00800000) +#define MCF5235_ETPU_ECDTROSR_DTROS24 (0x01000000) +#define MCF5235_ETPU_ECDTROSR_DTROS25 (0x02000000) +#define MCF5235_ETPU_ECDTROSR_DTROS26 (0x04000000) +#define MCF5235_ETPU_ECDTROSR_DTROS27 (0x08000000) +#define MCF5235_ETPU_ECDTROSR_DTROS28 (0x10000000) +#define MCF5235_ETPU_ECDTROSR_DTROS29 (0x20000000) +#define MCF5235_ETPU_ECDTROSR_DTROS30 (0x40000000) +#define MCF5235_ETPU_ECDTROSR_DTROS31 (0x80000000) +#define MCF5235_ETPU_ECIER_CIE0 (0x00000001) +#define MCF5235_ETPU_ECIER_CIE1 (0x00000002) +#define MCF5235_ETPU_ECIER_CIE2 (0x00000004) +#define MCF5235_ETPU_ECIER_CIE3 (0x00000008) +#define MCF5235_ETPU_ECIER_CIE4 (0x00000010) +#define MCF5235_ETPU_ECIER_CIE5 (0x00000020) +#define MCF5235_ETPU_ECIER_CIE6 (0x00000040) +#define MCF5235_ETPU_ECIER_CIE7 (0x00000080) +#define MCF5235_ETPU_ECIER_CIE8 (0x00000100) +#define MCF5235_ETPU_ECIER_CIE9 (0x00000200) +#define MCF5235_ETPU_ECIER_CIE10 (0x00000400) +#define MCF5235_ETPU_ECIER_CIE11 (0x00000800) +#define MCF5235_ETPU_ECIER_CIE12 (0x00001000) +#define MCF5235_ETPU_ECIER_CIE13 (0x00002000) +#define MCF5235_ETPU_ECIER_CIE14 (0x00004000) +#define MCF5235_ETPU_ECIER_CIE15 (0x00008000) +#define MCF5235_ETPU_ECIER_CIE16 (0x00010000) +#define MCF5235_ETPU_ECIER_CIE17 (0x00020000) +#define MCF5235_ETPU_ECIER_CIE18 (0x00040000) +#define MCF5235_ETPU_ECIER_CIE19 (0x00080000) +#define MCF5235_ETPU_ECIER_CIE20 (0x00100000) +#define MCF5235_ETPU_ECIER_CIE21 (0x00200000) +#define MCF5235_ETPU_ECIER_CIE22 (0x00400000) +#define MCF5235_ETPU_ECIER_CIE23 (0x00800000) +#define MCF5235_ETPU_ECIER_CIE24 (0x01000000) +#define MCF5235_ETPU_ECIER_CIE25 (0x02000000) +#define MCF5235_ETPU_ECIER_CIE26 (0x04000000) +#define MCF5235_ETPU_ECIER_CIE27 (0x08000000) +#define MCF5235_ETPU_ECIER_CIE28 (0x10000000) +#define MCF5235_ETPU_ECIER_CIE29 (0x20000000) +#define MCF5235_ETPU_ECIER_CIE30 (0x40000000) +#define MCF5235_ETPU_ECIER_CIE31 (0x80000000) +#define MCF5235_ETPU_ECDTRER_DTRE0 (0x00000001) +#define MCF5235_ETPU_ECDTRER_DTRE1 (0x00000002) +#define MCF5235_ETPU_ECDTRER_DTRE2 (0x00000004) +#define MCF5235_ETPU_ECDTRER_DTRE3 (0x00000008) +#define MCF5235_ETPU_ECDTRER_DTRE4 (0x00000010) +#define MCF5235_ETPU_ECDTRER_DTRE5 (0x00000020) +#define MCF5235_ETPU_ECDTRER_DTRE6 (0x00000040) +#define MCF5235_ETPU_ECDTRER_DTRE7 (0x00000080) +#define MCF5235_ETPU_ECDTRER_DTRE8 (0x00000100) +#define MCF5235_ETPU_ECDTRER_DTRE9 (0x00000200) +#define MCF5235_ETPU_ECDTRER_DTRE10 (0x00000400) +#define MCF5235_ETPU_ECDTRER_DTRE11 (0x00000800) +#define MCF5235_ETPU_ECDTRER_DTRE12 (0x00001000) +#define MCF5235_ETPU_ECDTRER_DTRE13 (0x00002000) +#define MCF5235_ETPU_ECDTRER_DTRE14 (0x00004000) +#define MCF5235_ETPU_ECDTRER_DTRE15 (0x00008000) +#define MCF5235_ETPU_ECDTRER_DTRE16 (0x00010000) +#define MCF5235_ETPU_ECDTRER_DTRE17 (0x00020000) +#define MCF5235_ETPU_ECDTRER_DTRE18 (0x00040000) +#define MCF5235_ETPU_ECDTRER_DTRE19 (0x00080000) +#define MCF5235_ETPU_ECDTRER_DTRE20 (0x00100000) +#define MCF5235_ETPU_ECDTRER_DTRE21 (0x00200000) +#define MCF5235_ETPU_ECDTRER_DTRE22 (0x00400000) +#define MCF5235_ETPU_ECDTRER_DTRE23 (0x00800000) +#define MCF5235_ETPU_ECDTRER_DTRE24 (0x01000000) +#define MCF5235_ETPU_ECDTRER_DTRE25 (0x02000000) +#define MCF5235_ETPU_ECDTRER_DTRE26 (0x04000000) +#define MCF5235_ETPU_ECDTRER_DTRE27 (0x08000000) +#define MCF5235_ETPU_ECDTRER_DTRE28 (0x10000000) +#define MCF5235_ETPU_ECDTRER_DTRE29 (0x20000000) +#define MCF5235_ETPU_ECDTRER_DTRE30 (0x40000000) +#define MCF5235_ETPU_ECDTRER_DTRE31 (0x80000000) +#define MCF5235_ETPU_ECPSSR_SR0 (0x00000001) +#define MCF5235_ETPU_ECPSSR_SR1 (0x00000002) +#define MCF5235_ETPU_ECPSSR_SR2 (0x00000004) +#define MCF5235_ETPU_ECPSSR_SR3 (0x00000008) +#define MCF5235_ETPU_ECPSSR_SR4 (0x00000010) +#define MCF5235_ETPU_ECPSSR_SR5 (0x00000020) +#define MCF5235_ETPU_ECPSSR_SR6 (0x00000040) +#define MCF5235_ETPU_ECPSSR_SR7 (0x00000080) +#define MCF5235_ETPU_ECPSSR_SR8 (0x00000100) +#define MCF5235_ETPU_ECPSSR_SR9 (0x00000200) +#define MCF5235_ETPU_ECPSSR_SR10 (0x00000400) +#define MCF5235_ETPU_ECPSSR_SR11 (0x00000800) +#define MCF5235_ETPU_ECPSSR_SR12 (0x00001000) +#define MCF5235_ETPU_ECPSSR_SR13 (0x00002000) +#define MCF5235_ETPU_ECPSSR_SR14 (0x00004000) +#define MCF5235_ETPU_ECPSSR_SR15 (0x00008000) +#define MCF5235_ETPU_ECPSSR_SR16 (0x00010000) +#define MCF5235_ETPU_ECPSSR_SR17 (0x00020000) +#define MCF5235_ETPU_ECPSSR_SR18 (0x00040000) +#define MCF5235_ETPU_ECPSSR_SR19 (0x00080000) +#define MCF5235_ETPU_ECPSSR_SR20 (0x00100000) +#define MCF5235_ETPU_ECPSSR_SR21 (0x00200000) +#define MCF5235_ETPU_ECPSSR_SR22 (0x00400000) +#define MCF5235_ETPU_ECPSSR_SR23 (0x00800000) +#define MCF5235_ETPU_ECPSSR_SR24 (0x01000000) +#define MCF5235_ETPU_ECPSSR_SR25 (0x02000000) +#define MCF5235_ETPU_ECPSSR_SR26 (0x04000000) +#define MCF5235_ETPU_ECPSSR_SR27 (0x08000000) +#define MCF5235_ETPU_ECPSSR_SR28 (0x10000000) +#define MCF5235_ETPU_ECPSSR_SR29 (0x20000000) +#define MCF5235_ETPU_ECPSSR_SR30 (0x40000000) +#define MCF5235_ETPU_ECPSSR_SR31 (0x80000000) +#define MCF5235_ETPU_ECSSR_SS0 (0x00000001) +#define MCF5235_ETPU_ECSSR_SS1 (0x00000002) +#define MCF5235_ETPU_ECSSR_SS2 (0x00000004) +#define MCF5235_ETPU_ECSSR_SS3 (0x00000008) +#define MCF5235_ETPU_ECSSR_SS4 (0x00000010) +#define MCF5235_ETPU_ECSSR_SS5 (0x00000020) +#define MCF5235_ETPU_ECSSR_SS6 (0x00000040) +#define MCF5235_ETPU_ECSSR_SS7 (0x00000080) +#define MCF5235_ETPU_ECSSR_SS8 (0x00000100) +#define MCF5235_ETPU_ECSSR_SS9 (0x00000200) +#define MCF5235_ETPU_ECSSR_SS10 (0x00000400) +#define MCF5235_ETPU_ECSSR_SS11 (0x00000800) +#define MCF5235_ETPU_ECSSR_SS12 (0x00001000) +#define MCF5235_ETPU_ECSSR_SS13 (0x00002000) +#define MCF5235_ETPU_ECSSR_SS14 (0x00004000) +#define MCF5235_ETPU_ECSSR_SS15 (0x00008000) +#define MCF5235_ETPU_ECSSR_SS16 (0x00010000) +#define MCF5235_ETPU_ECSSR_SS17 (0x00020000) +#define MCF5235_ETPU_ECSSR_SS18 (0x00040000) +#define MCF5235_ETPU_ECSSR_SS19 (0x00080000) +#define MCF5235_ETPU_ECSSR_SS20 (0x00100000) +#define MCF5235_ETPU_ECSSR_SS21 (0x00200000) +#define MCF5235_ETPU_ECSSR_SS22 (0x00400000) +#define MCF5235_ETPU_ECSSR_SS23 (0x00800000) +#define MCF5235_ETPU_ECSSR_SS24 (0x01000000) +#define MCF5235_ETPU_ECSSR_SS25 (0x02000000) +#define MCF5235_ETPU_ECSSR_SS26 (0x04000000) +#define MCF5235_ETPU_ECSSR_SS27 (0x08000000) +#define MCF5235_ETPU_ECSSR_SS28 (0x10000000) +#define MCF5235_ETPU_ECSSR_SS29 (0x20000000) +#define MCF5235_ETPU_ECSSR_SS30 (0x40000000) +#define MCF5235_ETPU_ECSSR_SS31 (0x80000000) +#define MCF5235_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) +#define MCF5235_ETPU_ECnSCR_OBE (0x00002000) +#define MCF5235_ETPU_ECnSCR_OPS (0x00004000) +#define MCF5235_ETPU_ECnSCR_IPS (0x00008000) +#define MCF5235_ETPU_ECnSCR_DTROS (0x00400000) +#define MCF5235_ETPU_ECnSCR_DTRS (0x00800000) +#define MCF5235_ETPU_ECnSCR_CIOS (0x40000000) +#define MCF5235_ETPU_ECnSCR_CIS (0x80000000) +#define MCF5235_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) +#define MCF5235_ETPU_ECnCR_OPOL (0x00004000) +#define MCF5235_ETPU_ECnCR_ODIS (0x00008000) +#define MCF5235_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) +#define MCF5235_ETPU_ECnCR_ETCS (0x01000000) +#define MCF5235_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) +#define MCF5235_ETPU_ECnCR_DTRE (0x40000000) +#define MCF5235_ETPU_ECnCR_CIE (0x80000000) +#define MCF5235_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) + + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_FEC_EIR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001004))) +#define MCF5235_FEC_EIMR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001008))) +#define MCF5235_FEC_RDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001010))) +#define MCF5235_FEC_TDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001014))) +#define MCF5235_FEC_ECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001024))) +#define MCF5235_FEC_MMFR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001040))) +#define MCF5235_FEC_MSCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001044))) +#define MCF5235_FEC_MIBC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001064))) +#define MCF5235_FEC_RCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001084))) +#define MCF5235_FEC_TCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010C4))) +#define MCF5235_FEC_PALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E4))) +#define MCF5235_FEC_PAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E8))) +#define MCF5235_FEC_OPD (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010EC))) +#define MCF5235_FEC_IAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001118))) +#define MCF5235_FEC_IALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00111C))) +#define MCF5235_FEC_GAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001120))) +#define MCF5235_FEC_GALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001124))) +#define MCF5235_FEC_TFWR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001144))) +#define MCF5235_FEC_FRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00114C))) +#define MCF5235_FEC_FRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001150))) +#define MCF5235_FEC_ERDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001180))) +#define MCF5235_FEC_ETDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001184))) +#define MCF5235_FEC_EMRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001188))) +#define MCF5235_FEC_RMON_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001200))) +#define MCF5235_FEC_RMON_T_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001204))) +#define MCF5235_FEC_RMON_T_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001208))) +#define MCF5235_FEC_RMON_T_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00120C))) +#define MCF5235_FEC_RMON_T_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001210))) +#define MCF5235_FEC_RMON_T_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001214))) +#define MCF5235_FEC_RMON_T_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001218))) +#define MCF5235_FEC_RMON_T_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00121C))) +#define MCF5235_FEC_RMON_T_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x001220))) +#define MCF5235_FEC_RMON_T_COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001224))) +#define MCF5235_FEC_RMON_T_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001228))) +#define MCF5235_FEC_RMON_T_P65TO127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00122C))) +#define MCF5235_FEC_RMON_T_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001230))) +#define MCF5235_FEC_RMON_T_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001234))) +#define MCF5235_FEC_RMON_T_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001238))) +#define MCF5235_FEC_RMON_T_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00123C))) +#define MCF5235_FEC_RMON_T_P_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001240))) +#define MCF5235_FEC_RMON_T_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001244))) +#define MCF5235_FEC_IEEE_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001248))) +#define MCF5235_FEC_IEEE_T_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00124C))) +#define MCF5235_FEC_IEEE_T_1COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001250))) +#define MCF5235_FEC_IEEE_T_MCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001254))) +#define MCF5235_FEC_IEEE_T_DEF (*(vuint32*)((uintptr_t)__IPSBAR + (0x001258))) +#define MCF5235_FEC_IEEE_T_LCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x00125C))) +#define MCF5235_FEC_IEEE_T_EXCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001260))) +#define MCF5235_FEC_IEEE_T_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001264))) +#define MCF5235_FEC_IEEE_T_CSERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001268))) +#define MCF5235_FEC_IEEE_T_SQE (*(vuint32*)((uintptr_t)__IPSBAR + (0x00126C))) +#define MCF5235_FEC_IEEE_T_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001270))) +#define MCF5235_FEC_IEEE_T_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x001274))) +#define MCF5235_FEC_RMON_R_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001284))) +#define MCF5235_FEC_RMON_R_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001288))) +#define MCF5235_FEC_RMON_R_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00128C))) +#define MCF5235_FEC_RMON_R_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001290))) +#define MCF5235_FEC_RMON_R_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001294))) +#define MCF5235_FEC_RMON_R_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001298))) +#define MCF5235_FEC_RMON_R_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00129C))) +#define MCF5235_FEC_RMON_R_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A0))) +#define MCF5235_FEC_RMON_R_RESVD_0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A4))) +#define MCF5235_FEC_RMON_R_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A8))) +#define MCF5235_FEC_RMON_R_P65T0127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012AC))) +#define MCF5235_FEC_RMON_R_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B0))) +#define MCF5235_FEC_RMON_R_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B4))) +#define MCF5235_FEC_RMON_R_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B8))) +#define MCF5235_FEC_RMON_R_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C0))) +#define MCF5235_FEC_RMON_R_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012BC))) +#define MCF5235_FEC_RMON_R_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C4))) +#define MCF5235_FEC_IEEE_R_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C8))) +#define MCF5235_FEC_IEEE_R_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012CC))) +#define MCF5235_FEC_IEEE_R_CRC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D0))) +#define MCF5235_FEC_IEEE_R_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D4))) +#define MCF5235_FEC_IEEE_R_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D8))) +#define MCF5235_FEC_IEEE_R_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012DC))) +#define MCF5235_FEC_IEEE_R_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012E0))) + +/* Bit definitions and macros for MCF5235_FEC_EIR */ +#define MCF5235_FEC_EIR_UN (0x00080000) +#define MCF5235_FEC_EIR_RL (0x00100000) +#define MCF5235_FEC_EIR_LC (0x00200000) +#define MCF5235_FEC_EIR_EBERR (0x00400000) +#define MCF5235_FEC_EIR_MII (0x00800000) +#define MCF5235_FEC_EIR_RXB (0x01000000) +#define MCF5235_FEC_EIR_RXF (0x02000000) +#define MCF5235_FEC_EIR_TXB (0x04000000) +#define MCF5235_FEC_EIR_TXF (0x08000000) +#define MCF5235_FEC_EIR_GRA (0x10000000) +#define MCF5235_FEC_EIR_BABT (0x20000000) +#define MCF5235_FEC_EIR_BABR (0x40000000) +#define MCF5235_FEC_EIR_HBERR (0x80000000) +#define MCF5235_FEC_EIMR_UN (0x00080000) +#define MCF5235_FEC_EIMR_RL (0x00100000) +#define MCF5235_FEC_EIMR_LC (0x00200000) +#define MCF5235_FEC_EIMR_EBERR (0x00400000) +#define MCF5235_FEC_EIMR_MII (0x00800000) +#define MCF5235_FEC_EIMR_RXB (0x01000000) +#define MCF5235_FEC_EIMR_RXF (0x02000000) +#define MCF5235_FEC_EIMR_TXB (0x04000000) +#define MCF5235_FEC_EIMR_TXF (0x08000000) +#define MCF5235_FEC_EIMR_GRA (0x10000000) +#define MCF5235_FEC_EIMR_BABT (0x20000000) +#define MCF5235_FEC_EIMR_BABR (0x40000000) +#define MCF5235_FEC_EIMR_HBERR (0x80000000) +#define MCF5235_FEC_RDAR_R_DES_ACTIVE (0x01000000) +#define MCF5235_FEC_TDAR_X_DES_ACTIVE (0x01000000) +#define MCF5235_FEC_ECR_RESET (0x00000001) +#define MCF5235_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5235_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF5235_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF5235_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF5235_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF5235_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF5235_FEC_MMFR_ST_01 (0x40000000) +#define MCF5235_FEC_MMFR_OP_READ (0x20000000) +#define MCF5235_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF5235_FEC_MMFR_TA_10 (0x00020000) +#define MCF5235_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF5235_FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define MCF5235_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF5235_FEC_MIBC_MIB_DISABLE (0x80000000) +#define MCF5235_FEC_RCR_LOOP (0x00000001) +#define MCF5235_FEC_RCR_DRT (0x00000002) +#define MCF5235_FEC_RCR_MII_MODE (0x00000004) +#define MCF5235_FEC_RCR_PROM (0x00000008) +#define MCF5235_FEC_RCR_BC_REJ (0x00000010) +#define MCF5235_FEC_RCR_FCE (0x00000020) +#define MCF5235_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) +#define MCF5235_FEC_TCR_GTS (0x00000001) +#define MCF5235_FEC_TCR_HBC (0x00000002) +#define MCF5235_FEC_TCR_FDEN (0x00000004) +#define MCF5235_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF5235_FEC_TCR_RFC_PAUSE (0x00000010) +#define MCF5235_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF5235_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) +#define MCF5235_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) +#define MCF5235_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) +#define MCF5235_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) +#define MCF5235_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) +#define MCF5235_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) +#define MCF5235_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) +#define MCF5235_FEC_TxBD_R 0x8000 +#define MCF5235_FEC_TxBD_BUSY 0x4000 +#define MCF5235_FEC_TxBD_TO1 0x4000 +#define MCF5235_FEC_TxBD_W 0x2000 +#define MCF5235_FEC_TxBD_TO2 0x1000 +#define MCF5235_FEC_TxBD_FIRST 0x1000 +#define MCF5235_FEC_TxBD_L 0x0800 +#define MCF5235_FEC_TxBD_TC 0x0400 +#define MCF5235_FEC_TxBD_DEF 0x0200 +#define MCF5235_FEC_TxBD_HB 0x0100 +#define MCF5235_FEC_TxBD_LC 0x0080 +#define MCF5235_FEC_TxBD_RL 0x0040 +#define MCF5235_FEC_TxBD_UN 0x0002 +#define MCF5235_FEC_TxBD_CSL 0x0001 +#define MCF5235_FEC_RxBD_E 0x8000 +#define MCF5235_FEC_RxBD_INUSE 0x4000 +#define MCF5235_FEC_RxBD_R01 0x4000 +#define MCF5235_FEC_RxBD_W 0x2000 +#define MCF5235_FEC_RxBD_R02 0x1000 +#define MCF5235_FEC_RxBD_L 0x0800 +#define MCF5235_FEC_RxBD_M 0x0100 +#define MCF5235_FEC_RxBD_BC 0x0080 +#define MCF5235_FEC_RxBD_MC 0x0040 +#define MCF5235_FEC_RxBD_LG 0x0020 +#define MCF5235_FEC_RxBD_NO 0x0010 +#define MCF5235_FEC_RxBD_CR 0x0004 +#define MCF5235_FEC_RxBD_OV 0x0002 +#define MCF5235_FEC_RxBD_TR 0x0001 + +/************************************************************ +* +* Clock +*************************************************************/ +/* Register read/write macros */ +#define MCF5235_FMPLL_SYNCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120000))) +#define MCF5235_FMPLL_SYNSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120004))) + +/* Bit definitions and macros for MCF5235_FMPLL_SYNCR */ +#define MCF5235_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) +#define MCF5235_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) +#define MCF5235_FMPLL_SYNCR_RATE (0x00001000) +#define MCF5235_FMPLL_SYNCR_LOCIRQ (0x00002000) +#define MCF5235_FMPLL_SYNCR_LOLIRQ (0x00004000) +#define MCF5235_FMPLL_SYNCR_DISCLK (0x00008000) +#define MCF5235_FMPLL_SYNCR_LOCRE (0x00010000) +#define MCF5235_FMPLL_SYNCR_LOLRE (0x00020000) +#define MCF5235_FMPLL_SYNCR_LOCEN (0x00040000) +#define MCF5235_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) +#define MCF5235_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) +#define MCF5235_FMPLL_SYNSR_CALPASS (0x00000001) +#define MCF5235_FMPLL_SYNSR_CALDONE (0x00000002) +#define MCF5235_FMPLL_SYNSR_LOCF (0x00000004) +#define MCF5235_FMPLL_SYNSR_LOCK (0x00000008) +#define MCF5235_FMPLL_SYNSR_LOCKS (0x00000010) +#define MCF5235_FMPLL_SYNSR_PLLREF (0x00000020) +#define MCF5235_FMPLL_SYNSR_PLLSEL (0x00000040) +#define MCF5235_FMPLL_SYNSR_MODE (0x00000080) +#define MCF5235_FMPLL_SYNSR_LOC (0x00000100) +#define MCF5235_FMPLL_SYNSR_LOLF (0x00000200) + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_GPIO_PODR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100000))) +#define MCF5235_GPIO_PODR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100001))) +#define MCF5235_GPIO_PODR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100002))) +#define MCF5235_GPIO_PODR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100003))) +#define MCF5235_GPIO_PODR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100004))) +#define MCF5235_GPIO_PODR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100005))) +#define MCF5235_GPIO_PODR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100006))) +#define MCF5235_GPIO_PODR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100007))) +#define MCF5235_GPIO_PODR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100008))) +#define MCF5235_GPIO_PODR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100009))) +#define MCF5235_GPIO_PODR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000A))) +#define MCF5235_GPIO_PODR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000B))) +#define MCF5235_GPIO_PODR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000C))) +#define MCF5235_GPIO_PDDR_APDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100010))) +#define MCF5235_GPIO_PDDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100011))) +#define MCF5235_GPIO_PDDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100012))) +#define MCF5235_GPIO_PDDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100013))) +#define MCF5235_GPIO_PDDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100014))) +#define MCF5235_GPIO_PDDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100015))) +#define MCF5235_GPIO_PDDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100016))) +#define MCF5235_GPIO_PDDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100017))) +#define MCF5235_GPIO_PDDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100018))) +#define MCF5235_GPIO_PDDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100019))) +#define MCF5235_GPIO_PDDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001A))) +#define MCF5235_GPIO_PDDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001B))) +#define MCF5235_GPIO_PDDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001C))) +#define MCF5235_GPIO_PPDSDR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100020))) +#define MCF5235_GPIO_PPDSDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100021))) +#define MCF5235_GPIO_PPDSDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100022))) +#define MCF5235_GPIO_PPDSDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100023))) +#define MCF5235_GPIO_PPDSDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100024))) +#define MCF5235_GPIO_PPDSDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100027))) +#define MCF5235_GPIO_PPDSDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100025))) +#define MCF5235_GPIO_PPDSDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100026))) +#define MCF5235_GPIO_PPDSDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100028))) +#define MCF5235_GPIO_PPDSDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100029))) +#define MCF5235_GPIO_PPDSDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002A))) +#define MCF5235_GPIO_PPDSDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002B))) +#define MCF5235_GPIO_PPDSDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002C))) +#define MCF5235_GPIO_PCLRR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100030))) +#define MCF5235_GPIO_PCLRR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100031))) +#define MCF5235_GPIO_PCLRR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100032))) +#define MCF5235_GPIO_PCLRR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100033))) +#define MCF5235_GPIO_PCLRR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100034))) +#define MCF5235_GPIO_PCLRR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100035))) +#define MCF5235_GPIO_PCLRR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100036))) +#define MCF5235_GPIO_PCLRR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100037))) +#define MCF5235_GPIO_PCLRR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100038))) +#define MCF5235_GPIO_PCLRR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100039))) +#define MCF5235_GPIO_PCLRR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003A))) +#define MCF5235_GPIO_PCLRR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003B))) +#define MCF5235_GPIO_PCLRR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003C))) +#define MCF5235_GPIO_PAR_AD (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100040))) +#define MCF5235_GPIO_PAR_BUSCTL (*(vuint16*)((uintptr_t)__IPSBAR + (0x100042))) +#define MCF5235_GPIO_PAR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100044))) +#define MCF5235_GPIO_PAR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100045))) +#define MCF5235_GPIO_PAR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100046))) +#define MCF5235_GPIO_PAR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100047))) +#define MCF5235_GPIO_UART (*(vuint16*)((uintptr_t)__IPSBAR + (0x100048))) +#define MCF5235_GPIO_PAR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004A))) +#define MCF5235_GPIO_PAR_TIMER (*(vuint16*)((uintptr_t)__IPSBAR + (0x10004C))) +#define MCF5235_GPIO_PAR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004E))) +#define MCF5235_GPIO_DSCR_EIM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100050))) +#define MCF5235_GPIO_DSCR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100051))) +#define MCF5235_GPIO_DSCR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100052))) +#define MCF5235_GPIO_DSCR_UART (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100053))) +#define MCF5235_GPIO_DSCR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100054))) +#define MCF5235_GPIO_DSCR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100055))) + +/* Bit definitions and macros for MCF5235_GPIO_PODR_ADDR */ +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) +#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) +#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) +#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PODR_BS_PODR_BS0 (0x01) +#define MCF5235_GPIO_PODR_BS_PODR_BS1 (0x02) +#define MCF5235_GPIO_PODR_BS_PODR_BS2 (0x04) +#define MCF5235_GPIO_PODR_BS_PODR_BS3 (0x08) +#define MCF5235_GPIO_PODR_CS_PODR_CS1 (0x02) +#define MCF5235_GPIO_PODR_CS_PODR_CS2 (0x04) +#define MCF5235_GPIO_PODR_CS_PODR_CS3 (0x08) +#define MCF5235_GPIO_PODR_CS_PODR_CS4 (0x10) +#define MCF5235_GPIO_PODR_CS_PODR_CS5 (0x20) +#define MCF5235_GPIO_PODR_CS_PODR_CS6 (0x40) +#define MCF5235_GPIO_PODR_CS_PODR_CS7 (0x80) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) +#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) +#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) +#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) +#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) +#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) +#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) +#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) +#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) +#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) +#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PDDR_BS_PDDR_BS0 (0x01) +#define MCF5235_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS1 (0x02) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS2 (0x04) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS3 (0x08) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS4 (0x10) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS5 (0x20) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS6 (0x40) +#define MCF5235_GPIO_PDDR_CS_PDDR_CS7 (0x80) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) +#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) +#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) +#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) +#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) +#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) +#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) +#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) +#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) +#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) +#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) +#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) +#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) +#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) +#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) +#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) +#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) +#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) +#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) +#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) +#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) +#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) +#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) +#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) +#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) +#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)*/ +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) +#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) +#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) +#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) +#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) +#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) +#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) +#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) +#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) +#define MCF5235_GPIO_PAR_AD_PAR_DATAL (0x01) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR21 (0x20) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR22 (0x40) +#define MCF5235_GPIO_PAR_AD_PAR_ADDR23 (0x80) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TA (0x1000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_OE (0x4000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) +#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) +#define MCF5235_GPIO_PAR_BS_PAR_BS0 (0x01) +#define MCF5235_GPIO_PAR_BS_PAR_BS1 (0x02) +#define MCF5235_GPIO_PAR_BS_PAR_BS2 (0x04) +#define MCF5235_GPIO_PAR_BS_PAR_BS3 (0x08) +#define MCF5235_GPIO_PAR_CS_PAR_CS1 (0x02) +#define MCF5235_GPIO_PAR_CS_PAR_CS2 (0x04) +#define MCF5235_GPIO_PAR_CS_PAR_CS3 (0x08) +#define MCF5235_GPIO_PAR_CS_PAR_CS4 (0x10) +#define MCF5235_GPIO_PAR_CS_PAR_CS5 (0x20) +#define MCF5235_GPIO_PAR_CS_PAR_CS6 (0x40) +#define MCF5235_GPIO_PAR_CS_PAR_CS7 (0x80) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SCKE (0x04) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SRAS (0x08) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SCAS (0x10) +#define MCF5235_GPIO_PAR_SDRAM_PAR_SDWE (0x20) +#define MCF5235_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) +#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) +#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) +#define MCF5235_GPIO_PAR_UART_PAR_U0RTS (0x0001) +#define MCF5235_GPIO_PAR_UART_PAR_U0CTS (0x0002) +#define MCF5235_GPIO_PAR_UART_PAR_U0TXD (0x0004) +#define MCF5235_GPIO_PAR_UART_PAR_U0RXD (0x0008) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_UART_PAR_U2TXD (0x1000) +#define MCF5235_GPIO_PAR_UART_PAR_U2RXD (0x2000) +#define MCF5235_GPIO_PAR_UART_PAR_CAN1EN (0x4000) +#define MCF5235_GPIO_PAR_UART_PAR_DREQ2 (0x8000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) +#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) +#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) +#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) +#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) +#define MCF5235_GPIO_PAR_QSPI_PAR_DOUT (0x04) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS0 (0x20) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) +#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) +#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) +#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) +#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) +#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) +#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) +#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) +#define MCF5235_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) +#define MCF5235_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) +#define MCF5235_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) +#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) +#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) +#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) +#define MCF5235_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) +#define MCF5235_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART0 (0x01) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART1 (0x04) +#define MCF5235_GPIO_DSCR_UART_DSCR_UART2 (0x10) +#define MCF5235_GPIO_DSCR_UART_DSCR_IRQ (0x40) +#define MCF5235_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)*/ +#define MCF5235_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_I2C_I2AR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000300))) +#define MCF5235_I2C_I2FDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000304))) +#define MCF5235_I2C_I2CR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000308))) +#define MCF5235_I2C_I2SR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00030C))) +#define MCF5235_I2C_I2DR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000310))) +#define MCF5235_I2C_I2ICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000320))) + +/* Bit definitions and macros for MCF5235_I2C_I2AR */ +#define MCF5235_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) +#define MCF5235_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) +#define MCF5235_I2C_I2CR_RSTA (0x04) +#define MCF5235_I2C_I2CR_TXAK (0x08) +#define MCF5235_I2C_I2CR_MTX (0x10) +#define MCF5235_I2C_I2CR_MSTA (0x20) +#define MCF5235_I2C_I2CR_IIEN (0x40) +#define MCF5235_I2C_I2CR_IEN (0x80) +#define MCF5235_I2C_I2SR_RXAK (0x01) +#define MCF5235_I2C_I2SR_IIF (0x02) +#define MCF5235_I2C_I2SR_SRW (0x04) +#define MCF5235_I2C_I2SR_IAL (0x10) +#define MCF5235_I2C_I2SR_IBB (0x20) +#define MCF5235_I2C_I2SR_IAAS (0x40) +#define MCF5235_I2C_I2SR_ICF (0x80) +#define MCF5235_I2C_I2ICR_IE (0x01) +#define MCF5235_I2C_I2ICR_RE (0x02) +#define MCF5235_I2C_I2ICR_TE (0x04) +#define MCF5235_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Interrupt Controller 0 (INTC0) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_INTC0_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C00))) +#define MCF5235_INTC0_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C04))) +#define MCF5235_INTC0_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C08))) +#define MCF5235_INTC0_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C0C))) +#define MCF5235_INTC0_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C10))) +#define MCF5235_INTC0_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C14))) +#define MCF5235_INTC0_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C18))) +#define MCF5235_INTC0_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C19))) +#define MCF5235_INTC0_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40))) +#define MCF5235_INTC0_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C41))) +#define MCF5235_INTC0_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C42))) +#define MCF5235_INTC0_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C43))) +#define MCF5235_INTC0_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C44))) +#define MCF5235_INTC0_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C45))) +#define MCF5235_INTC0_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C46))) +#define MCF5235_INTC0_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C47))) +#define MCF5235_INTC0_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C48))) +#define MCF5235_INTC0_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C49))) +#define MCF5235_INTC0_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4A))) +#define MCF5235_INTC0_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4B))) +#define MCF5235_INTC0_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4C))) +#define MCF5235_INTC0_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4D))) +#define MCF5235_INTC0_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4E))) +#define MCF5235_INTC0_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4F))) +#define MCF5235_INTC0_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C50))) +#define MCF5235_INTC0_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C51))) +#define MCF5235_INTC0_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C52))) +#define MCF5235_INTC0_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C53))) +#define MCF5235_INTC0_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C54))) +#define MCF5235_INTC0_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C55))) +#define MCF5235_INTC0_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C56))) +#define MCF5235_INTC0_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C57))) +#define MCF5235_INTC0_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C58))) +#define MCF5235_INTC0_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C59))) +#define MCF5235_INTC0_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5A))) +#define MCF5235_INTC0_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5B))) +#define MCF5235_INTC0_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5C))) +#define MCF5235_INTC0_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5D))) +#define MCF5235_INTC0_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5E))) +#define MCF5235_INTC0_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5F))) +#define MCF5235_INTC0_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C60))) +#define MCF5235_INTC0_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C61))) +#define MCF5235_INTC0_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C62))) +#define MCF5235_INTC0_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C63))) +#define MCF5235_INTC0_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C64))) +#define MCF5235_INTC0_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C65))) +#define MCF5235_INTC0_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C66))) +#define MCF5235_INTC0_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C67))) +#define MCF5235_INTC0_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C68))) +#define MCF5235_INTC0_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C69))) +#define MCF5235_INTC0_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6A))) +#define MCF5235_INTC0_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6B))) +#define MCF5235_INTC0_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6C))) +#define MCF5235_INTC0_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6D))) +#define MCF5235_INTC0_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6E))) +#define MCF5235_INTC0_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6F))) +#define MCF5235_INTC0_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C70))) +#define MCF5235_INTC0_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C71))) +#define MCF5235_INTC0_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C72))) +#define MCF5235_INTC0_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C73))) +#define MCF5235_INTC0_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C74))) +#define MCF5235_INTC0_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C75))) +#define MCF5235_INTC0_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C76))) +#define MCF5235_INTC0_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C77))) +#define MCF5235_INTC0_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C78))) +#define MCF5235_INTC0_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C79))) +#define MCF5235_INTC0_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7A))) +#define MCF5235_INTC0_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7B))) +#define MCF5235_INTC0_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7C))) +#define MCF5235_INTC0_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7D))) +#define MCF5235_INTC0_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7E))) +#define MCF5235_INTC0_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7F))) +#define MCF5235_INTC0_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40+((x)*0x001)))) +#define MCF5235_INTC0_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE0))) +#define MCF5235_INTC0_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4))) +#define MCF5235_INTC0_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE8))) +#define MCF5235_INTC0_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CEC))) +#define MCF5235_INTC0_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF0))) +#define MCF5235_INTC0_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF4))) +#define MCF5235_INTC0_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF8))) +#define MCF5235_INTC0_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CFC))) +#define MCF5235_INTC0_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4+((x)*0x004)))) +#define MCF5235_INTC1_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D00))) +#define MCF5235_INTC1_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D04))) +#define MCF5235_INTC1_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D08))) +#define MCF5235_INTC1_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D0C))) +#define MCF5235_INTC1_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D10))) +#define MCF5235_INTC1_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D14))) +#define MCF5235_INTC1_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D18))) +#define MCF5235_INTC1_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D19))) +#define MCF5235_INTC1_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40))) +#define MCF5235_INTC1_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D41))) +#define MCF5235_INTC1_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D42))) +#define MCF5235_INTC1_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D43))) +#define MCF5235_INTC1_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D44))) +#define MCF5235_INTC1_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D45))) +#define MCF5235_INTC1_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D46))) +#define MCF5235_INTC1_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D47))) +#define MCF5235_INTC1_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D48))) +#define MCF5235_INTC1_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D49))) +#define MCF5235_INTC1_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4A))) +#define MCF5235_INTC1_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4B))) +#define MCF5235_INTC1_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4C))) +#define MCF5235_INTC1_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4D))) +#define MCF5235_INTC1_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4E))) +#define MCF5235_INTC1_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4F))) +#define MCF5235_INTC1_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D50))) +#define MCF5235_INTC1_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D51))) +#define MCF5235_INTC1_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D52))) +#define MCF5235_INTC1_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D53))) +#define MCF5235_INTC1_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D54))) +#define MCF5235_INTC1_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D55))) +#define MCF5235_INTC1_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D56))) +#define MCF5235_INTC1_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D57))) +#define MCF5235_INTC1_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D58))) +#define MCF5235_INTC1_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D59))) +#define MCF5235_INTC1_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5A))) +#define MCF5235_INTC1_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5B))) +#define MCF5235_INTC1_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5C))) +#define MCF5235_INTC1_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5D))) +#define MCF5235_INTC1_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5E))) +#define MCF5235_INTC1_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5F))) +#define MCF5235_INTC1_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D60))) +#define MCF5235_INTC1_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D61))) +#define MCF5235_INTC1_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D62))) +#define MCF5235_INTC1_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D63))) +#define MCF5235_INTC1_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D64))) +#define MCF5235_INTC1_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D65))) +#define MCF5235_INTC1_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D66))) +#define MCF5235_INTC1_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D67))) +#define MCF5235_INTC1_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D68))) +#define MCF5235_INTC1_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D69))) +#define MCF5235_INTC1_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6A))) +#define MCF5235_INTC1_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6B))) +#define MCF5235_INTC1_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6C))) +#define MCF5235_INTC1_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6D))) +#define MCF5235_INTC1_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6E))) +#define MCF5235_INTC1_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6F))) +#define MCF5235_INTC1_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D70))) +#define MCF5235_INTC1_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D71))) +#define MCF5235_INTC1_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D72))) +#define MCF5235_INTC1_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D73))) +#define MCF5235_INTC1_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D74))) +#define MCF5235_INTC1_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D75))) +#define MCF5235_INTC1_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D76))) +#define MCF5235_INTC1_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D77))) +#define MCF5235_INTC1_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D78))) +#define MCF5235_INTC1_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D79))) +#define MCF5235_INTC1_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7A))) +#define MCF5235_INTC1_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7B))) +#define MCF5235_INTC1_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7C))) +#define MCF5235_INTC1_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7D))) +#define MCF5235_INTC1_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7E))) +#define MCF5235_INTC1_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7F))) +#define MCF5235_INTC1_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40+((x)*0x001)))) +#define MCF5235_INTC1_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE0))) +#define MCF5235_INTC1_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4))) +#define MCF5235_INTC1_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE8))) +#define MCF5235_INTC1_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DEC))) +#define MCF5235_INTC1_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF0))) +#define MCF5235_INTC1_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF4))) +#define MCF5235_INTC1_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF8))) +#define MCF5235_INTC1_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DFC))) +#define MCF5235_INTC1_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4+((x)*0x004)))) + +/* Bit definitions and macros for MCF5235_INTC0_IPRH */ +#define MCF5235_INTC0_IPRH_INT32 (0x00000001) +#define MCF5235_INTC0_IPRH_INT33 (0x00000002) +#define MCF5235_INTC0_IPRH_INT34 (0x00000004) +#define MCF5235_INTC0_IPRH_INT35 (0x00000008) +#define MCF5235_INTC0_IPRH_INT36 (0x00000010) +#define MCF5235_INTC0_IPRH_INT37 (0x00000020) +#define MCF5235_INTC0_IPRH_INT38 (0x00000040) +#define MCF5235_INTC0_IPRH_INT39 (0x00000080) +#define MCF5235_INTC0_IPRH_INT40 (0x00000100) +#define MCF5235_INTC0_IPRH_INT41 (0x00000200) +#define MCF5235_INTC0_IPRH_INT42 (0x00000400) +#define MCF5235_INTC0_IPRH_INT43 (0x00000800) +#define MCF5235_INTC0_IPRH_INT44 (0x00001000) +#define MCF5235_INTC0_IPRH_INT45 (0x00002000) +#define MCF5235_INTC0_IPRH_INT46 (0x00004000) +#define MCF5235_INTC0_IPRH_INT47 (0x00008000) +#define MCF5235_INTC0_IPRH_INT48 (0x00010000) +#define MCF5235_INTC0_IPRH_INT49 (0x00020000) +#define MCF5235_INTC0_IPRH_INT50 (0x00040000) +#define MCF5235_INTC0_IPRH_INT51 (0x00080000) +#define MCF5235_INTC0_IPRH_INT52 (0x00100000) +#define MCF5235_INTC0_IPRH_INT53 (0x00200000) +#define MCF5235_INTC0_IPRH_INT54 (0x00400000) +#define MCF5235_INTC0_IPRH_INT55 (0x00800000) +#define MCF5235_INTC0_IPRH_INT56 (0x01000000) +#define MCF5235_INTC0_IPRH_INT57 (0x02000000) +#define MCF5235_INTC0_IPRH_INT58 (0x04000000) +#define MCF5235_INTC0_IPRH_INT59 (0x08000000) +#define MCF5235_INTC0_IPRH_INT60 (0x10000000) +#define MCF5235_INTC0_IPRH_INT61 (0x20000000) +#define MCF5235_INTC0_IPRH_INT62 (0x40000000) +#define MCF5235_INTC0_IPRH_INT63 (0x80000000) +#define MCF5235_INTC0_IPRL_INT1 (0x00000002) +#define MCF5235_INTC0_IPRL_INT2 (0x00000004) +#define MCF5235_INTC0_IPRL_INT3 (0x00000008) +#define MCF5235_INTC0_IPRL_INT4 (0x00000010) +#define MCF5235_INTC0_IPRL_INT5 (0x00000020) +#define MCF5235_INTC0_IPRL_INT6 (0x00000040) +#define MCF5235_INTC0_IPRL_INT7 (0x00000080) +#define MCF5235_INTC0_IPRL_INT8 (0x00000100) +#define MCF5235_INTC0_IPRL_INT9 (0x00000200) +#define MCF5235_INTC0_IPRL_INT10 (0x00000400) +#define MCF5235_INTC0_IPRL_INT11 (0x00000800) +#define MCF5235_INTC0_IPRL_INT12 (0x00001000) +#define MCF5235_INTC0_IPRL_INT13 (0x00002000) +#define MCF5235_INTC0_IPRL_INT14 (0x00004000) +#define MCF5235_INTC0_IPRL_INT15 (0x00008000) +#define MCF5235_INTC0_IPRL_INT16 (0x00010000) +#define MCF5235_INTC0_IPRL_INT17 (0x00020000) +#define MCF5235_INTC0_IPRL_INT18 (0x00040000) +#define MCF5235_INTC0_IPRL_INT19 (0x00080000) +#define MCF5235_INTC0_IPRL_INT20 (0x00100000) +#define MCF5235_INTC0_IPRL_INT21 (0x00200000) +#define MCF5235_INTC0_IPRL_INT22 (0x00400000) +#define MCF5235_INTC0_IPRL_INT23 (0x00800000) +#define MCF5235_INTC0_IPRL_INT24 (0x01000000) +#define MCF5235_INTC0_IPRL_INT25 (0x02000000) +#define MCF5235_INTC0_IPRL_INT26 (0x04000000) +#define MCF5235_INTC0_IPRL_INT27 (0x08000000) +#define MCF5235_INTC0_IPRL_INT28 (0x10000000) +#define MCF5235_INTC0_IPRL_INT29 (0x20000000) +#define MCF5235_INTC0_IPRL_INT30 (0x40000000) +#define MCF5235_INTC0_IPRL_INT31 (0x80000000) +#define MCF5235_INTC0_IMRH_INT32 (0x00000001) +#define MCF5235_INTC0_IMRH_INT33 (0x00000002) +#define MCF5235_INTC0_IMRH_INT34 (0x00000004) +#define MCF5235_INTC0_IMRH_INT35 (0x00000008) +#define MCF5235_INTC0_IMRH_INT36 (0x00000010) +#define MCF5235_INTC0_IMRH_INT37 (0x00000020) +#define MCF5235_INTC0_IMRH_INT38 (0x00000040) +#define MCF5235_INTC0_IMRH_INT39 (0x00000080) +#define MCF5235_INTC0_IMRH_INT40 (0x00000100) +#define MCF5235_INTC0_IMRH_INT41 (0x00000200) +#define MCF5235_INTC0_IMRH_INT42 (0x00000400) +#define MCF5235_INTC0_IMRH_INT43 (0x00000800) +#define MCF5235_INTC0_IMRH_INT44 (0x00001000) +#define MCF5235_INTC0_IMRH_INT45 (0x00002000) +#define MCF5235_INTC0_IMRH_INT46 (0x00004000) +#define MCF5235_INTC0_IMRH_INT47 (0x00008000) +#define MCF5235_INTC0_IMRH_INT48 (0x00010000) +#define MCF5235_INTC0_IMRH_INT49 (0x00020000) +#define MCF5235_INTC0_IMRH_INT50 (0x00040000) +#define MCF5235_INTC0_IMRH_INT51 (0x00080000) +#define MCF5235_INTC0_IMRH_INT52 (0x00100000) +#define MCF5235_INTC0_IMRH_INT53 (0x00200000) +#define MCF5235_INTC0_IMRH_INT54 (0x00400000) +#define MCF5235_INTC0_IMRH_INT55 (0x00800000) +#define MCF5235_INTC0_IMRH_INT56 (0x01000000) +#define MCF5235_INTC0_IMRH_INT57 (0x02000000) +#define MCF5235_INTC0_IMRH_INT58 (0x04000000) +#define MCF5235_INTC0_IMRH_INT59 (0x08000000) +#define MCF5235_INTC0_IMRH_INT60 (0x10000000) +#define MCF5235_INTC0_IMRH_INT61 (0x20000000) +#define MCF5235_INTC0_IMRH_INT62 (0x40000000) +#define MCF5235_INTC0_IMRH_INT63 (0x80000000) +#define MCF5235_INTC0_IMRL_MASKALL (0x00000001) +#define MCF5235_INTC0_IMRL_INT1 (0x00000002) +#define MCF5235_INTC0_IMRL_INT2 (0x00000004) +#define MCF5235_INTC0_IMRL_INT3 (0x00000008) +#define MCF5235_INTC0_IMRL_INT4 (0x00000010) +#define MCF5235_INTC0_IMRL_INT5 (0x00000020) +#define MCF5235_INTC0_IMRL_INT6 (0x00000040) +#define MCF5235_INTC0_IMRL_INT7 (0x00000080) +#define MCF5235_INTC0_IMRL_INT8 (0x00000100) +#define MCF5235_INTC0_IMRL_INT9 (0x00000200) +#define MCF5235_INTC0_IMRL_INT10 (0x00000400) +#define MCF5235_INTC0_IMRL_INT11 (0x00000800) +#define MCF5235_INTC0_IMRL_INT12 (0x00001000) +#define MCF5235_INTC0_IMRL_INT13 (0x00002000) +#define MCF5235_INTC0_IMRL_INT14 (0x00004000) +#define MCF5235_INTC0_IMRL_INT15 (0x00008000) +#define MCF5235_INTC0_IMRL_INT16 (0x00010000) +#define MCF5235_INTC0_IMRL_INT17 (0x00020000) +#define MCF5235_INTC0_IMRL_INT18 (0x00040000) +#define MCF5235_INTC0_IMRL_INT19 (0x00080000) +#define MCF5235_INTC0_IMRL_INT20 (0x00100000) +#define MCF5235_INTC0_IMRL_INT21 (0x00200000) +#define MCF5235_INTC0_IMRL_INT22 (0x00400000) +#define MCF5235_INTC0_IMRL_INT23 (0x00800000) +#define MCF5235_INTC0_IMRL_INT24 (0x01000000) +#define MCF5235_INTC0_IMRL_INT25 (0x02000000) +#define MCF5235_INTC0_IMRL_INT26 (0x04000000) +#define MCF5235_INTC0_IMRL_INT27 (0x08000000) +#define MCF5235_INTC0_IMRL_INT28 (0x10000000) +#define MCF5235_INTC0_IMRL_INT29 (0x20000000) +#define MCF5235_INTC0_IMRL_INT30 (0x40000000) +#define MCF5235_INTC0_IMRL_INT31 (0x80000000) +#define MCF5235_INTC0_INTFRCH_INTFRC32 (0x00000001) +#define MCF5235_INTC0_INTFRCH_INTFRC33 (0x00000002) +#define MCF5235_INTC0_INTFRCH_INTFRC34 (0x00000004) +#define MCF5235_INTC0_INTFRCH_INTFRC35 (0x00000008) +#define MCF5235_INTC0_INTFRCH_INTFRC36 (0x00000010) +#define MCF5235_INTC0_INTFRCH_INTFRC37 (0x00000020) +#define MCF5235_INTC0_INTFRCH_INTFRC38 (0x00000040) +#define MCF5235_INTC0_INTFRCH_INTFRC39 (0x00000080) +#define MCF5235_INTC0_INTFRCH_INTFRC40 (0x00000100) +#define MCF5235_INTC0_INTFRCH_INTFRC41 (0x00000200) +#define MCF5235_INTC0_INTFRCH_INTFRC42 (0x00000400) +#define MCF5235_INTC0_INTFRCH_INTFRC43 (0x00000800) +#define MCF5235_INTC0_INTFRCH_INTFRC44 (0x00001000) +#define MCF5235_INTC0_INTFRCH_INTFRC45 (0x00002000) +#define MCF5235_INTC0_INTFRCH_INTFRC46 (0x00004000) +#define MCF5235_INTC0_INTFRCH_INTFRC47 (0x00008000) +#define MCF5235_INTC0_INTFRCH_INTFRC48 (0x00010000) +#define MCF5235_INTC0_INTFRCH_INTFRC49 (0x00020000) +#define MCF5235_INTC0_INTFRCH_INTFRC50 (0x00040000) +#define MCF5235_INTC0_INTFRCH_INTFRC51 (0x00080000) +#define MCF5235_INTC0_INTFRCH_INTFRC52 (0x00100000) +#define MCF5235_INTC0_INTFRCH_INTFRC53 (0x00200000) +#define MCF5235_INTC0_INTFRCH_INTFRC54 (0x00400000) +#define MCF5235_INTC0_INTFRCH_INTFRC55 (0x00800000) +#define MCF5235_INTC0_INTFRCH_INTFRC56 (0x01000000) +#define MCF5235_INTC0_INTFRCH_INTFRC57 (0x02000000) +#define MCF5235_INTC0_INTFRCH_INTFRC58 (0x04000000) +#define MCF5235_INTC0_INTFRCH_INTFRC59 (0x08000000) +#define MCF5235_INTC0_INTFRCH_INTFRC60 (0x10000000) +#define MCF5235_INTC0_INTFRCH_INTFRC61 (0x20000000) +#define MCF5235_INTC0_INTFRCH_INTFRC62 (0x40000000) +#define MCF5235_INTC0_INTFRCH_INTFRC63 (0x80000000) +#define MCF5235_INTC0_INTFRCL_INTFRC1 (0x00000002) +#define MCF5235_INTC0_INTFRCL_INTFRC2 (0x00000004) +#define MCF5235_INTC0_INTFRCL_INTFRC3 (0x00000008) +#define MCF5235_INTC0_INTFRCL_INTFRC4 (0x00000010) +#define MCF5235_INTC0_INTFRCL_INTFRC5 (0x00000020) +#define MCF5235_INTC0_INTFRCL_INT6 (0x00000040) +#define MCF5235_INTC0_INTFRCL_INT7 (0x00000080) +#define MCF5235_INTC0_INTFRCL_INT8 (0x00000100) +#define MCF5235_INTC0_INTFRCL_INT9 (0x00000200) +#define MCF5235_INTC0_INTFRCL_INT10 (0x00000400) +#define MCF5235_INTC0_INTFRCL_INTFRC11 (0x00000800) +#define MCF5235_INTC0_INTFRCL_INTFRC12 (0x00001000) +#define MCF5235_INTC0_INTFRCL_INTFRC13 (0x00002000) +#define MCF5235_INTC0_INTFRCL_INTFRC14 (0x00004000) +#define MCF5235_INTC0_INTFRCL_INT15 (0x00008000) +#define MCF5235_INTC0_INTFRCL_INTFRC16 (0x00010000) +#define MCF5235_INTC0_INTFRCL_INTFRC17 (0x00020000) +#define MCF5235_INTC0_INTFRCL_INTFRC18 (0x00040000) +#define MCF5235_INTC0_INTFRCL_INTFRC19 (0x00080000) +#define MCF5235_INTC0_INTFRCL_INTFRC20 (0x00100000) +#define MCF5235_INTC0_INTFRCL_INTFRC21 (0x00200000) +#define MCF5235_INTC0_INTFRCL_INTFRC22 (0x00400000) +#define MCF5235_INTC0_INTFRCL_INTFRC23 (0x00800000) +#define MCF5235_INTC0_INTFRCL_INTFRC24 (0x01000000) +#define MCF5235_INTC0_INTFRCL_INTFRC25 (0x02000000) +#define MCF5235_INTC0_INTFRCL_INTFRC26 (0x04000000) +#define MCF5235_INTC0_INTFRCL_INTFRC27 (0x08000000) +#define MCF5235_INTC0_INTFRCL_INTFRC28 (0x10000000) +#define MCF5235_INTC0_INTFRCL_INTFRC29 (0x20000000) +#define MCF5235_INTC0_INTFRCL_INTFRC30 (0x40000000) +#define MCF5235_INTC0_INTFRCL_INTFRC31 (0x80000000) +#define MCF5235_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) +#define MCF5235_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF5235_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) +#define MCF5235_INTC_ICR_IP(x) (((x)&0x07)<<0) +#define MCF5235_INTC_ICR_IL(x) (((x)&0x07)<<3) +#define MCF5235_INTC1_IPRH_INT32 (0x00000001) +#define MCF5235_INTC1_IPRH_INT33 (0x00000002) +#define MCF5235_INTC1_IPRH_INT34 (0x00000004) +#define MCF5235_INTC1_IPRH_INT35 (0x00000008) +#define MCF5235_INTC1_IPRH_INT36 (0x00000010) +#define MCF5235_INTC1_IPRH_INT37 (0x00000020) +#define MCF5235_INTC1_IPRH_INT38 (0x00000040) +#define MCF5235_INTC1_IPRH_INT39 (0x00000080) +#define MCF5235_INTC1_IPRH_INT40 (0x00000100) +#define MCF5235_INTC1_IPRH_INT41 (0x00000200) +#define MCF5235_INTC1_IPRH_INT42 (0x00000400) +#define MCF5235_INTC1_IPRH_INT43 (0x00000800) +#define MCF5235_INTC1_IPRH_INT44 (0x00001000) +#define MCF5235_INTC1_IPRH_INT45 (0x00002000) +#define MCF5235_INTC1_IPRH_INT46 (0x00004000) +#define MCF5235_INTC1_IPRH_INT47 (0x00008000) +#define MCF5235_INTC1_IPRH_INT48 (0x00010000) +#define MCF5235_INTC1_IPRH_INT49 (0x00020000) +#define MCF5235_INTC1_IPRH_INT50 (0x00040000) +#define MCF5235_INTC1_IPRH_INT51 (0x00080000) +#define MCF5235_INTC1_IPRH_INT52 (0x00100000) +#define MCF5235_INTC1_IPRH_INT53 (0x00200000) +#define MCF5235_INTC1_IPRH_INT54 (0x00400000) +#define MCF5235_INTC1_IPRH_INT55 (0x00800000) +#define MCF5235_INTC1_IPRH_INT56 (0x01000000) +#define MCF5235_INTC1_IPRH_INT57 (0x02000000) +#define MCF5235_INTC1_IPRH_INT58 (0x04000000) +#define MCF5235_INTC1_IPRH_INT59 (0x08000000) +#define MCF5235_INTC1_IPRH_INT60 (0x10000000) +#define MCF5235_INTC1_IPRH_INT61 (0x20000000) +#define MCF5235_INTC1_IPRH_INT62 (0x40000000) +#define MCF5235_INTC1_IPRH_INT63 (0x80000000) +#define MCF5235_INTC1_IPRL_INT1 (0x00000002) +#define MCF5235_INTC1_IPRL_INT2 (0x00000004) +#define MCF5235_INTC1_IPRL_INT3 (0x00000008) +#define MCF5235_INTC1_IPRL_INT4 (0x00000010) +#define MCF5235_INTC1_IPRL_INT5 (0x00000020) +#define MCF5235_INTC1_IPRL_INT6 (0x00000040) +#define MCF5235_INTC1_IPRL_INT7 (0x00000080) +#define MCF5235_INTC1_IPRL_INT8 (0x00000100) +#define MCF5235_INTC1_IPRL_INT9 (0x00000200) +#define MCF5235_INTC1_IPRL_INT10 (0x00000400) +#define MCF5235_INTC1_IPRL_INT11 (0x00000800) +#define MCF5235_INTC1_IPRL_INT12 (0x00001000) +#define MCF5235_INTC1_IPRL_INT13 (0x00002000) +#define MCF5235_INTC1_IPRL_INT14 (0x00004000) +#define MCF5235_INTC1_IPRL_INT15 (0x00008000) +#define MCF5235_INTC1_IPRL_INT16 (0x00010000) +#define MCF5235_INTC1_IPRL_INT17 (0x00020000) +#define MCF5235_INTC1_IPRL_INT18 (0x00040000) +#define MCF5235_INTC1_IPRL_INT19 (0x00080000) +#define MCF5235_INTC1_IPRL_INT20 (0x00100000) +#define MCF5235_INTC1_IPRL_INT21 (0x00200000) +#define MCF5235_INTC1_IPRL_INT22 (0x00400000) +#define MCF5235_INTC1_IPRL_INT23 (0x00800000) +#define MCF5235_INTC1_IPRL_INT24 (0x01000000) +#define MCF5235_INTC1_IPRL_INT25 (0x02000000) +#define MCF5235_INTC1_IPRL_INT26 (0x04000000) +#define MCF5235_INTC1_IPRL_INT27 (0x08000000) +#define MCF5235_INTC1_IPRL_INT28 (0x10000000) +#define MCF5235_INTC1_IPRL_INT29 (0x20000000) +#define MCF5235_INTC1_IPRL_INT30 (0x40000000) +#define MCF5235_INTC1_IPRL_INT31 (0x80000000) +#define MCF5235_INTC1_IMRH_INT_MASK32 (0x00000001) +#define MCF5235_INTC1_IMRH_INT_MASK33 (0x00000002) +#define MCF5235_INTC1_IMRH_INT_MASK34 (0x00000004) +#define MCF5235_INTC1_IMRH_INT_MASK35 (0x00000008) +#define MCF5235_INTC1_IMRH_INT_MASK36 (0x00000010) +#define MCF5235_INTC1_IMRH_INT_MASK37 (0x00000020) +#define MCF5235_INTC1_IMRH_INT_MASK38 (0x00000040) +#define MCF5235_INTC1_IMRH_INT_MASK39 (0x00000080) +#define MCF5235_INTC1_IMRH_INT_MASK40 (0x00000100) +#define MCF5235_INTC1_IMRH_INT_MASK41 (0x00000200) +#define MCF5235_INTC1_IMRH_INT_MASK42 (0x00000400) +#define MCF5235_INTC1_IMRH_INT_MASK43 (0x00000800) +#define MCF5235_INTC1_IMRH_INT_MASK44 (0x00001000) +#define MCF5235_INTC1_IMRH_INT_MASK45 (0x00002000) +#define MCF5235_INTC1_IMRH_INT_MASK46 (0x00004000) +#define MCF5235_INTC1_IMRH_INT_MASK47 (0x00008000) +#define MCF5235_INTC1_IMRH_INT_MASK48 (0x00010000) +#define MCF5235_INTC1_IMRH_INT_MASK49 (0x00020000) +#define MCF5235_INTC1_IMRH_INT_MASK50 (0x00040000) +#define MCF5235_INTC1_IMRH_INT_MASK51 (0x00080000) +#define MCF5235_INTC1_IMRH_INT_MASK52 (0x00100000) +#define MCF5235_INTC1_IMRH_INT_MASK53 (0x00200000) +#define MCF5235_INTC1_IMRH_INT_MASK54 (0x00400000) +#define MCF5235_INTC1_IMRH_INT_MASK55 (0x00800000) +#define MCF5235_INTC1_IMRH_INT_MASK56 (0x01000000) +#define MCF5235_INTC1_IMRH_INT_MASK57 (0x02000000) +#define MCF5235_INTC1_IMRH_INT_MASK58 (0x04000000) +#define MCF5235_INTC1_IMRH_INT_MASK59 (0x08000000) +#define MCF5235_INTC1_IMRH_INT_MASK60 (0x10000000) +#define MCF5235_INTC1_IMRH_INT_MASK61 (0x20000000) +#define MCF5235_INTC1_IMRH_INT_MASK62 (0x40000000) +#define MCF5235_INTC1_IMRH_INT_MASK63 (0x80000000) +#define MCF5235_INTC1_IMRL_MASKALL (0x00000001) +#define MCF5235_INTC1_IMRL_INT_MASK1 (0x00000002) +#define MCF5235_INTC1_IMRL_INT_MASK2 (0x00000004) +#define MCF5235_INTC1_IMRL_INT_MASK3 (0x00000008) +#define MCF5235_INTC1_IMRL_INT_MASK4 (0x00000010) +#define MCF5235_INTC1_IMRL_INT_MASK5 (0x00000020) +#define MCF5235_INTC1_IMRL_INT_MASK6 (0x00000040) +#define MCF5235_INTC1_IMRL_INT_MASK7 (0x00000080) +#define MCF5235_INTC1_IMRL_INT_MASK8 (0x00000100) +#define MCF5235_INTC1_IMRL_INT_MASK9 (0x00000200) +#define MCF5235_INTC1_IMRL_INT_MASK10 (0x00000400) +#define MCF5235_INTC1_IMRL_INT_MASK11 (0x00000800) +#define MCF5235_INTC1_IMRL_INT_MASK12 (0x00001000) +#define MCF5235_INTC1_IMRL_INT_MASK13 (0x00002000) +#define MCF5235_INTC1_IMRL_INT_MASK14 (0x00004000) +#define MCF5235_INTC1_IMRL_INT_MASK15 (0x00008000) +#define MCF5235_INTC1_IMRL_INT_MASK16 (0x00010000) +#define MCF5235_INTC1_IMRL_INT_MASK17 (0x00020000) +#define MCF5235_INTC1_IMRL_INT_MASK18 (0x00040000) +#define MCF5235_INTC1_IMRL_INT_MASK19 (0x00080000) +#define MCF5235_INTC1_IMRL_INT_MASK20 (0x00100000) +#define MCF5235_INTC1_IMRL_INT_MASK21 (0x00200000) +#define MCF5235_INTC1_IMRL_INT_MASK22 (0x00400000) +#define MCF5235_INTC1_IMRL_INT_MASK23 (0x00800000) +#define MCF5235_INTC1_IMRL_INT_MASK24 (0x01000000) +#define MCF5235_INTC1_IMRL_INT_MASK25 (0x02000000) +#define MCF5235_INTC1_IMRL_INT_MASK26 (0x04000000) +#define MCF5235_INTC1_IMRL_INT_MASK27 (0x08000000) +#define MCF5235_INTC1_IMRL_INT_MASK28 (0x10000000) +#define MCF5235_INTC1_IMRL_INT_MASK29 (0x20000000) +#define MCF5235_INTC1_IMRL_INT_MASK30 (0x40000000) +#define MCF5235_INTC1_IMRL_INT_MASK31 (0x80000000) +#define MCF5235_INTC1_INTFRCH_INTFRC32 (0x00000001) +#define MCF5235_INTC1_INTFRCH_INTFRC33 (0x00000002) +#define MCF5235_INTC1_INTFRCH_INTFRC34 (0x00000004) +#define MCF5235_INTC1_INTFRCH_INTFRC35 (0x00000008) +#define MCF5235_INTC1_INTFRCH_INTFRC36 (0x00000010) +#define MCF5235_INTC1_INTFRCH_INTFRC37 (0x00000020) +#define MCF5235_INTC1_INTFRCH_INTFRC38 (0x00000040) +#define MCF5235_INTC1_INTFRCH_INTFRC39 (0x00000080) +#define MCF5235_INTC1_INTFRCH_INTFRC40 (0x00000100) +#define MCF5235_INTC1_INTFRCH_INTFRC41 (0x00000200) +#define MCF5235_INTC1_INTFRCH_INTFRC42 (0x00000400) +#define MCF5235_INTC1_INTFRCH_INTFRC43 (0x00000800) +#define MCF5235_INTC1_INTFRCH_INTFRC44 (0x00001000) +#define MCF5235_INTC1_INTFRCH_INTFRC45 (0x00002000) +#define MCF5235_INTC1_INTFRCH_INTFRC46 (0x00004000) +#define MCF5235_INTC1_INTFRCH_INTFRC47 (0x00008000) +#define MCF5235_INTC1_INTFRCH_INTFRC48 (0x00010000) +#define MCF5235_INTC1_INTFRCH_INTFRC49 (0x00020000) +#define MCF5235_INTC1_INTFRCH_INTFRC50 (0x00040000) +#define MCF5235_INTC1_INTFRCH_INTFRC51 (0x00080000) +#define MCF5235_INTC1_INTFRCH_INTFRC52 (0x00100000) +#define MCF5235_INTC1_INTFRCH_INTFRC53 (0x00200000) +#define MCF5235_INTC1_INTFRCH_INTFRC54 (0x00400000) +#define MCF5235_INTC1_INTFRCH_INTFRC55 (0x00800000) +#define MCF5235_INTC1_INTFRCH_INTFRC56 (0x01000000) +#define MCF5235_INTC1_INTFRCH_INTFRC57 (0x02000000) +#define MCF5235_INTC1_INTFRCH_INTFRC58 (0x04000000) +#define MCF5235_INTC1_INTFRCH_INTFRC59 (0x08000000) +#define MCF5235_INTC1_INTFRCH_INTFRC60 (0x10000000) +#define MCF5235_INTC1_INTFRCH_INTFRC61 (0x20000000) +#define MCF5235_INTC1_INTFRCH_INTFRC62 (0x40000000) +#define MCF5235_INTC1_INTFRCH_INTFRC63 (0x80000000) +#define MCF5235_INTC1_INTFRCL_INTFRC1 (0x00000002) +#define MCF5235_INTC1_INTFRCL_INTFRC2 (0x00000004) +#define MCF5235_INTC1_INTFRCL_INTFRC3 (0x00000008) +#define MCF5235_INTC1_INTFRCL_INTFRC4 (0x00000010) +#define MCF5235_INTC1_INTFRCL_INTFRC5 (0x00000020) +#define MCF5235_INTC1_INTFRCL_INT6 (0x00000040) +#define MCF5235_INTC1_INTFRCL_INT7 (0x00000080) +#define MCF5235_INTC1_INTFRCL_INT8 (0x00000100) +#define MCF5235_INTC1_INTFRCL_INT9 (0x00000200) +#define MCF5235_INTC1_INTFRCL_INT10 (0x00000400) +#define MCF5235_INTC1_INTFRCL_INTFRC11 (0x00000800) +#define MCF5235_INTC1_INTFRCL_INTFRC12 (0x00001000) +#define MCF5235_INTC1_INTFRCL_INTFRC13 (0x00002000) +#define MCF5235_INTC1_INTFRCL_INTFRC14 (0x00004000) +#define MCF5235_INTC1_INTFRCL_INT15 (0x00008000) +#define MCF5235_INTC1_INTFRCL_INTFRC16 (0x00010000) +#define MCF5235_INTC1_INTFRCL_INTFRC17 (0x00020000) +#define MCF5235_INTC1_INTFRCL_INTFRC18 (0x00040000) +#define MCF5235_INTC1_INTFRCL_INTFRC19 (0x00080000) +#define MCF5235_INTC1_INTFRCL_INTFRC20 (0x00100000) +#define MCF5235_INTC1_INTFRCL_INTFRC21 (0x00200000) +#define MCF5235_INTC1_INTFRCL_INTFRC22 (0x00400000) +#define MCF5235_INTC1_INTFRCL_INTFRC23 (0x00800000) +#define MCF5235_INTC1_INTFRCL_INTFRC24 (0x01000000) +#define MCF5235_INTC1_INTFRCL_INTFRC25 (0x02000000) +#define MCF5235_INTC1_INTFRCL_INTFRC26 (0x04000000) +#define MCF5235_INTC1_INTFRCL_INTFRC27 (0x08000000) +#define MCF5235_INTC1_INTFRCL_INTFRC28 (0x10000000) +#define MCF5235_INTC1_INTFRCL_INTFRC29 (0x20000000) +#define MCF5235_INTC1_INTFRCL_INTFRC30 (0x40000000) +#define MCF5235_INTC1_INTFRCL_INTFRC31 (0x80000000) +#define MCF5235_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) +#define MCF5235_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF5235_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_PIT_PCSR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000))) +#define MCF5235_PIT_PMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002))) +#define MCF5235_PIT_PCNTR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004))) +#define MCF5235_PIT_PCSR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160000))) +#define MCF5235_PIT_PMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160002))) +#define MCF5235_PIT_PCNTR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160004))) +#define MCF5235_PIT_PCSR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170000))) +#define MCF5235_PIT_PMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170002))) +#define MCF5235_PIT_PCNTR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170004))) +#define MCF5235_PIT_PCSR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180000))) +#define MCF5235_PIT_PMR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180002))) +#define MCF5235_PIT_PCNTR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180004))) +#define MCF5235_PIT_PCSR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000+((x)*0x10000)))) +#define MCF5235_PIT_PMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002+((x)*0x10000)))) +#define MCF5235_PIT_PCNTR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004+((x)*0x10000)))) +#define MCF5235_PIT_PCSR_EN (0x0001) +#define MCF5235_PIT_PCSR_RLD (0x0002) +#define MCF5235_PIT_PCSR_PIF (0x0004) +#define MCF5235_PIT_PCSR_PIE (0x0008) +#define MCF5235_PIT_PCSR_OVW (0x0010) +#define MCF5235_PIT_PCSR_HALTED (0x0020) +#define MCF5235_PIT_PCSR_DOZE (0x0040) +#define MCF5235_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) +#define MCF5235_PIT_PMR_PM0 (0x0001) +#define MCF5235_PIT_PMR_PM1 (0x0002) +#define MCF5235_PIT_PMR_PM2 (0x0004) +#define MCF5235_PIT_PMR_PM3 (0x0008) +#define MCF5235_PIT_PMR_PM4 (0x0010) +#define MCF5235_PIT_PMR_PM5 (0x0020) +#define MCF5235_PIT_PMR_PM6 (0x0040) +#define MCF5235_PIT_PMR_PM7 (0x0080) +#define MCF5235_PIT_PMR_PM8 (0x0100) +#define MCF5235_PIT_PMR_PM9 (0x0200) +#define MCF5235_PIT_PMR_PM10 (0x0400) +#define MCF5235_PIT_PMR_PM11 (0x0800) +#define MCF5235_PIT_PMR_PM12 (0x1000) +#define MCF5235_PIT_PMR_PM13 (0x2000) +#define MCF5235_PIT_PMR_PM14 (0x4000) +#define MCF5235_PIT_PMR_PM15 (0x8000) +#define MCF5235_PIT_PCNTR_PC0 (0x0001) +#define MCF5235_PIT_PCNTR_PC1 (0x0002) +#define MCF5235_PIT_PCNTR_PC2 (0x0004) +#define MCF5235_PIT_PCNTR_PC3 (0x0008) +#define MCF5235_PIT_PCNTR_PC4 (0x0010) +#define MCF5235_PIT_PCNTR_PC5 (0x0020) +#define MCF5235_PIT_PCNTR_PC6 (0x0040) +#define MCF5235_PIT_PCNTR_PC7 (0x0080) +#define MCF5235_PIT_PCNTR_PC8 (0x0100) +#define MCF5235_PIT_PCNTR_PC9 (0x0200) +#define MCF5235_PIT_PCNTR_PC10 (0x0400) +#define MCF5235_PIT_PCNTR_PC11 (0x0800) +#define MCF5235_PIT_PCNTR_PC12 (0x1000) +#define MCF5235_PIT_PCNTR_PC13 (0x2000) +#define MCF5235_PIT_PCNTR_PC14 (0x4000) +#define MCF5235_PIT_PCNTR_PC15 (0x8000) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF5235_QSPI_QMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000340))) +#define MCF5235_QSPI_QDLYR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000344))) +#define MCF5235_QSPI_QWR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000348))) +#define MCF5235_QSPI_QIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x00034C))) +#define MCF5235_QSPI_QAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000350))) +#define MCF5235_QSPI_QDR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000354))) + +/* Bit definitions and macros for MCF5235_QSPI_QMR */ +#define MCF5235_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF5235_QSPI_QMR_CPHA (0x0100) +#define MCF5235_QSPI_QMR_CPOL (0x0200) +#define MCF5235_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF5235_QSPI_QMR_DOHIE (0x4000) +#define MCF5235_QSPI_QMR_MSTR (0x8000) +#define MCF5235_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF5235_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5235_QSPI_QDLYR_SPE (0x8000) +#define MCF5235_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF5235_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5235_QSPI_QWR_CSIV (0x1000) +#define MCF5235_QSPI_QWR_WRTO (0x2000) +#define MCF5235_QSPI_QWR_WREN (0x4000) +#define MCF5235_QSPI_QWR_HALT (0x8000) +#define MCF5235_QSPI_QIR_SPIF (0x0001) +#define MCF5235_QSPI_QIR_ABRT (0x0004) +#define MCF5235_QSPI_QIR_WCEF (0x0008) +#define MCF5235_QSPI_QIR_SPIFE (0x0100) +#define MCF5235_QSPI_QIR_ABRTE (0x0400) +#define MCF5235_QSPI_QIR_WCEFE (0x0800) +#define MCF5235_QSPI_QIR_ABRTL (0x1000) +#define MCF5235_QSPI_QIR_ABRTB (0x4000) +#define MCF5235_QSPI_QIR_WCEFB (0x8000) +#define MCF5235_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/********************************************************************/ + + +#endif /* _CPU_MCF5235_H */ diff --git a/bsps/m68k/include/mcf5272/mcf5272.h b/bsps/m68k/include/mcf5272/mcf5272.h new file mode 100644 index 0000000000..37dae92d98 --- /dev/null +++ b/bsps/m68k/include/mcf5272/mcf5272.h @@ -0,0 +1,699 @@ +/* + * Coldfire MCF5272 definitions. + * Contents of this file based on information provided in + * Motorola MCF5272 User's Manual. + * + * Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MCF5272_H__ +#define __MCF5272_H__ + +#ifndef ASM +#include <rtems.h> +#endif + +#define bit(x) (1 << (x)) + +#define MCF5272_SIM_BASE(mbar) ((mbar) + 0x0000) +#define MCF5272_INT_BASE(mbar) ((mbar) + 0x0020) +#define MCF5272_CS_BASE(mbar) ((mbar) + 0x0040) +#define MCF5272_GPIO_BASE(mbar) ((mbar) + 0x0080) +#define MCF5272_QSPI_BASE(mbar) ((mbar) + 0x00A0) +#define MCF5272_PWM_BASE(mbar) ((mbar) + 0x00C0) +#define MCF5272_DMAC_BASE(mbar) ((mbar) + 0x00E0) +#define MCF5272_UART0_BASE(mbar) ((mbar) + 0x0100) +#define MCF5272_UART1_BASE(mbar) ((mbar) + 0x0140) +#define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180) +#define MCF5272_TIMER_BASE(mbar) ((mbar) + 0x0200) +#define MCF5272_PLIC_BASE(mbar) ((mbar) + 0x0300) +#define MCF5272_ENET_BASE(mbar) ((mbar) + 0x0840) +#define MCF5272_USB_BASE(mbar) ((mbar) + 0x1000) + + +/* RAMBAR - SRAM Base Address Register */ +#define MCF5272_RAMBAR_BA (0xfffff000) /* SRAM Base Address */ +#define MCF5272_RAMBAR_WP (0x00000100) /* Write Protect */ +#define MCF5272_RAMBAR_CI (0x00000020) /* CPU Space mask */ +#define MCF5272_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5272_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5272_RAMBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5272_RAMBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5272_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ + +/* MBAR - Module Base Address Register */ +#define MCF5272_MBAR_BA (0xffff0000) /* Base Address */ +#define MCF5272_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ +#define MCF5272_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ +#define MCF5272_MBAR_UC (0x00000004) /* User Code Space Mask */ +#define MCF5272_MBAR_UD (0x00000002) /* User Data Space Mask */ +#define MCF5272_MBAR_V (0x00000001) /* Contents of MBAR are valid */ + +/* CACR - Cache Control Register */ +#define MCF5272_CACR_CENB (0x80000000) /* Cache Enable */ +#define MCF5272_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ +#define MCF5272_CACR_CFRZ (0x08000000) /* Cache Freeze */ +#define MCF5272_CACR_CINV (0x01000000) /* Cache Invalidate */ +#define MCF5272_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable + instruction bursting */ +#define MCF5272_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ +#define MCF5272_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ +#define MCF5272_CACR_DWP (0x00000020) /* Default Write Protection */ +#define MCF5272_CACR_CLNF (0x00000003) /* Cache Line Fill */ + +/* ACRx - Cache Access Control Registers */ +#define MCF5272_ACR_BA (0xff000000) /* Address Base */ +#define MCF5272_ACR_BAM (0x00ff0000) /* Address Mask */ +#define MCF5272_ACR_EN (0x00008000) /* Enable */ +#define MCF5272_ACR_SM_USR (0x00000000) /* Match if user mode */ +#define MCF5272_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ +#define MCF5272_ACR_SM_ANY (0x00004000) /* Match Always */ +#define MCF527_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ +#define MCF5272_ACR_BWE (0x00000020) /* Buffered Write Enable */ +#define MCF5272_ACR_WP (0x00000004) /* Write Protect */ +#define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA) +#define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM) + + +#define MCF5272_ICR1_INT1_PI (bit(31)) +#define MCF5272_ICR1_INT1_IPL(x) ((x) << 28) +#define MCF5272_ICR1_INT1_MASK ((7) << 28) +#define MCF5272_ICR1_INT2_PI (bit(27)) +#define MCF5272_ICR1_INT2_IPL(x) ((x) << 24) +#define MCF5272_ICR1_INT2_MASK ((7) << 24) +#define MCF5272_ICR1_INT3_PI (bit(23)) +#define MCF5272_ICR1_INT3_IPL(x) ((x) << 20) +#define MCF5272_ICR1_INT3_MASK ((7) << 20) +#define MCF5272_ICR1_INT3_PI (bit(19)) +#define MCF5272_ICR1_INT3_IPL(x) ((x) << 16) +#define MCF5272_ICR1_INT3_MASK ((7) << 16) +#define MCF5272_ICR1_TMR0_PI (bit(15)) +#define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12) +#define MCF5272_ICR1_TMR0_MASK ((7) << 12) +#define MCF5272_ICR1_TMR1_PI (bit(11)) +#define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8) +#define MCF5272_ICR1_TMR1_MASK ((7) << 8) +#define MCF5272_ICR1_TMR2_PI (bit(7)) +#define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4) +#define MCF5272_ICR1_TMR2_MASK ((7) << 4) +#define MCF5272_ICR1_TMR3_PI (bit(3)) +#define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0) +#define MCF5272_ICR1_TMR3_MASK ((7) << 0) + +#define MCF5272_ICR3_USB4_PI (bit(31)) +#define MCF5272_ICR3_USB4_IPL(x) ((x) << 28) +#define MCF5272_ICR3_USB4_MASK ((7) << 28) +#define MCF5272_ICR3_USB5_PI (bit(27)) +#define MCF5272_ICR3_USB5_IPL(x) ((x) << 24) +#define MCF5272_ICR3_USB5_MASK ((7) << 24) +#define MCF5272_ICR3_USB6_PI (bit(23)) +#define MCF5272_ICR3_USB6_IPL(x) ((x) << 20) +#define MCF5272_ICR3_USB6_MASK ((7) << 20) +#define MCF5272_ICR3_USB7_PI (bit(19)) +#define MCF5272_ICR3_USB7_IPL(x) ((x) << 16) +#define MCF5272_ICR3_USB7_MASK ((7) << 16) +#define MCF5272_ICR3_DMA_PI (bit(15)) +#define MCF5272_ICR3_DMA_IPL(x) ((x) << 12) +#define MCF5272_ICR3_DMA_MASK ((7) << 12) +#define MCF5272_ICR3_ERX_PI (bit(11)) +#define MCF5272_ICR3_ERX_IPL(x) ((x) << 8) +#define MCF5272_ICR3_ERX_MASK ((7) << 8) +#define MCF5272_ICR3_ETX_PI (bit(7)) +#define MCF5272_ICR3_ETX_IPL(x) ((x) << 4) +#define MCF5272_ICR3_ETX_MASK ((7) << 4) +#define MCF5272_ICR3_ENTC_PI (bit(3)) +#define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0) +#define MCF5272_ICR3_ENTC_MASK ((7) << 0) + + +#define MCF5272_USR_RB (bit(7)) +#define MCF5272_USR_FE (bit(6)) +#define MCF5272_USR_PE (bit(5)) +#define MCF5272_USR_OE (bit(4)) +#define MCF5272_USR_TXEMP (bit(3)) +#define MCF5272_USR_TXRDY (bit(2)) +#define MCF5272_USR_FFULL (bit(1)) +#define MCF5272_USR_RXRDY (bit(0)) + +#define MCF5272_TMR_PS_MASK 0xff00 +#define MCF5272_TMR_PS_SHIFT 8 +#define MCF5272_TMR_CE_DISABLE (0 << 6) +#define MCF5272_TMR_CE_RISING (1 << 6) +#define MCF5272_TMR_CE_FALLING (2 << 6) +#define MCF5272_TMR_CE_ANY (3 << 6) +#define MCF5272_TMR_OM (bit(5)) +#define MCF5272_TMR_ORI (bit(4)) +#define MCF5272_TMR_FRR (bit(3)) +#define MCF5272_TMR_CLK_STOP (0 << 1) +#define MCF5272_TMR_CLK_MSTR (1 << 1) +#define MCF5272_TMR_CLK_MSTR16 (2 << 1) +#define MCF5272_TMR_CLK_TIN (3 << 1) +#define MCF5272_TMR_RST (bit(0)) +#define MCF5272_TER_REF (bit(1)) +#define MCF5272_TER_CAP (bit(0)) + +#define MCF5272_SCR_PRI (bit(8)) +#define MCF5272_SCR_AR (bit(7)) +#define MCF5272_SCR_SRST (bit(6)) +#define MCF5272_SCR_BUSLOCK (bit(3)) +#define MCF5272_SCR_HWR_128 (0) +#define MCF5272_SCR_HWR_256 (1) +#define MCF5272_SCR_HWR_512 (2) +#define MCF5272_SCR_HWR_1024 (3) +#define MCF5272_SCR_HWR_2048 (4) +#define MCF5272_SCR_HWR_4096 (5) +#define MCF5272_SCR_HWR_8192 (6) +#define MCF5272_SCR_HWR_16384 (7) + +#define MCF5272_SPR_ADC (bit(15)) +#define MCF5272_SPR_WPV (bit(15)) +#define MCF5272_SPR_SMV (bit(15)) +#define MCF5272_SPR_PE (bit(15)) +#define MCF5272_SPR_HWT (bit(15)) +#define MCF5272_SPR_RPV (bit(15)) +#define MCF5272_SPR_EXT (bit(15)) +#define MCF5272_SPR_SUV (bit(15)) +#define MCF5272_SPR_ADCEN (bit(15)) +#define MCF5272_SPR_WPVEN (bit(15)) +#define MCF5272_SPR_SMVEN (bit(15)) +#define MCF5272_SPR_PEEN (bit(15)) +#define MCF5272_SPR_HWTEN (bit(15)) +#define MCF5272_SPR_RPVEN (bit(15)) +#define MCF5272_SPR_EXTEN (bit(15)) +#define MCF5272_SPR_SUVEN (bit(15)) + +#define MCF5272_ENET_TX_RT (bit(25)) +#define MCF5272_ENET_ETHERN_EN (bit(1)) +#define MCF5272_ENET_RESET (bit(0)) + +#define MCF5272_ENET_EIR_HBERR (bit(31)) +#define MCF5272_ENET_EIR_BABR (bit(30)) +#define MCF5272_ENET_EIR_BABT (bit(29)) +#define MCF5272_ENET_EIR_GRA (bit(28)) +#define MCF5272_ENET_EIR_TXF (bit(27)) +#define MCF5272_ENET_EIR_TXB (bit(26)) +#define MCF5272_ENET_EIR_RXF (bit(25)) +#define MCF5272_ENET_EIR_RXB (bit(24)) +#define MCF5272_ENET_EIR_MII (bit(23)) +#define MCF5272_ENET_EIR_EBERR (bit(22)) +#define MCF5272_ENET_EIR_UMINT (bit(21)) + +#define MCF5272_ENET_RCR_PROM (bit(3)) +#define MCF5272_ENET_RCR_MII (bit(2)) +#define MCF5272_ENET_RCR_DRT (bit(1)) +#define MCF5272_ENET_RCR_LOOP (bit(0)) + +#define MCF5272_ENET_TCR_FDEN (bit(2)) +#define MCF5272_ENET_TCR_HBC (bit(1)) +#define MCF5272_ENET_TCR_GTS (bit(0)) + + +#ifndef ASM +typedef struct { + volatile uint32_t mbar; /* READ ONLY!! */ + + volatile uint16_t scr; + volatile uint16_t _res0; + + volatile uint16_t _res1; + volatile uint16_t spr; + + volatile uint32_t pmr; + + volatile uint16_t _res2; + volatile uint16_t alpr; + + volatile uint32_t dir; +} sim_regs_t; + +typedef struct { + volatile uint32_t icr1; + volatile uint32_t icr2; + volatile uint32_t icr3; + volatile uint32_t icr4; + volatile uint32_t isr; + volatile uint32_t pitr; + volatile uint32_t piwr; + volatile uint8_t _res0[3]; + volatile uint8_t pivr; +} intctrl_regs_t; + +typedef struct { + volatile uint32_t csbr0; + volatile uint32_t csor0; + volatile uint32_t csbr1; + volatile uint32_t csor1; + volatile uint32_t csbr2; + volatile uint32_t csor2; + volatile uint32_t csbr3; + volatile uint32_t csor3; + volatile uint32_t csbr4; + volatile uint32_t csor4; + volatile uint32_t csbr5; + volatile uint32_t csor5; + volatile uint32_t csbr6; + volatile uint32_t csor6; + volatile uint32_t csbr7; + volatile uint32_t csor7; +} chipsel_regs_t; + +typedef struct { + volatile uint32_t pacnt; + + volatile uint16_t paddr; + volatile uint16_t _res0; + + volatile uint16_t _res1; + volatile uint16_t padat; + + volatile uint32_t pbcnt; + + volatile uint16_t pbddr; + volatile uint16_t _res2; + + volatile uint16_t _res3; + volatile uint16_t pbdat; + + volatile uint16_t pcddr; + volatile uint16_t _res4; + + volatile uint16_t _res5; + volatile uint16_t pcdat; + + volatile uint32_t pdcnt; +} gpio_regs_t; + +typedef struct { + volatile uint32_t qmr; + volatile uint32_t qdlyr; + volatile uint32_t qwr; + volatile uint32_t qir; + volatile uint32_t qar; + volatile uint32_t qdr; +} qspi_regs_t; + +typedef struct { + volatile uint8_t pwcr1; + volatile uint8_t _res0[3]; + + volatile uint8_t pwcr2; + volatile uint8_t _res1[3]; + + volatile uint8_t pwcr3; + volatile uint8_t _res2[3]; + + volatile uint8_t pwwd1; + volatile uint8_t _res3[3]; + + volatile uint8_t pwwd2; + volatile uint8_t _res4[3]; + + volatile uint8_t pwwd3; + volatile uint8_t _res5[3]; +} pwm_regs_t; + +typedef struct { + volatile uint32_t dcmr; + + volatile uint16_t _res0; + volatile uint16_t dcir; + + volatile uint32_t dbcr; + + volatile uint32_t dsar; + + volatile uint32_t ddar; +} dma_regs_t; + +typedef struct { + volatile uint8_t umr; /* 0x000 */ + volatile uint8_t _res0[3]; + + volatile uint8_t ucsr; /* 0x004 */ + volatile uint8_t _res2[3]; + + volatile uint8_t ucr; /* 0x008 */ + volatile uint8_t _res3[3]; + + volatile uint8_t udata; /* 0x00c */ + volatile uint8_t _res4[3]; + + volatile uint8_t uccr; /* 0x010 */ + volatile uint8_t _res6[3]; + + volatile uint8_t uisr; /* 0x014 */ + volatile uint8_t _res8[3]; + + volatile uint8_t ubg1; /* 0x018 */ + volatile uint8_t _res10[3]; + + volatile uint8_t ubg2; /* 0x01c */ + volatile uint8_t _res11[3]; + + volatile uint8_t uabr1; /* 0x020 */ + volatile uint8_t _res12[3]; + + volatile uint8_t uabr2; /* 0x024 */ + volatile uint8_t _res13[3]; + + volatile uint8_t utxfcsr; /* 0x028 */ + volatile uint8_t _res14[3]; + + volatile uint8_t urxfcsr; /* 0x02c */ + volatile uint8_t _res15[3]; + + volatile uint8_t ufpdn; /* 0x030 */ + volatile uint8_t _res16[3]; + + volatile uint8_t uip; /* 0x034 */ + volatile uint8_t _res17[3]; + + volatile uint8_t uop1; /* 0x038 */ + volatile uint8_t _res18[3]; + + volatile uint8_t uop0; /* 0x03c */ + volatile uint8_t _res19[3]; +} uart_regs_t; + +typedef struct { + volatile uint16_t tmr0; + volatile uint16_t _res0; + + volatile uint16_t trr0; + volatile uint16_t _res1; + + volatile uint16_t tcap0; + volatile uint16_t _res2; + + volatile uint16_t tcn0; + volatile uint16_t _res3; + + volatile uint16_t ter0; + volatile uint16_t _res4; + + volatile uint8_t _res40[12]; + + volatile uint16_t tmr1; + volatile uint16_t _res5; + + volatile uint16_t trr1; + volatile uint16_t _res6; + + volatile uint16_t tcap1; + volatile uint16_t _res7; + + volatile uint16_t tcn1; + volatile uint16_t _res8; + + volatile uint16_t ter1; + volatile uint16_t _res9; + + volatile uint8_t _res91[12]; + + volatile uint16_t tmr2; + volatile uint16_t _res10; + + volatile uint16_t trr2; + volatile uint16_t _res11; + + volatile uint16_t tcap2; + volatile uint16_t _res12; + + volatile uint16_t tcn2; + volatile uint16_t _res13; + + volatile uint16_t ter2; + volatile uint16_t _res14; + + volatile uint8_t _res140[12]; + + volatile uint16_t tmr3; + volatile uint16_t _res15; + + volatile uint16_t trr3; + volatile uint16_t _res16; + + volatile uint16_t tcap3; + volatile uint16_t _res17; + + volatile uint16_t tcn3; + volatile uint16_t _res18; + + volatile uint16_t ter3; + volatile uint16_t _res19; + + volatile uint8_t _res190[12]; + + volatile uint16_t wrrr; + volatile uint16_t _res20; + + volatile uint16_t wirr; + volatile uint16_t _res21; + + volatile uint16_t wcr; + volatile uint16_t _res22; + + volatile uint16_t wer; + volatile uint16_t _res23; +} timer_regs_t; + +typedef struct { + volatile uint32_t p0b1rr; + volatile uint32_t p1b1rr; + volatile uint32_t p2b1rr; + volatile uint32_t p3b1rr; + volatile uint32_t p0b2rr; + volatile uint32_t p1b2rr; + volatile uint32_t p2b2rr; + volatile uint32_t p3b2rr; + + volatile uint8_t p0drr; + volatile uint8_t p1drr; + volatile uint8_t p2drr; + volatile uint8_t p3drr; + + volatile uint32_t p0b1tr; + volatile uint32_t p1b1tr; + volatile uint32_t p2b1tr; + volatile uint32_t p3b1tr; + volatile uint32_t p0b2tr; + volatile uint32_t p1b2tr; + volatile uint32_t p2b2tr; + volatile uint32_t p3b2tr; + + volatile uint8_t p0dtr; + volatile uint8_t p1dtr; + volatile uint8_t p2dtr; + volatile uint8_t p3dtr; + + volatile uint16_t p0cr; + volatile uint16_t p1cr; + volatile uint16_t p2cr; + volatile uint16_t p3cr; + volatile uint16_t p0icr; + volatile uint16_t p1icr; + volatile uint16_t p2icr; + volatile uint16_t p3icr; + volatile uint16_t p0gmr; + volatile uint16_t p1gmr; + volatile uint16_t p2gmr; + volatile uint16_t p3gmr; + volatile uint16_t p0gmt; + volatile uint16_t p1gmt; + volatile uint16_t p2gmt; + volatile uint16_t p3gmt; + + volatile uint8_t _res0; + volatile uint8_t pgmts; + volatile uint8_t pgmta; + volatile uint8_t _res1; + volatile uint8_t p0gcir; + volatile uint8_t p1gcir; + volatile uint8_t p2gcir; + volatile uint8_t p3gcir; + volatile uint8_t p0gcit; + volatile uint8_t p1gcit; + volatile uint8_t p2gcit; + volatile uint8_t p3gcit; + volatile uint8_t _res3[3]; + volatile uint8_t pgcitsr; + volatile uint8_t _res4[3]; + volatile uint8_t pdcsr; + + volatile uint16_t p0psr; + volatile uint16_t p1psr; + volatile uint16_t p2psr; + volatile uint16_t p3psr; + volatile uint16_t pasr; + volatile uint8_t _res5; + volatile uint8_t plcr; + volatile uint16_t _res6; + volatile uint16_t pdrqr; + volatile uint16_t p0sdr; + volatile uint16_t p1sdr; + volatile uint16_t p2sdr; + volatile uint16_t p3sdr; + volatile uint16_t _res7; + volatile uint16_t pcsr; +} plic_regs_t; + +typedef struct { + volatile uint32_t ecr; + volatile uint32_t eir; + volatile uint32_t eimr; + volatile uint32_t ivsr; + volatile uint32_t rdar; + volatile uint32_t tdar; + volatile uint32_t _res0[10]; + volatile uint32_t mmfr; + volatile uint32_t mscr; + volatile uint32_t _res1[17]; + volatile uint32_t frbr; + volatile uint32_t frsr; + volatile uint32_t _res2[4]; + volatile uint32_t tfwr; + volatile uint32_t _res3[1]; + volatile uint32_t tfsr; + volatile uint32_t _res4[21]; + volatile uint32_t rcr; + volatile uint32_t mflr; + volatile uint32_t _res5[14]; + volatile uint32_t tcr; + volatile uint32_t _res6[158]; + volatile uint32_t malr; + volatile uint32_t maur; + volatile uint32_t htur; + volatile uint32_t htlr; + volatile uint32_t erdsr; + volatile uint32_t etdsr; + volatile uint32_t emrbr; +/* volatile uint8_t fifo[448]; */ +} enet_regs_t; + +typedef struct { + volatile uint16_t _res0; + volatile uint16_t fnr; + volatile uint16_t _res1; + volatile uint16_t fnmr; + volatile uint16_t _res2; + volatile uint16_t rfmr; + volatile uint16_t _res3; + volatile uint16_t rfmmr; + volatile uint8_t _res4[3]; + volatile uint8_t far; + volatile uint32_t asr; + volatile uint32_t drr1; + volatile uint32_t drr2; + volatile uint16_t _res5; + volatile uint16_t specr; + volatile uint16_t _res6; + volatile uint16_t ep0sr; + + volatile uint32_t iep0cfg; + volatile uint32_t oep0cfg; + volatile uint32_t ep1cfg; + volatile uint32_t ep2cfg; + volatile uint32_t ep3cfg; + volatile uint32_t ep4cfg; + volatile uint32_t ep5cfg; + volatile uint32_t ep6cfg; + volatile uint32_t ep7cfg; + volatile uint32_t ep0ctl; + + volatile uint16_t _res7; + volatile uint16_t ep1ctl; + volatile uint16_t _res8; + volatile uint16_t ep2ctl; + volatile uint16_t _res9; + volatile uint16_t ep3ctl; + volatile uint16_t _res10; + volatile uint16_t ep4ctl; + volatile uint16_t _res11; + volatile uint16_t ep5ctl; + volatile uint16_t _res12; + volatile uint16_t ep6ctl; + volatile uint16_t _res13; + volatile uint16_t ep7ctl; + + volatile uint32_t ep0isr; + + volatile uint16_t _res14; + volatile uint16_t ep1isr; + volatile uint16_t _res15; + volatile uint16_t ep2isr; + volatile uint16_t _res16; + volatile uint16_t ep3isr; + volatile uint16_t _res17; + volatile uint16_t ep4isr; + volatile uint16_t _res18; + volatile uint16_t ep5isr; + volatile uint16_t _res19; + volatile uint16_t ep6isr; + volatile uint16_t _res20; + volatile uint16_t ep7isr; + + volatile uint32_t ep0imr; + + volatile uint16_t _res21; + volatile uint16_t ep1imr; + volatile uint16_t _res22; + volatile uint16_t ep2imr; + volatile uint16_t _res23; + volatile uint16_t ep3imr; + volatile uint16_t _res24; + volatile uint16_t ep4imr; + volatile uint16_t _res25; + volatile uint16_t ep5imr; + volatile uint16_t _res26; + volatile uint16_t ep6imr; + volatile uint16_t _res27; + volatile uint16_t ep7imr; + + volatile uint32_t ep0dr; + volatile uint32_t ep1dr; + volatile uint32_t ep2dr; + volatile uint32_t ep3dr; + volatile uint32_t ep4dr; + volatile uint32_t ep5dr; + volatile uint32_t ep6dr; + volatile uint32_t ep7dr; + + volatile uint16_t _res28; + volatile uint16_t ep0dpr; + volatile uint16_t _res29; + volatile uint16_t ep1dpr; + volatile uint16_t _res30; + volatile uint16_t ep2dpr; + volatile uint16_t _res31; + volatile uint16_t ep3dpr; + volatile uint16_t _res32; + volatile uint16_t ep4dpr; + volatile uint16_t _res33; + volatile uint16_t ep5dpr; + volatile uint16_t _res34; + volatile uint16_t ep6dpr; + volatile uint16_t _res35; + volatile uint16_t ep7dpr; +/* uint8_t ram[1024]; */ +} usb_regs_t; + +extern intctrl_regs_t *g_intctrl_regs; +extern chipsel_regs_t *g_chipsel_regs; +extern gpio_regs_t *g_gpio_regs; +extern qspi_regs_t *g_qspi_regs; +extern pwm_regs_t *g_pwm_regs; +extern dma_regs_t *g_dma_regs; +extern uart_regs_t *g_uart0_regs; +extern uart_regs_t *g_uart1_regs; +extern timer_regs_t *g_timer_regs; +extern plic_regs_t *g_plic_regs; +extern enet_regs_t *g_enet_regs; +extern usb_regs_t *g_usb_regs; + +#endif /* ASM */ + +#endif /* __MCF5272_H__ */ diff --git a/bsps/m68k/include/mcf5282/mcf5282.h b/bsps/m68k/include/mcf5282/mcf5282.h new file mode 100644 index 0000000000..3724f489de --- /dev/null +++ b/bsps/m68k/include/mcf5282/mcf5282.h @@ -0,0 +1,2407 @@ +/* + ******************************************* + * Definitions from Motorola/FreeScale * + ******************************************* + */ + +/* + * File: mcf5282.h + * Purpose: MCF5282 definitions + * + * Notes: + */ + +#ifndef _CPU_MCF5282_H +#define _CPU_MCF5282_H + +/********************************************************************/ + +/* + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * The basic data types + * + * Those are low-level so we mark them so that they may alias anything + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16 __attribute__((__may_alias__)); /* 16 bits */ +typedef unsigned long int uint32 __attribute__((__may_alias__)); /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16 __attribute__((__may_alias__)); /* 16 bits */ +typedef signed long int int32 __attribute__((__may_alias__)); /* 32 bits */ + +typedef volatile uint8 vuint8 __attribute__((__may_alias__)); /* 8 bits */ +typedef volatile uint16 vuint16 __attribute__((__may_alias__)); /* 16 bits */ +typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + */ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +/* + * Used to set the initialize the cacr register to the BSP's desired + * starting value. + */ +void mcf5xxx_initialize_cacr(uint32_t); + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + + +/********************************************************************/ +/* + * Memory map definitions from linker command files + */ +extern uint8 __IPSBAR[]; + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SCM_IPSBAR (*(vuint32 *)(&__IPSBAR[0x0000])) +#define MCF5282_SCM_RAMBAR (*(vuint32 *)(&__IPSBAR[0x0008])) +#define MCF5282_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x0010])) +#define MCF5282_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x0011])) +#define MCF5282_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x0012])) +#define MCF5282_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x0013])) +#define MCF5282_SCM_DMAREQC (*(vuint32 *)(&__IPSBAR[0x0014])) +#define MCF5282_SCM_MPARK (*(vuint32 *)(&__IPSBAR[0x001C])) +#define MCF5282_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x0020])) +#define MCF5282_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x0024])) +#define MCF5282_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x0025])) +#define MCF5282_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x0026])) +#define MCF5282_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x0027])) +#define MCF5282_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x0028])) +#define MCF5282_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x002A])) +#define MCF5282_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x002B])) +#define MCF5282_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x002C])) +#define MCF5282_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x002E])) +#define MCF5282_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x0030])) +#define MCF5282_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x0031])) + +/* Bit level definitions and macros */ +#define MCF5282_SCM_IPSBAR_BA(x) ((x)&0xC0000000) +#define MCF5282_SCM_IPSBAR_V (0x00000001) + +#define MCF5282_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) +#define MCF5282_SCM_RAMBAR_BDE (0x00000200) + +#define MCF5282_SCM_CRSR_EXT (0x80) +#define MCF5282_SCM_CRSR_CWDR (0x20) + +#define MCF5282_SCM_CWCR_CWE (0x80) +#define MCF5282_SCM_CWCR_CWRI (0x40) +#define MCF5282_SCM_CWCR_CWT(x) (((x)&0x03)<<3) +#define MCF5282_SCM_CWCR_CWTA (0x04) +#define MCF5282_SCM_CWCR_CWTAVAL (0x02) +#define MCF5282_SCM_CWCR_CWTIC (0x01) + +#define MCF5282_SCM_LPICR_ENBSTOP (0x80) +#define MCF5282_SCM_LPICR_XSTOP_IPL(x) (((x)&0x07)<<4) + +#define MCF5282_SCM_CWSR_SEQ1 (0x55) +#define MCF5282_SCM_CWSR_SEQ2 (0xAA) + +#define MCF5282_SCM_DMAREQC_DMAC3(x) (((x)&0x000F)<<12) +#define MCF5282_SCM_DMAREQC_DMAC2(x) (((x)&0x000F)<<8) +#define MCF5282_SCM_DMAREQC_DMAC1(x) (((x)&0x000F)<<4) +#define MCF5282_SCM_DMAREQC_DMAC0(x) (((x)&0x000F)) +#define MCF5282_SCM_DMAREQC_DMATIMER0 (0x4) +#define MCF5282_SCM_DMAREQC_DMATIMER1 (0x5) +#define MCF5282_SCM_DMAREQC_DMATIMER2 (0x6) +#define MCF5282_SCM_DMAREQC_DMATIMER3 (0x7) +#define MCF5282_SCM_DMAREQC_UART0 (0x8) +#define MCF5282_SCM_DMAREQC_UART1 (0x9) +#define MCF5282_SCM_DMAREQC_UART2 (0xA) + +#define MCF5282_SCM_MPARK_M2_P_EN (0x02000000) +#define MCF5282_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF5282_SCM_MPARK_M3_PRTY(x) (((x)&0x03)<<22) +#define MCF5282_SCM_MPARK_M2_PRTY(x) (((x)&0x03)<<20) +#define MCF5282_SCM_MPARK_M0_PRTY(x) (((x)&0x03)<<18) +#define MCF5282_SCM_MPARK_M1_PRTY(x) (((x)&0x03)<<16) +#define MCF5282_SCM_MPARK_FIXED (0x00040000) +#define MCF5282_SCM_MPARK_TIMEOUT (0x00020000) +#define MCF5282_SCM_MPARK_PRK_LAST (0x00010000) +#define MCF5282_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x000F)<<8) + +#define MCF5282_SCM_MPARK_MX_PRTY_FIRST (0x3) +#define MCF5282_SCM_MPARK_MX_PRTY_SECOND (0x2) +#define MCF5282_SCM_MPARK_MX_PRTY_THIRD (0x1) +#define MCF5282_SCM_MPARK_MX_PRTY_FOURTH (0x0) + +#define MCF5282_SCM_MPR_MPR(x) (((x)&0x0F)) + +#define MCF5282_SCM_PACR_LOCK1 (0x80) +#define MCF5282_SCM_PACR_ACCESSCTRL1(x) (((x)&0x07)<<4) +#define MCF5282_SCM_PACR_LOCK0 (0x08) +#define MCF5282_SCM_PACR_ACCESSCTRL0(x) (((x)&0x07)) +#define MCF5282_SCM_PACR_RW_NA (0x0) +#define MCF5282_SCM_PACR_R_NA (0x1) +#define MCF5282_SCM_PACR_R_R (0x2) +#define MCF5282_SCM_PACR_RW_RW (0x4) +#define MCF5282_SCM_PACR_RW_R (0x5) +#define MCF5282_SCM_PACR_NA_NA (0x7) + +#define MCF5282_SCM_GPACR_LOCK (0x80) +#define MCF5282_SCM_GPACR_ACCESSCTRL(x) (((x)&0x0F)) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_NA (0x0) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_NA (0x1) +#define MCF5282_SCM_GPACR_ACCESSCTRL_R_R (0x2) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_RW (0x4) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_R (0x5) +#define MCF5282_SCM_GPACR_ACCESSCTRL_NA_NA (0x7) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_NA (0x8) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_NA (0x9) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_RE (0xA) +#define MCF5282_SCM_GPACR_ACCESSCTRL_E_NA (0xB) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RWE (0xC) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RE (0xD) +#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_E (0xF) + +/********************************************************************* +* +* SDRAM Controller Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_SDRAMC_DCR (*(vuint16 *)(&__IPSBAR[0x0040])) +#define MCF5282_SDRAMC_DACR0 (*(vuint32 *)(&__IPSBAR[0x0048])) +#define MCF5282_SDRAMC_DMR0 (*(vuint32 *)(&__IPSBAR[0x004C])) +#define MCF5282_SDRAMC_DACR1 (*(vuint32 *)(&__IPSBAR[0x0050])) +#define MCF5282_SDRAMC_DMR1 (*(vuint32 *)(&__IPSBAR[0x0054])) + +/* Bit level definitions and macros */ +#define MCF5282_SDRAMC_DCR_NAM (0x2000) +#define MCF5282_SDRAMC_DCR_COC (0x1000) +#define MCF5282_SDRAMC_DCR_IS (0x0800) +#define MCF5282_SDRAMC_DCR_RTIM_3 (0x0000) +#define MCF5282_SDRAMC_DCR_RTIM_6 (0x0200) +#define MCF5282_SDRAMC_DCR_RTIM_9 (0x0400) +#define MCF5282_SDRAMC_DCR_RC(x) ((x)&0x01FF) + +#define MCF5282_SDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) +#define MCF5282_SDRAMC_DACR_RE (0x00008000) +#define MCF5282_SDRAMC_DACR_CASL(x) (((x)&0x03)<<12) +#define MCF5282_SDRAMC_DACR_CBM(x) (((x)&0x07)<<8) +#define MCF5282_SDRAMC_DACR_PS_32 (0x00000000) +#define MCF5282_SDRAMC_DACR_PS_8 (0x00000010) +#define MCF5282_SDRAMC_DACR_PS_16 (0x00000020) +#define MCF5282_SDRAMC_DACR_IMRS (0x00000040) +#define MCF5282_SDRAMC_DACR_IP (0x00000008) + +#define MCF5282_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF5282_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF5282_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF5282_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF5282_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF5282_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF5282_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF5282_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF5282_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF5282_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF5282_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF5282_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF5282_SDRAMC_DMR_WP (0x00000100) +#define MCF5282_SDRAMC_DMR_CI (0x00000040) +#define MCF5282_SDRAMC_DMR_AM (0x00000020) +#define MCF5282_SDRAMC_DMR_SC (0x00000010) +#define MCF5282_SDRAMC_DMR_SD (0x00000008) +#define MCF5282_SDRAMC_DMR_UC (0x00000004) +#define MCF5282_SDRAMC_DMR_UD (0x00000002) +#define MCF5282_SDRAMC_DMR_V (0x00000001) + +/********************************************************************* +* +* Chip Select Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CS0_CSAR (*(vuint16 *)(&__IPSBAR[0x0080])) +#define MCF5282_CS0_CSMR (*(vuint32 *)(&__IPSBAR[0x0084])) +#define MCF5282_CS0_CSCR (*(vuint16 *)(&__IPSBAR[0x008A])) + +#define MCF5282_CS1_CSAR (*(vuint16 *)(&__IPSBAR[0x008C])) +#define MCF5282_CS1_CSMR (*(vuint32 *)(&__IPSBAR[0x0090])) +#define MCF5282_CS1_CSCR (*(vuint16 *)(&__IPSBAR[0x0096])) + +#define MCF5282_CS2_CSAR (*(vuint16 *)(&__IPSBAR[0x0098])) +#define MCF5282_CS2_CSMR (*(vuint32 *)(&__IPSBAR[0x009C])) +#define MCF5282_CS2_CSCR (*(vuint16 *)(&__IPSBAR[0x00A2])) + +#define MCF5282_CS3_CSAR (*(vuint16 *)(&__IPSBAR[0x00A4])) +#define MCF5282_CS3_CSMR (*(vuint32 *)(&__IPSBAR[0x00A8])) +#define MCF5282_CS3_CSCR (*(vuint16 *)(&__IPSBAR[0x00AE])) + +#define MCF5282_CS4_CSAR (*(vuint16 *)(&__IPSBAR[0x00B0])) +#define MCF5282_CS4_CSMR (*(vuint32 *)(&__IPSBAR[0x00B4])) +#define MCF5282_CS4_CSCR (*(vuint16 *)(&__IPSBAR[0x00BA])) + +#define MCF5282_CS5_CSAR (*(vuint16 *)(&__IPSBAR[0x00BC])) +#define MCF5282_CS5_CSMR (*(vuint32 *)(&__IPSBAR[0x00C0])) +#define MCF5282_CS5_CSCR (*(vuint16 *)(&__IPSBAR[0x00C6])) + +#define MCF5282_CS6_CSAR (*(vuint16 *)(&__IPSBAR[0x00C8])) +#define MCF5282_CS6_CSMR (*(vuint32 *)(&__IPSBAR[0x00CC])) +#define MCF5282_CS6_CSCR (*(vuint16 *)(&__IPSBAR[0x00D2])) + +#define MCF5282_CS_CSAR(x) (*(vuint16 *)(&__IPSBAR[0x0080+((x)*0x0C)])) +#define MCF5282_CS_CSMR(x) (*(vuint32 *)(&__IPSBAR[0x0084+((x)*0x0C)])) +#define MCF5282_CS_CSCR(x) (*(vuint16 *)(&__IPSBAR[0x008A+((x)*0x0C)])) + +/* Bit level definitions and macros */ +#define MCF5282_CS_CSAR_BA(a) (uint16)(((a)&0xFFFF0000)>>16) + +#define MCF5282_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF5282_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF5282_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF5282_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF5282_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF5282_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF5282_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF5282_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF5282_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF5282_CS_CSMR_BAM_8M (0x007F0000) +#define MCF5282_CS_CSMR_BAM_4M (0x003F0000) +#define MCF5282_CS_CSMR_BAM_2M (0x001F0000) +#define MCF5282_CS_CSMR_BAM_1M (0x000F0000) +#define MCF5282_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF5282_CS_CSMR_BAM_512K (0x00070000) +#define MCF5282_CS_CSMR_BAM_256K (0x00030000) +#define MCF5282_CS_CSMR_BAM_128K (0x00010000) +#define MCF5282_CS_CSMR_BAM_64K (0x00000000) +#define MCF5282_CS_CSMR_WP (0x00000100) +#define MCF5282_CS_CSMR_AM (0x00000040) +#define MCF5282_CS_CSMR_CI (0x00000020) +#define MCF5282_CS_CSMR_SC (0x00000010) +#define MCF5282_CS_CSMR_SD (0x00000008) +#define MCF5282_CS_CSMR_UC (0x00000004) +#define MCF5282_CS_CSMR_UD (0x00000002) +#define MCF5282_CS_CSMR_V (0x00000001) + +#define MCF5282_CS_CSCR_WS(x) (((x)&0x0F)<<10) +#define MCF5282_CS_CSCR_AA (0x0100) +#define MCF5282_CS_CSCR_PS_8 (0x0040) +#define MCF5282_CS_CSCR_PS_16 (0x0080) +#define MCF5282_CS_CSCR_PS_32 (0x0000) +#define MCF5282_CS_CSCR_BEM (0x0020) +#define MCF5282_CS_CSCR_BSTR (0x0010) +#define MCF5282_CS_CSCR_BSTW (0x0008) + +/********************************************************************* +* +* Direct Memory Access (DMA) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_DMA0_SAR (*(vuint32 *)(&__IPSBAR[0x0100])) +#define MCF5282_DMA0_DAR (*(vuint32 *)(&__IPSBAR[0x0104])) +#define MCF5282_DMA0_DCR (*(vuint32 *)(&__IPSBAR[0x0108])) +#define MCF5282_DMA0_BCR (*(vuint32 *)(&__IPSBAR[0x010C])) +#define MCF5282_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x0110])) + +#define MCF5282_DMA1_SAR (*(vuint32 *)(&__IPSBAR[0x0140])) +#define MCF5282_DMA1_DAR (*(vuint32 *)(&__IPSBAR[0x0144])) +#define MCF5282_DMA1_DCR (*(vuint32 *)(&__IPSBAR[0x0148])) +#define MCF5282_DMA1_BCR (*(vuint32 *)(&__IPSBAR[0x014C])) +#define MCF5282_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x0150])) + +#define MCF5282_DMA2_SAR (*(vuint32 *)(&__IPSBAR[0x0180])) +#define MCF5282_DMA2_DAR (*(vuint32 *)(&__IPSBAR[0x0184])) +#define MCF5282_DMA2_DCR (*(vuint32 *)(&__IPSBAR[0x0188])) +#define MCF5282_DMA2_BCR (*(vuint32 *)(&__IPSBAR[0x018C])) +#define MCF5282_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x0190])) + +#define MCF5282_DMA3_SAR (*(vuint32 *)(&__IPSBAR[0x01C0])) +#define MCF5282_DMA3_DAR (*(vuint32 *)(&__IPSBAR[0x01C4])) +#define MCF5282_DMA3_DCR (*(vuint32 *)(&__IPSBAR[0x01C8])) +#define MCF5282_DMA3_BCR (*(vuint32 *)(&__IPSBAR[0x01CC])) +#define MCF5282_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x01D0])) + +#define MCF5282_DMA_SAR(x) (*(vuint32 *)(&__IPSBAR[0x0100+((x)*0x40)])) +#define MCF5282_DMA_DAR(x) (*(vuint32 *)(&__IPSBAR[0x0104+((x)*0x40)])) +#define MCF5282_DMA_DCR(x) (*(vuint32 *)(&__IPSBAR[0x0108+((x)*0x40)])) +#define MCF5282_DMA_BCR(x) (*(vuint32 *)(&__IPSBAR[0x010C+((x)*0x40)])) +#define MCF5282_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x0110+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_DMA_DCR_INT (0x80000000) +#define MCF5282_DMA_DCR_EEXT (0x40000000) +#define MCF5282_DMA_DCR_CS (0x20000000) +#define MCF5282_DMA_DCR_AA (0x10000000) +#define MCF5282_DMA_DCR_BWC_DMA (0x00000000) +#define MCF5282_DMA_DCR_BWC_512 (0x02000000) +#define MCF5282_DMA_DCR_BWC_1024 (0x04000000) +#define MCF5282_DMA_DCR_BWC_2048 (0x06000000) +#define MCF5282_DMA_DCR_BWC_4096 (0x08000000) +#define MCF5282_DMA_DCR_BWC_8192 (0x0A000000) +#define MCF5282_DMA_DCR_BWC_16384 (0x0C000000) +#define MCF5282_DMA_DCR_BWC_32768 (0x0E000000) +#define MCF5282_DMA_DCR_SINC (0x00400000) +#define MCF5282_DMA_DCR_SSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_SSIZE_BYTE (0x00100000) +#define MCF5282_DMA_DCR_SSIZE_WORD (0x00200000) +#define MCF5282_DMA_DCR_SSIZE_LINE (0x00300000) +#define MCF5282_DMA_DCR_DINC (0x00080000) +#define MCF5282_DMA_DCR_DSIZE_LONG (0x00000000) +#define MCF5282_DMA_DCR_DSIZE_BYTE (0x00020000) +#define MCF5282_DMA_DCR_DSIZE_WORD (0x00040000) +#define MCF5282_DMA_DCR_START (0x00010000) +#define MCF5282_DMA_DCR_AT (0x00008000) + +#define MCF5282_DMA_DSR_CE (0x40) +#define MCF5282_DMA_DSR_BES (0x20) +#define MCF5282_DMA_DSR_BED (0x10) +#define MCF5282_DMA_DSR_REQ (0x04) +#define MCF5282_DMA_DSR_BSY (0x02) +#define MCF5282_DMA_DSR_DONE (0x01) + +/********************************************************************* +* +* Universal Asychronous Receiver/Transmitter (UART) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x0200])) +#define MCF5282_UART0_USR (*(vuint8 *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x0204])) +#define MCF5282_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x0208])) +#define MCF5282_UART0_URB (*(vuint8 *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x020C])) +#define MCF5282_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x0210])) +#define MCF5282_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x0214])) +#define MCF5282_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x0218])) +#define MCF5282_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x021C])) +#define MCF5282_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x0234])) +#define MCF5282_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x0238])) +#define MCF5282_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x023C])) + +#define MCF5282_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x0240])) +#define MCF5282_UART1_USR (*(vuint8 *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x0244])) +#define MCF5282_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x0248])) +#define MCF5282_UART1_URB (*(vuint8 *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x024C])) +#define MCF5282_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x0250])) +#define MCF5282_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x0254])) +#define MCF5282_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x0258])) +#define MCF5282_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x025C])) +#define MCF5282_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x0274])) +#define MCF5282_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x0278])) +#define MCF5282_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x027C])) + +#define MCF5282_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x0280])) +#define MCF5282_UART2_USR (*(vuint8 *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x0284])) +#define MCF5282_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x0288])) +#define MCF5282_UART2_URB (*(vuint8 *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x028C])) +#define MCF5282_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x0290])) +#define MCF5282_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x0294])) +#define MCF5282_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x0298])) +#define MCF5282_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x029C])) +#define MCF5282_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x02B4])) +#define MCF5282_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x02B8])) +#define MCF5282_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x02BC])) + +#define MCF5282_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x0200+((x)*0x40)])) +#define MCF5282_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) +#define MCF5282_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) +#define MCF5282_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x0208+((x)*0x40)])) +#define MCF5282_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) +#define MCF5282_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) +#define MCF5282_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) +#define MCF5282_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) +#define MCF5282_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) +#define MCF5282_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) +#define MCF5282_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x0218+((x)*0x40)])) +#define MCF5282_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x021C+((x)*0x40)])) +#define MCF5282_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x0234+((x)*0x40)])) +#define MCF5282_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x0238+((x)*0x40)])) +#define MCF5282_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x023C+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_UART_UMR1_RXRTS (0x80) +#define MCF5282_UART_UMR1_RXIRQ (0x40) +#define MCF5282_UART_UMR1_ERR (0x20) +#define MCF5282_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5282_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5282_UART_UMR1_PM_NONE (0x10) +#define MCF5282_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5282_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5282_UART_UMR1_PM_ODD (0x04) +#define MCF5282_UART_UMR1_PM_EVEN (0x00) +#define MCF5282_UART_UMR1_BC_5 (0x00) +#define MCF5282_UART_UMR1_BC_6 (0x01) +#define MCF5282_UART_UMR1_BC_7 (0x02) +#define MCF5282_UART_UMR1_BC_8 (0x03) + +#define MCF5282_UART_UMR2_CM_NORMAL (0x00) +#define MCF5282_UART_UMR2_CM_ECHO (0x40) +#define MCF5282_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5282_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5282_UART_UMR2_TXRTS (0x20) +#define MCF5282_UART_UMR2_TXCTS (0x10) +#define MCF5282_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5282_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5282_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5282_UART_UMR2_STOP_BITS(a) ((a)&0x0f) + +#define MCF5282_UART_USR_RB (0x80) +#define MCF5282_UART_USR_FE (0x40) +#define MCF5282_UART_USR_PE (0x20) +#define MCF5282_UART_USR_OE (0x10) +#define MCF5282_UART_USR_TXEMP (0x08) +#define MCF5282_UART_USR_TXRDY (0x04) +#define MCF5282_UART_USR_FFULL (0x02) +#define MCF5282_UART_USR_RXRDY (0x01) + +#define MCF5282_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF5282_UART_UCSR_RCS_DTIN16 (0xE0) +#define MCF5282_UART_UCSR_RCS_DTIN (0xF0) +#define MCF5282_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF5282_UART_UCSR_TCS_DTIN16 (0x0E) +#define MCF5282_UART_UCSR_TCS_DTIN (0x0F) + +#define MCF5282_UART_UCR_NONE (0x00) +#define MCF5282_UART_UCR_STOP_BREAK (0x70) +#define MCF5282_UART_UCR_START_BREAK (0x60) +#define MCF5282_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5282_UART_UCR_RESET_ERROR (0x40) +#define MCF5282_UART_UCR_RESET_TX (0x30) +#define MCF5282_UART_UCR_RESET_RX (0x20) +#define MCF5282_UART_UCR_RESET_MR (0x10) +#define MCF5282_UART_UCR_TX_DISABLED (0x08) +#define MCF5282_UART_UCR_TX_ENABLED (0x04) +#define MCF5282_UART_UCR_RX_DISABLED (0x02) +#define MCF5282_UART_UCR_RX_ENABLED (0x01) + +#define MCF5282_UART_UIPCR_COS (0x10) +#define MCF5282_UART_UIPCR_CTS (0x01) + +#define MCF5282_UART_UACR_IEC (0x01) + +#define MCF5282_UART_UISR_COS (0x80) +#define MCF5282_UART_UISR_ABC (0x40) +#define MCF5282_UART_UISR_RXFIFO (0x20) +#define MCF5282_UART_UISR_TXFIFO (0x10) +#define MCF5282_UART_UISR_RXFTO (0x08) +#define MCF5282_UART_UISR_DB (0x04) +#define MCF5282_UART_UISR_RXRDY (0x02) +#define MCF5282_UART_UISR_TXRDY (0x01) + +#define MCF5282_UART_UIMR_COS (0x80) +#define MCF5282_UART_UIMR_DB (0x04) +#define MCF5282_UART_UIMR_FFULL (0x02) +#define MCF5282_UART_UIMR_TXRDY (0x01) + +#define MCF5282_UART_UIP_CTS (0x01) + +#define MCF5282_UART_UOP_RTS (0x01) + +/********************************************************************* +* +* Inter-IC (I2C) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x0300])) +#define MCF5282_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x0304])) +#define MCF5282_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x0308])) +#define MCF5282_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x030C])) +#define MCF5282_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x0310])) + +/* Bit level definitions and macros */ +#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF5282_I2C_I2CR_IEN (0x80) +#define MCF5282_I2C_I2CR_IIEN (0x40) +#define MCF5282_I2C_I2CR_MSTA (0x20) +#define MCF5282_I2C_I2CR_MTX (0x10) +#define MCF5282_I2C_I2CR_TXAK (0x08) +#define MCF5282_I2C_I2CR_RSTA (0x04) + +#define MCF5282_I2C_I2SR_ICF (0x80) +#define MCF5282_I2C_I2SR_IAAS (0x40) +#define MCF5282_I2C_I2SR_IBB (0x20) +#define MCF5282_I2C_I2SR_IAL (0x10) +#define MCF5282_I2C_I2SR_SRW (0x04) +#define MCF5282_I2C_I2SR_IIF (0x02) +#define MCF5282_I2C_I2SR_RXAK (0x01) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_QSPI_QMR (*(vuint16 *)(&__IPSBAR[0x0340])) +#define MCF5282_QSPI_QDLYR (*(vuint16 *)(&__IPSBAR[0x0344])) +#define MCF5282_QSPI_QWR (*(vuint16 *)(&__IPSBAR[0x0348])) +#define MCF5282_QSPI_QIR (*(vuint16 *)(&__IPSBAR[0x034C])) +#define MCF5282_QSPI_QAR (*(vuint16 *)(&__IPSBAR[0x0350])) +#define MCF5282_QSPI_QDR (*(vuint16 *)(&__IPSBAR[0x0354])) +#define MCF5282_QSPI_QCR (*(vuint16 *)(&__IPSBAR[0x0354])) + +/* Bit level definitions and macros */ +#define MCF5282_QSPI_QMR_MSTR (0x8000) +#define MCF5282_QSPI_QMR_DOHIE (0x4000) +#define MCF5282_QSPI_QMR_BITS_16 (0x0000) +#define MCF5282_QSPI_QMR_BITS_8 (0x2000) +#define MCF5282_QSPI_QMR_BITS_9 (0x2400) +#define MCF5282_QSPI_QMR_BITS_10 (0x2800) +#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) +#define MCF5282_QSPI_QMR_BITS_12 (0x3000) +#define MCF5282_QSPI_QMR_BITS_13 (0x3400) +#define MCF5282_QSPI_QMR_BITS_14 (0x3800) +#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) +#define MCF5282_QSPI_QMR_CPOL (0x0200) +#define MCF5282_QSPI_QMR_CPHA (0x0100) +#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QDLYR_SPE (0x8000) +#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QWR_HALT (0x8000) +#define MCF5282_QSPI_QWR_WREN (0x4000) +#define MCF5282_QSPI_QWR_WRTO (0x2000) +#define MCF5282_QSPI_QWR_CSIV (0x1000) +#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) +#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) + +#define MCF5282_QSPI_QIR_WCEFB (0x8000) +#define MCF5282_QSPI_QIR_ABRTB (0x4000) +#define MCF5282_QSPI_QIR_ABRTL (0x1000) +#define MCF5282_QSPI_QIR_WCEFE (0x0800) +#define MCF5282_QSPI_QIR_ABRTE (0x0400) +#define MCF5282_QSPI_QIR_SPIFE (0x0100) +#define MCF5282_QSPI_QIR_WCEF (0x0008) +#define MCF5282_QSPI_QIR_ABRT (0x0004) +#define MCF5282_QSPI_QIR_SPIF (0x0001) + +#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) + +#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) + +#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) +#define MCF5282_QSPI_QCR_CONT (0x8000) +#define MCF5282_QSPI_QCR_BITSE (0x4000) +#define MCF5282_QSPI_QCR_DT (0x2000) +#define MCF5282_QSPI_QCR_DSCK (0x1000) +#define MCF5282_QSPI_QCR_CS(x) (((x)&0x000F)<<8) + +/********************************************************************* +* +* DMA Timer Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_TIMER0_DTMR (*(vuint16 *)(&__IPSBAR[0x0400])) +#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(&__IPSBAR[0x0402])) +#define MCF5282_TIMER0_DTER (*(vuint8 *)(&__IPSBAR[0x0403])) +#define MCF5282_TIMER0_DTRR (*(vuint32 *)(&__IPSBAR[0x0404])) +#define MCF5282_TIMER0_DTCR (*(vuint32 *)(&__IPSBAR[0x0408])) +#define MCF5282_TIMER0_DTCN (*(vuint32 *)(&__IPSBAR[0x040C])) + +#define MCF5282_TIMER1_DTMR (*(vuint16 *)(&__IPSBAR[0x0440])) +#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(&__IPSBAR[0x0442])) +#define MCF5282_TIMER1_DTER (*(vuint8 *)(&__IPSBAR[0x0443])) +#define MCF5282_TIMER1_DTRR (*(vuint32 *)(&__IPSBAR[0x0444])) +#define MCF5282_TIMER1_DTCR (*(vuint32 *)(&__IPSBAR[0x0448])) +#define MCF5282_TIMER1_DTCN (*(vuint32 *)(&__IPSBAR[0x044C])) + +#define MCF5282_TIMER2_DTMR (*(vuint16 *)(&__IPSBAR[0x0480])) +#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(&__IPSBAR[0x0482])) +#define MCF5282_TIMER2_DTER (*(vuint8 *)(&__IPSBAR[0x0483])) +#define MCF5282_TIMER2_DTRR (*(vuint32 *)(&__IPSBAR[0x0484])) +#define MCF5282_TIMER2_DTCR (*(vuint32 *)(&__IPSBAR[0x0488])) +#define MCF5282_TIMER2_DTCN (*(vuint32 *)(&__IPSBAR[0x048C])) + +#define MCF5282_TIMER3_DTMR (*(vuint16 *)(&__IPSBAR[0x04C0])) +#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(&__IPSBAR[0x04C2])) +#define MCF5282_TIMER3_DTER (*(vuint8 *)(&__IPSBAR[0x04C3])) +#define MCF5282_TIMER3_DTRR (*(vuint32 *)(&__IPSBAR[0x04C4])) +#define MCF5282_TIMER3_DTCR (*(vuint32 *)(&__IPSBAR[0x04C8])) +#define MCF5282_TIMER3_DTCN (*(vuint32 *)(&__IPSBAR[0x04CC])) + +#define MCF5282_TIMER_DTMR(x) (*(vuint16 *)(&__IPSBAR[0x0400+((x)*0x40)])) +#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x0402+((x)*0x40)])) +#define MCF5282_TIMER_DTER(x) (*(vuint8 *)(&__IPSBAR[0x0403+((x)*0x40)])) +#define MCF5282_TIMER_DTRR(x) (*(vuint32 *)(&__IPSBAR[0x0404+((x)*0x40)])) +#define MCF5282_TIMER_DTCR(x) (*(vuint32 *)(&__IPSBAR[0x0408+((x)*0x40)])) +#define MCF5282_TIMER_DTCN(x) (*(vuint32 *)(&__IPSBAR[0x040C+((x)*0x40)])) + +/* Bit level definitions and macros */ +#define MCF5282_TIMER_DTMR_PS(a) (((a)&0x00FF)<<8) +#define MCF5282_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF5282_TIMER_DTMR_CE_FALL (0x0080) +#define MCF5282_TIMER_DTMR_CE_RISE (0x0040) +#define MCF5282_TIMER_DTMR_CE_NONE (0x0000) +#define MCF5282_TIMER_DTMR_OM (0x0020) +#define MCF5282_TIMER_DTMR_ORRI (0x0010) +#define MCF5282_TIMER_DTMR_FRR (0x0008) +#define MCF5282_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF5282_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF5282_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF5282_TIMER_DTMR_CLK_STOP (0x0000) +#define MCF5282_TIMER_DTMR_RST (0x0001) + +#define MCF5282_TIMER_DTXMR_DMAEN (0x80) +#define MCF5282_TIMER_DTXMR_MODE16 (0x01) + +#define MCF5282_TIMER_DTER_REF (0x02) +#define MCF5282_TIMER_DTER_CAP (0x01) + +/********************************************************************* +* +* Interrupt Controller (INTC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_INTC0_IPRH (*(vuint32 *)(&__IPSBAR[0x0C00])) +#define MCF5282_INTC0_IPRL (*(vuint32 *)(&__IPSBAR[0x0C04])) +#define MCF5282_INTC0_IMRH (*(vuint32 *)(&__IPSBAR[0x0C08])) +#define MCF5282_INTC0_IMRL (*(vuint32 *)(&__IPSBAR[0x0C0C])) +#define MCF5282_INTC0_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0C10])) +#define MCF5282_INTC0_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0C14])) +#define MCF5282_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x0C18])) +#define MCF5282_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0C19])) +#define MCF5282_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x0C41])) +#define MCF5282_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x0C42])) +#define MCF5282_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x0C43])) +#define MCF5282_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x0C44])) +#define MCF5282_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x0C45])) +#define MCF5282_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x0C46])) +#define MCF5282_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x0C47])) +#define MCF5282_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x0C48])) +#define MCF5282_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x0C49])) +#define MCF5282_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x0C4A])) +#define MCF5282_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x0C4B])) +#define MCF5282_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x0C4C])) +#define MCF5282_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x0C4D])) +#define MCF5282_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x0C4E])) +#define MCF5282_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x0C4F])) +#define MCF5282_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x0C51])) +#define MCF5282_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x0C52])) +#define MCF5282_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x0C53])) +#define MCF5282_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x0C54])) +#define MCF5282_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x0C55])) +#define MCF5282_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x0C56])) +#define MCF5282_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x0C57])) +#define MCF5282_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x0C58])) +#define MCF5282_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x0C59])) +#define MCF5282_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x0C5A])) +#define MCF5282_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x0C5B])) +#define MCF5282_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x0C5C])) +#define MCF5282_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x0C5D])) +#define MCF5282_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x0C5E])) +#define MCF5282_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x0C5F])) +#define MCF5282_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x0C60])) +#define MCF5282_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x0C61])) +#define MCF5282_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x0C62])) +#define MCF5282_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x0C63])) +#define MCF5282_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x0C64])) +#define MCF5282_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x0C65])) +#define MCF5282_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x0C66])) +#define MCF5282_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x0C67])) +#define MCF5282_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x0C68])) +#define MCF5282_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x0C69])) +#define MCF5282_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x0C6A])) +#define MCF5282_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x0C6B])) +#define MCF5282_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x0C6C])) +#define MCF5282_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x0C6D])) +#define MCF5282_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x0C6E])) +#define MCF5282_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x0C6F])) +#define MCF5282_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x0C70])) +#define MCF5282_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x0C71])) +#define MCF5282_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x0C72])) +#define MCF5282_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x0C73])) +#define MCF5282_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x0C74])) +#define MCF5282_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x0C75])) +#define MCF5282_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x0C76])) +#define MCF5282_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x0C77])) +#define MCF5282_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x0C78])) +#define MCF5282_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x0C79])) +#define MCF5282_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x0C7A])) +#define MCF5282_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x0C7B])) +#define MCF5282_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x0C7C])) +#define MCF5282_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x0C7D])) +#define MCF5282_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x0C7E])) +#define MCF5282_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x0CE0])) +#define MCF5282_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x0CE4])) +#define MCF5282_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x0CE8])) +#define MCF5282_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x0CEC])) +#define MCF5282_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x0CF0])) +#define MCF5282_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x0CF4])) +#define MCF5282_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x0CF8])) +#define MCF5282_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x0CFC])) + +#define MCF5282_INTC1_IPRH (*(vuint32 *)(&__IPSBAR[0x0D00])) +#define MCF5282_INTC1_IPRL (*(vuint32 *)(&__IPSBAR[0x0D04])) +#define MCF5282_INTC1_IMRH (*(vuint32 *)(&__IPSBAR[0x0D08])) +#define MCF5282_INTC1_IMRL (*(vuint32 *)(&__IPSBAR[0x0D0C])) +#define MCF5282_INTC1_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0D10])) +#define MCF5282_INTC1_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0D14])) +#define MCF5282_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x0D18])) +#define MCF5282_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0D19])) +#define MCF5282_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0x0D48])) +#define MCF5282_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0x0D49])) +#define MCF5282_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x0D4A])) +#define MCF5282_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x0D4B])) +#define MCF5282_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x0D4C])) +#define MCF5282_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x0D4D])) +#define MCF5282_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x0D4E])) +#define MCF5282_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x0D4F])) +#define MCF5282_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x0D50])) +#define MCF5282_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x0D51])) +#define MCF5282_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x0D52])) +#define MCF5282_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x0D53])) +#define MCF5282_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x0D54])) +#define MCF5282_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x0D55])) +#define MCF5282_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x0D56])) +#define MCF5282_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x0D57])) +#define MCF5282_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x0D58])) +#define MCF5282_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x0D59])) +#define MCF5282_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x0D5A])) +#define MCF5282_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x0DE0])) +#define MCF5282_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x0DE4])) +#define MCF5282_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x0DE8])) +#define MCF5282_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x0DEC])) +#define MCF5282_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x0DF0])) +#define MCF5282_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x0DF4])) +#define MCF5282_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x0DF8])) +#define MCF5282_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x0DFC])) + +/* Bit level definitions and macros */ +#define MCF5282_INTC_IPRH_INT63 (0x80000000) +#define MCF5282_INTC_IPRH_INT62 (0x40000000) +#define MCF5282_INTC_IPRH_INT61 (0x20000000) +#define MCF5282_INTC_IPRH_INT60 (0x10000000) +#define MCF5282_INTC_IPRH_INT59 (0x08000000) +#define MCF5282_INTC_IPRH_INT58 (0x04000000) +#define MCF5282_INTC_IPRH_INT57 (0x02000000) +#define MCF5282_INTC_IPRH_INT56 (0x01000000) +#define MCF5282_INTC_IPRH_INT55 (0x00800000) +#define MCF5282_INTC_IPRH_INT54 (0x00400000) +#define MCF5282_INTC_IPRH_INT53 (0x00200000) +#define MCF5282_INTC_IPRH_INT52 (0x00100000) +#define MCF5282_INTC_IPRH_INT51 (0x00080000) +#define MCF5282_INTC_IPRH_INT50 (0x00040000) +#define MCF5282_INTC_IPRH_INT49 (0x00020000) +#define MCF5282_INTC_IPRH_INT48 (0x00010000) +#define MCF5282_INTC_IPRH_INT47 (0x00008000) +#define MCF5282_INTC_IPRH_INT46 (0x00004000) +#define MCF5282_INTC_IPRH_INT45 (0x00002000) +#define MCF5282_INTC_IPRH_INT44 (0x00001000) +#define MCF5282_INTC_IPRH_INT43 (0x00000800) +#define MCF5282_INTC_IPRH_INT42 (0x00000400) +#define MCF5282_INTC_IPRH_INT41 (0x00000200) +#define MCF5282_INTC_IPRH_INT40 (0x00000100) +#define MCF5282_INTC_IPRH_INT39 (0x00000080) +#define MCF5282_INTC_IPRH_INT38 (0x00000040) +#define MCF5282_INTC_IPRH_INT37 (0x00000020) +#define MCF5282_INTC_IPRH_INT36 (0x00000010) +#define MCF5282_INTC_IPRH_INT35 (0x00000008) +#define MCF5282_INTC_IPRH_INT34 (0x00000004) +#define MCF5282_INTC_IPRH_INT33 (0x00000002) +#define MCF5282_INTC_IPRH_INT32 (0x00000001) + +#define MCF5282_INTC_IPRL_INT31 (0x80000000) +#define MCF5282_INTC_IPRL_INT30 (0x40000000) +#define MCF5282_INTC_IPRL_INT29 (0x20000000) +#define MCF5282_INTC_IPRL_INT28 (0x10000000) +#define MCF5282_INTC_IPRL_INT27 (0x08000000) +#define MCF5282_INTC_IPRL_INT26 (0x04000000) +#define MCF5282_INTC_IPRL_INT25 (0x02000000) +#define MCF5282_INTC_IPRL_INT24 (0x01000000) +#define MCF5282_INTC_IPRL_INT23 (0x00800000) +#define MCF5282_INTC_IPRL_INT22 (0x00400000) +#define MCF5282_INTC_IPRL_INT21 (0x00200000) +#define MCF5282_INTC_IPRL_INT20 (0x00100000) +#define MCF5282_INTC_IPRL_INT19 (0x00080000) +#define MCF5282_INTC_IPRL_INT18 (0x00040000) +#define MCF5282_INTC_IPRL_INT17 (0x00020000) +#define MCF5282_INTC_IPRL_INT16 (0x00010000) +#define MCF5282_INTC_IPRL_INT15 (0x00008000) +#define MCF5282_INTC_IPRL_INT14 (0x00004000) +#define MCF5282_INTC_IPRL_INT13 (0x00002000) +#define MCF5282_INTC_IPRL_INT12 (0x00001000) +#define MCF5282_INTC_IPRL_INT11 (0x00000800) +#define MCF5282_INTC_IPRL_INT10 (0x00000400) +#define MCF5282_INTC_IPRL_INT9 (0x00000200) +#define MCF5282_INTC_IPRL_INT8 (0x00000100) +#define MCF5282_INTC_IPRL_INT7 (0x00000080) +#define MCF5282_INTC_IPRL_INT6 (0x00000040) +#define MCF5282_INTC_IPRL_INT5 (0x00000020) +#define MCF5282_INTC_IPRL_INT4 (0x00000010) +#define MCF5282_INTC_IPRL_INT3 (0x00000008) +#define MCF5282_INTC_IPRL_INT2 (0x00000004) +#define MCF5282_INTC_IPRL_INT1 (0x00000002) + +#define MCF5282_INTC_IMRH_INT63 (0x80000000) +#define MCF5282_INTC_IMRH_INT62 (0x40000000) +#define MCF5282_INTC_IMRH_INT61 (0x20000000) +#define MCF5282_INTC_IMRH_INT60 (0x10000000) +#define MCF5282_INTC_IMRH_INT59 (0x08000000) +#define MCF5282_INTC_IMRH_INT58 (0x04000000) +#define MCF5282_INTC_IMRH_INT57 (0x02000000) +#define MCF5282_INTC_IMRH_INT56 (0x01000000) +#define MCF5282_INTC_IMRH_INT55 (0x00800000) +#define MCF5282_INTC_IMRH_INT54 (0x00400000) +#define MCF5282_INTC_IMRH_INT53 (0x00200000) +#define MCF5282_INTC_IMRH_INT52 (0x00100000) +#define MCF5282_INTC_IMRH_INT51 (0x00080000) +#define MCF5282_INTC_IMRH_INT50 (0x00040000) +#define MCF5282_INTC_IMRH_INT49 (0x00020000) +#define MCF5282_INTC_IMRH_INT48 (0x00010000) +#define MCF5282_INTC_IMRH_INT47 (0x00008000) +#define MCF5282_INTC_IMRH_INT46 (0x00004000) +#define MCF5282_INTC_IMRH_INT45 (0x00002000) +#define MCF5282_INTC_IMRH_INT44 (0x00001000) +#define MCF5282_INTC_IMRH_INT43 (0x00000800) +#define MCF5282_INTC_IMRH_INT42 (0x00000400) +#define MCF5282_INTC_IMRH_INT41 (0x00000200) +#define MCF5282_INTC_IMRH_INT40 (0x00000100) +#define MCF5282_INTC_IMRH_INT39 (0x00000080) +#define MCF5282_INTC_IMRH_INT38 (0x00000040) +#define MCF5282_INTC_IMRH_INT37 (0x00000020) +#define MCF5282_INTC_IMRH_INT36 (0x00000010) +#define MCF5282_INTC_IMRH_INT35 (0x00000008) +#define MCF5282_INTC_IMRH_INT34 (0x00000004) +#define MCF5282_INTC_IMRH_INT33 (0x00000002) +#define MCF5282_INTC_IMRH_INT32 (0x00000001) + +#define MCF5282_INTC_IMRL_INT31 (0x80000000) +#define MCF5282_INTC_IMRL_INT30 (0x40000000) +#define MCF5282_INTC_IMRL_INT29 (0x20000000) +#define MCF5282_INTC_IMRL_INT28 (0x10000000) +#define MCF5282_INTC_IMRL_INT27 (0x08000000) +#define MCF5282_INTC_IMRL_INT26 (0x04000000) +#define MCF5282_INTC_IMRL_INT25 (0x02000000) +#define MCF5282_INTC_IMRL_INT24 (0x01000000) +#define MCF5282_INTC_IMRL_INT23 (0x00800000) +#define MCF5282_INTC_IMRL_INT22 (0x00400000) +#define MCF5282_INTC_IMRL_INT21 (0x00200000) +#define MCF5282_INTC_IMRL_INT20 (0x00100000) +#define MCF5282_INTC_IMRL_INT19 (0x00080000) +#define MCF5282_INTC_IMRL_INT18 (0x00040000) +#define MCF5282_INTC_IMRL_INT17 (0x00020000) +#define MCF5282_INTC_IMRL_INT16 (0x00010000) +#define MCF5282_INTC_IMRL_INT15 (0x00008000) +#define MCF5282_INTC_IMRL_INT14 (0x00004000) +#define MCF5282_INTC_IMRL_INT13 (0x00002000) +#define MCF5282_INTC_IMRL_INT12 (0x00001000) +#define MCF5282_INTC_IMRL_INT11 (0x00000800) +#define MCF5282_INTC_IMRL_INT10 (0x00000400) +#define MCF5282_INTC_IMRL_INT9 (0x00000200) +#define MCF5282_INTC_IMRL_INT8 (0x00000100) +#define MCF5282_INTC_IMRL_INT7 (0x00000080) +#define MCF5282_INTC_IMRL_INT6 (0x00000040) +#define MCF5282_INTC_IMRL_INT5 (0x00000020) +#define MCF5282_INTC_IMRL_INT4 (0x00000010) +#define MCF5282_INTC_IMRL_INT3 (0x00000008) +#define MCF5282_INTC_IMRL_INT2 (0x00000004) +#define MCF5282_INTC_IMRL_INT1 (0x00000002) +#define MCF5282_INTC_IMRL_MASKALL (0x00000001) + +#define MCF5282_INTC_INTFRCH_INT63 (0x80000000) +#define MCF5282_INTC_INTFRCH_INT62 (0x40000000) +#define MCF5282_INTC_INTFRCH_INT61 (0x20000000) +#define MCF5282_INTC_INTFRCH_INT60 (0x10000000) +#define MCF5282_INTC_INTFRCH_INT59 (0x08000000) +#define MCF5282_INTC_INTFRCH_INT58 (0x04000000) +#define MCF5282_INTC_INTFRCH_INT57 (0x02000000) +#define MCF5282_INTC_INTFRCH_INT56 (0x01000000) +#define MCF5282_INTC_INTFRCH_INT55 (0x00800000) +#define MCF5282_INTC_INTFRCH_INT54 (0x00400000) +#define MCF5282_INTC_INTFRCH_INT53 (0x00200000) +#define MCF5282_INTC_INTFRCH_INT52 (0x00100000) +#define MCF5282_INTC_INTFRCH_INT51 (0x00080000) +#define MCF5282_INTC_INTFRCH_INT50 (0x00040000) +#define MCF5282_INTC_INTFRCH_INT49 (0x00020000) +#define MCF5282_INTC_INTFRCH_INT48 (0x00010000) +#define MCF5282_INTC_INTFRCH_INT47 (0x00008000) +#define MCF5282_INTC_INTFRCH_INT46 (0x00004000) +#define MCF5282_INTC_INTFRCH_INT45 (0x00002000) +#define MCF5282_INTC_INTFRCH_INT44 (0x00001000) +#define MCF5282_INTC_INTFRCH_INT43 (0x00000800) +#define MCF5282_INTC_INTFRCH_INT42 (0x00000400) +#define MCF5282_INTC_INTFRCH_INT41 (0x00000200) +#define MCF5282_INTC_INTFRCH_INT40 (0x00000100) +#define MCF5282_INTC_INTFRCH_INT39 (0x00000080) +#define MCF5282_INTC_INTFRCH_INT38 (0x00000040) +#define MCF5282_INTC_INTFRCH_INT37 (0x00000020) +#define MCF5282_INTC_INTFRCH_INT36 (0x00000010) +#define MCF5282_INTC_INTFRCH_INT35 (0x00000008) +#define MCF5282_INTC_INTFRCH_INT34 (0x00000004) +#define MCF5282_INTC_INTFRCH_INT33 (0x00000002) +#define MCF5282_INTC_INTFRCH_INT32 (0x00000001) + +#define MCF5282_INTC_INTFRCL_INT31 (0x80000000) +#define MCF5282_INTC_INTFRCL_INT30 (0x40000000) +#define MCF5282_INTC_INTFRCL_INT29 (0x20000000) +#define MCF5282_INTC_INTFRCL_INT28 (0x10000000) +#define MCF5282_INTC_INTFRCL_INT27 (0x08000000) +#define MCF5282_INTC_INTFRCL_INT26 (0x04000000) +#define MCF5282_INTC_INTFRCL_INT25 (0x02000000) +#define MCF5282_INTC_INTFRCL_INT24 (0x01000000) +#define MCF5282_INTC_INTFRCL_INT23 (0x00800000) +#define MCF5282_INTC_INTFRCL_INT22 (0x00400000) +#define MCF5282_INTC_INTFRCL_INT21 (0x00200000) +#define MCF5282_INTC_INTFRCL_INT20 (0x00100000) +#define MCF5282_INTC_INTFRCL_INT19 (0x00080000) +#define MCF5282_INTC_INTFRCL_INT18 (0x00040000) +#define MCF5282_INTC_INTFRCL_INT17 (0x00020000) +#define MCF5282_INTC_INTFRCL_INT16 (0x00010000) +#define MCF5282_INTC_INTFRCL_INT15 (0x00008000) +#define MCF5282_INTC_INTFRCL_INT14 (0x00004000) +#define MCF5282_INTC_INTFRCL_INT13 (0x00002000) +#define MCF5282_INTC_INTFRCL_INT12 (0x00001000) +#define MCF5282_INTC_INTFRCL_INT11 (0x00000800) +#define MCF5282_INTC_INTFRCL_INT10 (0x00000400) +#define MCF5282_INTC_INTFRCL_INT9 (0x00000200) +#define MCF5282_INTC_INTFRCL_INT8 (0x00000100) +#define MCF5282_INTC_INTFRCL_INT7 (0x00000080) +#define MCF5282_INTC_INTFRCL_INT6 (0x00000040) +#define MCF5282_INTC_INTFRCL_INT5 (0x00000020) +#define MCF5282_INTC_INTFRCL_INT4 (0x00000010) +#define MCF5282_INTC_INTFRCL_INT3 (0x00000008) +#define MCF5282_INTC_INTFRCL_INT2 (0x00000004) +#define MCF5282_INTC_INTFRCL_INT1 (0x00000002) + +#define MCF5282_INTC_IRLR_IRQ7 (0x80) +#define MCF5282_INTC_IRLR_IRQ6 (0x40) +#define MCF5282_INTC_IRLR_IRQ5 (0x20) +#define MCF5282_INTC_IRLR_IRQ4 (0x10) +#define MCF5282_INTC_IRLR_IRQ3 (0x08) +#define MCF5282_INTC_IRLR_IRQ2 (0x04) +#define MCF5282_INTC_IRLR_IRQ1 (0x02) + +#define MCF5282_INTC_ICR_IL(x) (((x)&0x07)<<3) +#define MCF5282_INTC_ICR_IP(x) (((x)&0x07)<<0) + +/********************************************************************* +* +* Global Interrupt Acknowledge Cycle (GIAC) Registers +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GIAC_GSWIACK (*(vuint8 *)(&__IPSBAR[0x0FE0])) +#define MCF5282_GIAC_GL1IACK (*(vuint8 *)(&__IPSBAR[0x0FE4])) +#define MCF5282_GIAC_GL2IACK (*(vuint8 *)(&__IPSBAR[0x0FE8])) +#define MCF5282_GIAC_GL3IACK (*(vuint8 *)(&__IPSBAR[0x0FEC])) +#define MCF5282_GIAC_GL4IACK (*(vuint8 *)(&__IPSBAR[0x0FF0])) +#define MCF5282_GIAC_GL5IACK (*(vuint8 *)(&__IPSBAR[0x0FF4])) +#define MCF5282_GIAC_GL6IACK (*(vuint8 *)(&__IPSBAR[0x0FF8])) +#define MCF5282_GIAC_GL7IACK (*(vuint8 *)(&__IPSBAR[0x0FFC])) + +/* Bit level definitions and macros */ + +/* To do - add bit level definintions */ + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_FEC_EIR (*(vuint32 *)(&__IPSBAR[0x1004])) +#define MCF5282_FEC_EIMR (*(vuint32 *)(&__IPSBAR[0x1008])) +#define MCF5282_FEC_RDAR (*(vuint32 *)(&__IPSBAR[0x1010])) +#define MCF5282_FEC_TDAR (*(vuint32 *)(&__IPSBAR[0x1014])) +#define MCF5282_FEC_ECR (*(vuint32 *)(&__IPSBAR[0x1024])) +#define MCF5282_FEC_MMFR (*(vuint32 *)(&__IPSBAR[0x1040])) +#define MCF5282_FEC_MSCR (*(vuint32 *)(&__IPSBAR[0x1044])) +#define MCF5282_FEC_MIBC (*(vuint32 *)(&__IPSBAR[0x1064])) +#define MCF5282_FEC_RCR (*(vuint32 *)(&__IPSBAR[0x1084])) +#define MCF5282_FEC_TCR (*(vuint32 *)(&__IPSBAR[0x10C4])) +#define MCF5282_FEC_PALR (*(vuint32 *)(&__IPSBAR[0x10E4])) +#define MCF5282_FEC_PAUR (*(vuint32 *)(&__IPSBAR[0x10E8])) +#define MCF5282_FEC_OPD (*(vuint32 *)(&__IPSBAR[0x10EC])) +#define MCF5282_FEC_IAUR (*(vuint32 *)(&__IPSBAR[0x1118])) +#define MCF5282_FEC_IALR (*(vuint32 *)(&__IPSBAR[0x111C])) +#define MCF5282_FEC_GAUR (*(vuint32 *)(&__IPSBAR[0x1120])) +#define MCF5282_FEC_GALR (*(vuint32 *)(&__IPSBAR[0x1124])) +#define MCF5282_FEC_TFWR (*(vuint32 *)(&__IPSBAR[0x1144])) +#define MCF5282_FEC_FRBR (*(vuint32 *)(&__IPSBAR[0x114C])) +#define MCF5282_FEC_FRSR (*(vuint32 *)(&__IPSBAR[0x1150])) +#define MCF5282_FEC_ERDSR (*(vuint32 *)(&__IPSBAR[0x1180])) +#define MCF5282_FEC_ETDSR (*(vuint32 *)(&__IPSBAR[0x1184])) +#define MCF5282_FEC_EMRBR (*(vuint32 *)(&__IPSBAR[0x1188])) + +#define MCF5282_FEC_RMON_T_DROP (*(vuint32 *)(&__IPSBAR[0x1200])) +#define MCF5282_FEC_RMON_T_PACKETS (*(vuint32 *)(&__IPSBAR[0x1204])) +#define MCF5282_FEC_RMON_T_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1208])) +#define MCF5282_FEC_RMON_T_MC_PKT (*(vuint32 *)(&__IPSBAR[0x120C])) +#define MCF5282_FEC_RMON_T_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1210])) +#define MCF5282_FEC_RMON_T_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1214])) +#define MCF5282_FEC_RMON_T_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1218])) +#define MCF5282_FEC_RMON_T_FRAG (*(vuint32 *)(&__IPSBAR[0x121C])) +#define MCF5282_FEC_RMON_T_JAB (*(vuint32 *)(&__IPSBAR[0x1220])) +#define MCF5282_FEC_RMON_T_COL (*(vuint32 *)(&__IPSBAR[0x1224])) +#define MCF5282_FEC_RMON_T_P64 (*(vuint32 *)(&__IPSBAR[0x1228])) +#define MCF5282_FEC_RMON_T_P65TO127 (*(vuint32 *)(&__IPSBAR[0x122C])) +#define MCF5282_FEC_RMON_T_P128TO255 (*(vuint32 *)(&__IPSBAR[0x1230])) +#define MCF5282_FEC_RMON_T_P256TO511 (*(vuint32 *)(&__IPSBAR[0x1234])) +#define MCF5282_FEC_RMON_T_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x1238])) +#define MCF5282_FEC_RMON_T_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x123C])) +#define MCF5282_FEC_RMON_T_P_GTE2048 (*(vuint32 *)(&__IPSBAR[0x1240])) +#define MCF5282_FEC_RMON_T_OCTETS (*(vuint32 *)(&__IPSBAR[0x1244])) +#define MCF5282_FEC_IEEE_T_DROP (*(vuint32 *)(&__IPSBAR[0x1248])) +#define MCF5282_FEC_IEEE_T_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x124C])) +#define MCF5282_FEC_IEEE_T_1COL (*(vuint32 *)(&__IPSBAR[0x1250])) +#define MCF5282_FEC_IEEE_T_MCOL (*(vuint32 *)(&__IPSBAR[0x1254])) +#define MCF5282_FEC_IEEE_T_DEF (*(vuint32 *)(&__IPSBAR[0x1258])) +#define MCF5282_FEC_IEEE_T_LCOL (*(vuint32 *)(&__IPSBAR[0x125C])) +#define MCF5282_FEC_IEEE_T_EXCOL (*(vuint32 *)(&__IPSBAR[0x1260])) +#define MCF5282_FEC_IEEE_T_MACERR (*(vuint32 *)(&__IPSBAR[0x1264])) +#define MCF5282_FEC_IEEE_T_CSERR (*(vuint32 *)(&__IPSBAR[0x1268])) +#define MCF5282_FEC_IEEE_T_SQE (*(vuint32 *)(&__IPSBAR[0x126C])) +#define MCF5282_FEC_IEEE_T_FDXFC (*(vuint32 *)(&__IPSBAR[0x1270])) +#define MCF5282_FEC_IEEE_T_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x1274])) +#define MCF5282_FEC_RMON_R_PACKETS (*(vuint32 *)(&__IPSBAR[0x1284])) +#define MCF5282_FEC_RMON_R_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1288])) +#define MCF5282_FEC_RMON_R_MC_PKT (*(vuint32 *)(&__IPSBAR[0x128C])) +#define MCF5282_FEC_RMON_R_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1290])) +#define MCF5282_FEC_RMON_R_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1294])) +#define MCF5282_FEC_RMON_R_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1298])) +#define MCF5282_FEC_RMON_R_FRAG (*(vuint32 *)(&__IPSBAR[0x129C])) +#define MCF5282_FEC_RMON_R_JAB (*(vuint32 *)(&__IPSBAR[0x12A0])) +#define MCF5282_FEC_RMON_R_RESVD_0 (*(vuint32 *)(&__IPSBAR[0x12A4])) +#define MCF5282_FEC_RMON_R_P64 (*(vuint32 *)(&__IPSBAR[0x12A8])) +#define MCF5282_FEC_RMON_R_P65T0127 (*(vuint32 *)(&__IPSBAR[0x12AC])) +#define MCF5282_FEC_RMON_R_P128TO255 (*(vuint32 *)(&__IPSBAR[0x12B0])) +#define MCF5282_FEC_RMON_R_P256TO511 (*(vuint32 *)(&__IPSBAR[0x12B4])) +#define MCF5282_FEC_RMON_R_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x12B8])) +#define MCF5282_FEC_RMON_R_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x12BC])) +#define MCF5282_FEC_RMON_R_GTE2048 (*(vuint32 *)(&__IPSBAR[0x12C0])) +#define MCF5282_FEC_RMON_R_OCTETS (*(vuint32 *)(&__IPSBAR[0x12C4])) +#define MCF5282_FEC_IEEE_R_DROP (*(vuint32 *)(&__IPSBAR[0x12C8])) +#define MCF5282_FEC_IEEE_R_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x12CC])) +#define MCF5282_FEC_IEEE_R_CRC (*(vuint32 *)(&__IPSBAR[0x12D0])) +#define MCF5282_FEC_IEEE_R_ALIGN (*(vuint32 *)(&__IPSBAR[0x12D4])) +#define MCF5282_FEC_IEEE_R_MACERR (*(vuint32 *)(&__IPSBAR[0x12D8])) +#define MCF5282_FEC_IEEE_R_FDXFC (*(vuint32 *)(&__IPSBAR[0x12DC])) +#define MCF5282_FEC_IEEE_R_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x12E0])) + +/* Bit level definitions and macros */ +#define MCF5282_FEC_EIR_HBERR (0x80000000) +#define MCF5282_FEC_EIR_BABR (0x40000000) +#define MCF5282_FEC_EIR_BABT (0x20000000) +#define MCF5282_FEC_EIR_GRA (0x10000000) +#define MCF5282_FEC_EIR_TXF (0x08000000) +#define MCF5282_FEC_EIR_TXB (0x04000000) +#define MCF5282_FEC_EIR_RXF (0x02000000) +#define MCF5282_FEC_EIR_RXB (0x01000000) +#define MCF5282_FEC_EIR_MII (0x00800000) +#define MCF5282_FEC_EIR_EBERR (0x00400000) +#define MCF5282_FEC_EIR_LC (0x00200000) +#define MCF5282_FEC_EIR_RL (0x00100000) +#define MCF5282_FEC_EIR_UN (0x00080000) + +#define MCF5282_FEC_EIMR_HBERR (0x80000000) +#define MCF5282_FEC_EIMR_BABR (0x40000000) +#define MCF5282_FEC_EIMR_BABT (0x20000000) +#define MCF5282_FEC_EIMR_GRA (0x10000000) +#define MCF5282_FEC_EIMR_TXF (0x08000000) +#define MCF5282_FEC_EIMR_TXB (0x04000000) +#define MCF5282_FEC_EIMR_RXF (0x02000000) +#define MCF5282_FEC_EIMR_RXB (0x01000000) +#define MCF5282_FEC_EIMR_MII (0x00800000) +#define MCF5282_FEC_EIMR_EBERR (0x00400000) +#define MCF5282_FEC_EIMR_LC (0x00200000) +#define MCF5282_FEC_EIMR_RL (0x00100000) +#define MCF5282_FEC_EIMR_UN (0x00080000) + +#define MCF5282_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +#define MCF5282_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5282_FEC_ECR_RESET (0x00000001) + +#define MCF5282_FEC_MMFR_ST (0x40000000) +#define MCF5282_FEC_MMFR_OP_RD (0x20000000) +#define MCF5282_FEC_MMFR_OP_WR (0x10000000) +#define MCF5282_FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define MCF5282_FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define MCF5282_FEC_MMFR_TA (0x00020000) +#define MCF5282_FEC_MMFR_DATA(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_MSCR_DIS_PREAMBLE (0x00000008) +#define MCF5282_FEC_MSCR_MII_SPEED(x) (((x)&0x1F)<<1) + +#define MCF5282_FEC_MIBC_MIB_DISABLE (0x80000000) +#define MCF5282_FEC_MIBC_MIB_IDLE (0x40000000) + +#define MCF5282_FEC_RCR_MAX_FL(x) (((x)&0x07FF)<<16) +#define MCF5282_FEC_RCR_FCE (0x00000020) +#define MCF5282_FEC_RCR_BC_REJ (0x00000010) +#define MCF5282_FEC_RCR_PROM (0x00000008) +#define MCF5282_FEC_RCR_MII_MODE (0x00000004) +#define MCF5282_FEC_RCR_DRT (0x00000002) +#define MCF5282_FEC_RCR_LOOP (0x00000001) + +#define MCF5282_FEC_TCR_RFC_PAUSE (0x00000010) +#define MCF5282_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF5282_FEC_TCR_FDEN (0x00000004) +#define MCF5282_FEC_TCR_HBC (0x00000002) +#define MCF5282_FEC_TCR_GTS (0x00000001) + +#define MCF5282_FEC_PALR_BYTE0(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PALR_BYTE1(x) (((x)&0xFF)<<16) +#define MCF5282_FEC_PALR_BYTE2(x) (((x)&0xFF)<<8) +#define MCF5282_FEC_PALR_BYTE3(x) (((x)&0xFF)) + +#define MCF5282_FEC_PAUR_BYTE4(x) (((x)&0xFF)<<24) +#define MCF5282_FEC_PAUR_BYTE5(x) (((x)&0xFF)<<16) + +#define MCF5282_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)) + +#define MCF5282_FEC_TFWR_X_WMRK_64 (0x00000001) +#define MCF5282_FEC_TFWR_X_WMRK_128 (0x00000002) +#define MCF5282_FEC_TFWR_X_WMRK_192 (0x00000003) + +#define MCF5282_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define MCF5282_FEC_TxBD_R 0x8000 +#define MCF5282_FEC_TxBD_BUSY 0x4000 +#define MCF5282_FEC_TxBD_TO1 0x4000 +#define MCF5282_FEC_TxBD_W 0x2000 +#define MCF5282_FEC_TxBD_TO2 0x1000 +#define MCF5282_FEC_TxBD_FIRST 0x1000 +#define MCF5282_FEC_TxBD_L 0x0800 +#define MCF5282_FEC_TxBD_TC 0x0400 +#define MCF5282_FEC_TxBD_DEF 0x0200 +#define MCF5282_FEC_TxBD_HB 0x0100 +#define MCF5282_FEC_TxBD_LC 0x0080 +#define MCF5282_FEC_TxBD_RL 0x0040 +#define MCF5282_FEC_TxBD_UN 0x0002 +#define MCF5282_FEC_TxBD_CSL 0x0001 + +#define MCF5282_FEC_RxBD_E 0x8000 +#define MCF5282_FEC_RxBD_INUSE 0x4000 +#define MCF5282_FEC_RxBD_R01 0x4000 +#define MCF5282_FEC_RxBD_W 0x2000 +#define MCF5282_FEC_RxBD_R02 0x1000 +#define MCF5282_FEC_RxBD_L 0x0800 +#define MCF5282_FEC_RxBD_M 0x0100 +#define MCF5282_FEC_RxBD_BC 0x0080 +#define MCF5282_FEC_RxBD_MC 0x0040 +#define MCF5282_FEC_RxBD_LG 0x0020 +#define MCF5282_FEC_RxBD_NO 0x0010 +#define MCF5282_FEC_RxBD_CR 0x0004 +#define MCF5282_FEC_RxBD_OV 0x0002 +#define MCF5282_FEC_RxBD_TR 0x0001 + +/********************************************************************* +* +* General Purpose I/O (GPIO) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GPIO_PORTA (*(vuint8 *)(&__IPSBAR[0x100000])) +#define MCF5282_GPIO_PORTB (*(vuint8 *)(&__IPSBAR[0x100001])) +#define MCF5282_GPIO_PORTC (*(vuint8 *)(&__IPSBAR[0x100002])) +#define MCF5282_GPIO_PORTD (*(vuint8 *)(&__IPSBAR[0x100003])) +#define MCF5282_GPIO_PORTE (*(vuint8 *)(&__IPSBAR[0x100004])) +#define MCF5282_GPIO_PORTF (*(vuint8 *)(&__IPSBAR[0x100005])) +#define MCF5282_GPIO_PORTG (*(vuint8 *)(&__IPSBAR[0x100006])) +#define MCF5282_GPIO_PORTH (*(vuint8 *)(&__IPSBAR[0x100007])) +#define MCF5282_GPIO_PORTJ (*(vuint8 *)(&__IPSBAR[0x100008])) +#define MCF5282_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100009])) +#define MCF5282_GPIO_PORTEH (*(vuint8 *)(&__IPSBAR[0x10000A])) +#define MCF5282_GPIO_PORTEL (*(vuint8 *)(&__IPSBAR[0x10000B])) +#define MCF5282_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000C])) +#define MCF5282_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000D])) +#define MCF5282_GPIO_PORTSD (*(vuint8 *)(&__IPSBAR[0x10000E])) +#define MCF5282_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) +#define MCF5282_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) +#define MCF5282_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) + +#define MCF5282_GPIO_DDRA (*(vuint8 *)(&__IPSBAR[0x100014])) +#define MCF5282_GPIO_DDRB (*(vuint8 *)(&__IPSBAR[0x100015])) +#define MCF5282_GPIO_DDRC (*(vuint8 *)(&__IPSBAR[0x100016])) +#define MCF5282_GPIO_DDRD (*(vuint8 *)(&__IPSBAR[0x100017])) +#define MCF5282_GPIO_DDRE (*(vuint8 *)(&__IPSBAR[0x100018])) +#define MCF5282_GPIO_DDRF (*(vuint8 *)(&__IPSBAR[0x100019])) +#define MCF5282_GPIO_DDRG (*(vuint8 *)(&__IPSBAR[0x10001A])) +#define MCF5282_GPIO_DDRH (*(vuint8 *)(&__IPSBAR[0x10001B])) +#define MCF5282_GPIO_DDRJ (*(vuint8 *)(&__IPSBAR[0x10001C])) +#define MCF5282_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10001D])) +#define MCF5282_GPIO_DDREH (*(vuint8 *)(&__IPSBAR[0x10001E])) +#define MCF5282_GPIO_DDREL (*(vuint8 *)(&__IPSBAR[0x10001F])) +#define MCF5282_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100020])) +#define MCF5282_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100021])) +#define MCF5282_GPIO_DDRSD (*(vuint8 *)(&__IPSBAR[0x100022])) +#define MCF5282_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100023])) +#define MCF5282_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100024])) +#define MCF5282_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100025])) + +#define MCF5282_GPIO_PORTAP (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_PORTBP (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_PORTCP (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_PORTDP (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_PORTEP (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_PORTFP (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_PORTHP (*(vuint8 *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_PORTJP (*(vuint8 *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_PORTDDP (*(vuint8 *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_PORTEHP (*(vuint8 *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_PORTELP (*(vuint8 *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_PORTASP (*(vuint8 *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_PORTQSP (*(vuint8 *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_PORTSDP (*(vuint8 *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_PORTTCP (*(vuint8 *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_PORTTDP (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_PORTUAP (*(vuint8 *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_SETA (*(vuint8 *)(&__IPSBAR[0x100028])) +#define MCF5282_GPIO_SETB (*(vuint8 *)(&__IPSBAR[0x100029])) +#define MCF5282_GPIO_SETC (*(vuint8 *)(&__IPSBAR[0x10002A])) +#define MCF5282_GPIO_SETD (*(vuint8 *)(&__IPSBAR[0x10002B])) +#define MCF5282_GPIO_SETE (*(vuint8 *)(&__IPSBAR[0x10002C])) +#define MCF5282_GPIO_SETF (*(vuint8 *)(&__IPSBAR[0x10002D])) +#define MCF5282_GPIO_SETG (*(vuint8 *)(&__IPSBAR[0x10002E])) +#define MCF5282_GPIO_SETH (*(vuint8 *)(&__IPSBAR[0x10002F])) +#define MCF5282_GPIO_SETJ (*(vuint8 *)(&__IPSBAR[0x100030])) +#define MCF5282_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100031])) +#define MCF5282_GPIO_SETEH (*(vuint8 *)(&__IPSBAR[0x100032])) +#define MCF5282_GPIO_SETEL (*(vuint8 *)(&__IPSBAR[0x100033])) +#define MCF5282_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x100034])) +#define MCF5282_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x100035])) +#define MCF5282_GPIO_SETSD (*(vuint8 *)(&__IPSBAR[0x100036])) +#define MCF5282_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x100037])) +#define MCF5282_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100038])) +#define MCF5282_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100039])) + +#define MCF5282_GPIO_CLRA (*(vuint8 *)(&__IPSBAR[0x10003C])) +#define MCF5282_GPIO_CLRB (*(vuint8 *)(&__IPSBAR[0x10003D])) +#define MCF5282_GPIO_CLRC (*(vuint8 *)(&__IPSBAR[0x10003E])) +#define MCF5282_GPIO_CLRD (*(vuint8 *)(&__IPSBAR[0x10003F])) +#define MCF5282_GPIO_CLRE (*(vuint8 *)(&__IPSBAR[0x100040])) +#define MCF5282_GPIO_CLRF (*(vuint8 *)(&__IPSBAR[0x100041])) +#define MCF5282_GPIO_CLRG (*(vuint8 *)(&__IPSBAR[0x100042])) +#define MCF5282_GPIO_CLRH (*(vuint8 *)(&__IPSBAR[0x100043])) +#define MCF5282_GPIO_CLRJ (*(vuint8 *)(&__IPSBAR[0x100044])) +#define MCF5282_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x100045])) +#define MCF5282_GPIO_CLREH (*(vuint8 *)(&__IPSBAR[0x100046])) +#define MCF5282_GPIO_CLREL (*(vuint8 *)(&__IPSBAR[0x100047])) +#define MCF5282_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100048])) +#define MCF5282_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100049])) +#define MCF5282_GPIO_CLRSD (*(vuint8 *)(&__IPSBAR[0x10004A])) +#define MCF5282_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x10004B])) +#define MCF5282_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x10004C])) +#define MCF5282_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x10004D])) + +#define MCF5282_GPIO_PBCDPAR (*(vuint8 *)(&__IPSBAR[0x100050])) +#define MCF5282_GPIO_PFPAR (*(vuint8 *)(&__IPSBAR[0x100051])) +#define MCF5282_GPIO_PEPAR (*(vuint16 *)(&__IPSBAR[0x100052])) +#define MCF5282_GPIO_PJPAR (*(vuint8 *)(&__IPSBAR[0x100054])) +#define MCF5282_GPIO_PSDPAR (*(vuint8 *)(&__IPSBAR[0x100055])) +#define MCF5282_GPIO_PASPAR (*(vuint16 *)(&__IPSBAR[0x100056])) +#define MCF5282_GPIO_PEHLPAR (*(vuint8 *)(&__IPSBAR[0x100058])) +#define MCF5282_GPIO_PQSPAR (*(vuint8 *)(&__IPSBAR[0x100059])) +#define MCF5282_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10005A])) +#define MCF5282_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x10005B])) +#define MCF5282_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x10005C])) + +/* Bit level definitions and macros */ +#define MCF5282_GPIO_PORTx7 (0x80) +#define MCF5282_GPIO_PORTx6 (0x40) +#define MCF5282_GPIO_PORTx5 (0x20) +#define MCF5282_GPIO_PORTx4 (0x10) +#define MCF5282_GPIO_PORTx3 (0x08) +#define MCF5282_GPIO_PORTx2 (0x04) +#define MCF5282_GPIO_PORTx1 (0x02) +#define MCF5282_GPIO_PORTx0 (0x01) +#define MCF5282_GPIO_PORTx(x) (0x01<<(x)) + +#define MCF5282_GPIO_DDRx7 (0x80) +#define MCF5282_GPIO_DDRx6 (0x40) +#define MCF5282_GPIO_DDRx5 (0x20) +#define MCF5282_GPIO_DDRx4 (0x10) +#define MCF5282_GPIO_DDRx3 (0x08) +#define MCF5282_GPIO_DDRx2 (0x04) +#define MCF5282_GPIO_DDRx1 (0x02) +#define MCF5282_GPIO_DDRx0 (0x01) +#define MCF5282_GPIO_DDRx(x) (0x01<<(x)) + +#define MCF5282_GPIO_PORTxP7 (0x80) +#define MCF5282_GPIO_PORTxP6 (0x40) +#define MCF5282_GPIO_PORTxP5 (0x20) +#define MCF5282_GPIO_PORTxP4 (0x10) +#define MCF5282_GPIO_PORTxP3 (0x08) +#define MCF5282_GPIO_PORTxP2 (0x04) +#define MCF5282_GPIO_PORTxP1 (0x02) +#define MCF5282_GPIO_PORTxP0 (0x01) +#define MCF5282_GPIO_PORTxP(x) (0x01<<(x)) + +#define MCF5282_GPIO_SETx7 (0x80) +#define MCF5282_GPIO_SETx6 (0x40) +#define MCF5282_GPIO_SETx5 (0x20) +#define MCF5282_GPIO_SETx4 (0x10) +#define MCF5282_GPIO_SETx3 (0x08) +#define MCF5282_GPIO_SETx2 (0x04) +#define MCF5282_GPIO_SETx1 (0x02) +#define MCF5282_GPIO_SETx0 (0x01) +#define MCF5282_GPIO_SETx(x) (0x01<<(x)) + +#define MCF5282_GPIO_CLRx7 (0x80) +#define MCF5282_GPIO_CLRx6 (0x40) +#define MCF5282_GPIO_CLRx5 (0x20) +#define MCF5282_GPIO_CLRx4 (0x10) +#define MCF5282_GPIO_CLRx3 (0x08) +#define MCF5282_GPIO_CLRx2 (0x04) +#define MCF5282_GPIO_CLRx1 (0x02) +#define MCF5282_GPIO_CLRx0 (0x01) +#define MCF5282_GPIO_CLRx(x) (0x01<<(x)) + +#define MCF5282_GPIO_PBCDPAR_PBPA (0x80) +#define MCF5282_GPIO_PBCDPAR_PCDPA (0x40) + +#define MCF5282_GPIO_PEPAR_PEPA7 (0x4000) +#define MCF5282_GPIO_PEPAR_PEPA6 (0x1000) +#define MCF5282_GPIO_PEPAR_PEPA5 (0x0400) +#define MCF5282_GPIO_PEPAR_PEPA4 (0x0100) +#define MCF5282_GPIO_PEPAR_PEPA3 (0x0040) +#define MCF5282_GPIO_PEPAR_PEPA2 (0x0010) +#define MCF5282_GPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PEPAR_PEPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PFPAR_PFPA7 (0x80) +#define MCF5282_GPIO_PFPAR_PFPA6 (0x40) +#define MCF5282_GPIO_PFPAR_PFPA5 (0x20) + +#define MCF5282_GPIO_PJPAR_PJPA7 (0x80) +#define MCF5282_GPIO_PJPAR_PJPA6 (0x40) +#define MCF5282_GPIO_PJPAR_PJPA5 (0x20) +#define MCF5282_GPIO_PJPAR_PJPA4 (0x10) +#define MCF5282_GPIO_PJPAR_PJPA3 (0x08) +#define MCF5282_GPIO_PJPAR_PJPA2 (0x04) +#define MCF5282_GPIO_PJPAR_PJPA1 (0x02) +#define MCF5282_GPIO_PJPAR_PJPA0 (0x01) +#define MCF5282_GPIO_PJPAR_PJPA(x) (0x01<<(x)) + +#define MCF5282_GPIO_PSDPAR_PSDPA (0x80) + +#define MCF5282_GPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) +#define MCF5282_GPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) +#define MCF5282_GPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PASPAR_PASPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PEHLPAR_PEHPA (0x80) +#define MCF5282_GPIO_PEHLPAR_PELPA (0x40) + +#define MCF5282_GPIO_PQSPAR_PQSPA6 (0x40) +#define MCF5282_GPIO_PQSPAR_PQSPA5 (0x20) +#define MCF5282_GPIO_PQSPAR_PQSPA4 (0x10) +#define MCF5282_GPIO_PQSPAR_PQSPA3 (0x08) +#define MCF5282_GPIO_PQSPAR_PQSPA2 (0x04) +#define MCF5282_GPIO_PQSPAR_PQSPA1 (0x02) +#define MCF5282_GPIO_PQSPAR_PQSPA0 (0x01) +#define MCF5282_GPIO_PQSPAR_PQSPA(x) (0x01<<(x)) + +#define MCF5282_GPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) +#define MCF5282_GPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) +#define MCF5282_GPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) +#define MCF5282_GPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) + +#define MCF5282_GPIO_PUAPAR_PUAPA3 (0x08) +#define MCF5282_GPIO_PUAPAR_PUAPA2 (0x04) +#define MCF5282_GPIO_PUAPAR_PUAPA1 (0x02) +#define MCF5282_GPIO_PUAPAR_PUAPA0 (0x01) + +/********************************************************************* +* +* Reset Controller Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_RESET_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) +#define MCF5282_RESET_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) + +/* Bit level definitions and macros */ +#define MCF5282_RESET_RCR_SOFTRST (0x80) +#define MCF5282_RESET_RCR_FRCRSTOUT (0x40) +#define MCF5282_RESET_RCR_LVDF (0x10) +#define MCF5282_RESET_RCR_LVDIE (0x08) +#define MCF5282_RESET_RCR_LVDRE (0x04) +#define MCF5282_RESET_RCR_LVDE (0x01) + +#define MCF5282_RESET_RSR_LVD (0x40) +#define MCF5282_RESET_RSR_SOFT (0x20) +#define MCF5282_RESET_RSR_WDR (0x10) +#define MCF5282_RESET_RSR_POR (0x08) +#define MCF5282_RESET_RSR_EXT (0x04) +#define MCF5282_RESET_RSR_LOC (0x02) +#define MCF5282_RESET_RSR_LOL (0x01) + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CCM_CCR (*(vuint16 *)(&__IPSBAR[0x110004])) +#define MCF5282_CCM_RCON (*(vuint16 *)(&__IPSBAR[0x110008])) +#define MCF5282_CCM_CIR (*(vuint16 *)(&__IPSBAR[0x11000A])) + +/* Bit level definitions and macros */ +#define MCF5282_CCM_CCR_LOAD (0x8000) +#define MCF5282_CCM_CCR_MODE(x) (((x)&0x0007)<<8) +#define MCF5282_CCM_CCR_SZEN (0x0040) +#define MCF5282_CCM_CCR_PSTEN (0x0020) +#define MCF5282_CCM_CCR_BME (0x0008) +#define MCF5282_CCM_CCR_BMT(x) (((x)&0x0007)) + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) +#define MCF5282_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) + +/* Bit level definitions and macros */ +#define MCF5282_PMM_LPICR_ENBSTOP (0x80) +#define MCF5282_PMM_LPICR_XLMP_IPL(x) (((x)&0x07)<<4) + +#define MCF5282_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF5282_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF5282_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF5282_PMM_LPCR_LPMD_RUN (0x00) +#define MCF5282_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF5282_PMM_LPCR_LVDSE (0x02) + +/********************************************************************* +* +* Clock Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CLOCK_SYNCR (*(vuint16 *)(&__IPSBAR[0x120000])) +#define MCF5282_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) + +/* Bit level definitions and macros */ +#define MCF5282_CLOCK_SYNCR_LOLRE (0x8000) +#define MCF5282_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) +#define MCF5282_CLOCK_SYNCR_LOCRE (0x0800) +#define MCF5282_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) +#define MCF5282_CLOCK_SYNCR_LOCEN (0x0080) +#define MCF5282_CLOCK_SYNCR_DISCLK (0x0040) +#define MCF5282_CLOCK_SYNCR_FWKUP (0x0020) +#define MCF5282_CLOCK_SYNCR_STPMD(x) (((x)&0x0003)<<2) + +#define MCF5282_CLOCK_SYNSR_PLLMODE (0x80) +#define MCF5282_CLOCK_SYNSR_PLLSEL (0x40) +#define MCF5282_CLOCK_SYNSR_PLLREF (0x20) +#define MCF5282_CLOCK_SYNSR_LOCKS (0x10) +#define MCF5282_CLOCK_SYNSR_LOCK (0x08) +#define MCF5282_CLOCK_SYNSR_LOCS (0x04) + +/********************************************************************* +* +* Edge Port (EPORT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_EPORT_EPPAR (*(vuint16 *)(&__IPSBAR[0x130000])) +#define MCF5282_EPORT_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002])) +#define MCF5282_EPORT_EPIER (*(vuint8 *)(&__IPSBAR[0x130003])) +#define MCF5282_EPORT_EPDR (*(vuint8 *)(&__IPSBAR[0x130004])) +#define MCF5282_EPORT_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005])) +#define MCF5282_EPORT_EPFR (*(vuint8 *)(&__IPSBAR[0x130006])) + +/* Bit level definitions and macros */ +#define MCF5282_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF5282_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF5282_EPORT_EPPAR_EPPA7_BOTHEDGE (0xC000) +#define MCF5282_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF5282_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF5282_EPORT_EPPAR_EPPA6_BOTHEDGE (0x3000) +#define MCF5282_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF5282_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF5282_EPORT_EPPAR_EPPA5_BOTHEDGE (0x0C00) +#define MCF5282_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF5282_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF5282_EPORT_EPPAR_EPPA4_BOTHEDGE (0x0300) +#define MCF5282_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF5282_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF5282_EPORT_EPPAR_EPPA3_BOTHEDGE (0x00C0) +#define MCF5282_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF5282_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF5282_EPORT_EPPAR_EPPA2_BOTHEDGE (0x0030) +#define MCF5282_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF5282_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF5282_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF5282_EPORT_EPPAR_EPPA1_BOTHEDGE (0x000C) + + +#define MCF5282_EPORT_EPDDR_EPDD7 (0x80) +#define MCF5282_EPORT_EPDDR_EPDD6 (0x40) +#define MCF5282_EPORT_EPDDR_EPDD5 (0x20) +#define MCF5282_EPORT_EPDDR_EPDD4 (0x10) +#define MCF5282_EPORT_EPDDR_EPDD3 (0x08) +#define MCF5282_EPORT_EPDDR_EPDD2 (0x04) +#define MCF5282_EPORT_EPDDR_EPDD1 (0x02) +#define MCF5282_EPORT_EPDDR_EPDD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPIER_EPIE7 (0x80) +#define MCF5282_EPORT_EPIER_EPIE6 (0x40) +#define MCF5282_EPORT_EPIER_EPIE5 (0x20) +#define MCF5282_EPORT_EPIER_EPIE4 (0x10) +#define MCF5282_EPORT_EPIER_EPIE3 (0x08) +#define MCF5282_EPORT_EPIER_EPIE2 (0x04) +#define MCF5282_EPORT_EPIER_EPIE1 (0x02) +#define MCF5282_EPORT_EPIER_EPIE(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPDR_EPD7 (0x80) +#define MCF5282_EPORT_EPDR_EPD6 (0x40) +#define MCF5282_EPORT_EPDR_EPD5 (0x20) +#define MCF5282_EPORT_EPDR_EPD4 (0x10) +#define MCF5282_EPORT_EPDR_EPD3 (0x08) +#define MCF5282_EPORT_EPDR_EPD2 (0x04) +#define MCF5282_EPORT_EPDR_EPD1 (0x02) +#define MCF5282_EPORT_EPDR_EPD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPPDR_EPPD7 (0x80) +#define MCF5282_EPORT_EPPDR_EPPD6 (0x40) +#define MCF5282_EPORT_EPPDR_EPPD5 (0x20) +#define MCF5282_EPORT_EPPDR_EPPD4 (0x10) +#define MCF5282_EPORT_EPPDR_EPPD3 (0x08) +#define MCF5282_EPORT_EPPDR_EPPD2 (0x04) +#define MCF5282_EPORT_EPPDR_EPPD1 (0x02) +#define MCF5282_EPORT_EPPDR_EPPD(x) (0x01<<(x)) + +#define MCF5282_EPORT_EPFR_EPF7 (0x80) +#define MCF5282_EPORT_EPFR_EPF6 (0x40) +#define MCF5282_EPORT_EPFR_EPF5 (0x20) +#define MCF5282_EPORT_EPFR_EPF4 (0x10) +#define MCF5282_EPORT_EPFR_EPF3 (0x08) +#define MCF5282_EPORT_EPFR_EPF2 (0x04) +#define MCF5282_EPORT_EPFR_EPF1 (0x02) +#define MCF5282_EPORT_EPFR_EPF(x) (0x01<<(x)) + +/********************************************************************* +* +* Watchdog Timer Module (WTM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_WTM_WCR (*(vuint16 *)(&__IPSBAR[0x140000])) +#define MCF5282_WTM_WMR (*(vuint16 *)(&__IPSBAR[0x140002])) +#define MCF5282_WTM_WCNTR (*(vuint16 *)(&__IPSBAR[0x140004])) +#define MCF5282_WTM_WSR (*(vuint16 *)(&__IPSBAR[0x140006])) + +/* Bit level definitions and macros */ +#define MCF5282_WTM_WCR_WAIT (0x0008) +#define MCF5282_WTM_WCR_DOZE (0x0004) +#define MCF5282_WTM_WCR_HALTED (0x0002) +#define MCF5282_WTM_WCR_EN (0x0001) + +#define MCF5282_WTM_WSR_SEQ1 (0x5555) +#define MCF5282_WTM_WSR_SEQ2 (0xAAAA) + +/********************************************************************* +* +* Programmable Interrupt Timer (PIT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_PIT0_PCSR (*(vuint16 *)(&__IPSBAR[0x150000])) +#define MCF5282_PIT0_PMR (*(vuint16 *)(&__IPSBAR[0x150002])) +#define MCF5282_PIT0_PCNTR (*(vuint16 *)(&__IPSBAR[0x150004])) + +#define MCF5282_PIT1_PCSR (*(vuint16 *)(&__IPSBAR[0x160000])) +#define MCF5282_PIT1_PMR (*(vuint16 *)(&__IPSBAR[0x160002])) +#define MCF5282_PIT1_PCNTR (*(vuint16 *)(&__IPSBAR[0x160004])) + +#define MCF5282_PIT2_PCSR (*(vuint16 *)(&__IPSBAR[0x170000])) +#define MCF5282_PIT2_PMR (*(vuint16 *)(&__IPSBAR[0x170002])) +#define MCF5282_PIT2_PCNTR (*(vuint16 *)(&__IPSBAR[0x170004])) + +#define MCF5282_PIT3_PCSR (*(vuint16 *)(&__IPSBAR[0x180000])) +#define MCF5282_PIT3_PMR (*(vuint16 *)(&__IPSBAR[0x180002])) +#define MCF5282_PIT3_PCNTR (*(vuint16 *)(&__IPSBAR[0x180004])) + +#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x1000*(x))])) +#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x1000*(x))])) +#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x1000*(x))])) + +/* Bit level definitions and macros */ +#define MCF5282_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) +#define MCF5282_PIT_PCSR_DOZE (0x0040) +#define MCF5282_PIT_PCSR_HALTED (0x0020) +#define MCF5282_PIT_PCSR_OVW (0x0010) +#define MCF5282_PIT_PCSR_PIE (0x0008) +#define MCF5282_PIT_PCSR_PIF (0x0004) +#define MCF5282_PIT_PCSR_RLD (0x0002) +#define MCF5282_PIT_PCSR_EN (0x0001) + +/********************************************************************* +* +* Queued Analog to Digital Converter (QADC) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_QADC_QADCMCR (*(vuint16 *)(&__IPSBAR[0x190000])) +#define MCF5282_QADC_PORTQA (*(vuint8 *)(&__IPSBAR[0x190006])) +#define MCF5282_QADC_PORTQB (*(vuint8 *)(&__IPSBAR[0x190007])) +#define MCF5282_QADC_DDRQA (*(vuint8 *)(&__IPSBAR[0x190008])) +#define MCF5282_QADC_DDRQB (*(vuint8 *)(&__IPSBAR[0x190009])) +#define MCF5282_QADC_QACR0 (*(vuint16 *)(&__IPSBAR[0x19000A])) +#define MCF5282_QADC_QACR1 (*(vuint16 *)(&__IPSBAR[0x19000C])) +#define MCF5282_QADC_QACR2 (*(vuint16 *)(&__IPSBAR[0x19000E])) +#define MCF5282_QADC_QASR0 (*(vuint16 *)(&__IPSBAR[0x190010])) +#define MCF5282_QADC_QASR1 (*(vuint16 *)(&__IPSBAR[0x190012])) +#define MCF5282_QADC_CCW(x) (*(vuint16 *)(&__IPSBAR[0x190200+((x)*2)])) +#define MCF5282_QADC_RJURR(x) (*(vuint16 *)(&__IPSBAR[0x190280+((x)*2)])) +#define MCF5282_QADC_LJSRR(x) (*(vuint16 *)(&__IPSBAR[0x190300+((x)*2)])) +#define MCF5282_QADC_LJURR(x) (*(vuint16 *)(&__IPSBAR[0x190380+((x)*2)])) + +/* Bit level definitions and macros */ +#define MCF5282_QADC_QADCMCR_QSTOP (0x8000) +#define MCF5282_QADC_QADCMCR_QDBG (0x4000) +#define MCF5282_QADC_QADCMCR_SUPV (0x0080) + +#define MCF5282_QADC_PORTQA_PQA4 (0x10) +#define MCF5282_QADC_PORTQA_PQA3 (0x08) +#define MCF5282_QADC_PORTQA_PQA1 (0x02) +#define MCF5282_QADC_PORTQA_PQA0 (0x01) +#define MCF5282_QADC_PORTQA_AN56 (0x10) +#define MCF5282_QADC_PORTQA_AN55 (0x08) +#define MCF5282_QADC_PORTQA_ETRIG2 (0x10) +#define MCF5282_QADC_PORTQA_ETRIG1 (0x08) +#define MCF5282_QADC_PORTQA_AN53 (0x02) +#define MCF5282_QADC_PORTQA_AN52 (0x01) +#define MCF5282_QADC_PORTQA_MA1 (0x02) +#define MCF5282_QADC_PORTQA_MA0 (0x01) + +#define MCF5282_QADC_PORTQB_PQB3 (0x08) +#define MCF5282_QADC_PORTQB_PQB2 (0x04) +#define MCF5282_QADC_PORTQB_PQB1 (0x02) +#define MCF5282_QADC_PORTQB_PQB0 (0x01) +#define MCF5282_QADC_PORTQB_AN3 (0x08) +#define MCF5282_QADC_PORTQB_AN2 (0x04) +#define MCF5282_QADC_PORTQB_AN1 (0x02) +#define MCF5282_QADC_PORTQB_AN0 (0x01) +#define MCF5282_QADC_PORTQB_ANZ (0x08) +#define MCF5282_QADC_PORTQB_ANY (0x04) +#define MCF5282_QADC_PORTQB_ANX (0x02) +#define MCF5282_QADC_PORTQB_ANW (0x01) + +#define MCF5282_QADC_DDRQA_DDQA4 (0x10) +#define MCF5282_QADC_DDRQA_DDQA3 (0x08) +#define MCF5282_QADC_DDRQA_DDQA1 (0x02) +#define MCF5282_QADC_DDRQA_DDQA0 (0x01) + +#define MCF5282_QADC_DDRQB_DDQB3 (0x08) +#define MCF5282_QADC_DDRQB_DDQB2 (0x04) +#define MCF5282_QADC_DDRQB_DDQB1 (0x02) +#define MCF5282_QADC_DDRQB_DDQB0 (0x01) + +#define MCF5282_QADC_QACR0_MUX (0x8000) +#define MCF5282_QADC_QACR0_TRG (0x1000) +#define MCF5282_QADC_QACR0_QPR(x) (((x)&0x007F)) + +#define MCF5282_QADC_QACRx_CIE (0x8000) +#define MCF5282_QADC_QACRx_PIE (0x4000) +#define MCF5282_QADC_QACRx_SSE (0x2000) +#define MCF5282_QADC_QACRx_MQ(x) (((x)&0x001F)<<8) +#define MCF5282_QADC_QACRx_RESUME (0x0080) +#define MCF5282_QADC_QACRx_BQ(x) (((x)&0x007F)) + +#define MCF5282_QADC_QASR0_CF1 (0x8000) +#define MCF5282_QADC_QASR0_PF1 (0x4000) +#define MCF5282_QADC_QASR0_CF2 (0x2000) +#define MCF5282_QADC_QASR0_PF2 (0x1000) +#define MCF5282_QADC_QASR0_TOR1 (0x0800) +#define MCF5282_QADC_QASR0_TOR2 (0x0400) + +#define MCF5282_QADC_CCW_P (0x0200) +#define MCF5282_QADC_CCW_BYP (0x0100) +#define MCF5282_QADC_CCW_IST(x) (((x)&0x0003)<<14) +#define MCF5282_QADC_CCW_CHAN(x) (((x)&0x003F)) + +/********************************************************************* +* +* General Purpose Timer (GPT) Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) +#define MCF5282_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) +#define MCF5282_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) +#define MCF5282_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) +#define MCF5282_GPTA_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1A0004])) +#define MCF5282_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) +#define MCF5282_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) +#define MCF5282_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) +#define MCF5282_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) +#define MCF5282_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) +#define MCF5282_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) +#define MCF5282_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) +#define MCF5282_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) +#define MCF5282_GPTA_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1A0010])) +#define MCF5282_GPTA_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1A0012])) +#define MCF5282_GPTA_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1A0014])) +#define MCF5282_GPTA_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1A0016])) +#define MCF5282_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) +#define MCF5282_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) +#define MCF5282_GPTA_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1A001A])) +#define MCF5282_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) +#define MCF5282_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) + +#define MCF5282_GPTB_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1B0000])) +#define MCF5282_GPTB_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1B0001])) +#define MCF5282_GPTB_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1B0002])) +#define MCF5282_GPTB_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1B0003])) +#define MCF5282_GPTB_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1B0004])) +#define MCF5282_GPTB_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1B0006])) +#define MCF5282_GPTB_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1B0008])) +#define MCF5282_GPTB_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1B0009])) +#define MCF5282_GPTB_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1B000B])) +#define MCF5282_GPTB_GPTIE (*(vuint8 *)(&__IPSBAR[0x1B000C])) +#define MCF5282_GPTB_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1B000D])) +#define MCF5282_GPTB_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1B000E])) +#define MCF5282_GPTB_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1B000F])) +#define MCF5282_GPTB_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1B0010])) +#define MCF5282_GPTB_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1B0012])) +#define MCF5282_GPTB_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1B0014])) +#define MCF5282_GPTB_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1B0016])) +#define MCF5282_GPTB_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1B0018])) +#define MCF5282_GPTB_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1B0019])) +#define MCF5282_GPTB_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1B001A])) +#define MCF5282_GPTB_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1B001D])) +#define MCF5282_GPTB_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1B001E])) + +/* Bit level definitions and macros */ +#define MCF5282_GPT_GPTIOS_IOS3 (0x08) +#define MCF5282_GPT_GPTIOS_IOS2 (0x04) +#define MCF5282_GPT_GPTIOS_IOS1 (0x02) +#define MCF5282_GPT_GPTIOS_IOS0 (0x01) + +#define MCF5282_GPT_GPTCFORC_FOC3 (0x08) +#define MCF5282_GPT_GPTCFORC_FOC2 (0x04) +#define MCF5282_GPT_GPTCFORC_FOC1 (0x02) +#define MCF5282_GPT_GPTCFORC_FOC0 (0x01) + +#define MCF5282_GPT_GPTOC3M_OC3M3 (0x08) +#define MCF5282_GPT_GPTOC3M_OC3M2 (0x04) +#define MCF5282_GPT_GPTOC3M_OC3M1 (0x02) +#define MCF5282_GPT_GPTOC3M_OC3M0 (0x01) + +#define MCF5282_GPT_GPTOC3M_OC3D(x) (((x)&0x04)) + +#define MCF5282_GPT_GPTSCR1_GPTEN (0x80) +#define MCF5282_GPT_GPTSCR1_TFFCA (0x10) + +#define MCF5282_GPT_GPTTOV3 (0x08) +#define MCF5282_GPT_GPTTOV2 (0x04) +#define MCF5282_GPT_GPTTOV1 (0x02) +#define MCF5282_GPT_GPTTOV0 (0x01) + +#define MCF5282_GPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) +#define MCF5282_GPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) +#define MCF5282_GPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTCTL_OMOL0(x) (((x)&0x03)) + +#define MCF5282_GPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) +#define MCF5282_GPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) +#define MCF5282_GPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTCTL2_EDG0(x) (((x)&0x03)) + +#define MCF5282_GPT_GPTIE_C3I (0x08) +#define MCF5282_GPT_GPTIE_C2I (0x04) +#define MCF5282_GPT_GPTIE_C1I (0x02) +#define MCF5282_GPT_GPTIE_C0I (0x01) + +#define MCF5282_GPT_GPTSCR2_TOI (0x80) +#define MCF5282_GPT_GPTSCR2_PUPT (0x20) +#define MCF5282_GPT_GPTSCR2_RDPT (0x10) +#define MCF5282_GPT_GPTSCR2_TCRE (0x08) +#define MCF5282_GPT_GPTSCR2_PR(x) (((x)&0x07)) + +#define MCF5282_GPT_GPTFLG1_C3F (0x08) +#define MCF5282_GPT_GPTFLG1_C2F (0x04) +#define MCF5282_GPT_GPTFLG1_C1F (0x02) +#define MCF5282_GPT_GPTFLG1_C0F (0x01) + +#define MCF5282_GPT_GPTFLG2_TOF (0x80) +#define MCF5282_GPT_GPTFLG2_C3F (0x08) +#define MCF5282_GPT_GPTFLG2_C2F (0x04) +#define MCF5282_GPT_GPTFLG2_C1F (0x02) +#define MCF5282_GPT_GPTFLG2_C0F (0x01) + +#define MCF5282_GPT_GPTPACTL_PAE (0x40) +#define MCF5282_GPT_GPTPACTL_PAMOD (0x20) +#define MCF5282_GPT_GPTPACTL_PEDGE (0x10) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK (0x04) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK256 (0x08) +#define MCF5282_GPT_GPTPACTL_CLK_PACLK65536 (0x0C) +#define MCF5282_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) +#define MCF5282_GPT_GPTPACTL_PAOVI (0x02) +#define MCF5282_GPT_GPTPACTL_PAI (0x01) + +#define MCF5282_GPT_GPTPAFLG_PAOVF (0x02) +#define MCF5282_GPT_GPTPAFLG_PAIF (0x01) + +#define MCF5282_GPT_GPTPORT_PORTT3 (0x08) +#define MCF5282_GPT_GPTPORT_PORTT2 (0x04) +#define MCF5282_GPT_GPTPORT_PORTT1 (0x02) +#define MCF5282_GPT_GPTPORT_PORTT0 (0x01) + +#define MCF5282_GPT_GPTDDR_DDRT3 (0x08) +#define MCF5282_GPT_GPTDDR_DDRT2 (0x04) +#define MCF5282_GPT_GPTDDR_DDRT1 (0x02) +#define MCF5282_GPT_GPTDDR_DDRT0 (0x01) + +/********************************************************************* +* +* FlexCAN Module +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_FLEXCAN_CANMCR (*(vuint16 *)(&__IPSBAR[0x1C0000])) +#define MCF5282_FLEXCAN_CANCTRL0 (*(vuint8 *)(&__IPSBAR[0x1C0006])) +#define MCF5282_FLEXCAN_CANCTRL1 (*(vuint8 *)(&__IPSBAR[0x1C0007])) +#define MCF5282_FLEXCAN_PRESDIV (*(vuint8 *)(&__IPSBAR[0x1C0008])) +#define MCF5282_FLEXCAN_CANCTRL2 (*(vuint8 *)(&__IPSBAR[0x1C0009])) +#define MCF5282_FLEXCAN_TIMER (*(vuint16 *)(&__IPSBAR[0x1C000A])) +#define MCF5282_FLEXCAN_RXGMASK (*(vuint32 *)(&__IPSBAR[0x1C0010])) +#define MCF5282_FLEXCAN_RX14MASK (*(vuint32 *)(&__IPSBAR[0x1C0014])) +#define MCF5282_FLEXCAN_RX15MASK (*(vuint32 *)(&__IPSBAR[0x1C0018])) +#define MCF5282_FLEXCAN_ESTAT (*(vuint16 *)(&__IPSBAR[0x1C0020])) +#define MCF5282_FLEXCAN_IMASK (*(vuint16 *)(&__IPSBAR[0x1C0022])) +#define MCF5282_FLEXCAN_IFLAG (*(vuint16 *)(&__IPSBAR[0x1C0024])) +#define MCF5282_FLEXCAN_RXECTR (*(vuint8 *)(&__IPSBAR[0x1C0026])) +#define MCF5282_FLEXCAN_TXECTR (*(vuint8 *)(&__IPSBAR[0x1C0027])) +#define MCF5282_FLEXCAN_MBUF0_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0081])) +#define MCF5282_FLEXCAN_MBUF0_IDH (*(vuint16 *)(&__IPSBAR[0x1C0082])) +#define MCF5282_FLEXCAN_MBUF0_IDL (*(vuint16 *)(&__IPSBAR[0x1C0084])) +#define MCF5282_FLEXCAN_MBUF0_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0086])) +#define MCF5282_FLEXCAN_MBUF0_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0087])) +#define MCF5282_FLEXCAN_MBUF0_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0088])) +#define MCF5282_FLEXCAN_MBUF0_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0089])) +#define MCF5282_FLEXCAN_MBUF0_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C008A])) +#define MCF5282_FLEXCAN_MBUF0_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C008B])) +#define MCF5282_FLEXCAN_MBUF0_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C008C])) +#define MCF5282_FLEXCAN_MBUF0_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C008D])) +#define MCF5282_FLEXCAN_MBUF1_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0091])) +#define MCF5282_FLEXCAN_MBUF1_IDH (*(vuint16 *)(&__IPSBAR[0x1C0092])) +#define MCF5282_FLEXCAN_MBUF1_IDL (*(vuint16 *)(&__IPSBAR[0x1C0094])) +#define MCF5282_FLEXCAN_MBUF1_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0096])) +#define MCF5282_FLEXCAN_MBUF1_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0097])) +#define MCF5282_FLEXCAN_MBUF1_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0098])) +#define MCF5282_FLEXCAN_MBUF1_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0099])) +#define MCF5282_FLEXCAN_MBUF1_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C009A])) +#define MCF5282_FLEXCAN_MBUF1_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C009B])) +#define MCF5282_FLEXCAN_MBUF1_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C009C])) +#define MCF5282_FLEXCAN_MBUF1_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C009D])) +#define MCF5282_FLEXCAN_MBUF2_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00A1])) +#define MCF5282_FLEXCAN_MBUF2_IDH (*(vuint16 *)(&__IPSBAR[0x1C00A2])) +#define MCF5282_FLEXCAN_MBUF2_IDL (*(vuint16 *)(&__IPSBAR[0x1C00A4])) +#define MCF5282_FLEXCAN_MBUF2_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00A6])) +#define MCF5282_FLEXCAN_MBUF2_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00A7])) +#define MCF5282_FLEXCAN_MBUF2_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00A8])) +#define MCF5282_FLEXCAN_MBUF2_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00A9])) +#define MCF5282_FLEXCAN_MBUF2_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00AA])) +#define MCF5282_FLEXCAN_MBUF2_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00AB])) +#define MCF5282_FLEXCAN_MBUF2_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00AC])) +#define MCF5282_FLEXCAN_MBUF2_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00AD])) +#define MCF5282_FLEXCAN_MBUF3_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00B1])) +#define MCF5282_FLEXCAN_MBUF3_IDH (*(vuint16 *)(&__IPSBAR[0x1C00B2])) +#define MCF5282_FLEXCAN_MBUF3_IDL (*(vuint16 *)(&__IPSBAR[0x1C00B4])) +#define MCF5282_FLEXCAN_MBUF3_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00B6])) +#define MCF5282_FLEXCAN_MBUF3_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00B7])) +#define MCF5282_FLEXCAN_MBUF3_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00B8])) +#define MCF5282_FLEXCAN_MBUF3_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00B9])) +#define MCF5282_FLEXCAN_MBUF3_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00BA])) +#define MCF5282_FLEXCAN_MBUF3_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00BB])) +#define MCF5282_FLEXCAN_MBUF3_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00BC])) +#define MCF5282_FLEXCAN_MBUF3_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00BD])) +#define MCF5282_FLEXCAN_MBUF4_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00C1])) +#define MCF5282_FLEXCAN_MBUF4_IDH (*(vuint16 *)(&__IPSBAR[0x1C00C2])) +#define MCF5282_FLEXCAN_MBUF4_IDL (*(vuint16 *)(&__IPSBAR[0x1C00C4])) +#define MCF5282_FLEXCAN_MBUF4_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00C6])) +#define MCF5282_FLEXCAN_MBUF4_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00C7])) +#define MCF5282_FLEXCAN_MBUF4_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00C8])) +#define MCF5282_FLEXCAN_MBUF4_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00C9])) +#define MCF5282_FLEXCAN_MBUF4_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00CA])) +#define MCF5282_FLEXCAN_MBUF4_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00CB])) +#define MCF5282_FLEXCAN_MBUF4_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00CC])) +#define MCF5282_FLEXCAN_MBUF4_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00CD])) +#define MCF5282_FLEXCAN_MBUF5_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00D1])) +#define MCF5282_FLEXCAN_MBUF5_IDH (*(vuint16 *)(&__IPSBAR[0x1C00D2])) +#define MCF5282_FLEXCAN_MBUF5_IDL (*(vuint16 *)(&__IPSBAR[0x1C00D4])) +#define MCF5282_FLEXCAN_MBUF5_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00D6])) +#define MCF5282_FLEXCAN_MBUF5_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00D7])) +#define MCF5282_FLEXCAN_MBUF5_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00D8])) +#define MCF5282_FLEXCAN_MBUF5_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00D9])) +#define MCF5282_FLEXCAN_MBUF5_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00DA])) +#define MCF5282_FLEXCAN_MBUF5_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00DB])) +#define MCF5282_FLEXCAN_MBUF5_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00DC])) +#define MCF5282_FLEXCAN_MBUF5_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00DD])) +#define MCF5282_FLEXCAN_MBUF6_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00E1])) +#define MCF5282_FLEXCAN_MBUF6_IDH (*(vuint16 *)(&__IPSBAR[0x1C00E2])) +#define MCF5282_FLEXCAN_MBUF6_IDL (*(vuint16 *)(&__IPSBAR[0x1C00E4])) +#define MCF5282_FLEXCAN_MBUF6_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00E6])) +#define MCF5282_FLEXCAN_MBUF6_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00E7])) +#define MCF5282_FLEXCAN_MBUF6_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00E8])) +#define MCF5282_FLEXCAN_MBUF6_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00E9])) +#define MCF5282_FLEXCAN_MBUF6_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00EA])) +#define MCF5282_FLEXCAN_MBUF6_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00EB])) +#define MCF5282_FLEXCAN_MBUF6_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00EC])) +#define MCF5282_FLEXCAN_MBUF6_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00ED])) +#define MCF5282_FLEXCAN_MBUF7_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00F1])) +#define MCF5282_FLEXCAN_MBUF7_IDH (*(vuint16 *)(&__IPSBAR[0x1C00F2])) +#define MCF5282_FLEXCAN_MBUF7_IDL (*(vuint16 *)(&__IPSBAR[0x1C00F4])) +#define MCF5282_FLEXCAN_MBUF7_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00F6])) +#define MCF5282_FLEXCAN_MBUF7_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00F7])) +#define MCF5282_FLEXCAN_MBUF7_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00F8])) +#define MCF5282_FLEXCAN_MBUF7_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00F9])) +#define MCF5282_FLEXCAN_MBUF7_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00FA])) +#define MCF5282_FLEXCAN_MBUF7_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00FB])) +#define MCF5282_FLEXCAN_MBUF7_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00FC])) +#define MCF5282_FLEXCAN_MBUF7_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00FD])) +#define MCF5282_FLEXCAN_MBUF8_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0101])) +#define MCF5282_FLEXCAN_MBUF8_IDH (*(vuint16 *)(&__IPSBAR[0x1C0102])) +#define MCF5282_FLEXCAN_MBUF8_IDL (*(vuint16 *)(&__IPSBAR[0x1C0104])) +#define MCF5282_FLEXCAN_MBUF8_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0106])) +#define MCF5282_FLEXCAN_MBUF8_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0107])) +#define MCF5282_FLEXCAN_MBUF8_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0108])) +#define MCF5282_FLEXCAN_MBUF8_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0109])) +#define MCF5282_FLEXCAN_MBUF8_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C010A])) +#define MCF5282_FLEXCAN_MBUF8_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C010B])) +#define MCF5282_FLEXCAN_MBUF8_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C010C])) +#define MCF5282_FLEXCAN_MBUF8_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C010D])) +#define MCF5282_FLEXCAN_MBUF9_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0111])) +#define MCF5282_FLEXCAN_MBUF9_IDH (*(vuint16 *)(&__IPSBAR[0x1C0112])) +#define MCF5282_FLEXCAN_MBUF9_IDL (*(vuint16 *)(&__IPSBAR[0x1C0114])) +#define MCF5282_FLEXCAN_MBUF9_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0116])) +#define MCF5282_FLEXCAN_MBUF9_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0117])) +#define MCF5282_FLEXCAN_MBUF9_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0118])) +#define MCF5282_FLEXCAN_MBUF9_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0119])) +#define MCF5282_FLEXCAN_MBUF9_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C011A])) +#define MCF5282_FLEXCAN_MBUF9_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C011B])) +#define MCF5282_FLEXCAN_MBUF9_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C011C])) +#define MCF5282_FLEXCAN_MBUF9_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C011D])) +#define MCF5282_FLEXCAN_MBUF10_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0121])) +#define MCF5282_FLEXCAN_MBUF10_IDH (*(vuint16 *)(&__IPSBAR[0x1C0122])) +#define MCF5282_FLEXCAN_MBUF10_IDL (*(vuint16 *)(&__IPSBAR[0x1C0124])) +#define MCF5282_FLEXCAN_MBUF10_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0126])) +#define MCF5282_FLEXCAN_MBUF10_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0127])) +#define MCF5282_FLEXCAN_MBUF10_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0128])) +#define MCF5282_FLEXCAN_MBUF10_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0129])) +#define MCF5282_FLEXCAN_MBUF10_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C012A])) +#define MCF5282_FLEXCAN_MBUF10_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C012B])) +#define MCF5282_FLEXCAN_MBUF10_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C012C])) +#define MCF5282_FLEXCAN_MBUF10_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C012D])) +#define MCF5282_FLEXCAN_MBUF11_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0131])) +#define MCF5282_FLEXCAN_MBUF11_IDH (*(vuint16 *)(&__IPSBAR[0x1C0132])) +#define MCF5282_FLEXCAN_MBUF11_IDL (*(vuint16 *)(&__IPSBAR[0x1C0134])) +#define MCF5282_FLEXCAN_MBUF11_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0136])) +#define MCF5282_FLEXCAN_MBUF11_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0137])) +#define MCF5282_FLEXCAN_MBUF11_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0138])) +#define MCF5282_FLEXCAN_MBUF11_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0139])) +#define MCF5282_FLEXCAN_MBUF11_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C013A])) +#define MCF5282_FLEXCAN_MBUF11_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C013B])) +#define MCF5282_FLEXCAN_MBUF11_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C013C])) +#define MCF5282_FLEXCAN_MBUF11_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C013D])) +#define MCF5282_FLEXCAN_MBUF12_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0141])) +#define MCF5282_FLEXCAN_MBUF12_IDH (*(vuint16 *)(&__IPSBAR[0x1C0142])) +#define MCF5282_FLEXCAN_MBUF12_IDL (*(vuint16 *)(&__IPSBAR[0x1C0144])) +#define MCF5282_FLEXCAN_MBUF12_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0146])) +#define MCF5282_FLEXCAN_MBUF12_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0147])) +#define MCF5282_FLEXCAN_MBUF12_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0148])) +#define MCF5282_FLEXCAN_MBUF12_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0149])) +#define MCF5282_FLEXCAN_MBUF12_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C014A])) +#define MCF5282_FLEXCAN_MBUF12_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C014B])) +#define MCF5282_FLEXCAN_MBUF12_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C014C])) +#define MCF5282_FLEXCAN_MBUF12_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C014D])) +#define MCF5282_FLEXCAN_MBUF13_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0151])) +#define MCF5282_FLEXCAN_MBUF13_IDH (*(vuint16 *)(&__IPSBAR[0x1C0152])) +#define MCF5282_FLEXCAN_MBUF13_IDL (*(vuint16 *)(&__IPSBAR[0x1C0154])) +#define MCF5282_FLEXCAN_MBUF13_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0156])) +#define MCF5282_FLEXCAN_MBUF13_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0157])) +#define MCF5282_FLEXCAN_MBUF13_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0158])) +#define MCF5282_FLEXCAN_MBUF13_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0159])) +#define MCF5282_FLEXCAN_MBUF13_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C015A])) +#define MCF5282_FLEXCAN_MBUF13_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C015B])) +#define MCF5282_FLEXCAN_MBUF13_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C015C])) +#define MCF5282_FLEXCAN_MBUF13_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C015D])) +#define MCF5282_FLEXCAN_MBUF14_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0161])) +#define MCF5282_FLEXCAN_MBUF14_IDH (*(vuint16 *)(&__IPSBAR[0x1C0162])) +#define MCF5282_FLEXCAN_MBUF14_IDL (*(vuint16 *)(&__IPSBAR[0x1C0164])) +#define MCF5282_FLEXCAN_MBUF14_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0166])) +#define MCF5282_FLEXCAN_MBUF14_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0167])) +#define MCF5282_FLEXCAN_MBUF14_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0168])) +#define MCF5282_FLEXCAN_MBUF14_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0169])) +#define MCF5282_FLEXCAN_MBUF14_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C016A])) +#define MCF5282_FLEXCAN_MBUF14_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C016B])) +#define MCF5282_FLEXCAN_MBUF14_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C016C])) +#define MCF5282_FLEXCAN_MBUF14_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C016D])) +#define MCF5282_FLEXCAN_MBUF15_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0171])) +#define MCF5282_FLEXCAN_MBUF15_IDH (*(vuint16 *)(&__IPSBAR[0x1C0172])) +#define MCF5282_FLEXCAN_MBUF15_IDL (*(vuint16 *)(&__IPSBAR[0x1C0174])) +#define MCF5282_FLEXCAN_MBUF15_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0176])) +#define MCF5282_FLEXCAN_MBUF15_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0177])) +#define MCF5282_FLEXCAN_MBUF15_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0178])) +#define MCF5282_FLEXCAN_MBUF15_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0179])) +#define MCF5282_FLEXCAN_MBUF15_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C017A])) +#define MCF5282_FLEXCAN_MBUF15_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C017B])) +#define MCF5282_FLEXCAN_MBUF15_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C017C])) +#define MCF5282_FLEXCAN_MBUF15_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C017D])) + +#define MCF5282_FLEXCAN_MBUF0_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0086+(x))])) +#define MCF5282_FLEXCAN_MBUF1_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0096+(x))])) +#define MCF5282_FLEXCAN_MBUF2_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00A6+(x))])) +#define MCF5282_FLEXCAN_MBUF3_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00B6+(x))])) +#define MCF5282_FLEXCAN_MBUF4_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00C6+(x))])) +#define MCF5282_FLEXCAN_MBUF5_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00D6+(x))])) +#define MCF5282_FLEXCAN_MBUF6_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00E6+(x))])) +#define MCF5282_FLEXCAN_MBUF7_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00F6+(x))])) +#define MCF5282_FLEXCAN_MBUF8_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0106+(x))])) +#define MCF5282_FLEXCAN_MBUF9_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0116+(x))])) +#define MCF5282_FLEXCAN_MBUF10_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0126+(x))])) +#define MCF5282_FLEXCAN_MBUF11_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0136+(x))])) +#define MCF5282_FLEXCAN_MBUF12_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0146+(x))])) +#define MCF5282_FLEXCAN_MBUF13_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0156+(x))])) +#define MCF5282_FLEXCAN_MBUF14_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0166+(x))])) +#define MCF5282_FLEXCAN_MBUF15_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0176+(x))])) + +#define MCF5282_FLEXCAN_MBUF_BYTE(x,y) (*(vuint8 *)(&__IPSBAR[((0x1C0086+(0x10*(x))+(y))])) + +/* Bit level definitions and macros */ +#define MCF5282_FLEXCAN_CANMCR_STOP (0x8000) +#define MCF5282_FLEXCAN_CANMCR_FRZ (0x4000) +#define MCF5282_FLEXCAN_CANMCR_HALT (0x1000) +#define MCF5282_FLEXCAN_CANMCR_NOTRDY (0x0800) +#define MCF5282_FLEXCAN_CANMCR_WAKEMSK (0x0400) +#define MCF5282_FLEXCAN_CANMCR_SOFTRST (0x0200) +#define MCF5282_FLEXCAN_CANMCR_FRZACK (0x0100) +#define MCF5282_FLEXCAN_CANMCR_SUPV (0x0080) +#define MCF5282_FLEXCAN_CANMCR_SELFWAKE (0x0040) +#define MCF5282_FLEXCAN_CANMCR_APS (0x0020) + +#define MCF5282_FLEXCAN_CANCTRL0_BOFFMSK (0x80) +#define MCF5282_FLEXCAN_CANCTRL0_ERRMSK (0x40) +#define MCF5282_FLEXCAN_CANCTRL0_RXMODE (0x04) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSPOS (0x00) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSNEG (0x01) +#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_OPENDRAIN (0x02) + +#define MCF5282_FLEXCAN_CANCTRL1_SAMP (0x80) +#define MCF5282_FLEXCAN_CANCTRL1_TSYNC (0x20) +#define MCF5282_FLEXCAN_CANCTRL1_LBUF (0x10) +#define MCF5282_FLEXCAN_CANCTRL1_LOM (0x08) +#define MCF5282_FLEXCAN_CANCTRL1_PROPSEG(x) (((x)&0x07)) + +#define MCF5282_FLEXCAN_CANCTRL2_RJW(x) (((x)&0x03)<<6) +#define MCF5282_FLEXCAN_CANCTRL2_PSEG1(x) (((x)&0x07)<<3) +#define MCF5282_FLEXCAN_CANCTRL2_PSEG2(x) (((x)&0x07)<<0) + +#define MCF5282_FLEXCAN_ESTAT_BITERR(x) (((x)&0x03)<<14) +#define MCF5282_FLEXCAN_ESTAT_ACKERR (0x2000) +#define MCF5282_FLEXCAN_ESTAT_CRCERR (0x1000) +#define MCF5282_FLEXCAN_ESTAT_FORMERR (0x0800) +#define MCF5282_FLEXCAN_ESTAT_STUFFERR (0x0400) +#define MCF5282_FLEXCAN_ESTAT_TXWARN (0x0200) +#define MCF5282_FLEXCAN_ESTAT_RXWARN (0x0100) +#define MCF5282_FLEXCAN_ESTAT_IDLE (0x0080) +#define MCF5282_FLEXCAN_ESTAT_TXRX (0x0040) +#define MCF5282_FLEXCAN_ESTAT_FCS(x) (((x)&0x03)<<4) +#define MCF5282_FLEXCAN_ESTAT_BOFFINT (0x0004) +#define MCF5282_FLEXCAN_ESTAT_ERRINT (0x0002) +#define MCF5282_FLEXCAN_ESTAT_WAKEINT (0x0001) + +#define MCF5282_FLEXCAN_IMASK_BUF15M (0x8000) +#define MCF5282_FLEXCAN_IMASK_BUF14M (0x4000) +#define MCF5282_FLEXCAN_IMASK_BUF13M (0x2000) +#define MCF5282_FLEXCAN_IMASK_BUF12M (0x1000) +#define MCF5282_FLEXCAN_IMASK_BUF11M (0x0800) +#define MCF5282_FLEXCAN_IMASK_BUF10M (0x0400) +#define MCF5282_FLEXCAN_IMASK_BUF9M (0x0200) +#define MCF5282_FLEXCAN_IMASK_BUF8M (0x0100) +#define MCF5282_FLEXCAN_IMASK_BUF7M (0x0080) +#define MCF5282_FLEXCAN_IMASK_BUF6M (0x0040) +#define MCF5282_FLEXCAN_IMASK_BUF5M (0x0020) +#define MCF5282_FLEXCAN_IMASK_BUF4M (0x0010) +#define MCF5282_FLEXCAN_IMASK_BUF3M (0x0008) +#define MCF5282_FLEXCAN_IMASK_BUF2M (0x0004) +#define MCF5282_FLEXCAN_IMASK_BUF1M (0x0002) +#define MCF5282_FLEXCAN_IMASK_BUF0M (0x0001) + +#define MCF5282_FLEXCAN_IFLAG_BUF15I (0x8000) +#define MCF5282_FLEXCAN_IFLAG_BUF14I (0x4000) +#define MCF5282_FLEXCAN_IFLAG_BUF13I (0x2000) +#define MCF5282_FLEXCAN_IFLAG_BUF12I (0x1000) +#define MCF5282_FLEXCAN_IFLAG_BUF11I (0x0800) +#define MCF5282_FLEXCAN_IFLAG_BUF10I (0x0400) +#define MCF5282_FLEXCAN_IFLAG_BUF9I (0x0200) +#define MCF5282_FLEXCAN_IFLAG_BUF8I (0x0100) +#define MCF5282_FLEXCAN_IFLAG_BUF7I (0x0080) +#define MCF5282_FLEXCAN_IFLAG_BUF6I (0x0040) +#define MCF5282_FLEXCAN_IFLAG_BUF5I (0x0020) +#define MCF5282_FLEXCAN_IFLAG_BUF4I (0x0010) +#define MCF5282_FLEXCAN_IFLAG_BUF3I (0x0008) +#define MCF5282_FLEXCAN_IFLAG_BUF2I (0x0004) +#define MCF5282_FLEXCAN_IFLAG_BUF1I (0x0002) +#define MCF5282_FLEXCAN_IFLAG_BUF0I (0x0001) + +/********************************************************************* +* +* ColdFire Flash Module (CFM) +* +*********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF5282_CFM_CFMMCR (*(vuint16 *)(&__IPSBAR[0x1D0000])) +#define MCF5282_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) +#define MCF5282_CFM_CFMSEC (*(vuint32 *)(&__IPSBAR[0x1D0008])) +#define MCF5282_CFM_CFMPROT (*(vuint32 *)(&__IPSBAR[0x1D0010])) +#define MCF5282_CFM_CFMSACC (*(vuint32 *)(&__IPSBAR[0x1D0014])) +#define MCF5282_CFM_CFMDACC (*(vuint32 *)(&__IPSBAR[0x1D0018])) +#define MCF5282_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) +#define MCF5282_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) +#define MCF5282_CFM_CFMDISU (*(vuint16 *)(&__IPSBAR[0x1D0042])) + +/* Bit level definitions and macros */ +#define MCF5282_CFM_FLASHBAR_BA(a) ((a)&0xFFF8000) +#define MCF5282_CFM_FLASHBAR_WP (0x00000100) +#define MCF5282_CFM_FLASHBAR_CI (0x00000020) +#define MCF5282_CFM_FLASHBAR_SC (0x00000010) +#define MCF5282_CFM_FLASHBAR_SD (0x00000008) +#define MCF5282_CFM_FLASHBAR_UC (0x00000004) +#define MCF5282_CFM_FLASHBAR_UD (0x00000002) +#define MCF5282_CFM_FLASHBAR_V (0x00000001) + +#define MCF5282_CFM_CFMMCR_LOCK (0x0400) +#define MCF5282_CFM_CFMMCR_PVIE (0x0200) +#define MCF5282_CFM_CFMMCR_AEIE (0x0100) +#define MCF5282_CFM_CFMMCR_CBEIE (0x0080) +#define MCF5282_CFM_CFMMCR_CCIE (0x0040) +#define MCF5282_CFM_CFMMCR_KEYACC (0x0020) + +#define MCF5282_CFM_CFMCLKD_DIVLD (0x80) +#define MCF5282_CFM_CFMCLKD_PRDIV8 (0x40) +#define MCF5282_CFM_CFMCLKD_DIV(x) (((x)&0x3F)) + +#define MCF5282_CFM_CFMSEC_KEYEN (0x80000000) +#define MCF5282_CFM_CFMSEC_SECSTAT (0x40000000) +#define MCF5282_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)) + +#define MCF5282_CFM_CFMUSTAT_CBEIF (0x80) +#define MCF5282_CFM_CFMUSTAT_CCIF (0x40) +#define MCF5282_CFM_CFMUSTAT_PVIOL (0x20) +#define MCF5282_CFM_CFMUSTAT_ACCERR (0x10) +#define MCF5282_CFM_CFMUSTAT_BLANK (0x04) + +#define MCF5282_CFM_CFMCMD_CMD(x) (((x)&0x7F)) + +/********************************************************************/ + +#endif /* _CPU_MCF5282_H */ diff --git a/bsps/m68k/include/mcf532x/mcf532x.h b/bsps/m68k/include/mcf532x/mcf532x.h new file mode 100644 index 0000000000..798fb1175b --- /dev/null +++ b/bsps/m68k/include/mcf532x/mcf532x.h @@ -0,0 +1,4483 @@ +/* + * File: mcf532x.h + * Purpose: Register and bit definitions + */ + +#ifndef __MCF532X_H__ +#define __MCF532X_H__ + +/********************************************************************* +* +* Cache +* +*********************************************************************/ + +#define MCF_CACR_CENB (1 << 31) +#define MCF_CACR_ESB (1 << 29) +#define MCF_CACR_DPI (1 << 28) +#define MCF_CACR_HLCK (1 << 27) +#define MCF_CACR_CINVA (1 << 24) +#define MCF_CACR_DNFB (1 << 10) +#define MCF_CACR_DCM(A) (((A) & 0x3) << 8) +#define MCF_CACR_DW (1 << 5) +#define MCF_CACR_EUSP (1 << 4) + +#define MCF_ACR_ADDR_BASE(A) (((A) & 0xFF) << 24) +#define MCF_ACR_ADDR_MASK(A) (((A) & 0xFF) << 16) +#define MCF_ACR_E (1 << 15) +#define MCF_ACR_S(A) (((A) & 0x3) << 13) +#define MCF_ACR_CM(A) (((A) & 0x3) << 5) +#define MCF_ACR_W (1 << 2) + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_MPR0 (*(vuint32*)(0xEC000000)) +#define MCF_SCM_MPR1 (*(vuint32*)(0xFC000000)) +#define MCF_SCM_BMT0 (*(vuint32*)(0xEC000054)) +#define MCF_SCM_BMT1 (*(vuint32*)(0xFC000054)) +#define MCF_SCM_PACRA (*(vuint32*)(0xFC000020)) +#define MCF_SCM_PACRB (*(vuint32*)(0xFC000024)) +#define MCF_SCM_PACRC (*(vuint32*)(0xFC000028)) +#define MCF_SCM_PACRD (*(vuint32*)(0xFC00002C)) +#define MCF_SCM_PACRE (*(vuint32*)(0xFC000040)) +#define MCF_SCM_PACRF (*(vuint32*)(0xFC000044)) +#define MCF_SCM_PACRG (*(vuint32*)(0xEC000048)) +#define MCF_SCM_PACRH (*(vuint32*)(0xEC000040)) +#define MCF_SCM_CWCR (*(vuint16*)(0xFC040016)) +#define MCF_SCM_CWSR (*(vuint8 *)(0xFC04001B)) +#define MCF_SCM_CWIR (*(vuint8 *)(0xFC04001F)) +#define MCF_SCM_BCR (*(vuint32*)(0xFC040024)) +#define MCF_SCM_CFADR (*(vuint32*)(0xFC040070)) +#define MCF_SCM_CFIER (*(vuint8 *)(0xFC040075)) +#define MCF_SCM_CFLOC (*(vuint8 *)(0xFC040076)) +#define MCF_SCM_CFATR (*(vuint8 *)(0xFC040077)) +#define MCF_SCM_CFDTR (*(vuint32*)(0xFC04007C)) + +/* Bit definitions and macros for MCF_SCM_MPR */ +#define MCF_SCM_MPR_MPROT6(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_MPR_MPROT5(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPR_MPROT4(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_MPR_MPROT2(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_MPR_MPROT1(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_MPR_MPROT0(x) (((x)&0x0000000F)<<28) +#define MCF_SCM_MPR_MPROT_MTR (0x4) +#define MCF_SCM_MPR_MPROT_MTW (0x2) +#define MCF_SCM_MPR_MPROT_MPL (0x1) + +/* Bit definitions and macros for MCF_SCM_BMT */ +#define MCF_SCM_BMT_BMT(x) (((x)&0x00000007)<<0) +#define MCF_SCM_BMT_BME (0x00000008) +#define MCF_SCM_BMT_BMT_1024 (0x00000000) +#define MCF_SCM_BMT_BMT_512 (0x00000001) +#define MCF_SCM_BMT_BMT_256 (0x00000002) +#define MCF_SCM_BMT_BMT_128 (0x00000003) +#define MCF_SCM_BMT_BMT_64 (0x00000004) +#define MCF_SCM_BMT_BMT_32 (0x00000005) +#define MCF_SCM_BMT_BMT_16 (0x00000006) +#define MCF_SCM_BMT_BMT_8 (0x00000007) + +/* Bit definitions and macros for MCF_SCM_PACRA */ +#define MCF_SCM_PACRA_PACR2(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRA_PACR1(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRA_PACR0(x) (((x)&0x0000000F)<<28) +#define MCF_SCM_PACRA_PACR_SP (0x4) +#define MCF_SCM_PACRA_PACR_WP (0x2) +#define MCF_SCM_PACRA_PACR_TP (0x1) + +/* Bit definitions and macros for MCF_SCM_PACRB */ +#define MCF_SCM_PACRB_PACR12(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRB_PACR8(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRC */ +#define MCF_SCM_PACRC_PACR23(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRC_PACR22(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRC_PACR21(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRC_PACR19(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRC_PACR18(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRC_PACR17(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRC_PACR16(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRD */ +#define MCF_SCM_PACRD_PACR31(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRD_PACR30(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRD_PACR29(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRD_PACR28(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRD_PACR26(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRD_PACR25(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRD_PACR24(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRE */ +#define MCF_SCM_PACRE_PACR38(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRE_PACR37(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRE_PACR36(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRE_PACR35(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRE_PACR34(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRE_PACR33(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRE_PACR32(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRF */ +#define MCF_SCM_PACRF_PACR47(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_PACRF_PACR46(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_PACRF_PACR45(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_PACRF_PACR44(x) (((x)&0x0000000F)<<12) +#define MCF_SCM_PACRF_PACR43(x) (((x)&0x0000000F)<<16) +#define MCF_SCM_PACRF_PACR42(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRF_PACR41(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRF_PACR40(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRG */ +#define MCF_SCM_PACRG_PACR48(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_PACRH */ +#define MCF_SCM_PACRH_PACR58(x) (((x)&0x0000000F)<<20) +#define MCF_SCM_PACRH_PACR57(x) (((x)&0x0000000F)<<24) +#define MCF_SCM_PACRH_PACR56(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWT(x) (((x)&0x001F)<<0) +#define MCF_SCM_CWCR_CWRI(x) (((x)&0x0003)<<5) +#define MCF_SCM_CWCR_CWE (0x0080) +#define MCF_SCM_CWCR_CWR_WH (0x0100) +#define MCF_SCM_CWCR_RO (0x8000) +#define MCF_SCM_CWCR_CWRI_INT (0x0000) +#define MCF_SCM_CWCR_CWRI_INT_THEN_RESET (0x0020) +#define MCF_SCM_CWCR_CWRI_RESET (0x0040) +#define MCF_SCM_CWCR_CWRI_WINDOW (0x0060) + +/* Bit definitions and macros for MCF_SCM_CWSR */ +#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SCM_CWIR */ +#define MCF_SCM_CWIR_CWIC (0x01) +#define MCF_SCM_CWIR_CFEI (0x02) + +/* Bit definitions and macros for MCF_SCM_BCR */ +#define MCF_SCM_BCR_S1 (0x00000002) +#define MCF_SCM_BCR_S4 (0x00000010) +#define MCF_SCM_BCR_S6 (0x00000040) +#define MCF_SCM_BCR_S7 (0x00000080) +#define MCF_SCM_BCR_GBW (0x00000100) +#define MCF_SCM_BCR_GBR (0x00000200) + +/* Bit definitions and macros for MCF_SCM_CFADR */ +#define MCF_SCM_CFADR_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SCM_CFIER */ +#define MCF_SCM_CFIER_ECFEI (0x01) + +/* Bit definitions and macros for MCF_SCM_CFLOC */ +#define MCF_SCM_CFLOC_LOC (0x80) + +/* Bit definitions and macros for MCF_SCM_CFATR */ +#define MCF_SCM_CFATR_TYPE (0x01) +#define MCF_SCM_CFATR_MODE (0x02) +#define MCF_SCM_CFATR_CACHE (0x08) +#define MCF_SCM_CFATR_SIZE(x) (((x)&0x07)<<4) +#define MCF_SCM_CFATR_WRITE (0x80) + +/* Bit definitions and macros for MCF_SCM_CFDTR */ +#define MCF_SCM_CFDTR_CFDTR(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Message Digest Hardware Accelerator (MDHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MDHA_MDMR (*(vuint32*)(0xEC080000)) +#define MCF_MDHA_MDCR (*(vuint32*)(0xEC080004)) +#define MCF_MDHA_MDCMR (*(vuint32*)(0xEC080008)) +#define MCF_MDHA_MDSR (*(vuint32*)(0xEC08000C)) +#define MCF_MDHA_MDISR (*(vuint32*)(0xEC080010)) +#define MCF_MDHA_MDIMR (*(vuint32*)(0xEC080014)) +#define MCF_MDHA_MDDSR (*(vuint32*)(0xEC08001C)) +#define MCF_MDHA_MDIN (*(vuint32*)(0xEC080020)) +#define MCF_MDHA_MDA0 (*(vuint32*)(0xEC080030)) +#define MCF_MDHA_MDB0 (*(vuint32*)(0xEC080034)) +#define MCF_MDHA_MDC0 (*(vuint32*)(0xEC080038)) +#define MCF_MDHA_MDD0 (*(vuint32*)(0xEC08003C)) +#define MCF_MDHA_MDE0 (*(vuint32*)(0xEC080040)) +#define MCF_MDHA_MDMDS (*(vuint32*)(0xEC080044)) +#define MCF_MDHA_MDA1 (*(vuint32*)(0xEC080070)) +#define MCF_MDHA_MDB1 (*(vuint32*)(0xEC080074)) +#define MCF_MDHA_MDC1 (*(vuint32*)(0xEC080078)) +#define MCF_MDHA_MDD1 (*(vuint32*)(0xEC08007C)) +#define MCF_MDHA_MDE1 (*(vuint32*)(0xEC080080)) + +/* Bit definitions and macros for MCF_MDHA_MDMR */ +#define MCF_MDHA_MDMR_ALG (0x00000001) +#define MCF_MDHA_MDMR_PDATA (0x00000004) +#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) +#define MCF_MDHA_MDMR_INIT (0x00000020) +#define MCF_MDHA_MDMR_IPAD (0x00000040) +#define MCF_MDHA_MDMR_OPAD (0x00000080) +#define MCF_MDHA_MDMR_SWAP (0x00000100) +#define MCF_MDHA_MDMR_MACFULL (0x00000200) +#define MCF_MDHA_MDMR_SSL (0x00000400) + +/* Bit definitions and macros for MCF_MDHA_MDCR */ +#define MCF_MDHA_MDCR_IE (0x00000001) +#define MCF_MDHA_MDCR_DMA (0x00000002) +#define MCF_MDHA_MDCR_ENDIAN (0x00000004) +#define MCF_MDHA_MDCR_DMAL(x) (((x)&0x0000001F)<<16) + +/* Bit definitions and macros for MCF_MDHA_MDCMR */ +#define MCF_MDHA_MDCMR_SWR (0x00000001) +#define MCF_MDHA_MDCMR_RI (0x00000002) +#define MCF_MDHA_MDCMR_CI (0x00000004) +#define MCF_MDHA_MDCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_MDHA_MDSR */ +#define MCF_MDHA_MDSR_INT (0x00000001) +#define MCF_MDHA_MDSR_DONE (0x00000002) +#define MCF_MDHA_MDSR_ERR (0x00000004) +#define MCF_MDHA_MDSR_RD (0x00000008) +#define MCF_MDHA_MDSR_BUSY (0x00000010) +#define MCF_MDHA_MDSR_END (0x00000020) +#define MCF_MDHA_MDSR_HSH (0x00000040) +#define MCF_MDHA_MDSR_GNW (0x00000080) +#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) +#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) +#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_MDHA_MDISR */ +#define MCF_MDHA_MDISR_IFO (0x00000001) +#define MCF_MDHA_MDISR_NON (0x00000004) +#define MCF_MDHA_MDISR_IME (0x00000010) +#define MCF_MDHA_MDISR_IDS (0x00000020) +#define MCF_MDHA_MDISR_RMDP (0x00000080) +#define MCF_MDHA_MDISR_ERE (0x00000100) +#define MCF_MDHA_MDISR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDIMR */ +#define MCF_MDHA_MDIMR_IFO (0x00000001) +#define MCF_MDHA_MDIMR_NON (0x00000004) +#define MCF_MDHA_MDIMR_IME (0x00000010) +#define MCF_MDHA_MDIMR_IDS (0x00000020) +#define MCF_MDHA_MDIMR_RMDP (0x00000080) +#define MCF_MDHA_MDIMR_ERE (0x00000100) +#define MCF_MDHA_MDIMR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDDSR */ +#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDIN */ +#define MCF_MDHA_MDIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDA0 */ +#define MCF_MDHA_MDA0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDB0 */ +#define MCF_MDHA_MDB0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDC0 */ +#define MCF_MDHA_MDC0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDD0 */ +#define MCF_MDHA_MDD0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDE0 */ +#define MCF_MDHA_MDE0_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDMDS */ +#define MCF_MDHA_MDMDS_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDA1 */ +#define MCF_MDHA_MDA1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDB1 */ +#define MCF_MDHA_MDB1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDC1 */ +#define MCF_MDHA_MDC1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDD1 */ +#define MCF_MDHA_MDD1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MDHA_MDE1 */ +#define MCF_MDHA_MDE1_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Symmetric Key Hardware Accelerator (SKHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SKHA_SKMR (*(vuint32*)(0xEC084000)) +#define MCF_SKHA_SKCR (*(vuint32*)(0xEC084004)) +#define MCF_SKHA_SKCMR (*(vuint32*)(0xEC084008)) +#define MCF_SKHA_SKSR (*(vuint32*)(0xEC08400C)) +#define MCF_SKHA_SKISR (*(vuint32*)(0xEC084010)) +#define MCF_SKHA_SKIMR (*(vuint32*)(0xEC084014)) +#define MCF_SKHA_SKKSR (*(vuint32*)(0xEC084018)) +#define MCF_SKHA_SKDSR (*(vuint32*)(0xEC08401C)) +#define MCF_SKHA_SKIN (*(vuint32*)(0xEC084020)) +#define MCF_SKHA_SKOUT (*(vuint32*)(0xEC084024)) +#define MCF_SKHA_SKK0 (*(vuint32*)(0xEC084030)) +#define MCF_SKHA_SKK1 (*(vuint32*)(0xEC084034)) +#define MCF_SKHA_SKK2 (*(vuint32*)(0xEC084038)) +#define MCF_SKHA_SKK3 (*(vuint32*)(0xEC08403C)) +#define MCF_SKHA_SKK4 (*(vuint32*)(0xEC084040)) +#define MCF_SKHA_SKK5 (*(vuint32*)(0xEC084044)) +#define MCF_SKHA_SKK(x) (*(vuint32*)(0xEC084030+((x)*0x004))) +#define MCF_SKHA_SKC0 (*(vuint32*)(0xEC084070)) +#define MCF_SKHA_SKC1 (*(vuint32*)(0xEC084074)) +#define MCF_SKHA_SKC2 (*(vuint32*)(0xEC084078)) +#define MCF_SKHA_SKC3 (*(vuint32*)(0xEC08407C)) +#define MCF_SKHA_SKC4 (*(vuint32*)(0xEC084080)) +#define MCF_SKHA_SKC5 (*(vuint32*)(0xEC084084)) +#define MCF_SKHA_SKC6 (*(vuint32*)(0xEC084088)) +#define MCF_SKHA_SKC7 (*(vuint32*)(0xEC08408C)) +#define MCF_SKHA_SKC8 (*(vuint32*)(0xEC084090)) +#define MCF_SKHA_SKC9 (*(vuint32*)(0xEC084094)) +#define MCF_SKHA_SKC10 (*(vuint32*)(0xEC084098)) +#define MCF_SKHA_SKC11 (*(vuint32*)(0xEC08409C)) +#define MCF_SKHA_SKC(x) (*(vuint32*)(0xEC084070+((x)*0x004))) + +/* Bit definitions and macros for MCF_SKHA_SKMR */ +#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) +#define MCF_SKHA_SKMR_DIR (0x00000004) +#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) +#define MCF_SKHA_SKMR_DKP (0x00000100) +#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) +#define MCF_SKHA_SKMR_CM_ECB (0x00000000) +#define MCF_SKHA_SKMR_CM_CBC (0x00000008) +#define MCF_SKHA_SKMR_CM_CTR (0x00000018) +#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) +#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) +#define MCF_SKHA_SKMR_ALG_AES (0x00000000) +#define MCF_SKHA_SKMR_ALG_DES (0x00000001) +#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) + +/* Bit definitions and macros for MCF_SKHA_SKCR */ +#define MCF_SKHA_SKCR_IE (0x00000001) +#define MCF_SKHA_SKCR_IDMA (0x00000002) +#define MCF_SKHA_SKCR_ODMA (0x00000004) +#define MCF_SKHA_SKCR_ENDIAN (0x00000008) +#define MCF_SKHA_SKCR_IDMAL(x) (((x)&0x0000003F)<<16) +#define MCF_SKHA_SKCR_ODMAL(x) (((x)&0x0000003F)<<24) + +/* Bit definitions and macros for MCF_SKHA_SKCMR */ +#define MCF_SKHA_SKCMR_SWR (0x00000001) +#define MCF_SKHA_SKCMR_RI (0x00000002) +#define MCF_SKHA_SKCMR_CI (0x00000004) +#define MCF_SKHA_SKCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_SKHA_SKSR */ +#define MCF_SKHA_SKSR_INT (0x00000001) +#define MCF_SKHA_SKSR_DONE (0x00000002) +#define MCF_SKHA_SKSR_ERR (0x00000004) +#define MCF_SKHA_SKSR_RD (0x00000008) +#define MCF_SKHA_SKSR_BUSY (0x00000010) +#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) +#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_SKHA_SKISR */ +#define MCF_SKHA_SKISR_IFO (0x00000001) +#define MCF_SKHA_SKISR_OFU (0x00000002) +#define MCF_SKHA_SKISR_NEIF (0x00000004) +#define MCF_SKHA_SKISR_NEOF (0x00000008) +#define MCF_SKHA_SKISR_IME (0x00000010) +#define MCF_SKHA_SKISR_DSE (0x00000020) +#define MCF_SKHA_SKISR_KSE (0x00000040) +#define MCF_SKHA_SKISR_RMDP (0x00000080) +#define MCF_SKHA_SKISR_ERE (0x00000100) +#define MCF_SKHA_SKISR_KPE (0x00000200) +#define MCF_SKHA_SKISR_KRE (0x00000400) +#define MCF_SKHA_SKISR_DRL (0x00000800) + +/* Bit definitions and macros for MCF_SKHA_SKIMR */ +#define MCF_SKHA_SKIMR_IFO (0x00000001) +#define MCF_SKHA_SKIMR_OFU (0x00000002) +#define MCF_SKHA_SKIMR_NEIF (0x00000004) +#define MCF_SKHA_SKIMR_NEOF (0x00000008) +#define MCF_SKHA_SKIMR_IME (0x00000010) +#define MCF_SKHA_SKIMR_DSE (0x00000020) +#define MCF_SKHA_SKIMR_KSE (0x00000040) +#define MCF_SKHA_SKIMR_RMDP (0x00000080) +#define MCF_SKHA_SKIMR_ERE (0x00000100) +#define MCF_SKHA_SKIMR_KPE (0x00000200) +#define MCF_SKHA_SKIMR_KRE (0x00000400) +#define MCF_SKHA_SKIMR_DRL (0x00000800) + +/* Bit definitions and macros for MCF_SKHA_SKKSR */ +#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKDSR */ +#define MCF_SKHA_SKDSR_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKIN */ +#define MCF_SKHA_SKIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKOUT */ +#define MCF_SKHA_SKOUT_DATAOUT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKK */ +#define MCF_SKHA_SKK_KEY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SKHA_SKC */ +#define MCF_SKHA_SKC_CONTEXT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RNG_RNGCR (*(vuint32*)(0xEC088000)) +#define MCF_RNG_RNGSR (*(vuint32*)(0xEC088004)) +#define MCF_RNG_RNGER (*(vuint32*)(0xEC088008)) +#define MCF_RNG_RNGOUT (*(vuint32*)(0xEC08800C)) + +/* Bit definitions and macros for MCF_RNG_RNGCR */ +#define MCF_RNG_RNGCR_GO (0x00000001) +#define MCF_RNG_RNGCR_HA (0x00000002) +#define MCF_RNG_RNGCR_IM (0x00000004) +#define MCF_RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for MCF_RNG_RNGSR */ +#define MCF_RNG_RNGSR_SV (0x00000001) +#define MCF_RNG_RNGSR_LRS (0x00000002) +#define MCF_RNG_RNGSR_FUF (0x00000004) +#define MCF_RNG_RNGSR_EI (0x00000008) +#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_RNG_RNGER */ +#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_RNG_RNGOUT */ +#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Power Management Module (PMM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PMM_WCR (*(vuint8 *)(0xFC040013)) +#define MCF_PMM_PPMSR0 (*(vuint8 *)(0xFC04002C)) +#define MCF_PMM_PPMSR1 (*(vuint8 *)(0xFC04002E)) +#define MCF_PMM_PPMCR0 (*(vuint8 *)(0xFC04002D)) +#define MCF_PMM_PPMCR1 (*(vuint8 *)(0xFC04002F)) +#define MCF_PMM_PPMHR0 (*(vuint32*)(0xFC040030)) +#define MCF_PMM_PPMLR0 (*(vuint32*)(0xFC040034)) +#define MCF_PMM_PPMHR1 (*(vuint32*)(0xFC040038)) +#define MCF_PMM_LPCR (*(vuint8 *)(0xFC0A0007)) + +/* Bit definitions and macros for MCF_PMM_WCR */ +#define MCF_PMM_WCR_PRILVL(x) (((x)&0x07)<<0) +#define MCF_PMM_WCR_ENBWCR (0x80) + +/* Bit definitions and macros for MCF_PMM_PPMSR */ +#define MCF_PMM_PPMSR_SMCD(x) (((x)&0x3F)<<0) +#define MCF_PMM_PPMSR_SAMCD (0x40) + +/* Bit definitions and macros for MCF_PMM_PPMCR */ +#define MCF_PMM_PPMCR_CMCD(x) (((x)&0x3F)<<0) +#define MCF_PMM_PPMCR_CAMCD (0x40) + +/* Bit definitions and macros for MCF_PMM_PPMHR0 */ +#define MCF_PMM_PPMHR0_CD32 (0x00000001) +#define MCF_PMM_PPMHR0_CD33 (0x00000002) +#define MCF_PMM_PPMHR0_CD34 (0x00000004) +#define MCF_PMM_PPMHR0_CD35 (0x00000008) +#define MCF_PMM_PPMHR0_CD36 (0x00000010) +#define MCF_PMM_PPMHR0_CD37 (0x00000020) +#define MCF_PMM_PPMHR0_CD38 (0x00000040) +#define MCF_PMM_PPMHR0_CD40 (0x00000100) +#define MCF_PMM_PPMHR0_CD41 (0x00000200) +#define MCF_PMM_PPMHR0_CD42 (0x00000400) +#define MCF_PMM_PPMHR0_CD43 (0x00000800) +#define MCF_PMM_PPMHR0_CD44 (0x00001000) +#define MCF_PMM_PPMHR0_CD45 (0x00002000) +#define MCF_PMM_PPMHR0_CD46 (0x00004000) +#define MCF_PMM_PPMHR0_CD47 (0x00008000) +#define MCF_PMM_PPMHR0_CD48 (0x00010000) + +/* Bit definitions and macros for MCF_PMM_PPMLR0 */ +#define MCF_PMM_PPMLR0_CD2 (0x00000004) +#define MCF_PMM_PPMLR0_CD8 (0x00000100) +#define MCF_PMM_PPMLR0_CD12 (0x00001000) +#define MCF_PMM_PPMLR0_CD17 (0x00020000) +#define MCF_PMM_PPMLR0_CD18 (0x00040000) +#define MCF_PMM_PPMLR0_CD19 (0x00080000) +#define MCF_PMM_PPMLR0_CD21 (0x00200000) +#define MCF_PMM_PPMLR0_CD22 (0x00400000) +#define MCF_PMM_PPMLR0_CD23 (0x00800000) +#define MCF_PMM_PPMLR0_CD24 (0x01000000) +#define MCF_PMM_PPMLR0_CD25 (0x02000000) +#define MCF_PMM_PPMLR0_CD26 (0x04000000) +#define MCF_PMM_PPMLR0_CD28 (0x10000000) +#define MCF_PMM_PPMLR0_CD29 (0x20000000) +#define MCF_PMM_PPMLR0_CD30 (0x40000000) +#define MCF_PMM_PPMLR0_CD31 (0x80000000) + +/* Bit definitions and macros for MCF_PMM_PPMHR1 */ +#define MCF_PMM_PPMHR1_CD32 (0x00000001) +#define MCF_PMM_PPMHR1_CD33 (0x00000002) +#define MCF_PMM_PPMHR1_CD34 (0x00000004) + +/* Bit definitions and macros for MCF_PMM_LPCR */ +#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_PMM_LPCR_FWKUP (0x20) +#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_PMM_LPCR_LPMD_RUN (0x00) +#define MCF_PMM_LPCR_LPMD_DOZE (0x40) +#define MCF_PMM_LPCR_LPMD_WAIT (0x80) +#define MCF_PMM_LPCR_LPMD_STOP (0xC0) +#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0x00) +#define MCF_PMM_LPCR_STPMD_SYS_BUSCLK_DISABLED (0x04) +#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x08) +#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x0C) + +/********************************************************************* +* +* Cross-bar switch (XBS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XBS_PRS1 (*(vuint32*)(0xFC004100)) +#define MCF_XBS_PRS2 (*(vuint32*)(0xFC004200)) +#define MCF_XBS_PRS3 (*(vuint32*)(0xFC004300)) +#define MCF_XBS_PRS4 (*(vuint32*)(0xFC004400)) +#define MCF_XBS_PRS5 (*(vuint32*)(0xFC004500)) +#define MCF_XBS_PRS6 (*(vuint32*)(0xFC004600)) +#define MCF_XBS_PRS7 (*(vuint32*)(0xFC004700)) +#define MCF_XBS_PRS(x) (*(vuint32*)(0xFC004100+((x-1)*0x100))) +#define MCF_XBS_CRS1 (*(vuint32*)(0xFC004110)) +#define MCF_XBS_CRS2 (*(vuint32*)(0xFC004210)) +#define MCF_XBS_CRS3 (*(vuint32*)(0xFC004310)) +#define MCF_XBS_CRS4 (*(vuint32*)(0xFC004410)) +#define MCF_XBS_CRS5 (*(vuint32*)(0xFC004510)) +#define MCF_XBS_CRS6 (*(vuint32*)(0xFC004610)) +#define MCF_XBS_CRS7 (*(vuint32*)(0xFC004710)) +#define MCF_XBS_CRS(x) (*(vuint32*)(0xFC004110+((x-1)*0x100))) + +/* Bit definitions and macros for MCF_XBS_PRS */ +#define MCF_XBS_PRS_M0(x) (((x)&0x00000007)<<0) +#define MCF_XBS_PRS_M1(x) (((x)&0x00000007)<<4) +#define MCF_XBS_PRS_M2(x) (((x)&0x00000007)<<8) +#define MCF_XBS_PRS_M4(x) (((x)&0x00000007)<<16) +#define MCF_XBS_PRS_M5(x) (((x)&0x00000007)<<20) +#define MCF_XBS_PRS_M6(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF_XBS_CRS */ +#define MCF_XBS_CRS_PARK(x) (((x)&0x00000007)<<0) +#define MCF_XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) +#define MCF_XBS_CRS_ARB (0x00000100) +#define MCF_XBS_CRS_RO (0x80000000) +#define MCF_XBS_CRS_PCTL_PARK_FIELD (0x00000000) +#define MCF_XBS_CRS_PCTL_PARK_ON_LAST (0x00000010) +#define MCF_XBS_CRS_PCTL_PARK_NO_MASTER (0x00000020) +#define MCF_XBS_CRS_PCTL_PARK_CORE (0x00000000) +#define MCF_XBS_CRS_PCTL_PARK_EDMA (0x00000001) +#define MCF_XBS_CRS_PCTL_PARK_FEC (0x00000002) + +/********************************************************************* +* +* FlexBus Chip Selects (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(vuint32*)(0xFC008000)) +#define MCF_FBCS0_CSMR (*(vuint32*)(0xFC008004)) +#define MCF_FBCS0_CSCR (*(vuint32*)(0xFC008008)) +#define MCF_FBCS1_CSAR (*(vuint32*)(0xFC00800C)) +#define MCF_FBCS1_CSMR (*(vuint32*)(0xFC008010)) +#define MCF_FBCS1_CSCR (*(vuint32*)(0xFC008014)) +#define MCF_FBCS2_CSAR (*(vuint32*)(0xFC008018)) +#define MCF_FBCS2_CSMR (*(vuint32*)(0xFC00801C)) +#define MCF_FBCS2_CSCR (*(vuint32*)(0xFC008020)) +#define MCF_FBCS3_CSAR (*(vuint32*)(0xFC008024)) +#define MCF_FBCS3_CSMR (*(vuint32*)(0xFC008028)) +#define MCF_FBCS3_CSCR (*(vuint32*)(0xFC00802C)) +#define MCF_FBCS4_CSAR (*(vuint32*)(0xFC008030)) +#define MCF_FBCS4_CSMR (*(vuint32*)(0xFC008034)) +#define MCF_FBCS4_CSCR (*(vuint32*)(0xFC008038)) +#define MCF_FBCS5_CSAR (*(vuint32*)(0xFC00803C)) +#define MCF_FBCS5_CSMR (*(vuint32*)(0xFC008040)) +#define MCF_FBCS5_CSCR (*(vuint32*)(0xFC008044)) +#define MCF_FBCS_CSAR(x) (*(vuint32*)(0xFC008000+((x)*0x00C))) +#define MCF_FBCS_CSMR(x) (*(vuint32*)(0xFC008004+((x)*0x00C))) +#define MCF_FBCS_CSCR(x) (*(vuint32*)(0xFC008008+((x)*0x00C))) + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x00000001) +#define MCF_FBCS_CSMR_WP (0x00000100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x00000008) +#define MCF_FBCS_CSCR_BSTR (0x00000010) +#define MCF_FBCS_CSCR_BEM (0x00000020) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +#define MCF_FBCS_CSCR_AA (0x00000100) +#define MCF_FBCS_CSCR_SBM (0x00000200) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +#define MCF_FBCS_CSCR_SWSEN (0x00800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +#define MCF_FBCS_CSCR_PS_8 (0x00000040) +#define MCF_FBCS_CSCR_PS_16 (0x00000080) +#define MCF_FBCS_CSCR_PS_32 (0x00000000) + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR (*(vuint32*)(0xFC020000)) +#define MCF_CAN_CANCTRL (*(vuint32*)(0xFC020004)) +#define MCF_CAN_TIMER (*(vuint32*)(0xFC020008)) +#define MCF_CAN_RXGMASK (*(vuint32*)(0xFC020010)) +#define MCF_CAN_RX14MASK (*(vuint32*)(0xFC020014)) +#define MCF_CAN_RX15MASK (*(vuint32*)(0xFC020018)) +#define MCF_CAN_ERRCNT (*(vuint32*)(0xFC02001C)) +#define MCF_CAN_ERRSTAT (*(vuint32*)(0xFC020020)) +#define MCF_CAN_IMASK (*(vuint32*)(0xFC020028)) +#define MCF_CAN_IFLAG (*(vuint32*)(0xFC020030)) + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_LPMACK (0x00100000) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_NOTRDY (0x08000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF0M (0x00000001) +#define MCF_CAN_IMASK_BUF1M (0x00000002) +#define MCF_CAN_IMASK_BUF2M (0x00000004) +#define MCF_CAN_IMASK_BUF3M (0x00000008) +#define MCF_CAN_IMASK_BUF4M (0x00000010) +#define MCF_CAN_IMASK_BUF5M (0x00000020) +#define MCF_CAN_IMASK_BUF6M (0x00000040) +#define MCF_CAN_IMASK_BUF7M (0x00000080) +#define MCF_CAN_IMASK_BUF8M (0x00000100) +#define MCF_CAN_IMASK_BUF9M (0x00000200) +#define MCF_CAN_IMASK_BUF10M (0x00000400) +#define MCF_CAN_IMASK_BUF11M (0x00000800) +#define MCF_CAN_IMASK_BUF12M (0x00001000) +#define MCF_CAN_IMASK_BUF13M (0x00002000) +#define MCF_CAN_IMASK_BUF14M (0x00004000) +#define MCF_CAN_IMASK_BUF15M (0x00008000) +#define MCF_CAN_IMASK_BUF(x) (1<<x) + +/* Bit definitions and macros for MCF_CAN_IFLAG */ +#define MCF_CAN_IFLAG_BUF0I (0x00000001) +#define MCF_CAN_IFLAG_BUF1I (0x00000002) +#define MCF_CAN_IFLAG_BUF2I (0x00000004) +#define MCF_CAN_IFLAG_BUF3I (0x00000008) +#define MCF_CAN_IFLAG_BUF4I (0x00000010) +#define MCF_CAN_IFLAG_BUF5I (0x00000020) +#define MCF_CAN_IFLAG_BUF6I (0x00000040) +#define MCF_CAN_IFLAG_BUF7I (0x00000080) +#define MCF_CAN_IFLAG_BUF8I (0x00000100) +#define MCF_CAN_IFLAG_BUF9I (0x00000200) +#define MCF_CAN_IFLAG_BUF10I (0x00000400) +#define MCF_CAN_IFLAG_BUF11I (0x00000800) +#define MCF_CAN_IFLAG_BUF12I (0x00001000) +#define MCF_CAN_IFLAG_BUF13I (0x00002000) +#define MCF_CAN_IFLAG_BUF14I (0x00004000) +#define MCF_CAN_IFLAG_BUF15I (0x00008000) +#define MCF_CAN_IFLAG_BUF(x) (1<<x) + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC_EIR (*(vuint32*)(0xFC030004)) +#define MCF_FEC_EIMR (*(vuint32*)(0xFC030008)) +#define MCF_FEC_RDAR (*(vuint32*)(0xFC030010)) +#define MCF_FEC_TDAR (*(vuint32*)(0xFC030014)) +#define MCF_FEC_ECR (*(vuint32*)(0xFC030024)) +#define MCF_FEC_MMFR (*(vuint32*)(0xFC030040)) +#define MCF_FEC_MSCR (*(vuint32*)(0xFC030044)) +#define MCF_FEC_MIBC (*(vuint32*)(0xFC030064)) +#define MCF_FEC_RCR (*(vuint32*)(0xFC030084)) +#define MCF_FEC_TCR (*(vuint32*)(0xFC0300C4)) +#define MCF_FEC_PALR (*(vuint32*)(0xFC0300E4)) +#define MCF_FEC_PAUR (*(vuint32*)(0xFC0300E8)) +#define MCF_FEC_OPD (*(vuint32*)(0xFC0300EC)) +#define MCF_FEC_IAUR (*(vuint32*)(0xFC030118)) +#define MCF_FEC_IALR (*(vuint32*)(0xFC03011C)) +#define MCF_FEC_GAUR (*(vuint32*)(0xFC030120)) +#define MCF_FEC_GALR (*(vuint32*)(0xFC030124)) +#define MCF_FEC_TFWR (*(vuint32*)(0xFC030144)) +#define MCF_FEC_FRBR (*(vuint32*)(0xFC03014C)) +#define MCF_FEC_FRSR (*(vuint32*)(0xFC030150)) +#define MCF_FEC_ERDSR (*(vuint32*)(0xFC030180)) +#define MCF_FEC_ETDSR (*(vuint32*)(0xFC030184)) +#define MCF_FEC_EMRBR (*(vuint32*)(0xFC030188)) +#define MCF_FEC_RMON_T_DROP (*(vuint32*)(0xFC030200)) +#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(0xFC030204)) +#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(0xFC030208)) +#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(0xFC03020C)) +#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(0xFC030210)) +#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(0xFC030214)) +#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(0xFC030218)) +#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(0xFC03021C)) +#define MCF_FEC_RMON_T_JAB (*(vuint32*)(0xFC030220)) +#define MCF_FEC_RMON_T_COL (*(vuint32*)(0xFC030224)) +#define MCF_FEC_RMON_T_P64 (*(vuint32*)(0xFC030228)) +#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(0xFC03022C)) +#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(0xFC030230)) +#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(0xFC030234)) +#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(0xFC030238)) +#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(0xFC03023C)) +#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(0xFC030240)) +#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(0xFC030244)) +#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(0xFC030248)) +#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(0xFC03024C)) +#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(0xFC030250)) +#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(0xFC030254)) +#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(0xFC030258)) +#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(0xFC03025C)) +#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(0xFC030260)) +#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(0xFC030264)) +#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(0xFC030268)) +#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(0xFC03026C)) +#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(0xFC030270)) +#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(0xFC030274)) +#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(0xFC030284)) +#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(0xFC030288)) +#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(0xFC03028C)) +#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(0xFC030290)) +#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(0xFC030294)) +#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(0xFC030298)) +#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(0xFC03029C)) +#define MCF_FEC_RMON_R_JAB (*(vuint32*)(0xFC0302A0)) +#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(0xFC0302A4)) +#define MCF_FEC_RMON_R_P64 (*(vuint32*)(0xFC0302A8)) +#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(0xFC0302AC)) +#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(0xFC0302B0)) +#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(0xFC0302B4)) +#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(0xFC0302B8)) +#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(0xFC0302C0)) +#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(0xFC0302BC)) +#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(0xFC0302C4)) +#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(0xFC0302C8)) +#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(0xFC0302CC)) +#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(0xFC0302D0)) +#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(0xFC0302D4)) +#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(0xFC0302D8)) +#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(0xFC0302DC)) +#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(0xFC0302E0)) + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_UN (0x00080000) +#define MCF_FEC_EIR_RL (0x00100000) +#define MCF_FEC_EIR_LC (0x00200000) +#define MCF_FEC_EIR_EBERR (0x00400000) +#define MCF_FEC_EIR_MII (0x00800000) +#define MCF_FEC_EIR_RXB (0x01000000) +#define MCF_FEC_EIR_RXF (0x02000000) +#define MCF_FEC_EIR_TXB (0x04000000) +#define MCF_FEC_EIR_TXF (0x08000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_UN (0x00080000) +#define MCF_FEC_EIMR_RL (0x00100000) +#define MCF_FEC_EIMR_LC (0x00200000) +#define MCF_FEC_EIMR_EBERR (0x00400000) +#define MCF_FEC_EIMR_MII (0x00800000) +#define MCF_FEC_EIMR_RXB (0x01000000) +#define MCF_FEC_EIMR_RXF (0x02000000) +#define MCF_FEC_EIMR_TXB (0x04000000) +#define MCF_FEC_EIMR_TXF (0x08000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0x00000000) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_RDAR */ +#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_TDAR */ +#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF_FEC_MMFR_ST_01 (0x40000000) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x00000001) +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_MII_MODE (0x00000004) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_BC_REJ (0x00000010) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x00000001) +#define MCF_FEC_TCR_HBC (0x00000002) +#define MCF_FEC_TCR_FDEN (0x00000004) +#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAUR */ +#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_TFWR */ +#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) + +/* Bit definitions and macros for MCF_FEC_FRBR */ +#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_FRSR */ +#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_ERDSR */ +#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_ETDSR */ +#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_EMRBR */ +#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) + +#define MCF_FEC_TxBD_R 0x8000 +#define MCF_FEC_TxBD_BUSY 0x4000 +#define MCF_FEC_TxBD_TO1 0x4000 +#define MCF_FEC_TxBD_W 0x2000 +#define MCF_FEC_TxBD_TO2 0x1000 +#define MCF_FEC_TxBD_FIRST 0x1000 +#define MCF_FEC_TxBD_L 0x0800 +#define MCF_FEC_TxBD_TC 0x0400 +#define MCF_FEC_TxBD_DEF 0x0200 +#define MCF_FEC_TxBD_HB 0x0100 +#define MCF_FEC_TxBD_LC 0x0080 +#define MCF_FEC_TxBD_RL 0x0040 +#define MCF_FEC_TxBD_UN 0x0002 +#define MCF_FEC_TxBD_CSL 0x0001 +#define MCF_FEC_RxBD_E 0x8000 +#define MCF_FEC_RxBD_INUSE 0x4000 +#define MCF_FEC_RxBD_R01 0x4000 +#define MCF_FEC_RxBD_W 0x2000 +#define MCF_FEC_RxBD_R02 0x1000 +#define MCF_FEC_RxBD_L 0x0800 +#define MCF_FEC_RxBD_M 0x0100 +#define MCF_FEC_RxBD_BC 0x0080 +#define MCF_FEC_RxBD_MC 0x0040 +#define MCF_FEC_RxBD_LG 0x0020 +#define MCF_FEC_RxBD_NO 0x0010 +#define MCF_FEC_RxBD_CR 0x0004 +#define MCF_FEC_RxBD_OV 0x0002 +#define MCF_FEC_RxBD_TR 0x0001 + +/********************************************************************* +* +* Enhanced DMA (EDMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EDMA_CR (*(vuint32*)(0xFC044000)) +#define MCF_EDMA_ES (*(vuint32*)(0xFC044004)) +#define MCF_EDMA_ERQ (*(vuint16*)(0xFC04400E)) +#define MCF_EDMA_EEI (*(vuint16*)(0xFC044016)) +#define MCF_EDMA_SERQ (*(vuint8 *)(0xFC044018)) +#define MCF_EDMA_CERQ (*(vuint8 *)(0xFC044019)) +#define MCF_EDMA_SEEI (*(vuint8 *)(0xFC04401A)) +#define MCF_EDMA_CEEI (*(vuint8 *)(0xFC04401B)) +#define MCF_EDMA_CINT (*(vuint8 *)(0xFC04401C)) +#define MCF_EDMA_CERR (*(vuint8 *)(0xFC04401D)) +#define MCF_EDMA_SSRT (*(vuint8 *)(0xFC04401E)) +#define MCF_EDMA_CDNE (*(vuint8 *)(0xFC04401F)) +#define MCF_EDMA_INT (*(vuint16*)(0xFC044026)) +#define MCF_EDMA_ERR (*(vuint16*)(0xFC04402E)) +#define MCF_EDMA_DCHPRI0 (*(vuint8 *)(0xFC044100)) +#define MCF_EDMA_DCHPRI1 (*(vuint8 *)(0xFC044101)) +#define MCF_EDMA_DCHPRI2 (*(vuint8 *)(0xFC044102)) +#define MCF_EDMA_DCHPRI3 (*(vuint8 *)(0xFC044103)) +#define MCF_EDMA_DCHPRI4 (*(vuint8 *)(0xFC044104)) +#define MCF_EDMA_DCHPRI5 (*(vuint8 *)(0xFC044105)) +#define MCF_EDMA_DCHPRI6 (*(vuint8 *)(0xFC044106)) +#define MCF_EDMA_DCHPRI7 (*(vuint8 *)(0xFC044107)) +#define MCF_EDMA_DCHPRI8 (*(vuint8 *)(0xFC044108)) +#define MCF_EDMA_DCHPRI9 (*(vuint8 *)(0xFC044109)) +#define MCF_EDMA_DCHPRI10 (*(vuint8 *)(0xFC04410A)) +#define MCF_EDMA_DCHPRI11 (*(vuint8 *)(0xFC04410B)) +#define MCF_EDMA_DCHPRI12 (*(vuint8 *)(0xFC04410C)) +#define MCF_EDMA_DCHPRI13 (*(vuint8 *)(0xFC04410D)) +#define MCF_EDMA_DCHPRI14 (*(vuint8 *)(0xFC04410E)) +#define MCF_EDMA_DCHPRI15 (*(vuint8 *)(0xFC04410F)) +#define MCF_EDMA_DCHPRI(x) (*(vuint8 *)(0xFC044100+((x)*0x001))) +#define MCF_EDMA_TCD0_SADDR (*(vuint32*)(0xFC045000)) +#define MCF_EDMA_TCD1_SADDR (*(vuint32*)(0xFC045020)) +#define MCF_EDMA_TCD2_SADDR (*(vuint32*)(0xFC045040)) +#define MCF_EDMA_TCD3_SADDR (*(vuint32*)(0xFC045060)) +#define MCF_EDMA_TCD4_SADDR (*(vuint32*)(0xFC045080)) +#define MCF_EDMA_TCD5_SADDR (*(vuint32*)(0xFC0450A0)) +#define MCF_EDMA_TCD6_SADDR (*(vuint32*)(0xFC0450C0)) +#define MCF_EDMA_TCD7_SADDR (*(vuint32*)(0xFC0450E0)) +#define MCF_EDMA_TCD8_SADDR (*(vuint32*)(0xFC045100)) +#define MCF_EDMA_TCD9_SADDR (*(vuint32*)(0xFC045120)) +#define MCF_EDMA_TCD10_SADDR (*(vuint32*)(0xFC045140)) +#define MCF_EDMA_TCD11_SADDR (*(vuint32*)(0xFC045160)) +#define MCF_EDMA_TCD12_SADDR (*(vuint32*)(0xFC045180)) +#define MCF_EDMA_TCD13_SADDR (*(vuint32*)(0xFC0451A0)) +#define MCF_EDMA_TCD14_SADDR (*(vuint32*)(0xFC0451C0)) +#define MCF_EDMA_TCD15_SADDR (*(vuint32*)(0xFC0451E0)) +#define MCF_EDMA_TCD_SADDR(x) (*(vuint32*)(0xFC045000+((x)*0x020))) +#define MCF_EDMA_TCD0_ATTR (*(vuint16*)(0xFC045004)) +#define MCF_EDMA_TCD1_ATTR (*(vuint16*)(0xFC045024)) +#define MCF_EDMA_TCD2_ATTR (*(vuint16*)(0xFC045044)) +#define MCF_EDMA_TCD3_ATTR (*(vuint16*)(0xFC045064)) +#define MCF_EDMA_TCD4_ATTR (*(vuint16*)(0xFC045084)) +#define MCF_EDMA_TCD5_ATTR (*(vuint16*)(0xFC0450A4)) +#define MCF_EDMA_TCD6_ATTR (*(vuint16*)(0xFC0450C4)) +#define MCF_EDMA_TCD7_ATTR (*(vuint16*)(0xFC0450E4)) +#define MCF_EDMA_TCD8_ATTR (*(vuint16*)(0xFC045104)) +#define MCF_EDMA_TCD9_ATTR (*(vuint16*)(0xFC045124)) +#define MCF_EDMA_TCD10_ATTR (*(vuint16*)(0xFC045144)) +#define MCF_EDMA_TCD11_ATTR (*(vuint16*)(0xFC045164)) +#define MCF_EDMA_TCD12_ATTR (*(vuint16*)(0xFC045184)) +#define MCF_EDMA_TCD13_ATTR (*(vuint16*)(0xFC0451A4)) +#define MCF_EDMA_TCD14_ATTR (*(vuint16*)(0xFC0451C4)) +#define MCF_EDMA_TCD15_ATTR (*(vuint16*)(0xFC0451E4)) +#define MCF_EDMA_TCD_ATTR(x) (*(vuint16*)(0xFC045004+((x)*0x020))) +#define MCF_EDMA_TCD0_SOFF (*(vuint16*)(0xFC045006)) +#define MCF_EDMA_TCD1_SOFF (*(vuint16*)(0xFC045026)) +#define MCF_EDMA_TCD2_SOFF (*(vuint16*)(0xFC045046)) +#define MCF_EDMA_TCD3_SOFF (*(vuint16*)(0xFC045066)) +#define MCF_EDMA_TCD4_SOFF (*(vuint16*)(0xFC045086)) +#define MCF_EDMA_TCD5_SOFF (*(vuint16*)(0xFC0450A6)) +#define MCF_EDMA_TCD6_SOFF (*(vuint16*)(0xFC0450C6)) +#define MCF_EDMA_TCD7_SOFF (*(vuint16*)(0xFC0450E6)) +#define MCF_EDMA_TCD8_SOFF (*(vuint16*)(0xFC045106)) +#define MCF_EDMA_TCD9_SOFF (*(vuint16*)(0xFC045126)) +#define MCF_EDMA_TCD10_SOFF (*(vuint16*)(0xFC045146)) +#define MCF_EDMA_TCD11_SOFF (*(vuint16*)(0xFC045166)) +#define MCF_EDMA_TCD12_SOFF (*(vuint16*)(0xFC045186)) +#define MCF_EDMA_TCD13_SOFF (*(vuint16*)(0xFC0451A6)) +#define MCF_EDMA_TCD14_SOFF (*(vuint16*)(0xFC0451C6)) +#define MCF_EDMA_TCD15_SOFF (*(vuint16*)(0xFC0451E6)) +#define MCF_EDMA_TCD_SOFF(x) (*(vuint16*)(0xFC045006+((x)*0x020))) +#define MCF_EDMA_TCD0_NBYTES (*(vuint32*)(0xFC045008)) +#define MCF_EDMA_TCD1_NBYTES (*(vuint32*)(0xFC045028)) +#define MCF_EDMA_TCD2_NBYTES (*(vuint32*)(0xFC045048)) +#define MCF_EDMA_TCD3_NBYTES (*(vuint32*)(0xFC045068)) +#define MCF_EDMA_TCD4_NBYTES (*(vuint32*)(0xFC045088)) +#define MCF_EDMA_TCD5_NBYTES (*(vuint32*)(0xFC0450A8)) +#define MCF_EDMA_TCD6_NBYTES (*(vuint32*)(0xFC0450C8)) +#define MCF_EDMA_TCD7_NBYTES (*(vuint32*)(0xFC0450E8)) +#define MCF_EDMA_TCD8_NBYTES (*(vuint32*)(0xFC045108)) +#define MCF_EDMA_TCD9_NBYTES (*(vuint32*)(0xFC045128)) +#define MCF_EDMA_TCD10_NBYTES (*(vuint32*)(0xFC045148)) +#define MCF_EDMA_TCD11_NBYTES (*(vuint32*)(0xFC045168)) +#define MCF_EDMA_TCD12_NBYTES (*(vuint32*)(0xFC045188)) +#define MCF_EDMA_TCD13_NBYTES (*(vuint32*)(0xFC0451A8)) +#define MCF_EDMA_TCD14_NBYTES (*(vuint32*)(0xFC0451C8)) +#define MCF_EDMA_TCD15_NBYTES (*(vuint32*)(0xFC0451E8)) +#define MCF_EDMA_TCD_NBYTES(x) (*(vuint32*)(0xFC045008+((x)*0x020))) +#define MCF_EDMA_TCD0_SLAST (*(vuint32*)(0xFC04500C)) +#define MCF_EDMA_TCD1_SLAST (*(vuint32*)(0xFC04502C)) +#define MCF_EDMA_TCD2_SLAST (*(vuint32*)(0xFC04504C)) +#define MCF_EDMA_TCD3_SLAST (*(vuint32*)(0xFC04506C)) +#define MCF_EDMA_TCD4_SLAST (*(vuint32*)(0xFC04508C)) +#define MCF_EDMA_TCD5_SLAST (*(vuint32*)(0xFC0450AC)) +#define MCF_EDMA_TCD6_SLAST (*(vuint32*)(0xFC0450CC)) +#define MCF_EDMA_TCD7_SLAST (*(vuint32*)(0xFC0450EC)) +#define MCF_EDMA_TCD8_SLAST (*(vuint32*)(0xFC04510C)) +#define MCF_EDMA_TCD9_SLAST (*(vuint32*)(0xFC04512C)) +#define MCF_EDMA_TCD10_SLAST (*(vuint32*)(0xFC04514C)) +#define MCF_EDMA_TCD11_SLAST (*(vuint32*)(0xFC04516C)) +#define MCF_EDMA_TCD12_SLAST (*(vuint32*)(0xFC04518C)) +#define MCF_EDMA_TCD13_SLAST (*(vuint32*)(0xFC0451AC)) +#define MCF_EDMA_TCD14_SLAST (*(vuint32*)(0xFC0451CC)) +#define MCF_EDMA_TCD15_SLAST (*(vuint32*)(0xFC0451EC)) +#define MCF_EDMA_TCD_SLAST(x) (*(vuint32*)(0xFC04500C+((x)*0x020))) +#define MCF_EDMA_TCD0_DADDR (*(vuint32*)(0xFC045010)) +#define MCF_EDMA_TCD1_DADDR (*(vuint32*)(0xFC045030)) +#define MCF_EDMA_TCD2_DADDR (*(vuint32*)(0xFC045050)) +#define MCF_EDMA_TCD3_DADDR (*(vuint32*)(0xFC045070)) +#define MCF_EDMA_TCD4_DADDR (*(vuint32*)(0xFC045090)) +#define MCF_EDMA_TCD5_DADDR (*(vuint32*)(0xFC0450B0)) +#define MCF_EDMA_TCD6_DADDR (*(vuint32*)(0xFC0450D0)) +#define MCF_EDMA_TCD7_DADDR (*(vuint32*)(0xFC0450F0)) +#define MCF_EDMA_TCD8_DADDR (*(vuint32*)(0xFC045110)) +#define MCF_EDMA_TCD9_DADDR (*(vuint32*)(0xFC045130)) +#define MCF_EDMA_TCD10_DADDR (*(vuint32*)(0xFC045150)) +#define MCF_EDMA_TCD11_DADDR (*(vuint32*)(0xFC045170)) +#define MCF_EDMA_TCD12_DADDR (*(vuint32*)(0xFC045190)) +#define MCF_EDMA_TCD13_DADDR (*(vuint32*)(0xFC0451B0)) +#define MCF_EDMA_TCD14_DADDR (*(vuint32*)(0xFC0451D0)) +#define MCF_EDMA_TCD15_DADDR (*(vuint32*)(0xFC0451F0)) +#define MCF_EDMA_TCD_DADDR(x) (*(vuint32*)(0xFC045010+((x)*0x020))) +#define MCF_EDMA_TCD0_CITER (*(vuint16*)(0xFC045014)) +#define MCF_EDMA_TCD1_CITER (*(vuint16*)(0xFC045034)) +#define MCF_EDMA_TCD2_CITER (*(vuint16*)(0xFC045054)) +#define MCF_EDMA_TCD3_CITER (*(vuint16*)(0xFC045074)) +#define MCF_EDMA_TCD4_CITER (*(vuint16*)(0xFC045094)) +#define MCF_EDMA_TCD5_CITER (*(vuint16*)(0xFC0450B4)) +#define MCF_EDMA_TCD6_CITER (*(vuint16*)(0xFC0450D4)) +#define MCF_EDMA_TCD7_CITER (*(vuint16*)(0xFC0450F4)) +#define MCF_EDMA_TCD8_CITER (*(vuint16*)(0xFC045114)) +#define MCF_EDMA_TCD9_CITER (*(vuint16*)(0xFC045134)) +#define MCF_EDMA_TCD10_CITER (*(vuint16*)(0xFC045154)) +#define MCF_EDMA_TCD11_CITER (*(vuint16*)(0xFC045174)) +#define MCF_EDMA_TCD12_CITER (*(vuint16*)(0xFC045194)) +#define MCF_EDMA_TCD13_CITER (*(vuint16*)(0xFC0451B4)) +#define MCF_EDMA_TCD14_CITER (*(vuint16*)(0xFC0451D4)) +#define MCF_EDMA_TCD15_CITER (*(vuint16*)(0xFC0451F4)) +#define MCF_EDMA_TCD_CITER(x) (*(vuint16*)(0xFC045014+((x)*0x020))) +#define MCF_EDMA_TCD0_CITER_ELINK (*(vuint16*)(0xFC045014)) +#define MCF_EDMA_TCD1_CITER_ELINK (*(vuint16*)(0xFC045034)) +#define MCF_EDMA_TCD2_CITER_ELINK (*(vuint16*)(0xFC045054)) +#define MCF_EDMA_TCD3_CITER_ELINK (*(vuint16*)(0xFC045074)) +#define MCF_EDMA_TCD4_CITER_ELINK (*(vuint16*)(0xFC045094)) +#define MCF_EDMA_TCD5_CITER_ELINK (*(vuint16*)(0xFC0450B4)) +#define MCF_EDMA_TCD6_CITER_ELINK (*(vuint16*)(0xFC0450D4)) +#define MCF_EDMA_TCD7_CITER_ELINK (*(vuint16*)(0xFC0450F4)) +#define MCF_EDMA_TCD8_CITER_ELINK (*(vuint16*)(0xFC045114)) +#define MCF_EDMA_TCD9_CITER_ELINK (*(vuint16*)(0xFC045134)) +#define MCF_EDMA_TCD10_CITER_ELINK (*(vuint16*)(0xFC045154)) +#define MCF_EDMA_TCD11_CITER_ELINK (*(vuint16*)(0xFC045174)) +#define MCF_EDMA_TCD12_CITER_ELINK (*(vuint16*)(0xFC045194)) +#define MCF_EDMA_TCD13_CITER_ELINK (*(vuint16*)(0xFC0451B4)) +#define MCF_EDMA_TCD14_CITER_ELINK (*(vuint16*)(0xFC0451D4)) +#define MCF_EDMA_TCD15_CITER_ELINK (*(vuint16*)(0xFC0451F4)) +#define MCF_EDMA_TCD_CITER_ELINK(x) (*(vuint16*)(0xFC045014+((x)*0x020))) +#define MCF_EDMA_TCD0_DOFF (*(vuint16*)(0xFC045016)) +#define MCF_EDMA_TCD1_DOFF (*(vuint16*)(0xFC045036)) +#define MCF_EDMA_TCD2_DOFF (*(vuint16*)(0xFC045056)) +#define MCF_EDMA_TCD3_DOFF (*(vuint16*)(0xFC045076)) +#define MCF_EDMA_TCD4_DOFF (*(vuint16*)(0xFC045096)) +#define MCF_EDMA_TCD5_DOFF (*(vuint16*)(0xFC0450B6)) +#define MCF_EDMA_TCD6_DOFF (*(vuint16*)(0xFC0450D6)) +#define MCF_EDMA_TCD7_DOFF (*(vuint16*)(0xFC0450F6)) +#define MCF_EDMA_TCD8_DOFF (*(vuint16*)(0xFC045116)) +#define MCF_EDMA_TCD9_DOFF (*(vuint16*)(0xFC045136)) +#define MCF_EDMA_TCD10_DOFF (*(vuint16*)(0xFC045156)) +#define MCF_EDMA_TCD11_DOFF (*(vuint16*)(0xFC045176)) +#define MCF_EDMA_TCD12_DOFF (*(vuint16*)(0xFC045196)) +#define MCF_EDMA_TCD13_DOFF (*(vuint16*)(0xFC0451B6)) +#define MCF_EDMA_TCD14_DOFF (*(vuint16*)(0xFC0451D6)) +#define MCF_EDMA_TCD15_DOFF (*(vuint16*)(0xFC0451F6)) +#define MCF_EDMA_TCD_DOFF(x) (*(vuint16*)(0xFC045016+((x)*0x020))) +#define MCF_EDMA_TCD0_DLAST_SGA (*(vuint32*)(0xFC045018)) +#define MCF_EDMA_TCD1_DLAST_SGA (*(vuint32*)(0xFC045038)) +#define MCF_EDMA_TCD2_DLAST_SGA (*(vuint32*)(0xFC045058)) +#define MCF_EDMA_TCD3_DLAST_SGA (*(vuint32*)(0xFC045078)) +#define MCF_EDMA_TCD4_DLAST_SGA (*(vuint32*)(0xFC045098)) +#define MCF_EDMA_TCD5_DLAST_SGA (*(vuint32*)(0xFC0450B8)) +#define MCF_EDMA_TCD6_DLAST_SGA (*(vuint32*)(0xFC0450D8)) +#define MCF_EDMA_TCD7_DLAST_SGA (*(vuint32*)(0xFC0450F8)) +#define MCF_EDMA_TCD8_DLAST_SGA (*(vuint32*)(0xFC045118)) +#define MCF_EDMA_TCD9_DLAST_SGA (*(vuint32*)(0xFC045138)) +#define MCF_EDMA_TCD10_DLAST_SGA (*(vuint32*)(0xFC045158)) +#define MCF_EDMA_TCD11_DLAST_SGA (*(vuint32*)(0xFC045178)) +#define MCF_EDMA_TCD12_DLAST_SGA (*(vuint32*)(0xFC045198)) +#define MCF_EDMA_TCD13_DLAST_SGA (*(vuint32*)(0xFC0451B8)) +#define MCF_EDMA_TCD14_DLAST_SGA (*(vuint32*)(0xFC0451D8)) +#define MCF_EDMA_TCD15_DLAST_SGA (*(vuint32*)(0xFC0451F8)) +#define MCF_EDMA_TCD_DLAST_SGA(x) (*(vuint32*)(0xFC045018+((x)*0x020))) +#define MCF_EDMA_TCD0_BITER (*(vuint16*)(0xFC04501C)) +#define MCF_EDMA_TCD1_BITER (*(vuint16*)(0xFC04503C)) +#define MCF_EDMA_TCD2_BITER (*(vuint16*)(0xFC04505C)) +#define MCF_EDMA_TCD3_BITER (*(vuint16*)(0xFC04507C)) +#define MCF_EDMA_TCD4_BITER (*(vuint16*)(0xFC04509C)) +#define MCF_EDMA_TCD5_BITER (*(vuint16*)(0xFC0450BC)) +#define MCF_EDMA_TCD6_BITER (*(vuint16*)(0xFC0450DC)) +#define MCF_EDMA_TCD7_BITER (*(vuint16*)(0xFC0450FC)) +#define MCF_EDMA_TCD8_BITER (*(vuint16*)(0xFC04511C)) +#define MCF_EDMA_TCD9_BITER (*(vuint16*)(0xFC04513C)) +#define MCF_EDMA_TCD10_BITER (*(vuint16*)(0xFC04515C)) +#define MCF_EDMA_TCD11_BITER (*(vuint16*)(0xFC04517C)) +#define MCF_EDMA_TCD12_BITER (*(vuint16*)(0xFC04519C)) +#define MCF_EDMA_TCD13_BITER (*(vuint16*)(0xFC0451BC)) +#define MCF_EDMA_TCD14_BITER (*(vuint16*)(0xFC0451DC)) +#define MCF_EDMA_TCD15_BITER (*(vuint16*)(0xFC0451FC)) +#define MCF_EDMA_TCD_BITER(x) (*(vuint16*)(0xFC04501C+((x)*0x020))) +#define MCF_EDMA_TCD0_BITER_ELINK (*(vuint16*)(0xFC04501C)) +#define MCF_EDMA_TCD1_BITER_ELINK (*(vuint16*)(0xFC04503C)) +#define MCF_EDMA_TCD2_BITER_ELINK (*(vuint16*)(0xFC04505C)) +#define MCF_EDMA_TCD3_BITER_ELINK (*(vuint16*)(0xFC04507C)) +#define MCF_EDMA_TCD4_BITER_ELINK (*(vuint16*)(0xFC04509C)) +#define MCF_EDMA_TCD5_BITER_ELINK (*(vuint16*)(0xFC0450BC)) +#define MCF_EDMA_TCD6_BITER_ELINK (*(vuint16*)(0xFC0450DC)) +#define MCF_EDMA_TCD7_BITER_ELINK (*(vuint16*)(0xFC0450FC)) +#define MCF_EDMA_TCD8_BITER_ELINK (*(vuint16*)(0xFC04511C)) +#define MCF_EDMA_TCD9_BITER_ELINK (*(vuint16*)(0xFC04513C)) +#define MCF_EDMA_TCD10_BITER_ELINK (*(vuint16*)(0xFC04515C)) +#define MCF_EDMA_TCD11_BITER_ELINK (*(vuint16*)(0xFC04517C)) +#define MCF_EDMA_TCD12_BITER_ELINK (*(vuint16*)(0xFC04519C)) +#define MCF_EDMA_TCD13_BITER_ELINK (*(vuint16*)(0xFC0451BC)) +#define MCF_EDMA_TCD14_BITER_ELINK (*(vuint16*)(0xFC0451DC)) +#define MCF_EDMA_TCD15_BITER_ELINK (*(vuint16*)(0xFC0451FC)) +#define MCF_EDMA_TCD_BITER_ELINK(x) (*(vuint16*)(0xFC04501C+((x)*0x020))) +#define MCF_EDMA_TCD0_CSR (*(vuint16*)(0xFC04501E)) +#define MCF_EDMA_TCD1_CSR (*(vuint16*)(0xFC04503E)) +#define MCF_EDMA_TCD2_CSR (*(vuint16*)(0xFC04505E)) +#define MCF_EDMA_TCD3_CSR (*(vuint16*)(0xFC04507E)) +#define MCF_EDMA_TCD4_CSR (*(vuint16*)(0xFC04509E)) +#define MCF_EDMA_TCD5_CSR (*(vuint16*)(0xFC0450BE)) +#define MCF_EDMA_TCD6_CSR (*(vuint16*)(0xFC0450DE)) +#define MCF_EDMA_TCD7_CSR (*(vuint16*)(0xFC0450FE)) +#define MCF_EDMA_TCD8_CSR (*(vuint16*)(0xFC04511E)) +#define MCF_EDMA_TCD9_CSR (*(vuint16*)(0xFC04513E)) +#define MCF_EDMA_TCD10_CSR (*(vuint16*)(0xFC04515E)) +#define MCF_EDMA_TCD11_CSR (*(vuint16*)(0xFC04517E)) +#define MCF_EDMA_TCD12_CSR (*(vuint16*)(0xFC04519E)) +#define MCF_EDMA_TCD13_CSR (*(vuint16*)(0xFC0451BE)) +#define MCF_EDMA_TCD14_CSR (*(vuint16*)(0xFC0451DE)) +#define MCF_EDMA_TCD15_CSR (*(vuint16*)(0xFC0451FE)) +#define MCF_EDMA_TCD_CSR(x) (*(vuint16*)(0xFC04501E +((x)*0x020))) + +/* Bit definitions and macros for MCF_EDMA_CR */ +#define MCF_EDMA_CR_EDBG (0x00000002) +#define MCF_EDMA_CR_ERCA (0x00000004) + +/* Bit definitions and macros for MCF_EDMA_ES */ +#define MCF_EDMA_ES_DBE (0x00000001) +#define MCF_EDMA_ES_SBE (0x00000002) +#define MCF_EDMA_ES_SGE (0x00000004) +#define MCF_EDMA_ES_NCE (0x00000008) +#define MCF_EDMA_ES_DOE (0x00000010) +#define MCF_EDMA_ES_DAE (0x00000020) +#define MCF_EDMA_ES_SOE (0x00000040) +#define MCF_EDMA_ES_SAE (0x00000080) +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8) +#define MCF_EDMA_ES_CPE (0x00004000) +#define MCF_EDMA_ES_VLD (0x80000000) + +/* Bit definitions and macros for MCF_EDMA_ERQ */ +#define MCF_EDMA_ERQ_ERQ0 (0x0001) +#define MCF_EDMA_ERQ_ERQ1 (0x0002) +#define MCF_EDMA_ERQ_ERQ2 (0x0004) +#define MCF_EDMA_ERQ_ERQ3 (0x0008) +#define MCF_EDMA_ERQ_ERQ4 (0x0010) +#define MCF_EDMA_ERQ_ERQ5 (0x0020) +#define MCF_EDMA_ERQ_ERQ6 (0x0040) +#define MCF_EDMA_ERQ_ERQ7 (0x0080) +#define MCF_EDMA_ERQ_ERQ8 (0x0100) +#define MCF_EDMA_ERQ_ERQ9 (0x0200) +#define MCF_EDMA_ERQ_ERQ10 (0x0400) +#define MCF_EDMA_ERQ_ERQ11 (0x0800) +#define MCF_EDMA_ERQ_ERQ12 (0x1000) +#define MCF_EDMA_ERQ_ERQ13 (0x2000) +#define MCF_EDMA_ERQ_ERQ14 (0x4000) +#define MCF_EDMA_ERQ_ERQ15 (0x8000) + +/* Bit definitions and macros for MCF_EDMA_EEI */ +#define MCF_EDMA_EEI_EEI0 (0x0001) +#define MCF_EDMA_EEI_EEI1 (0x0002) +#define MCF_EDMA_EEI_EEI2 (0x0004) +#define MCF_EDMA_EEI_EEI3 (0x0008) +#define MCF_EDMA_EEI_EEI4 (0x0010) +#define MCF_EDMA_EEI_EEI5 (0x0020) +#define MCF_EDMA_EEI_EEI6 (0x0040) +#define MCF_EDMA_EEI_EEI7 (0x0080) +#define MCF_EDMA_EEI_EEI8 (0x0100) +#define MCF_EDMA_EEI_EEI9 (0x0200) +#define MCF_EDMA_EEI_EEI10 (0x0400) +#define MCF_EDMA_EEI_EEI11 (0x0800) +#define MCF_EDMA_EEI_EEI12 (0x1000) +#define MCF_EDMA_EEI_EEI13 (0x2000) +#define MCF_EDMA_EEI_EEI14 (0x4000) +#define MCF_EDMA_EEI_EEI15 (0x8000) + +/* Bit definitions and macros for MCF_EDMA_SERQ */ +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)<<0) +#define MCF_EDMA_SERQ_SAER (0x40) + +/* Bit definitions and macros for MCF_EDMA_CERQ */ +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)<<0) +#define MCF_EDMA_CERQ_CAER (0x40) + +/* Bit definitions and macros for MCF_EDMA_SEEI */ +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)<<0) +#define MCF_EDMA_SEEI_SAEE (0x40) + +/* Bit definitions and macros for MCF_EDMA_CEEI */ +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)<<0) +#define MCF_EDMA_CEEI_CAEE (0x40) + +/* Bit definitions and macros for MCF_EDMA_CINT */ +#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)<<0) +#define MCF_EDMA_CINT_CAIR (0x40) + +/* Bit definitions and macros for MCF_EDMA_CERR */ +#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)<<0) +#define MCF_EDMA_CERR_CAER (0x40) + +/* Bit definitions and macros for MCF_EDMA_SSRT */ +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)<<0) +#define MCF_EDMA_SSRT_SAST (0x40) + +/* Bit definitions and macros for MCF_EDMA_CDNE */ +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)<<0) +#define MCF_EDMA_CDNE_CADN (0x40) + +/* Bit definitions and macros for MCF_EDMA_INT */ +#define MCF_EDMA_INT_INT0 (0x0001) +#define MCF_EDMA_INT_INT1 (0x0002) +#define MCF_EDMA_INT_INT2 (0x0004) +#define MCF_EDMA_INT_INT3 (0x0008) +#define MCF_EDMA_INT_INT4 (0x0010) +#define MCF_EDMA_INT_INT5 (0x0020) +#define MCF_EDMA_INT_INT6 (0x0040) +#define MCF_EDMA_INT_INT7 (0x0080) +#define MCF_EDMA_INT_INT8 (0x0100) +#define MCF_EDMA_INT_INT9 (0x0200) +#define MCF_EDMA_INT_INT10 (0x0400) +#define MCF_EDMA_INT_INT11 (0x0800) +#define MCF_EDMA_INT_INT12 (0x1000) +#define MCF_EDMA_INT_INT13 (0x2000) +#define MCF_EDMA_INT_INT14 (0x4000) +#define MCF_EDMA_INT_INT15 (0x8000) + +/* Bit definitions and macros for MCF_EDMA_ERR */ +#define MCF_EDMA_ERR_ERR0 (0x0001) +#define MCF_EDMA_ERR_ERR1 (0x0002) +#define MCF_EDMA_ERR_ERR2 (0x0004) +#define MCF_EDMA_ERR_ERR3 (0x0008) +#define MCF_EDMA_ERR_ERR4 (0x0010) +#define MCF_EDMA_ERR_ERR5 (0x0020) +#define MCF_EDMA_ERR_ERR6 (0x0040) +#define MCF_EDMA_ERR_ERR7 (0x0080) +#define MCF_EDMA_ERR_ERR8 (0x0100) +#define MCF_EDMA_ERR_ERR9 (0x0200) +#define MCF_EDMA_ERR_ERR10 (0x0400) +#define MCF_EDMA_ERR_ERR11 (0x0800) +#define MCF_EDMA_ERR_ERR12 (0x1000) +#define MCF_EDMA_ERR_ERR13 (0x2000) +#define MCF_EDMA_ERR_ERR14 (0x4000) +#define MCF_EDMA_ERR_ERR15 (0x8000) + +/* Bit definitions and macros for MCF_EDMA_DCHPRI */ +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)<<0) +#define MCF_EDMA_DCHPRI_ECP (0x80) + +/* Bit definitions and macros for MCF_EDMA_TCD_SADDR */ +#define MCF_EDMA_TCD_SADDR_SADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_ATTR */ +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)<<0) +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) + +/* Bit definitions and macros for MCF_EDMA_TCD_SOFF */ +#define MCF_EDMA_TCD_SOFF_SOFF(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_NBYTES */ +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_SLAST */ +#define MCF_EDMA_TCD_SLAST_SLAST(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_DADDR */ +#define MCF_EDMA_TCD_DADDR_DADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_CITER */ +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)<<0) +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for MCF_EDMA_TCD_CITER_ELINK */ +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)<<0) +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for MCF_EDMA_TCD_DOFF */ +#define MCF_EDMA_TCD_DOFF_DOFF(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_DLAST_SGA */ +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_EDMA_TCD_BITER */ +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)<<0) +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for MCF_EDMA_TCD_BITER_ELINK */ +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)<<0) +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for MCF_EDMA_TCD_CSR */ +#define MCF_EDMA_TCD_CSR_START (0x0001) +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD_CSR_DONE (0x0080) +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(0xFC048000)) +#define MCF_INTC0_IPRL (*(vuint32*)(0xFC048004)) +#define MCF_INTC0_IMRH (*(vuint32*)(0xFC048008)) +#define MCF_INTC0_IMRL (*(vuint32*)(0xFC04800C)) +#define MCF_INTC0_INTFRCH (*(vuint32*)(0xFC048010)) +#define MCF_INTC0_INTFRCL (*(vuint32*)(0xFC048014)) +#define MCF_INTC0_ICONFIG (*(vuint16*)(0xFC04801A)) +#define MCF_INTC0_SIMR (*(vuint8 *)(0xFC04801C)) +#define MCF_INTC0_CIMR (*(vuint8 *)(0xFC04801D)) +#define MCF_INTC0_CLMASK (*(vuint8 *)(0xFC04801E)) +#define MCF_INTC0_SLMASK (*(vuint8 *)(0xFC04801F)) +#define MCF_INTC0_ICR0 (*(vuint8 *)(0xFC048040)) +#define MCF_INTC0_ICR1 (*(vuint8 *)(0xFC048041)) +#define MCF_INTC0_ICR2 (*(vuint8 *)(0xFC048042)) +#define MCF_INTC0_ICR3 (*(vuint8 *)(0xFC048043)) +#define MCF_INTC0_ICR4 (*(vuint8 *)(0xFC048044)) +#define MCF_INTC0_ICR5 (*(vuint8 *)(0xFC048045)) +#define MCF_INTC0_ICR6 (*(vuint8 *)(0xFC048046)) +#define MCF_INTC0_ICR7 (*(vuint8 *)(0xFC048047)) +#define MCF_INTC0_ICR8 (*(vuint8 *)(0xFC048048)) +#define MCF_INTC0_ICR9 (*(vuint8 *)(0xFC048049)) +#define MCF_INTC0_ICR10 (*(vuint8 *)(0xFC04804A)) +#define MCF_INTC0_ICR11 (*(vuint8 *)(0xFC04804B)) +#define MCF_INTC0_ICR12 (*(vuint8 *)(0xFC04804C)) +#define MCF_INTC0_ICR13 (*(vuint8 *)(0xFC04804D)) +#define MCF_INTC0_ICR14 (*(vuint8 *)(0xFC04804E)) +#define MCF_INTC0_ICR15 (*(vuint8 *)(0xFC04804F)) +#define MCF_INTC0_ICR16 (*(vuint8 *)(0xFC048050)) +#define MCF_INTC0_ICR17 (*(vuint8 *)(0xFC048051)) +#define MCF_INTC0_ICR18 (*(vuint8 *)(0xFC048052)) +#define MCF_INTC0_ICR19 (*(vuint8 *)(0xFC048053)) +#define MCF_INTC0_ICR20 (*(vuint8 *)(0xFC048054)) +#define MCF_INTC0_ICR21 (*(vuint8 *)(0xFC048055)) +#define MCF_INTC0_ICR22 (*(vuint8 *)(0xFC048056)) +#define MCF_INTC0_ICR23 (*(vuint8 *)(0xFC048057)) +#define MCF_INTC0_ICR24 (*(vuint8 *)(0xFC048058)) +#define MCF_INTC0_ICR25 (*(vuint8 *)(0xFC048059)) +#define MCF_INTC0_ICR26 (*(vuint8 *)(0xFC04805A)) +#define MCF_INTC0_ICR27 (*(vuint8 *)(0xFC04805B)) +#define MCF_INTC0_ICR28 (*(vuint8 *)(0xFC04805C)) +#define MCF_INTC0_ICR29 (*(vuint8 *)(0xFC04805D)) +#define MCF_INTC0_ICR30 (*(vuint8 *)(0xFC04805E)) +#define MCF_INTC0_ICR31 (*(vuint8 *)(0xFC04805F)) +#define MCF_INTC0_ICR32 (*(vuint8 *)(0xFC048060)) +#define MCF_INTC0_ICR33 (*(vuint8 *)(0xFC048061)) +#define MCF_INTC0_ICR34 (*(vuint8 *)(0xFC048062)) +#define MCF_INTC0_ICR35 (*(vuint8 *)(0xFC048063)) +#define MCF_INTC0_ICR36 (*(vuint8 *)(0xFC048064)) +#define MCF_INTC0_ICR37 (*(vuint8 *)(0xFC048065)) +#define MCF_INTC0_ICR38 (*(vuint8 *)(0xFC048066)) +#define MCF_INTC0_ICR39 (*(vuint8 *)(0xFC048067)) +#define MCF_INTC0_ICR40 (*(vuint8 *)(0xFC048068)) +#define MCF_INTC0_ICR41 (*(vuint8 *)(0xFC048069)) +#define MCF_INTC0_ICR42 (*(vuint8 *)(0xFC04806A)) +#define MCF_INTC0_ICR43 (*(vuint8 *)(0xFC04806B)) +#define MCF_INTC0_ICR44 (*(vuint8 *)(0xFC04806C)) +#define MCF_INTC0_ICR45 (*(vuint8 *)(0xFC04806D)) +#define MCF_INTC0_ICR46 (*(vuint8 *)(0xFC04806E)) +#define MCF_INTC0_ICR47 (*(vuint8 *)(0xFC04806F)) +#define MCF_INTC0_ICR48 (*(vuint8 *)(0xFC048070)) +#define MCF_INTC0_ICR49 (*(vuint8 *)(0xFC048071)) +#define MCF_INTC0_ICR50 (*(vuint8 *)(0xFC048072)) +#define MCF_INTC0_ICR51 (*(vuint8 *)(0xFC048073)) +#define MCF_INTC0_ICR52 (*(vuint8 *)(0xFC048074)) +#define MCF_INTC0_ICR53 (*(vuint8 *)(0xFC048075)) +#define MCF_INTC0_ICR54 (*(vuint8 *)(0xFC048076)) +#define MCF_INTC0_ICR55 (*(vuint8 *)(0xFC048077)) +#define MCF_INTC0_ICR56 (*(vuint8 *)(0xFC048078)) +#define MCF_INTC0_ICR57 (*(vuint8 *)(0xFC048079)) +#define MCF_INTC0_ICR58 (*(vuint8 *)(0xFC04807A)) +#define MCF_INTC0_ICR59 (*(vuint8 *)(0xFC04807B)) +#define MCF_INTC0_ICR60 (*(vuint8 *)(0xFC04807C)) +#define MCF_INTC0_ICR61 (*(vuint8 *)(0xFC04807D)) +#define MCF_INTC0_ICR62 (*(vuint8 *)(0xFC04807E)) +#define MCF_INTC0_ICR63 (*(vuint8 *)(0xFC04807F)) +#define MCF_INTC0_ICR(x) (*(vuint8 *)(0xFC048040+((x)*0x001))) +#define MCF_INTC0_SWIACK (*(vuint8 *)(0xFC0480E0)) +#define MCF_INTC0_L1IACK (*(vuint8 *)(0xFC0480E4)) +#define MCF_INTC0_L2IACK (*(vuint8 *)(0xFC0480E8)) +#define MCF_INTC0_L3IACK (*(vuint8 *)(0xFC0480EC)) +#define MCF_INTC0_L4IACK (*(vuint8 *)(0xFC0480F0)) +#define MCF_INTC0_L5IACK (*(vuint8 *)(0xFC0480F4)) +#define MCF_INTC0_L6IACK (*(vuint8 *)(0xFC0480F8)) +#define MCF_INTC0_L7IACK (*(vuint8 *)(0xFC0480FC)) +#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0xFC0480E4+((x-1)*0x004))) +#define MCF_INTC1_IPRH (*(vuint32*)(0xFC04C000)) +#define MCF_INTC1_IPRL (*(vuint32*)(0xFC04C004)) +#define MCF_INTC1_IMRH (*(vuint32*)(0xFC04C008)) +#define MCF_INTC1_IMRL (*(vuint32*)(0xFC04C00C)) +#define MCF_INTC1_INTFRCH (*(vuint32*)(0xFC04C010)) +#define MCF_INTC1_INTFRCL (*(vuint32*)(0xFC04C014)) +#define MCF_INTC1_ICONFIG (*(vuint16*)(0xFC04C01A)) +#define MCF_INTC1_SIMR (*(vuint8 *)(0xFC04C01C)) +#define MCF_INTC1_CIMR (*(vuint8 *)(0xFC04C01D)) +#define MCF_INTC1_CLMASK (*(vuint8 *)(0xFC04C01E)) +#define MCF_INTC1_SLMASK (*(vuint8 *)(0xFC04C01F)) +#define MCF_INTC1_ICR0 (*(vuint8 *)(0xFC04C040)) +#define MCF_INTC1_ICR1 (*(vuint8 *)(0xFC04C041)) +#define MCF_INTC1_ICR2 (*(vuint8 *)(0xFC04C042)) +#define MCF_INTC1_ICR3 (*(vuint8 *)(0xFC04C043)) +#define MCF_INTC1_ICR4 (*(vuint8 *)(0xFC04C044)) +#define MCF_INTC1_ICR5 (*(vuint8 *)(0xFC04C045)) +#define MCF_INTC1_ICR6 (*(vuint8 *)(0xFC04C046)) +#define MCF_INTC1_ICR7 (*(vuint8 *)(0xFC04C047)) +#define MCF_INTC1_ICR8 (*(vuint8 *)(0xFC04C048)) +#define MCF_INTC1_ICR9 (*(vuint8 *)(0xFC04C049)) +#define MCF_INTC1_ICR10 (*(vuint8 *)(0xFC04C04A)) +#define MCF_INTC1_ICR11 (*(vuint8 *)(0xFC04C04B)) +#define MCF_INTC1_ICR12 (*(vuint8 *)(0xFC04C04C)) +#define MCF_INTC1_ICR13 (*(vuint8 *)(0xFC04C04D)) +#define MCF_INTC1_ICR14 (*(vuint8 *)(0xFC04C04E)) +#define MCF_INTC1_ICR15 (*(vuint8 *)(0xFC04C04F)) +#define MCF_INTC1_ICR16 (*(vuint8 *)(0xFC04C050)) +#define MCF_INTC1_ICR17 (*(vuint8 *)(0xFC04C051)) +#define MCF_INTC1_ICR18 (*(vuint8 *)(0xFC04C052)) +#define MCF_INTC1_ICR19 (*(vuint8 *)(0xFC04C053)) +#define MCF_INTC1_ICR20 (*(vuint8 *)(0xFC04C054)) +#define MCF_INTC1_ICR21 (*(vuint8 *)(0xFC04C055)) +#define MCF_INTC1_ICR22 (*(vuint8 *)(0xFC04C056)) +#define MCF_INTC1_ICR23 (*(vuint8 *)(0xFC04C057)) +#define MCF_INTC1_ICR24 (*(vuint8 *)(0xFC04C058)) +#define MCF_INTC1_ICR25 (*(vuint8 *)(0xFC04C059)) +#define MCF_INTC1_ICR26 (*(vuint8 *)(0xFC04C05A)) +#define MCF_INTC1_ICR27 (*(vuint8 *)(0xFC04C05B)) +#define MCF_INTC1_ICR28 (*(vuint8 *)(0xFC04C05C)) +#define MCF_INTC1_ICR29 (*(vuint8 *)(0xFC04C05D)) +#define MCF_INTC1_ICR30 (*(vuint8 *)(0xFC04C05E)) +#define MCF_INTC1_ICR31 (*(vuint8 *)(0xFC04C05F)) +#define MCF_INTC1_ICR32 (*(vuint8 *)(0xFC04C060)) +#define MCF_INTC1_ICR33 (*(vuint8 *)(0xFC04C061)) +#define MCF_INTC1_ICR34 (*(vuint8 *)(0xFC04C062)) +#define MCF_INTC1_ICR35 (*(vuint8 *)(0xFC04C063)) +#define MCF_INTC1_ICR36 (*(vuint8 *)(0xFC04C064)) +#define MCF_INTC1_ICR37 (*(vuint8 *)(0xFC04C065)) +#define MCF_INTC1_ICR38 (*(vuint8 *)(0xFC04C066)) +#define MCF_INTC1_ICR39 (*(vuint8 *)(0xFC04C067)) +#define MCF_INTC1_ICR40 (*(vuint8 *)(0xFC04C068)) +#define MCF_INTC1_ICR41 (*(vuint8 *)(0xFC04C069)) +#define MCF_INTC1_ICR42 (*(vuint8 *)(0xFC04C06A)) +#define MCF_INTC1_ICR43 (*(vuint8 *)(0xFC04C06B)) +#define MCF_INTC1_ICR44 (*(vuint8 *)(0xFC04C06C)) +#define MCF_INTC1_ICR45 (*(vuint8 *)(0xFC04C06D)) +#define MCF_INTC1_ICR46 (*(vuint8 *)(0xFC04C06E)) +#define MCF_INTC1_ICR47 (*(vuint8 *)(0xFC04C06F)) +#define MCF_INTC1_ICR48 (*(vuint8 *)(0xFC04C070)) +#define MCF_INTC1_ICR49 (*(vuint8 *)(0xFC04C071)) +#define MCF_INTC1_ICR50 (*(vuint8 *)(0xFC04C072)) +#define MCF_INTC1_ICR51 (*(vuint8 *)(0xFC04C073)) +#define MCF_INTC1_ICR52 (*(vuint8 *)(0xFC04C074)) +#define MCF_INTC1_ICR53 (*(vuint8 *)(0xFC04C075)) +#define MCF_INTC1_ICR54 (*(vuint8 *)(0xFC04C076)) +#define MCF_INTC1_ICR55 (*(vuint8 *)(0xFC04C077)) +#define MCF_INTC1_ICR56 (*(vuint8 *)(0xFC04C078)) +#define MCF_INTC1_ICR57 (*(vuint8 *)(0xFC04C079)) +#define MCF_INTC1_ICR58 (*(vuint8 *)(0xFC04C07A)) +#define MCF_INTC1_ICR59 (*(vuint8 *)(0xFC04C07B)) +#define MCF_INTC1_ICR60 (*(vuint8 *)(0xFC04C07C)) +#define MCF_INTC1_ICR61 (*(vuint8 *)(0xFC04C07D)) +#define MCF_INTC1_ICR62 (*(vuint8 *)(0xFC04C07E)) +#define MCF_INTC1_ICR63 (*(vuint8 *)(0xFC04C07F)) +#define MCF_INTC1_ICR(x) (*(vuint8 *)(0xFC04C040+((x)*0x001))) +#define MCF_INTC1_SWIACK (*(vuint8 *)(0xFC04C0E0)) +#define MCF_INTC1_L1IACK (*(vuint8 *)(0xFC04C0E4)) +#define MCF_INTC1_L2IACK (*(vuint8 *)(0xFC04C0E8)) +#define MCF_INTC1_L3IACK (*(vuint8 *)(0xFC04C0EC)) +#define MCF_INTC1_L4IACK (*(vuint8 *)(0xFC04C0F0)) +#define MCF_INTC1_L5IACK (*(vuint8 *)(0xFC04C0F4)) +#define MCF_INTC1_L6IACK (*(vuint8 *)(0xFC04C0F8)) +#define MCF_INTC1_L7IACK (*(vuint8 *)(0xFC04C0FC)) +#define MCF_INTC1_LIACK(x) (*(vuint8 *)(0xFC04C0E4+((x-1)*0x004))) +#define MCF_INTC_IPRH(x) (*(vuint32*)(0xFC048000+((x)*0x4000))) +#define MCF_INTC_IPRL(x) (*(vuint32*)(0xFC048004+((x)*0x4000))) +#define MCF_INTC_IMRH(x) (*(vuint32*)(0xFC048008+((x)*0x4000))) +#define MCF_INTC_IMRL(x) (*(vuint32*)(0xFC04800C+((x)*0x4000))) +#define MCF_INTC_INTFRCH(x) (*(vuint32*)(0xFC048010+((x)*0x4000))) +#define MCF_INTC_INTFRCL(x) (*(vuint32*)(0xFC048014+((x)*0x4000))) +#define MCF_INTC_ICONFIG(x) (*(vuint16*)(0xFC04801A+((x)*0x4000))) +#define MCF_INTC_SIMR(x) (*(vuint8 *)(0xFC04801C+((x)*0x4000))) +#define MCF_INTC_CIMR(x) (*(vuint8 *)(0xFC04801D+((x)*0x4000))) +#define MCF_INTC_CLMASK(x) (*(vuint8 *)(0xFC04801E+((x)*0x4000))) +#define MCF_INTC_SLMASK(x) (*(vuint8 *)(0xFC04801F+((x)*0x4000))) +#define MCF_INTC_ICR0(x) (*(vuint8 *)(0xFC048040+((x)*0x4000))) +#define MCF_INTC_ICR1(x) (*(vuint8 *)(0xFC048041+((x)*0x4000))) +#define MCF_INTC_ICR2(x) (*(vuint8 *)(0xFC048042+((x)*0x4000))) +#define MCF_INTC_ICR3(x) (*(vuint8 *)(0xFC048043+((x)*0x4000))) +#define MCF_INTC_ICR4(x) (*(vuint8 *)(0xFC048044+((x)*0x4000))) +#define MCF_INTC_ICR5(x) (*(vuint8 *)(0xFC048045+((x)*0x4000))) +#define MCF_INTC_ICR6(x) (*(vuint8 *)(0xFC048046+((x)*0x4000))) +#define MCF_INTC_ICR7(x) (*(vuint8 *)(0xFC048047+((x)*0x4000))) +#define MCF_INTC_ICR8(x) (*(vuint8 *)(0xFC048048+((x)*0x4000))) +#define MCF_INTC_ICR9(x) (*(vuint8 *)(0xFC048049+((x)*0x4000))) +#define MCF_INTC_ICR10(x) (*(vuint8 *)(0xFC04804A+((x)*0x4000))) +#define MCF_INTC_ICR11(x) (*(vuint8 *)(0xFC04804B+((x)*0x4000))) +#define MCF_INTC_ICR12(x) (*(vuint8 *)(0xFC04804C+((x)*0x4000))) +#define MCF_INTC_ICR13(x) (*(vuint8 *)(0xFC04804D+((x)*0x4000))) +#define MCF_INTC_ICR14(x) (*(vuint8 *)(0xFC04804E+((x)*0x4000))) +#define MCF_INTC_ICR15(x) (*(vuint8 *)(0xFC04804F+((x)*0x4000))) +#define MCF_INTC_ICR16(x) (*(vuint8 *)(0xFC048050+((x)*0x4000))) +#define MCF_INTC_ICR17(x) (*(vuint8 *)(0xFC048051+((x)*0x4000))) +#define MCF_INTC_ICR18(x) (*(vuint8 *)(0xFC048052+((x)*0x4000))) +#define MCF_INTC_ICR19(x) (*(vuint8 *)(0xFC048053+((x)*0x4000))) +#define MCF_INTC_ICR20(x) (*(vuint8 *)(0xFC048054+((x)*0x4000))) +#define MCF_INTC_ICR21(x) (*(vuint8 *)(0xFC048055+((x)*0x4000))) +#define MCF_INTC_ICR22(x) (*(vuint8 *)(0xFC048056+((x)*0x4000))) +#define MCF_INTC_ICR23(x) (*(vuint8 *)(0xFC048057+((x)*0x4000))) +#define MCF_INTC_ICR24(x) (*(vuint8 *)(0xFC048058+((x)*0x4000))) +#define MCF_INTC_ICR25(x) (*(vuint8 *)(0xFC048059+((x)*0x4000))) +#define MCF_INTC_ICR26(x) (*(vuint8 *)(0xFC04805A+((x)*0x4000))) +#define MCF_INTC_ICR27(x) (*(vuint8 *)(0xFC04805B+((x)*0x4000))) +#define MCF_INTC_ICR28(x) (*(vuint8 *)(0xFC04805C+((x)*0x4000))) +#define MCF_INTC_ICR29(x) (*(vuint8 *)(0xFC04805D+((x)*0x4000))) +#define MCF_INTC_ICR30(x) (*(vuint8 *)(0xFC04805E+((x)*0x4000))) +#define MCF_INTC_ICR31(x) (*(vuint8 *)(0xFC04805F+((x)*0x4000))) +#define MCF_INTC_ICR32(x) (*(vuint8 *)(0xFC048060+((x)*0x4000))) +#define MCF_INTC_ICR33(x) (*(vuint8 *)(0xFC048061+((x)*0x4000))) +#define MCF_INTC_ICR34(x) (*(vuint8 *)(0xFC048062+((x)*0x4000))) +#define MCF_INTC_ICR35(x) (*(vuint8 *)(0xFC048063+((x)*0x4000))) +#define MCF_INTC_ICR36(x) (*(vuint8 *)(0xFC048064+((x)*0x4000))) +#define MCF_INTC_ICR37(x) (*(vuint8 *)(0xFC048065+((x)*0x4000))) +#define MCF_INTC_ICR38(x) (*(vuint8 *)(0xFC048066+((x)*0x4000))) +#define MCF_INTC_ICR39(x) (*(vuint8 *)(0xFC048067+((x)*0x4000))) +#define MCF_INTC_ICR40(x) (*(vuint8 *)(0xFC048068+((x)*0x4000))) +#define MCF_INTC_ICR41(x) (*(vuint8 *)(0xFC048069+((x)*0x4000))) +#define MCF_INTC_ICR42(x) (*(vuint8 *)(0xFC04806A+((x)*0x4000))) +#define MCF_INTC_ICR43(x) (*(vuint8 *)(0xFC04806B+((x)*0x4000))) +#define MCF_INTC_ICR44(x) (*(vuint8 *)(0xFC04806C+((x)*0x4000))) +#define MCF_INTC_ICR45(x) (*(vuint8 *)(0xFC04806D+((x)*0x4000))) +#define MCF_INTC_ICR46(x) (*(vuint8 *)(0xFC04806E+((x)*0x4000))) +#define MCF_INTC_ICR47(x) (*(vuint8 *)(0xFC04806F+((x)*0x4000))) +#define MCF_INTC_ICR48(x) (*(vuint8 *)(0xFC048070+((x)*0x4000))) +#define MCF_INTC_ICR49(x) (*(vuint8 *)(0xFC048071+((x)*0x4000))) +#define MCF_INTC_ICR50(x) (*(vuint8 *)(0xFC048072+((x)*0x4000))) +#define MCF_INTC_ICR51(x) (*(vuint8 *)(0xFC048073+((x)*0x4000))) +#define MCF_INTC_ICR52(x) (*(vuint8 *)(0xFC048074+((x)*0x4000))) +#define MCF_INTC_ICR53(x) (*(vuint8 *)(0xFC048075+((x)*0x4000))) +#define MCF_INTC_ICR54(x) (*(vuint8 *)(0xFC048076+((x)*0x4000))) +#define MCF_INTC_ICR55(x) (*(vuint8 *)(0xFC048077+((x)*0x4000))) +#define MCF_INTC_ICR56(x) (*(vuint8 *)(0xFC048078+((x)*0x4000))) +#define MCF_INTC_ICR57(x) (*(vuint8 *)(0xFC048079+((x)*0x4000))) +#define MCF_INTC_ICR58(x) (*(vuint8 *)(0xFC04807A+((x)*0x4000))) +#define MCF_INTC_ICR59(x) (*(vuint8 *)(0xFC04807B+((x)*0x4000))) +#define MCF_INTC_ICR60(x) (*(vuint8 *)(0xFC04807C+((x)*0x4000))) +#define MCF_INTC_ICR61(x) (*(vuint8 *)(0xFC04807D+((x)*0x4000))) +#define MCF_INTC_ICR62(x) (*(vuint8 *)(0xFC04807E+((x)*0x4000))) +#define MCF_INTC_ICR63(x) (*(vuint8 *)(0xFC04807F+((x)*0x4000))) +#define MCF_INTC_SWIACK(x) (*(vuint8 *)(0xFC0480E0+((x)*0x4000))) +#define MCF_INTC_L1IACK(x) (*(vuint8 *)(0xFC0480E4+((x)*0x4000))) +#define MCF_INTC_L2IACK(x) (*(vuint8 *)(0xFC0480E8+((x)*0x4000))) +#define MCF_INTC_L3IACK(x) (*(vuint8 *)(0xFC0480EC+((x)*0x4000))) +#define MCF_INTC_L4IACK(x) (*(vuint8 *)(0xFC0480F0+((x)*0x4000))) +#define MCF_INTC_L5IACK(x) (*(vuint8 *)(0xFC0480F4+((x)*0x4000))) +#define MCF_INTC_L6IACK(x) (*(vuint8 *)(0xFC0480F8+((x)*0x4000))) +#define MCF_INTC_L7IACK(x) (*(vuint8 *)(0xFC0480FC+((x)*0x4000))) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT0 (0x00000001) +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_ICONFIG */ +#define MCF_INTC_ICONFIG_EMASK (0x0020) +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for MCF_INTC_SIMR */ +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_INTC_CIMR */ +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_INTC_CLMASK */ +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_INTC_SLMASK */ +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* Interrupt Controller (INTC_IACK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(0xFC0540E0)) +#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(0xFC0540E4)) +#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(0xFC0540E8)) +#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(0xFC0540EC)) +#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(0xFC0540F0)) +#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(0xFC0540F4)) +#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(0xFC0540F8)) +#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(0xFC0540FC)) +#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(0xFC0540E4+((x-1)*0x004))) + +/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ +#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ +#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(0xFC058000)) +#define MCF_I2C_I2FDR (*(vuint8 *)(0xFC058004)) +#define MCF_I2C_I2CR (*(vuint8 *)(0xFC058008)) +#define MCF_I2C_I2SR (*(vuint8 *)(0xFC05800C)) +#define MCF_I2C_I2DR (*(vuint8 *)(0xFC058010)) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(0xFC05C000)) +#define MCF_QSPI_QDLYR (*(vuint16*)(0xFC05C004)) +#define MCF_QSPI_QWR (*(vuint16*)(0xFC05C008)) +#define MCF_QSPI_QIR (*(vuint16*)(0xFC05C00C)) +#define MCF_QSPI_QAR (*(vuint16*)(0xFC05C010)) +#define MCF_QSPI_QDR (*(vuint16*)(0xFC05C014)) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) +#define MCF_QSPI_QAR_TRANS (0x0000) +#define MCF_QSPI_QAR_RECV (0x0010) +#define MCF_QSPI_QAR_CMD (0x0020) + +/* Bit definitions and macros for MCF_QSPI_QDR */ +#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_QSPI_QDR_CONT (0x8000) +#define MCF_QSPI_QDR_BITSE (0x4000) +#define MCF_QSPI_QDR_DT (0x2000) +#define MCF_QSPI_QDR_DSCK (0x1000) +#define MCF_QSPI_QDR_QSPI_CS3 (0x0800) +#define MCF_QSPI_QDR_QSPI_CS2 (0x0400) +#define MCF_QSPI_QDR_QSPI_CS1 (0x0200) +#define MCF_QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART0_UMR (*(vuint8 *)(0xFC060000)) +#define MCF_UART0_USR (*(vuint8 *)(0xFC060004)) +#define MCF_UART0_UCSR (*(vuint8 *)(0xFC060004)) +#define MCF_UART0_UCR (*(vuint8 *)(0xFC060008)) +#define MCF_UART0_URB (*(vuint8 *)(0xFC06000C)) +#define MCF_UART0_UTB (*(vuint8 *)(0xFC06000C)) +#define MCF_UART0_UIPCR (*(vuint8 *)(0xFC060010)) +#define MCF_UART0_UACR (*(vuint8 *)(0xFC060010)) +#define MCF_UART0_UISR (*(vuint8 *)(0xFC060014)) +#define MCF_UART0_UIMR (*(vuint8 *)(0xFC060014)) +#define MCF_UART0_UBG1 (*(vuint8 *)(0xFC060018)) +#define MCF_UART0_UBG2 (*(vuint8 *)(0xFC06001C)) +#define MCF_UART0_UIP (*(vuint8 *)(0xFC060034)) +#define MCF_UART0_UOP1 (*(vuint8 *)(0xFC060038)) +#define MCF_UART0_UOP0 (*(vuint8 *)(0xFC06003C)) +#define MCF_UART1_UMR (*(vuint8 *)(0xFC064000)) +#define MCF_UART1_USR (*(vuint8 *)(0xFC064004)) +#define MCF_UART1_UCSR (*(vuint8 *)(0xFC064004)) +#define MCF_UART1_UCR (*(vuint8 *)(0xFC064008)) +#define MCF_UART1_URB (*(vuint8 *)(0xFC06400C)) +#define MCF_UART1_UTB (*(vuint8 *)(0xFC06400C)) +#define MCF_UART1_UIPCR (*(vuint8 *)(0xFC064010)) +#define MCF_UART1_UACR (*(vuint8 *)(0xFC064010)) +#define MCF_UART1_UISR (*(vuint8 *)(0xFC064014)) +#define MCF_UART1_UIMR (*(vuint8 *)(0xFC064014)) +#define MCF_UART1_UBG1 (*(vuint8 *)(0xFC064018)) +#define MCF_UART1_UBG2 (*(vuint8 *)(0xFC06401C)) +#define MCF_UART1_UIP (*(vuint8 *)(0xFC064034)) +#define MCF_UART1_UOP1 (*(vuint8 *)(0xFC064038)) +#define MCF_UART1_UOP0 (*(vuint8 *)(0xFC06403C)) +#define MCF_UART2_UMR (*(vuint8 *)(0xFC068000)) +#define MCF_UART2_USR (*(vuint8 *)(0xFC068004)) +#define MCF_UART2_UCSR (*(vuint8 *)(0xFC068004)) +#define MCF_UART2_UCR (*(vuint8 *)(0xFC068008)) +#define MCF_UART2_URB (*(vuint8 *)(0xFC06800C)) +#define MCF_UART2_UTB (*(vuint8 *)(0xFC06800C)) +#define MCF_UART2_UIPCR (*(vuint8 *)(0xFC068010)) +#define MCF_UART2_UACR (*(vuint8 *)(0xFC068010)) +#define MCF_UART2_UISR (*(vuint8 *)(0xFC068014)) +#define MCF_UART2_UIMR (*(vuint8 *)(0xFC068014)) +#define MCF_UART2_UBG1 (*(vuint8 *)(0xFC068018)) +#define MCF_UART2_UBG2 (*(vuint8 *)(0xFC06801C)) +#define MCF_UART2_UIP (*(vuint8 *)(0xFC068034)) +#define MCF_UART2_UOP1 (*(vuint8 *)(0xFC068038)) +#define MCF_UART2_UOP0 (*(vuint8 *)(0xFC06803C)) +#define MCF_UART_UMR(x) (*(vuint8 *)(0xFC060000+((x)*0x4000))) +#define MCF_UART_USR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000))) +#define MCF_UART_UCSR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000))) +#define MCF_UART_UCR(x) (*(vuint8 *)(0xFC060008+((x)*0x4000))) +#define MCF_UART_URB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000))) +#define MCF_UART_UTB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000))) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000))) +#define MCF_UART_UACR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000))) +#define MCF_UART_UISR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000))) +#define MCF_UART_UIMR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000))) +#define MCF_UART_UBG1(x) (*(vuint8 *)(0xFC060018+((x)*0x4000))) +#define MCF_UART_UBG2(x) (*(vuint8 *)(0xFC06001C+((x)*0x4000))) +#define MCF_UART_UIP(x) (*(vuint8 *)(0xFC060034+((x)*0x4000))) +#define MCF_UART_UOP1(x) (*(vuint8 *)(0xFC060038+((x)*0x4000))) +#define MCF_UART_UOP0(x) (*(vuint8 *)(0xFC06003C+((x)*0x4000))) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR (*(vuint16*)(0xFC070000)) +#define MCF_DTIM0_DTXMR (*(vuint8 *)(0xFC070002)) +#define MCF_DTIM0_DTER (*(vuint8 *)(0xFC070003)) +#define MCF_DTIM0_DTRR (*(vuint32*)(0xFC070004)) +#define MCF_DTIM0_DTCR (*(vuint32*)(0xFC070008)) +#define MCF_DTIM0_DTCN (*(vuint32*)(0xFC07000C)) +#define MCF_DTIM1_DTMR (*(vuint16*)(0xFC074000)) +#define MCF_DTIM1_DTXMR (*(vuint8 *)(0xFC074002)) +#define MCF_DTIM1_DTER (*(vuint8 *)(0xFC074003)) +#define MCF_DTIM1_DTRR (*(vuint32*)(0xFC074004)) +#define MCF_DTIM1_DTCR (*(vuint32*)(0xFC074008)) +#define MCF_DTIM1_DTCN (*(vuint32*)(0xFC07400C)) +#define MCF_DTIM2_DTMR (*(vuint16*)(0xFC078000)) +#define MCF_DTIM2_DTXMR (*(vuint8 *)(0xFC078002)) +#define MCF_DTIM2_DTER (*(vuint8 *)(0xFC078003)) +#define MCF_DTIM2_DTRR (*(vuint32*)(0xFC078004)) +#define MCF_DTIM2_DTCR (*(vuint32*)(0xFC078008)) +#define MCF_DTIM2_DTCN (*(vuint32*)(0xFC07800C)) +#define MCF_DTIM3_DTMR (*(vuint16*)(0xFC07C000)) +#define MCF_DTIM3_DTXMR (*(vuint8 *)(0xFC07C002)) +#define MCF_DTIM3_DTER (*(vuint8 *)(0xFC07C003)) +#define MCF_DTIM3_DTRR (*(vuint32*)(0xFC07C004)) +#define MCF_DTIM3_DTCR (*(vuint32*)(0xFC07C008)) +#define MCF_DTIM3_DTCN (*(vuint32*)(0xFC07C00C)) +#define MCF_DTIM_DTMR(x) (*(vuint16*)(0xFC070000+((x)*0x4000))) +#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0xFC070002+((x)*0x4000))) +#define MCF_DTIM_DTER(x) (*(vuint8 *)(0xFC070003+((x)*0x4000))) +#define MCF_DTIM_DTRR(x) (*(vuint32*)(0xFC070004+((x)*0x4000))) +#define MCF_DTIM_DTCR(x) (*(vuint32*)(0xFC070008+((x)*0x4000))) +#define MCF_DTIM_DTCN(x) (*(vuint32*)(0xFC07000C+((x)*0x4000))) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT0_PCSR (*(vuint16*)(0xFC080000)) +#define MCF_PIT0_PMR (*(vuint16*)(0xFC080002)) +#define MCF_PIT0_PCNTR (*(vuint16*)(0xFC080004)) +#define MCF_PIT1_PCSR (*(vuint16*)(0xFC084000)) +#define MCF_PIT1_PMR (*(vuint16*)(0xFC084002)) +#define MCF_PIT1_PCNTR (*(vuint16*)(0xFC084004)) +#define MCF_PIT2_PCSR (*(vuint16*)(0xFC088000)) +#define MCF_PIT2_PMR (*(vuint16*)(0xFC088002)) +#define MCF_PIT2_PCNTR (*(vuint16*)(0xFC088004)) +#define MCF_PIT3_PCSR (*(vuint16*)(0xFC08C000)) +#define MCF_PIT3_PMR (*(vuint16*)(0xFC08C002)) +#define MCF_PIT3_PCNTR (*(vuint16*)(0xFC08C004)) +#define MCF_PIT_PCSR(x) (*(vuint16*)(0xFC080000+((x)*0x4000))) +#define MCF_PIT_PMR(x) (*(vuint16*)(0xFC080002+((x)*0x4000))) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(0xFC080004+((x)*0x4000))) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Pulse Width Modulation (PWM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PWM_PWME (*(vuint8 *)(0xFC090020)) +#define MCF_PWM_PWMPOL (*(vuint8 *)(0xFC090021)) +#define MCF_PWM_PWMCLK (*(vuint8 *)(0xFC090022)) +#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0xFC090023)) +#define MCF_PWM_PWMCAE (*(vuint8 *)(0xFC090024)) +#define MCF_PWM_PWMCTL (*(vuint8 *)(0xFC090025)) +#define MCF_PWM_PWMSCLA (*(vuint8 *)(0xFC090028)) +#define MCF_PWM_PWMSCLB (*(vuint8 *)(0xFC090029)) +#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0xFC09002C)) +#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0xFC09002D)) +#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0xFC09002E)) +#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0xFC09002F)) +#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0xFC090030)) +#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0xFC090031)) +#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0xFC090032)) +#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0xFC090033)) +#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0xFC09002C+((x)*0x001))) +#define MCF_PWM_PWMPER0 (*(vuint8 *)(0xFC090034)) +#define MCF_PWM_PWMPER1 (*(vuint8 *)(0xFC090035)) +#define MCF_PWM_PWMPER2 (*(vuint8 *)(0xFC090036)) +#define MCF_PWM_PWMPER3 (*(vuint8 *)(0xFC090037)) +#define MCF_PWM_PWMPER4 (*(vuint8 *)(0xFC090038)) +#define MCF_PWM_PWMPER5 (*(vuint8 *)(0xFC090039)) +#define MCF_PWM_PWMPER6 (*(vuint8 *)(0xFC09003A)) +#define MCF_PWM_PWMPER7 (*(vuint8 *)(0xFC09003B)) +#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0xFC090034+((x)*0x001))) +#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0xFC09003C)) +#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0xFC09003D)) +#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0xFC09003E)) +#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0xFC09003F)) +#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0xFC090040)) +#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0xFC090041)) +#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0xFC090042)) +#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0xFC090043)) +#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0xFC09003C+((x)*0x001))) +#define MCF_PWM_PWMSDN (*(vuint8 *)(0xFC090044)) + +/* Bit definitions and macros for MCF_PWM_PWME */ +#define MCF_PWM_PWME_PWME0 (0x01) +#define MCF_PWM_PWME_PWME1 (0x02) +#define MCF_PWM_PWME_PWME2 (0x04) +#define MCF_PWM_PWME_PWME3 (0x08) +#define MCF_PWM_PWME_PWME4 (0x10) +#define MCF_PWM_PWME_PWME5 (0x20) +#define MCF_PWM_PWME_PWME6 (0x40) +#define MCF_PWM_PWME_PWME7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMPOL */ +#define MCF_PWM_PWMPOL_PPOL0 (0x01) +#define MCF_PWM_PWMPOL_PPOL1 (0x02) +#define MCF_PWM_PWMPOL_PPOL2 (0x04) +#define MCF_PWM_PWMPOL_PPOL3 (0x08) +#define MCF_PWM_PWMPOL_PPOL4 (0x10) +#define MCF_PWM_PWMPOL_PPOL5 (0x20) +#define MCF_PWM_PWMPOL_PPOL6 (0x40) +#define MCF_PWM_PWMPOL_PPOL7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMCLK */ +#define MCF_PWM_PWMCLK_PCLK0 (0x01) +#define MCF_PWM_PWMCLK_PCLK1 (0x02) +#define MCF_PWM_PWMCLK_PCLK2 (0x04) +#define MCF_PWM_PWMCLK_PCLK3 (0x08) +#define MCF_PWM_PWMCLK_PCLK4 (0x10) +#define MCF_PWM_PWMCLK_PCLK5 (0x20) +#define MCF_PWM_PWMCLK_PCLK6 (0x40) +#define MCF_PWM_PWMCLK_PCLK7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ +#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) +#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_PWM_PWMCAE */ +#define MCF_PWM_PWMCAE_CAE0 (0x01) +#define MCF_PWM_PWMCAE_CAE1 (0x02) +#define MCF_PWM_PWMCAE_CAE2 (0x04) +#define MCF_PWM_PWMCAE_CAE3 (0x08) +#define MCF_PWM_PWMCAE_CAE4 (0x10) +#define MCF_PWM_PWMCAE_CAE5 (0x20) +#define MCF_PWM_PWMCAE_CAE6 (0x40) +#define MCF_PWM_PWMCAE_CAE7 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMCTL */ +#define MCF_PWM_PWMCTL_PFRZ (0x04) +#define MCF_PWM_PWMCTL_PSWAI (0x08) +#define MCF_PWM_PWMCTL_CON01 (0x10) +#define MCF_PWM_PWMCTL_CON23 (0x20) +#define MCF_PWM_PWMCTL_CON45 (0x40) +#define MCF_PWM_PWMCTL_CON67 (0x80) + +/* Bit definitions and macros for MCF_PWM_PWMSCLA */ +#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSCLB */ +#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMCNT */ +#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMPER */ +#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMDTY */ +#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PWM_PWMSDN */ +#define MCF_PWM_PWMSDN_SDNEN (0x01) +#define MCF_PWM_PWMSDN_PWM7IL (0x02) +#define MCF_PWM_PWMSDN_PWM7IN (0x04) +#define MCF_PWM_PWMSDN_LVL (0x10) +#define MCF_PWM_PWMSDN_RESTART (0x20) +#define MCF_PWM_PWMSDN_IE (0x40) +#define MCF_PWM_PWMSDN_IF (0x80) + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(vuint16*)(0xFC094000)) +#define MCF_EPORT_EPDDR (*(vuint8 *)(0xFC094002)) +#define MCF_EPORT_EPIER (*(vuint8 *)(0xFC094003)) +#define MCF_EPORT_EPDR (*(vuint8 *)(0xFC094004)) +#define MCF_EPORT_EPPDR (*(vuint8 *)(0xFC094005)) +#define MCF_EPORT_EPFR (*(vuint8 *)(0xFC094006)) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* +* Watchdog Timer Modules (WTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_WTM_WCR (*(vuint16*)(0xFC098000)) +#define MCF_WTM_WMR (*(vuint16*)(0xFC098002)) +#define MCF_WTM_WCNTR (*(vuint16*)(0xFC098004)) +#define MCF_WTM_WSR (*(vuint16*)(0xFC098006)) + +/* Bit definitions and macros for MCF_WTM_WCR */ +#define MCF_WTM_WCR_EN (0x0001) +#define MCF_WTM_WCR_HALTED (0x0002) +#define MCF_WTM_WCR_DOZE (0x0004) +#define MCF_WTM_WCR_WAIT (0x0008) + +/* Bit definitions and macros for MCF_WTM_WMR */ +#define MCF_WTM_WMR_WM(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_WTM_WCNTR */ +#define MCF_WTM_WCNTR_WC(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_WTM_WSR */ +#define MCF_WTM_WSR_WS(x) (((x)&0xFFFF)<<0) + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CCM_CCR (*(vuint16*)(0xFC0A0004)) +#define MCF_CCM_RCON (*(vuint16*)(0xFC0A0008)) +#define MCF_CCM_CIR (*(vuint16*)(0xFC0A000A)) +#define MCF_CCM_MISCCR (*(vuint16*)(0xFC0A0010)) +#define MCF_CCM_CDR (*(vuint16*)(0xFC0A0012)) +#define MCF_CCM_UHCSR (*(vuint16*)(0xFC0A0014)) +#define MCF_CCM_UOCSR (*(vuint16*)(0xFC0A0016)) + +/* Bit definitions and macros for MCF_CCM_CCR */ +#define MCF_CCM_CCR_RESERVED (0x0001) +#define MCF_CCM_CCR_PLL_MODE (0x0003) +#define MCF_CCM_CCR_OSC_MODE (0x0005) +#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define MCF_CCM_CCR_LOAD (0x0021) +#define MCF_CCM_CCR_LIMP (0x0041) +#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) + +/* Bit definitions and macros for MCF_CCM_RCON */ +#define MCF_CCM_RCON_RESERVED (0x0001) +#define MCF_CCM_RCON_PLL_MODE (0x0003) +#define MCF_CCM_RCON_OSC_MODE (0x0005) +#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define MCF_CCM_RCON_LOAD (0x0021) +#define MCF_CCM_RCON_LIMP (0x0041) +#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) + +/* Bit definitions and macros for MCF_CCM_CIR */ +#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) +#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) + +/* Bit definitions and macros for MCF_CCM_MISCCR */ +#define MCF_CCM_MISCCR_USBSRC (0x0001) +#define MCF_CCM_MISCCR_USBDIV (0x0002) +#define MCF_CCM_MISCCR_SSI_SRC (0x0010) +#define MCF_CCM_MISCCR_TIM_DMA (0x0020) +#define MCF_CCM_MISCCR_SSI_PUS (0x0040) +#define MCF_CCM_MISCCR_SSI_PUE (0x0080) +#define MCF_CCM_MISCCR_LCD_CHEN (0x0100) +#define MCF_CCM_MISCCR_LIMP (0x1000) +#define MCF_CCM_MISCCR_PLL_LOCK (0x2000) + +/* Bit definitions and macros for MCF_CCM_CDR */ +#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x003F)<<0) +#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_CCM_UHCSR */ +#define MCF_CCM_UHCSR_XPDE (0x0001) +#define MCF_CCM_UHCSR_UHMIE (0x0002) +#define MCF_CCM_UHCSR_WKUP (0x0004) +#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_CCM_UOCSR */ +#define MCF_CCM_UOCSR_XPDE (0x0001) +#define MCF_CCM_UOCSR_UOMIE (0x0002) +#define MCF_CCM_UOCSR_WKUP (0x0004) +#define MCF_CCM_UOCSR_PWRFLT (0x0008) +#define MCF_CCM_UOCSR_SEND (0x0010) +#define MCF_CCM_UOCSR_VVLD (0x0020) +#define MCF_CCM_UOCSR_BVLD (0x0040) +#define MCF_CCM_UOCSR_AVLD (0x0080) +#define MCF_CCM_UOCSR_DPPU (0x0100) +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) +#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) +#define MCF_CCM_UOCSR_DMPD (0x1000) +#define MCF_CCM_UOCSR_DPPD (0x2000) +#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) + +/********************************************************************* +* +* Reset Controller Module (RCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RCM_RCR (*(vuint8 *)(0xFC0A0000)) +#define MCF_RCM_RSR (*(vuint8 *)(0xFC0A0001)) + +/* Bit definitions and macros for MCF_RCM_RCR */ +#define MCF_RCM_RCR_FRCRSTOUT (0x40) +#define MCF_RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_RCM_RSR */ +#define MCF_RCM_RSR_LOL (0x01) +#define MCF_RCM_RSR_WDR_CORE (0x02) +#define MCF_RCM_RSR_EXT (0x04) +#define MCF_RCM_RSR_POR (0x08) +#define MCF_RCM_RSR_WDR_CHIP (0x10) +#define MCF_RCM_RSR_SOFT (0x20) + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FECH (*(vuint8 *)(0xFC0A4000)) +#define MCF_GPIO_PODR_FECL (*(vuint8 *)(0xFC0A4001)) +#define MCF_GPIO_PODR_SSI (*(vuint8 *)(0xFC0A4002)) +#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(0xFC0A4003)) +#define MCF_GPIO_PODR_BE (*(vuint8 *)(0xFC0A4004)) +#define MCF_GPIO_PODR_CS (*(vuint8 *)(0xFC0A4005)) +#define MCF_GPIO_PODR_PWM (*(vuint8 *)(0xFC0A4006)) +#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(0xFC0A4007)) +#define MCF_GPIO_PODR_UART (*(vuint8 *)(0xFC0A4009)) +#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(0xFC0A400A)) +#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(0xFC0A400B)) +#define MCF_GPIO_PODR_LCDDATAH (*(vuint8 *)(0xFC0A400D)) +#define MCF_GPIO_PODR_LCDDATAM (*(vuint8 *)(0xFC0A400E)) +#define MCF_GPIO_PODR_LCDDATAL (*(vuint8 *)(0xFC0A400F)) +#define MCF_GPIO_PODR_LCDCTLH (*(vuint8 *)(0xFC0A4010)) +#define MCF_GPIO_PODR_LCDCTLL (*(vuint8 *)(0xFC0A4011)) +#define MCF_GPIO_PDDR_FECH (*(vuint8 *)(0xFC0A4014)) +#define MCF_GPIO_PDDR_FECL (*(vuint8 *)(0xFC0A4015)) +#define MCF_GPIO_PDDR_SSI (*(vuint8 *)(0xFC0A4016)) +#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(0xFC0A4017)) +#define MCF_GPIO_PDDR_BE (*(vuint8 *)(0xFC0A4018)) +#define MCF_GPIO_PDDR_CS (*(vuint8 *)(0xFC0A4019)) +#define MCF_GPIO_PDDR_PWM (*(vuint8 *)(0xFC0A401A)) +#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(0xFC0A401B)) +#define MCF_GPIO_PDDR_UART (*(vuint8 *)(0xFC0A401D)) +#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(0xFC0A401E)) +#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(0xFC0A401F)) +#define MCF_GPIO_PDDR_LCDDATAH (*(vuint8 *)(0xFC0A4021)) +#define MCF_GPIO_PDDR_LCDDATAM (*(vuint8 *)(0xFC0A4022)) +#define MCF_GPIO_PDDR_LCDDATAL (*(vuint8 *)(0xFC0A4023)) +#define MCF_GPIO_PDDR_LCDCTLH (*(vuint8 *)(0xFC0A4024)) +#define MCF_GPIO_PDDR_LCDCTLL (*(vuint8 *)(0xFC0A4025)) +#define MCF_GPIO_PPDSDR_FECH (*(vuint8 *)(0xFC0A4028)) +#define MCF_GPIO_PPDSDR_FECL (*(vuint8 *)(0xFC0A4029)) +#define MCF_GPIO_PPDSDR_SSI (*(vuint8 *)(0xFC0A402A)) +#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(0xFC0A402B)) +#define MCF_GPIO_PPDSDR_BE (*(vuint8 *)(0xFC0A402C)) +#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(0xFC0A402D)) +#define MCF_GPIO_PPDSDR_PWM (*(vuint8 *)(0xFC0A402E)) +#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(0xFC0A402F)) +#define MCF_GPIO_PPDSDR_UART (*(vuint8 *)(0xFC0A4031)) +#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(0xFC0A4032)) +#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(0xFC0A4033)) +#define MCF_GPIO_PPDSDR_LCDDATAH (*(vuint8 *)(0xFC0A4035)) +#define MCF_GPIO_PPDSDR_LCDDATAM (*(vuint8 *)(0xFC0A4036)) +#define MCF_GPIO_PPDSDR_LCDDATAL (*(vuint8 *)(0xFC0A4037)) +#define MCF_GPIO_PPDSDR_LCDCTLH (*(vuint8 *)(0xFC0A4038)) +#define MCF_GPIO_PPDSDR_LCDCTLL (*(vuint8 *)(0xFC0A4039)) +#define MCF_GPIO_PCLRR_FECH (*(vuint8 *)(0xFC0A403C)) +#define MCF_GPIO_PCLRR_FECL (*(vuint8 *)(0xFC0A403D)) +#define MCF_GPIO_PCLRR_SSI (*(vuint8 *)(0xFC0A403E)) +#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(0xFC0A403F)) +#define MCF_GPIO_PCLRR_BE (*(vuint8 *)(0xFC0A4040)) +#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(0xFC0A4041)) +#define MCF_GPIO_PCLRR_PWM (*(vuint8 *)(0xFC0A4042)) +#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(0xFC0A4043)) +#define MCF_GPIO_PCLRR_UART (*(vuint8 *)(0xFC0A4045)) +#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(0xFC0A4046)) +#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(0xFC0A4047)) +#define MCF_GPIO_PCLRR_LCDDATAH (*(vuint8 *)(0xFC0A4049)) +#define MCF_GPIO_PCLRR_LCDDATAM (*(vuint8 *)(0xFC0A404A)) +#define MCF_GPIO_PCLRR_LCDDATAL (*(vuint8 *)(0xFC0A404B)) +#define MCF_GPIO_PCLRR_LCDCTLH (*(vuint8 *)(0xFC0A404C)) +#define MCF_GPIO_PCLRR_LCDCTLL (*(vuint8 *)(0xFC0A404D)) +#define MCF_GPIO_PAR_FEC (*(vuint8 *)(0xFC0A4050)) +#define MCF_GPIO_PAR_PWM (*(vuint8 *)(0xFC0A4051)) +#define MCF_GPIO_PAR_BUSCTL (*(vuint8 *)(0xFC0A4052)) +#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(0xFC0A4053)) +#define MCF_GPIO_PAR_BE (*(vuint8 *)(0xFC0A4054)) +#define MCF_GPIO_PAR_CS (*(vuint8 *)(0xFC0A4055)) +#define MCF_GPIO_PAR_SSI (*(vuint16*)(0xFC0A4056)) +#define MCF_GPIO_PAR_UART (*(vuint16*)(0xFC0A4058)) +#define MCF_GPIO_PAR_QSPI (*(vuint16*)(0xFC0A405A)) +#define MCF_GPIO_PAR_TIMER (*(vuint8 *)(0xFC0A405C)) +#define MCF_GPIO_PAR_LCDDATA (*(vuint8 *)(0xFC0A405D)) +#define MCF_GPIO_PAR_LCDCTL (*(vuint16*)(0xFC0A405E)) +#define MCF_GPIO_PAR_IRQ (*(vuint16*)(0xFC0A4060)) +#define MCF_GPIO_MSCR_FLEXBUS (*(vuint8 *)(0xFC0A4064)) +#define MCF_GPIO_MSCR_SDRAM (*(vuint8 *)(0xFC0A4065)) +#define MCF_GPIO_DSCR_I2C (*(vuint8 *)(0xFC0A4068)) +#define MCF_GPIO_DSCR_PWM (*(vuint8 *)(0xFC0A4069)) +#define MCF_GPIO_DSCR_FEC (*(vuint8 *)(0xFC0A406A)) +#define MCF_GPIO_DSCR_UART (*(vuint8 *)(0xFC0A406B)) +#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(0xFC0A406C)) +#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(0xFC0A406D)) +#define MCF_GPIO_DSCR_SSI (*(vuint8 *)(0xFC0A406E)) +#define MCF_GPIO_DSCR_LCD (*(vuint8 *)(0xFC0A406F)) +#define MCF_GPIO_DSCR_DEBUG (*(vuint8 *)(0xFC0A4070)) +#define MCF_GPIO_DSCR_CLKRST (*(vuint8 *)(0xFC0A4071)) +#define MCF_GPIO_DSCR_IRQ (*(vuint8 *)(0xFC0A4072)) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ +#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) +#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) +#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) +#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) +#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) +#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) +#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) +#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECL */ +#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) +#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) +#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) +#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) +#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) +#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) +#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) +#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_SSI */ +#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) +#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) +#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) +#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) +#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_BE */ +#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) +#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) +#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) +#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_CS */ +#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) +#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) +#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) +#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) +#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_PWM */ +#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) +#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) +#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) +#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_UART */ +#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) +#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) +#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) +#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) +#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) +#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) +#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) +#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ +#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ +#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ +#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ +#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ +#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ +#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BE */ +#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) +#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) +#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) +#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ +#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) +#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) +#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) +#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) +#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ +#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_UART */ +#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) +#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) +#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) +#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) +#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) +#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) +#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) +#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ +#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ +#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ +#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ +#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ +#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ +#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PAR_FEC */ +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_PWM */ +#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) +#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ +#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) + +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x01) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_BE */ +#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) +#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) +#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) +#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PAR_CS */ +#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) +#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) +#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) +#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) +#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_SSI */ +#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) +#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_GPIO_PAR_UART */ +#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) +#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) +#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) +#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) +#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) +#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) +#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) +#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) +#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) +#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) +#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) + +/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ +#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ +#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ +#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ +#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) +#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) +#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) +#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) +#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) +#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) +#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) +#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) +#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) + +/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ +#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) + +/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ +#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ +#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ +#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ +#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) +#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ +#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ +#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ +#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ +#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ +#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ +#define MCF_GPIO_DSCR_CLKRST_MSCR_FBCLK(x) (((x)&0x03)<<0) +#define MCF_GPIO_DSCR_CLKRST_RSTOUT_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ +#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) + +/********************************************************************* +* +* Real-time Clock (RTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RTC_HOURMIN (*(vuint32*)(0xFC0A8000)) +#define MCF_RTC_SECONDS (*(vuint32*)(0xFC0A8004)) +#define MCF_RTC_ALRM_HM (*(vuint32*)(0xFC0A8008)) +#define MCF_RTC_ALRM_SEC (*(vuint32*)(0xFC0A800C)) +#define MCF_RTC_CR (*(vuint32*)(0xFC0A8010)) +#define MCF_RTC_ISR (*(vuint32*)(0xFC0A8014)) +#define MCF_RTC_IER (*(vuint32*)(0xFC0A8018)) +#define MCF_RTC_STPWCH (*(vuint32*)(0xFC0A801C)) +#define MCF_RTC_DAYS (*(vuint32*)(0xFC0A8020)) +#define MCF_RTC_ALRM_DAY (*(vuint32*)(0xFC0A8024)) + +/* Bit definitions and macros for MCF_RTC_HOURMIN */ +#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_SECONDS */ +#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_HM */ +#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) +#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ +#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_CR */ +#define MCF_RTC_CR_SWR (0x00000001) +#define MCF_RTC_CR_XTL(x) (((x)&0x00000003)<<5) +#define MCF_RTC_CR_EN (0x00000080) +#define MCF_RTC_CR_32768 (0x0) +#define MCF_RTC_CR_32000 (0x1) +#define MCF_RTC_CR_38400 (0x2) + +/* Bit definitions and macros for MCF_RTC_ISR */ +#define MCF_RTC_ISR_SW (0x00000001) +#define MCF_RTC_ISR_MIN (0x00000002) +#define MCF_RTC_ISR_ALM (0x00000004) +#define MCF_RTC_ISR_DAY (0x00000008) +#define MCF_RTC_ISR_1HZ (0x00000010) +#define MCF_RTC_ISR_HR (0x00000020) +#define MCF_RTC_ISR_2HZ (0x00000080) +#define MCF_RTC_ISR_SAM0 (0x00000100) +#define MCF_RTC_ISR_SAM1 (0x00000200) +#define MCF_RTC_ISR_SAM2 (0x00000400) +#define MCF_RTC_ISR_SAM3 (0x00000800) +#define MCF_RTC_ISR_SAM4 (0x00001000) +#define MCF_RTC_ISR_SAM5 (0x00002000) +#define MCF_RTC_ISR_SAM6 (0x00004000) +#define MCF_RTC_ISR_SAM7 (0x00008000) + +/* Bit definitions and macros for MCF_RTC_IER */ +#define MCF_RTC_IER_SW (0x00000001) +#define MCF_RTC_IER_MIN (0x00000002) +#define MCF_RTC_IER_ALM (0x00000004) +#define MCF_RTC_IER_DAY (0x00000008) +#define MCF_RTC_IER_1HZ (0x00000010) +#define MCF_RTC_IER_HR (0x00000020) +#define MCF_RTC_IER_2HZ (0x00000080) +#define MCF_RTC_IER_SAM0 (0x00000100) +#define MCF_RTC_IER_SAM1 (0x00000200) +#define MCF_RTC_IER_SAM2 (0x00000400) +#define MCF_RTC_IER_SAM3 (0x00000800) +#define MCF_RTC_IER_SAM4 (0x00001000) +#define MCF_RTC_IER_SAM5 (0x00002000) +#define MCF_RTC_IER_SAM6 (0x00004000) +#define MCF_RTC_IER_SAM7 (0x00008000) + +/* Bit definitions and macros for MCF_RTC_STPWCH */ +#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_RTC_DAYS */ +#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ +#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) + +/********************************************************************* +* +* LCD Controller (LCDC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_LCDC_LSSAR (*(vuint32*)(0xFC0AC000)) +#define MCF_LCDC_LSR (*(vuint32*)(0xFC0AC004)) +#define MCF_LCDC_LVPWR (*(vuint32*)(0xFC0AC008)) +#define MCF_LCDC_LCPR (*(vuint32*)(0xFC0AC00C)) +#define MCF_LCDC_LCWHBR (*(vuint32*)(0xFC0AC010)) +#define MCF_LCDC_LCCMR (*(vuint32*)(0xFC0AC014)) +#define MCF_LCDC_LPCR (*(vuint32*)(0xFC0AC018)) +#define MCF_LCDC_LHCR (*(vuint32*)(0xFC0AC01C)) +#define MCF_LCDC_LVCR (*(vuint32*)(0xFC0AC020)) +#define MCF_LCDC_LPOR (*(vuint32*)(0xFC0AC024)) +#define MCF_LCDC_LSCR (*(vuint32*)(0xFC0AC028)) +#define MCF_LCDC_LPCCR (*(vuint32*)(0xFC0AC02C)) +#define MCF_LCDC_LDCR (*(vuint32*)(0xFC0AC030)) +#define MCF_LCDC_LRMCR (*(vuint32*)(0xFC0AC034)) +#define MCF_LCDC_LICR (*(vuint32*)(0xFC0AC038)) +#define MCF_LCDC_LIER (*(vuint32*)(0xFC0AC03C)) +#define MCF_LCDC_LISR (*(vuint32*)(0xFC0AC040)) +#define MCF_LCDC_LGWSAR (*(vuint32*)(0xFC0AC050)) +#define MCF_LCDC_LGWSR (*(vuint32*)(0xFC0AC054)) +#define MCF_LCDC_LGWVPWR (*(vuint32*)(0xFC0AC058)) +#define MCF_LCDC_LGWPOR (*(vuint32*)(0xFC0AC05C)) +#define MCF_LCDC_LGWPR (*(vuint32*)(0xFC0AC060)) +#define MCF_LCDC_LGWCR (*(vuint32*)(0xFC0AC064)) +#define MCF_LCDC_LGWDCR (*(vuint32*)(0xFC0AC068)) +#define MCF_LCDC_BPLUT_BASE (*(vuint32*)(0xFC0AC800)) +#define MCF_LCDC_GWLUT_BASE (*(vuint32*)(0xFC0ACC00)) + +/* Bit definitions and macros for MCF_LCDC_LSSAR */ +#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_LCDC_LSR */ +#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for MCF_LCDC_LVPWR */ +#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for MCF_LCDC_LCPR */ +#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define MCF_LCDC_LCPR_OP (0x10000000) +#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define MCF_LCDC_LCPR_CC_OR (0x40000000) +#define MCF_LCDC_LCPR_CC_XOR (0x80000000) +#define MCF_LCDC_LCPR_CC_AND (0xC0000000) +#define MCF_LCDC_LCPR_OP_ON (0x10000000) +#define MCF_LCDC_LCPR_OP_OFF (0x00000000) + +/* Bit definitions and macros for MCF_LCDC_LCWHBR */ +#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define MCF_LCDC_LCWHBR_BK_EN (0x80000000) +#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) + +/* Bit definitions and macros for MCF_LCDC_LCCMR */ +#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) + +/* Bit definitions and macros for MCF_LCDC_LPCR */ +#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LPCR_SHARP (0x00000040) +#define MCF_LCDC_LPCR_SCLKSEL (0x00000080) +#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define MCF_LCDC_LPCR_ACDSEL (0x00008000) +#define MCF_LCDC_LPCR_REV_VS (0x00010000) +#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) +#define MCF_LCDC_LPCR_ENDSEL (0x00040000) +#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) +#define MCF_LCDC_LPCR_OEPOL (0x00100000) +#define MCF_LCDC_LPCR_CLKPOL (0x00200000) +#define MCF_LCDC_LPCR_LPPOL (0x00400000) +#define MCF_LCDC_LPCR_FLM (0x00800000) +#define MCF_LCDC_LPCR_PIXPOL (0x01000000) +#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define MCF_LCDC_LPCR_COLOR (0x40000000) +#define MCF_LCDC_LPCR_TFT (0x80000000) +#define MCF_LCDC_LPCR_MODE_MONOCHROME (0x00000000) +#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) +#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) +#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) +#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) +#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) +#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) +#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) +#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) +#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) +#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) +#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) +#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) + +/* Bit definitions and macros for MCF_LCDC_LHCR */ +#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for MCF_LCDC_LVCR */ +#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for MCF_LCDC_LPOR */ +#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for MCF_LCDC_LPCCR */ +#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LPCCR_CC_EN (0x00000100) +#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define MCF_LCDC_LPCCR_LDMSK (0x00008000) +#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) + +/* Bit definitions and macros for MCF_LCDC_LDCR */ +#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LDCR_BURST (0x80000000) + +/* Bit definitions and macros for MCF_LCDC_LRMCR */ +#define MCF_LCDC_LRMCR_SEL_REF (0x00000001) + +/* Bit definitions and macros for MCF_LCDC_LICR */ +#define MCF_LCDC_LICR_INTCON (0x00000001) +#define MCF_LCDC_LICR_INTSYN (0x00000004) +#define MCF_LCDC_LICR_GW_INT_CON (0x00000010) + +/* Bit definitions and macros for MCF_LCDC_LIER */ +#define MCF_LCDC_LIER_BOF_EN (0x00000001) +#define MCF_LCDC_LIER_EOF_EN (0x00000002) +#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) +#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) +#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) +#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) +#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) + +/* Bit definitions and macros for MCF_LCDC_LISR */ +#define MCF_LCDC_LISR_BOF (0x00000001) +#define MCF_LCDC_LISR_EOF (0x00000002) +#define MCF_LCDC_LISR_ERR_RES (0x00000004) +#define MCF_LCDC_LISR_UDR_ERR (0x00000008) +#define MCF_LCDC_LISR_GW_BOF (0x00000010) +#define MCF_LCDC_LISR_GW_EOF (0x00000020) +#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) +#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) + +/* Bit definitions and macros for MCF_LCDC_LGWSAR */ +#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_LCDC_LGWSR */ +#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for MCF_LCDC_LGWVPWR */ +#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for MCF_LCDC_LGWPOR */ +#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for MCF_LCDC_LGWPR */ +#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) + +/* Bit definitions and macros for MCF_LCDC_LGWCR */ +#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define MCF_LCDC_LGWCR_GW_RVS (0x00200000) +#define MCF_LCDC_LGWCR_GWE (0x00400000) +#define MCF_LCDC_LGWCR_GWCKE (0x00800000) +#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_LCDC_LGWDCR */ +#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LGWDCR_GWBT (0x80000000) + +/* Bit definitions and macros for MCF_LCDC_LSCR */ +#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) +#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) +#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) +#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) +#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) + +/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ +#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ +#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* USB Controller (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB0_ID (*(vuint32*)(0xFC0B0000)) +#define MCF_USB0_HWGENERAL (*(vuint32*)(0xFC0B0004)) +#define MCF_USB0_HWHOST (*(vuint32*)(0xFC0B0008)) +#define MCF_USB0_HWDEVICE (*(vuint32*)(0xFC0B000C)) +#define MCF_USB0_HWTXBUF (*(vuint32*)(0xFC0B0010)) +#define MCF_USB0_HWRXBUF (*(vuint32*)(0xFC0B0014)) +#define MCF_USB0_CAPLENGTH (*(vuint8 *)(0xFC0B0100)) +#define MCF_USB0_HCIVERSION (*(vuint16*)(0xFC0B0102)) +#define MCF_USB0_HCSPARAMS (*(vuint32*)(0xFC0B0104)) +#define MCF_USB0_HCCPARAMS (*(vuint32*)(0xFC0B0108)) +#define MCF_USB0_DCIVERSION (*(vuint16*)(0xFC0B0120)) +#define MCF_USB0_DCCPARAMS (*(vuint32*)(0xFC0B0124)) +#define MCF_USB0_USBCMD (*(vuint32*)(0xFC0B0140)) +#define MCF_USB0_USBSTS (*(vuint32*)(0xFC0B0144)) +#define MCF_USB0_USBINTR (*(vuint32*)(0xFC0B0148)) +#define MCF_USB0_FRINDEX (*(vuint32*)(0xFC0B014C)) +#define MCF_USB0_PERIODICLISTBASE (*(vuint32*)(0xFC0B0154)) +#define MCF_USB0_DEVICEADDR (*(vuint32*)(0xFC0B0154)) +#define MCF_USB0_ASYNCLISTADDR (*(vuint32*)(0xFC0B0158)) +#define MCF_USB0_EPLISTADDR (*(vuint32*)(0xFC0B0158)) +#define MCF_USB0_ASYNCTTSTS (*(vuint32*)(0xFC0B015C)) +#define MCF_USB0_BURSTSIZE (*(vuint32*)(0xFC0B0160)) +#define MCF_USB0_TXFILLTUNING (*(vuint32*)(0xFC0B0164)) +#define MCF_USB0_TXTTFILLTUNING (*(vuint32*)(0xFC0B0168)) +#define MCF_USB_ULPI0_VIEWPORT (*(vuint32*)(0xFC0B0170)) +#define MCF_USB0_CONFIGFLAG (*(vuint32*)(0xFC0B0180)) +#define MCF_USB0_PORTSC (*(vuint32*)(0xFC0B0184)) +#define MCF_USB0_OTGSC (*(vuint32*)(0xFC0B01A4)) +#define MCF_USB0_USBMODE (*(vuint32*)(0xFC0B01A8)) +#define MCF_USB0_EPSETUPSR (*(vuint32*)(0xFC0B01AC)) +#define MCF_USB0_EPPRIME (*(vuint32*)(0xFC0B01B0)) +#define MCF_USB0_EPFLUSH (*(vuint32*)(0xFC0B01B4)) +#define MCF_USB0_EPSR (*(vuint32*)(0xFC0B01B8)) +#define MCF_USB0_EPCOMPLETE (*(vuint32*)(0xFC0B01BC)) +#define MCF_USB0_EPCR0 (*(vuint32*)(0xFC0B01C0)) +#define MCF_USB0_EPCR1 (*(vuint32*)(0xFC0B01C4)) +#define MCF_USB0_EPCR2 (*(vuint32*)(0xFC0B01C8)) +#define MCF_USB0_EPCR3 (*(vuint32*)(0xFC0B01CC)) +#define MCF_USB0_EPCR(x) (*(vuint32*)(0xFC0B01C4+((x-1)*0x004))) +#define MCF_USB1_ID (*(vuint32*)(0xFC0B4000)) +#define MCF_USB1_HWGENERAL (*(vuint32*)(0xFC0B4004)) +#define MCF_USB1_HWHOST (*(vuint32*)(0xFC0B4008)) +#define MCF_USB1_HWDEVICE (*(vuint32*)(0xFC0B400C)) +#define MCF_USB1_HWTXBUF (*(vuint32*)(0xFC0B4010)) +#define MCF_USB1_HWRXBUF (*(vuint32*)(0xFC0B4014)) +#define MCF_USB1_CAPLENGTH (*(vuint8 *)(0xFC0B4100)) +#define MCF_USB1_HCIVERSION (*(vuint16*)(0xFC0B4102)) +#define MCF_USB1_HCSPARAMS (*(vuint32*)(0xFC0B4104)) +#define MCF_USB1_HCCPARAMS (*(vuint32*)(0xFC0B4108)) +#define MCF_USB1_DCIVERSION (*(vuint16*)(0xFC0B4120)) +#define MCF_USB1_DCCPARAMS (*(vuint32*)(0xFC0B4124)) +#define MCF_USB1_USBCMD (*(vuint32*)(0xFC0B4140)) +#define MCF_USB1_USBSTS (*(vuint32*)(0xFC0B4144)) +#define MCF_USB1_USBINTR (*(vuint32*)(0xFC0B4148)) +#define MCF_USB1_FRINDEX (*(vuint32*)(0xFC0B414C)) +#define MCF_USB1_PERIODICLISTBASE (*(vuint32*)(0xFC0B4154)) +#define MCF_USB1_DEVICEADDR (*(vuint32*)(0xFC0B4154)) +#define MCF_USB1_ASYNCLISTADDR (*(vuint32*)(0xFC0B4158)) +#define MCF_USB1_EPLISTADDR (*(vuint32*)(0xFC0B4158)) +#define MCF_USB1_ASYNCTTSTS (*(vuint32*)(0xFC0B415C)) +#define MCF_USB1_BURSTSIZE (*(vuint32*)(0xFC0B4160)) +#define MCF_USB1_TXFILLTUNING (*(vuint32*)(0xFC0B4164)) +#define MCF_USB1_TXTTFILLTUNING (*(vuint32*)(0xFC0B4168)) +#define MCF_USB_ULPI1_VIEWPORT (*(vuint32*)(0xFC0B4170)) +#define MCF_USB1_CONFIGFLAG (*(vuint32*)(0xFC0B4180)) +#define MCF_USB1_PORTSC (*(vuint32*)(0xFC0B4184)) +#define MCF_USB1_OTGSC (*(vuint32*)(0xFC0B41A4)) +#define MCF_USB1_USBMODE (*(vuint32*)(0xFC0B41A8)) +#define MCF_USB1_EPSETUPSR (*(vuint32*)(0xFC0B41AC)) +#define MCF_USB1_EPPRIME (*(vuint32*)(0xFC0B41B0)) +#define MCF_USB1_EPFLUSH (*(vuint32*)(0xFC0B41B4)) +#define MCF_USB1_EPSR (*(vuint32*)(0xFC0B41B8)) +#define MCF_USB1_EPCOMPLETE (*(vuint32*)(0xFC0B41BC)) +#define MCF_USB1_EPCR0 (*(vuint32*)(0xFC0B41C0)) +#define MCF_USB1_EPCR1 (*(vuint32*)(0xFC0B41C4)) +#define MCF_USB1_EPCR2 (*(vuint32*)(0xFC0B41C8)) +#define MCF_USB1_EPCR3 (*(vuint32*)(0xFC0B41CC)) +#define MCF_USB1_EPCR(x) (*(vuint32*)(0xFC0B41C4+((x-1)*0x004))) +#define MCF_USB_ID(x) (*(vuint32*)(0xFC0B0000+((x)*0x4000))) +#define MCF_USB_HWGENERAL(x) (*(vuint32*)(0xFC0B0004+((x)*0x4000))) +#define MCF_USB_HWHOST(x) (*(vuint32*)(0xFC0B0008+((x)*0x4000))) +#define MCF_USB_HWDEVICE(x) (*(vuint32*)(0xFC0B000C+((x)*0x4000))) +#define MCF_USB_HWTXBUF(x) (*(vuint32*)(0xFC0B0010+((x)*0x4000))) +#define MCF_USB_HWRXBUF(x) (*(vuint32*)(0xFC0B0014+((x)*0x4000))) +#define MCF_USB_CAPLENGTH(x) (*(vuint8 *)(0xFC0B0100+((x)*0x4000))) +#define MCF_USB_HCIVERSION(x) (*(vuint16*)(0xFC0B0102+((x)*0x4000))) +#define MCF_USB_HCSPARAMS(x) (*(vuint32*)(0xFC0B0104+((x)*0x4000))) +#define MCF_USB_HCCPARAMS(x) (*(vuint32*)(0xFC0B0108+((x)*0x4000))) +#define MCF_USB_DCIVERSION(x) (*(vuint16*)(0xFC0B0120+((x)*0x4000))) +#define MCF_USB_DCCPARAMS(x) (*(vuint32*)(0xFC0B0124+((x)*0x4000))) +#define MCF_USB_USBCMD(x) (*(vuint32*)(0xFC0B0140+((x)*0x4000))) +#define MCF_USB_USBSTS(x) (*(vuint32*)(0xFC0B0144+((x)*0x4000))) +#define MCF_USB_USBINTR(x) (*(vuint32*)(0xFC0B0148+((x)*0x4000))) +#define MCF_USB_FRINDEX(x) (*(vuint32*)(0xFC0B014C+((x)*0x4000))) +#define MCF_USB_PERIODICLISTBASE(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000))) +#define MCF_USB_DEVICEADDR(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000))) +#define MCF_USB_ASYNCLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000))) +#define MCF_USB_EPLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000))) +#define MCF_USB_ASYNCTTSTS(x) (*(vuint32*)(0xFC0B015C+((x)*0x4000))) +#define MCF_USB_BURSTSIZE(x) (*(vuint32*)(0xFC0B0160+((x)*0x4000))) +#define MCF_USB_TXFILLTUNING(x) (*(vuint32*)(0xFC0B0164+((x)*0x4000))) +#define MCF_USB_TXTTFILLTUNING(x) (*(vuint32*)(0xFC0B0168+((x)*0x4000))) +#define MCF_USB_ULPI_VIEWPORT(x) (*(vuint32*)(0xFC0B0170+((x)*0x4000))) +#define MCF_USB_CONFIGFLAG(x) (*(vuint32*)(0xFC0B0180+((x)*0x4000))) +#define MCF_USB_PORTSC(x) (*(vuint32*)(0xFC0B0184+((x)*0x4000))) +#define MCF_USB_OTGSC(x) (*(vuint32*)(0xFC0B01A4+((x)*0x4000))) +#define MCF_USB_USBMODE(x) (*(vuint32*)(0xFC0B01A8+((x)*0x4000))) +#define MCF_USB_EPSETUPSR(x) (*(vuint32*)(0xFC0B01AC+((x)*0x4000))) +#define MCF_USB_EPPRIME(x) (*(vuint32*)(0xFC0B01B0+((x)*0x4000))) +#define MCF_USB_EPFLUSH(x) (*(vuint32*)(0xFC0B01B4+((x)*0x4000))) +#define MCF_USB_EPSR(x) (*(vuint32*)(0xFC0B01B8+((x)*0x4000))) +#define MCF_USB_EPCOMPLETE(x) (*(vuint32*)(0xFC0B01BC+((x)*0x4000))) +#define MCF_USB_EPCR0(x) (*(vuint32*)(0xFC0B01C0+((x)*0x4000))) +#define MCF_USB_EPCR1(x) (*(vuint32*)(0xFC0B01C4+((x)*0x4000))) +#define MCF_USB_EPCR2(x) (*(vuint32*)(0xFC0B01C8+((x)*0x4000))) +#define MCF_USB_EPCR3(x) (*(vuint32*)(0xFC0B01CC+((x)*0x4000))) + +/* Bit definitions and macros for MCF_USB_ID */ +#define MCF_USB_ID_RESERVED (0x0000C000) +#define MCF_USB_ID_ID(x) (((x)&0x0000003F)<<0|0x0000C000) +#define MCF_USB_ID_NID(x) (((x)&0x0000003F)<<8|0x0000C000) +#define MCF_USB_ID_REVISION(x) (((x)&0x000000FF)<<16|0x0000C000) + +/* Bit definitions and macros for MCF_USB_HWGENERAL */ +#define MCF_USB_HWGENERAL_RT (0x00000001) +#define MCF_USB_HWGENERAL_CLKC(x) (((x)&0x00000003)<<1) +#define MCF_USB_HWGENERAL_BWT (0x00000008) +#define MCF_USB_HWGENERAL_PHYW(x) (((x)&0x00000003)<<4) +#define MCF_USB_HWGENERAL_PHYM(x) (((x)&0x00000007)<<6) +#define MCF_USB_HWGENERAL_SM(x) (((x)&0x00000003)<<9) + +/* Bit definitions and macros for MCF_USB_HWHOST */ +#define MCF_USB_HWHOST_HC (0x00000001) +#define MCF_USB_HWHOST_NPORT(x) (((x)&0x00000007)<<1) +#define MCF_USB_HWHOST_TTASY(x) (((x)&0x000000FF)<<16) +#define MCF_USB_HWHOST_TTPER(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_USB_HWDEVICE */ +#define MCF_USB_HWDEVICE_DC (0x00000001) +#define MCF_USB_HWDEVICE_DEVEP(x) (((x)&0x0000001F)<<1) + +/* Bit definitions and macros for MCF_USB_HWTXBUF */ +#define MCF_USB_HWTXBUF_TXBURST(x) (((x)&0x000000FF)<<0) +#define MCF_USB_HWTXBUF_TXADD(x) (((x)&0x000000FF)<<8) +#define MCF_USB_HWTXBUF_TXCHANADD(x) (((x)&0x000000FF)<<16) +#define MCF_USB_HWTXBUF_TXLC (0x80000000) + +/* Bit definitions and macros for MCF_USB_HWRXBUF */ +#define MCF_USB_HWRXBUF_RXBURST(x) (((x)&0x000000FF)<<0) +#define MCF_USB_HWRXBUF_RXADD(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_USB_CAPLENGTH */ +#define MCF_USB_CAPLENGTH_CAPLENGTH(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_HCIVERSION */ +#define MCF_USB_HCIVERSION_HCIVERSION(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_HCSPARAMS */ +#define MCF_USB_HCSPARAMS_N_PORTS(x) (((x)&0x0000000F)<<0) +#define MCF_USB_HCSPARAMS_PPC (0x00000010) +#define MCF_USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) +#define MCF_USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) +#define MCF_USB_HCSPARAMS_PI (0x00010000) +#define MCF_USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) +#define MCF_USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF_USB_HCCPARAMS */ +#define MCF_USB_HCCPARAMS_ADC (0x00000001) +#define MCF_USB_HCCPARAMS_PFL (0x00000002) +#define MCF_USB_HCCPARAMS_ASP (0x00000004) +#define MCF_USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) +#define MCF_USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_USB_DCIVERSION */ +#define MCF_USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DCCPARAMS */ +#define MCF_USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) +#define MCF_USB_DCCPARAMS_DC (0x00000080) +#define MCF_USB_DCCPARAMS_HC (0x00000100) + +/* Bit definitions and macros for MCF_USB_USBCMD */ +#define MCF_USB_USBCMD_RS (0x00000001) +#define MCF_USB_USBCMD_RST (0x00000002) +#define MCF_USB_USBCMD_FS0 (0x00000004) +#define MCF_USB_USBCMD_FS1 (0x00000008) +#define MCF_USB_USBCMD_PSE (0x00000010) +#define MCF_USB_USBCMD_ASE (0x00000020) +#define MCF_USB_USBCMD_IAA (0x00000040) +#define MCF_USB_USBCMD_LR (0x00000080) +#define MCF_USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) +#define MCF_USB_USBCMD_ASPE (0x00000800) +#define MCF_USB_USBCMD_SUTW (0x00002000) +#define MCF_USB_USBCMD_ATDTW (0x00004000) +#define MCF_USB_USBCMD_FS2 (0x00008000) +#define MCF_USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) +#define MCF_USB_USBCMD_ITC_IMM (0x00000000) +#define MCF_USB_USBCMD_ITC_1 (0x00010000) +#define MCF_USB_USBCMD_ITC_2 (0x00020000) +#define MCF_USB_USBCMD_ITC_4 (0x00040000) +#define MCF_USB_USBCMD_ITC_8 (0x00080000) +#define MCF_USB_USBCMD_ITC_16 (0x00100000) +#define MCF_USB_USBCMD_ITC_32 (0x00200000) +#define MCF_USB_USBCMD_ITC_40 (0x00400000) +#define MCF_USB_USBCMD_FS_1024 (0x00000000) +#define MCF_USB_USBCMD_FS_512 (0x00000004) +#define MCF_USB_USBCMD_FS_256 (0x00000008) +#define MCF_USB_USBCMD_FS_128 (0x0000000C) +#define MCF_USB_USBCMD_FS_64 (0x00008000) +#define MCF_USB_USBCMD_FS_32 (0x00008004) +#define MCF_USB_USBCMD_FS_16 (0x00008008) +#define MCF_USB_USBCMD_FS_8 (0x0000800C) + +/* Bit definitions and macros for MCF_USB_USBSTS */ +#define MCF_USB_USBSTS_UI (0x00000001) +#define MCF_USB_USBSTS_UEI (0x00000002) +#define MCF_USB_USBSTS_PCI (0x00000004) +#define MCF_USB_USBSTS_FRI (0x00000008) +#define MCF_USB_USBSTS_SEI (0x00000010) +#define MCF_USB_USBSTS_AAI (0x00000020) +#define MCF_USB_USBSTS_URI (0x00000040) +#define MCF_USB_USBSTS_SRI (0x00000080) +#define MCF_USB_USBSTS_SLI (0x00000100) +#define MCF_USB_USBSTS_HCH (0x00001000) +#define MCF_USB_USBSTS_RCL (0x00002000) +#define MCF_USB_USBSTS_PS (0x00004000) +#define MCF_USB_USBSTS_AS (0x00008000) + +/* Bit definitions and macros for MCF_USB_USBINTR */ +#define MCF_USB_USBINTR_UE (0x00000001) +#define MCF_USB_USBINTR_UEE (0x00000002) +#define MCF_USB_USBINTR_PCE (0x00000004) +#define MCF_USB_USBINTR_FRE (0x00000008) +#define MCF_USB_USBINTR_SEE (0x00000010) +#define MCF_USB_USBINTR_AAE (0x00000020) +#define MCF_USB_USBINTR_URE (0x00000040) +#define MCF_USB_USBINTR_SRE (0x00000080) +#define MCF_USB_USBINTR_SLE (0x00000100) + +/* Bit definitions and macros for MCF_USB_FRINDEX */ +#define MCF_USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) + +/* Bit definitions and macros for MCF_USB_PERIODICLISTBASE */ +#define MCF_USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for MCF_USB_DEVICEADDR */ +#define MCF_USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) + +/* Bit definitions and macros for MCF_USB_ASYNCLISTADDR */ +#define MCF_USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) + +/* Bit definitions and macros for MCF_USB_EPLISTADDR */ +#define MCF_USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) + +/* Bit definitions and macros for MCF_USB_ASYNCTTSTS */ +#define MCF_USB_ASYNCTTSTS_TTAS (0x00000001) +#define MCF_USB_ASYNCTTSTS_TTAC (0x00000002) + +/* Bit definitions and macros for MCF_USB_BURSTSIZE */ +#define MCF_USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) +#define MCF_USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_USB_TXFILLTUNING */ +#define MCF_USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) +#define MCF_USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) +#define MCF_USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) + +/* Bit definitions and macros for MCF_USB_TXTTFILLTUNING */ +#define MCF_USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) +#define MCF_USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for MCF_USB_CONFIGFLAG */ +#define MCF_USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PORTSC */ +#define MCF_USB_PORTSC_CCS (0x00000001) +#define MCF_USB_PORTSC_CSC (0x00000002) +#define MCF_USB_PORTSC_PE (0x00000004) +#define MCF_USB_PORTSC_PEC (0x00000008) +#define MCF_USB_PORTSC_OCA (0x00000010) +#define MCF_USB_PORTSC_OCC (0x00000020) +#define MCF_USB_PORTSC_FPR (0x00000040) +#define MCF_USB_PORTSC_SUSP (0x00000080) +#define MCF_USB_PORTSC_PR (0x00000100) +#define MCF_USB_PORTSC_LS(x) (((x)&0x00000003)<<10) +#define MCF_USB_PORTSC_PP (0x00001000) +#define MCF_USB_PORTSC_PO (0x00002000) +#define MCF_USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) +#define MCF_USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) +#define MCF_USB_PORTSC_WLCN (0x00100000) +#define MCF_USB_PORTSC_WKDS (0x00200000) +#define MCF_USB_PORTSC_WKOC (0x00400000) +#define MCF_USB_PORTSC_PHCD (0x00800000) +#define MCF_USB_PORTSC_PFSC (0x01000000) +#define MCF_USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) +#define MCF_USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) +#define MCF_USB_PORTSC_PTS_ULPI (0x80000000) +#define MCF_USB_PORTSC_PTS_FS_LS (0xC0000000) +#define MCF_USB_PORTSC_PSPD_FULL (0x00000000) +#define MCF_USB_PORTSC_PSPD_LOW (0x04000000) +#define MCF_USB_PORTSC_PSPD_HIGH (0x08000000) +#define MCF_USB_PORTSC_PTC_DISBALE (0x00000000) +#define MCF_USB_PORTSC_PTC_JSTATE (0x00010000) +#define MCF_USB_PORTSC_PTC_KSTATE (0x00020000) +#define MCF_USB_PORTSC_PTC_SEQ_NAK (0x00030000) +#define MCF_USB_PORTSC_PTC_PACKET (0x00040000) +#define MCF_USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) +#define MCF_USB_PORTSC_PIC_OFF (0x00000000) +#define MCF_USB_PORTSC_PIC_AMBER (0x00004000) +#define MCF_USB_PORTSC_PIC_GREEN (0x00008000) +#define MCF_USB_PORTSC_LS_SE0 (0x00000000) +#define MCF_USB_PORTSC_LS_JSTATE (0x00000400) +#define MCF_USB_PORTSC_LS_KSTATE (0x00000800) + +/* Bit definitions and macros for MCF_USB_OTGSC */ +#define MCF_USB_OTGSC_VD (0x00000001) +#define MCF_USB_OTGSC_VC (0x00000002) +#define MCF_USB_OTGSC_OT (0x00000008) +#define MCF_USB_OTGSC_DP (0x00000010) +#define MCF_USB_OTGSC_ID (0x00000100) +#define MCF_USB_OTGSC_AVV (0x00000200) +#define MCF_USB_OTGSC_ASV (0x00000400) +#define MCF_USB_OTGSC_BSV (0x00000800) +#define MCF_USB_OTGSC_BSE (0x00001000) +#define MCF_USB_OTGSC_1MST (0x00002000) +#define MCF_USB_OTGSC_DPS (0x00004000) +#define MCF_USB_OTGSC_IDIS (0x00010000) +#define MCF_USB_OTGSC_AVVIS (0x00020000) +#define MCF_USB_OTGSC_ASVIS (0x00040000) +#define MCF_USB_OTGSC_BSVIS (0x00080000) +#define MCF_USB_OTGSC_BSEIS (0x00100000) +#define MCF_USB_OTGSC_1MSS (0x00200000) +#define MCF_USB_OTGSC_DPIS (0x00400000) +#define MCF_USB_OTGSC_IDIE (0x01000000) +#define MCF_USB_OTGSC_AVVIE (0x02000000) +#define MCF_USB_OTGSC_ASVIE (0x04000000) +#define MCF_USB_OTGSC_BSVIE (0x08000000) +#define MCF_USB_OTGSC_BSEIE (0x10000000) +#define MCF_USB_OTGSC_1MSE (0x20000000) +#define MCF_USB_OTGSC_DPIE (0x40000000) +#define MCF_USB_OTGSC_CLEAR (0x007F0000) +#define MCF_USB_OTGSC_ENABLE_ALL (0x7F000000) + +/* Bit definitions and macros for MCF_USB_USBMODE */ +#define MCF_USB_USBMODE_CM(x) (((x)&0x00000003)<<0) +#define MCF_USB_USBMODE_ES (0x00000004) +#define MCF_USB_USBMODE_SLOM (0x00000008) +#define MCF_USB_USBMODE_SDIS (0x00000010) +#define MCF_USB_USBMODE_CM_IDLE (0x00000000) +#define MCF_USB_USBMODE_CM_DEVICE (0x00000002) +#define MCF_USB_USBMODE_CM_HOST (0x00000003) + +/* Bit definitions and macros for MCF_USB_EPSETUPSR */ +#define MCF_USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for MCF_USB_EPPRIME */ +#define MCF_USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) +#define MCF_USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) +#define MCF_USB_EPPRIME_PETB0 (0x00010000) +#define MCF_USB_EPPRIME_PETB1 (0x00020000) +#define MCF_USB_EPPRIME_PETB2 (0x00040000) +#define MCF_USB_EPPRIME_PETB3 (0x00080000) +#define MCF_USB_EPPRIME_PETB4 (0x00100000) +#define MCF_USB_EPPRIME_PETB5 (0x00200000) +#define MCF_USB_EPPRIME_PERB0 (0x00000001) +#define MCF_USB_EPPRIME_PERB1 (0x00000002) +#define MCF_USB_EPPRIME_PERB2 (0x00000004) +#define MCF_USB_EPPRIME_PERB3 (0x00000008) +#define MCF_USB_EPPRIME_PERB4 (0x00000010) +#define MCF_USB_EPPRIME_PERB5 (0x00000020) + +/* Bit definitions and macros for MCF_USB_EPFLUSH */ +#define MCF_USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) +#define MCF_USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) +#define MCF_USB_EPFLUSH_FETB0 (0x00010000) +#define MCF_USB_EPFLUSH_FETB1 (0x00020000) +#define MCF_USB_EPFLUSH_FETB2 (0x00040000) +#define MCF_USB_EPFLUSH_FETB3 (0x00080000) +#define MCF_USB_EPFLUSH_FETB4 (0x00100000) +#define MCF_USB_EPFLUSH_FETB5 (0x00200000) +#define MCF_USB_EPFLUSH_FERB0 (0x00000001) +#define MCF_USB_EPFLUSH_FERB1 (0x00000002) +#define MCF_USB_EPFLUSH_FERB2 (0x00000004) +#define MCF_USB_EPFLUSH_FERB3 (0x00000008) +#define MCF_USB_EPFLUSH_FERB4 (0x00000010) +#define MCF_USB_EPFLUSH_FERB5 (0x00000020) + +/* Bit definitions and macros for MCF_USB_EPSR */ +#define MCF_USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) +#define MCF_USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) +#define MCF_USB_EPSR_ETBR0 (0x00010000) +#define MCF_USB_EPSR_ETBR1 (0x00020000) +#define MCF_USB_EPSR_ETBR2 (0x00040000) +#define MCF_USB_EPSR_ETBR3 (0x00080000) +#define MCF_USB_EPSR_ETBR4 (0x00100000) +#define MCF_USB_EPSR_ETBR5 (0x00200000) +#define MCF_USB_EPSR_ERBR0 (0x00000001) +#define MCF_USB_EPSR_ERBR1 (0x00000002) +#define MCF_USB_EPSR_ERBR2 (0x00000004) +#define MCF_USB_EPSR_ERBR3 (0x00000008) +#define MCF_USB_EPSR_ERBR4 (0x00000010) +#define MCF_USB_EPSR_ERBR5 (0x00000020) + +/* Bit definitions and macros for MCF_USB_EPCOMPLETE */ +#define MCF_USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) +#define MCF_USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) +#define MCF_USB_EPCOMPLETE_ETCE0 (0x00010000) +#define MCF_USB_EPCOMPLETE_ETCE1 (0x00020000) +#define MCF_USB_EPCOMPLETE_ETCE2 (0x00040000) +#define MCF_USB_EPCOMPLETE_ETCE3 (0x00080000) +#define MCF_USB_EPCOMPLETE_ETCE4 (0x00100000) +#define MCF_USB_EPCOMPLETE_ETCE5 (0x00200000) +#define MCF_USB_EPCOMPLETE_ERCE0 (0x00000001) +#define MCF_USB_EPCOMPLETE_ERCE1 (0x00000002) +#define MCF_USB_EPCOMPLETE_ERCE2 (0x00000004) +#define MCF_USB_EPCOMPLETE_ERCE3 (0x00000008) +#define MCF_USB_EPCOMPLETE_ERCE4 (0x00000010) +#define MCF_USB_EPCOMPLETE_ERCE5 (0x00000020) + +/* Bit definitions and macros for MCF_USB_EPCR0 */ +#define MCF_USB_EPCR0_RXS (0x00000001) +#define MCF_USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) +#define MCF_USB_EPCR0_RXE (0x00000080) +#define MCF_USB_EPCR0_TXS (0x00010000) +#define MCF_USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) +#define MCF_USB_EPCR0_TXE (0x00800000) + +/* Bit definitions and macros for MCF_USB_EPCR */ +#define MCF_USB_EPCR_RXS (0x00000001) +#define MCF_USB_EPCR_RXD (0x00000002) +#define MCF_USB_EPCR_RXT(x) (((x)&0x00000003)<<2) +#define MCF_USB_EPCR_RXI (0x00000020) +#define MCF_USB_EPCR_RXR (0x00000040) +#define MCF_USB_EPCR_RXE (0x00000080) +#define MCF_USB_EPCR_TXS (0x00010000) +#define MCF_USB_EPCR_TXD (0x00020000) +#define MCF_USB_EPCR_TXT(x) (((x)&0x00000003)<<18) +#define MCF_USB_EPCR_TXI (0x00200000) +#define MCF_USB_EPCR_TXR (0x00400000) +#define MCF_USB_EPCR_TXE (0x00800000) +#define MCF_USB_EPCR_TXT_CONTROL (0x00000000) +#define MCF_USB_EPCR_TXT_ISO (0x00040000) +#define MCF_USB_EPCR_TXT_BULK (0x00080000) +#define MCF_USB_EPCR_TXT_INT (0x000C0000) +#define MCF_USB_EPCR_RXT_CONTROL (0x00000000) +#define MCF_USB_EPCR_RXT_ISO (0x00000004) +#define MCF_USB_EPCR_RXT_BULK (0x00000008) +#define MCF_USB_EPCR_RXT_INT (0x0000000C) + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDMR (*(vuint32*)(0xFC0B8000)) +#define MCF_SDRAMC_SDCR (*(vuint32*)(0xFC0B8004)) +#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(0xFC0B8008)) +#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(0xFC0B800C)) +#define MCF_SDRAMC_SDDS (*(vuint32*)(0xFC0B8100)) +#define MCF_SDRAMC_SDCS0 (*(vuint32*)(0xFC0B8110)) +#define MCF_SDRAMC_SDCS1 (*(vuint32*)(0xFC0B8114)) +#define MCF_SDRAMC_SDCS2 (*(vuint32*)(0xFC0B8118)) +#define MCF_SDRAMC_SDCS3 (*(vuint32*)(0xFC0B811C)) +#define MCF_SDRAMC_SDCS(x) (*(vuint32*)(0xFC0B8110+((x)*0x004))) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x00010000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) +#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) +#define MCF_SDRAMC_SDCR_IREF (0x00000004) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) +#define MCF_SDRAMC_SDCR_PS_16 (0x00002000) +#define MCF_SDRAMC_SDCR_PS_32 (0x00000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SDRAMC_SDDS */ +#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) +#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) + +/* Bit definitions and macros for MCF_SDRAMC_SDCS */ +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) +#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* +* Synchronous Serial Interface (SSI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SSI_TX0 (*(vuint32*)(0xFC0BC000)) +#define MCF_SSI_TX1 (*(vuint32*)(0xFC0BC004)) +#define MCF_SSI_RX0 (*(vuint32*)(0xFC0BC008)) +#define MCF_SSI_RX1 (*(vuint32*)(0xFC0BC00C)) +#define MCF_SSI_CR (*(vuint32*)(0xFC0BC010)) +#define MCF_SSI_ISR (*(vuint32*)(0xFC0BC014)) +#define MCF_SSI_IER (*(vuint32*)(0xFC0BC018)) +#define MCF_SSI_TCR (*(vuint32*)(0xFC0BC01C)) +#define MCF_SSI_RCR (*(vuint32*)(0xFC0BC020)) +#define MCF_SSI_CCR (*(vuint32*)(0xFC0BC024)) +#define MCF_SSI_FCSR (*(vuint32*)(0xFC0BC02C)) +#define MCF_SSI_ACR (*(vuint32*)(0xFC0BC038)) +#define MCF_SSI_ACADD (*(vuint32*)(0xFC0BC03C)) +#define MCF_SSI_ACDAT (*(vuint32*)(0xFC0BC040)) +#define MCF_SSI_ATAG (*(vuint32*)(0xFC0BC044)) +#define MCF_SSI_TMASK (*(vuint32*)(0xFC0BC048)) +#define MCF_SSI_RMASK (*(vuint32*)(0xFC0BC04C)) + +/* Bit definitions and macros for MCF_SSI_TX */ +#define MCF_SSI_TX_SSI_TX(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_RX */ +#define MCF_SSI_RX_SSI_RX(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_CR */ +#define MCF_SSI_CR_SSI_EN (0x00000001) +#define MCF_SSI_CR_TE (0x00000002) +#define MCF_SSI_CR_RE (0x00000004) +#define MCF_SSI_CR_NET (0x00000008) +#define MCF_SSI_CR_SYN (0x00000010) +#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5) +#define MCF_SSI_CR_MCE (0x00000080) +#define MCF_SSI_CR_TCH (0x00000100) +#define MCF_SSI_CR_CIS (0x00000200) +#define MCF_SSI_CR_I2S_NORMAL (0x00000000) +#define MCF_SSI_CR_I2S_MASTER (0x00000020) +#define MCF_SSI_CR_I2S_SLAVE (0x00000040) + +/* Bit definitions and macros for MCF_SSI_ISR */ +#define MCF_SSI_ISR_TFE0 (0x00000001) +#define MCF_SSI_ISR_TFE1 (0x00000002) +#define MCF_SSI_ISR_RFF0 (0x00000004) +#define MCF_SSI_ISR_RFF1 (0x00000008) +#define MCF_SSI_ISR_RLS (0x00000010) +#define MCF_SSI_ISR_TLS (0x00000020) +#define MCF_SSI_ISR_RFS (0x00000040) +#define MCF_SSI_ISR_TFS (0x00000080) +#define MCF_SSI_ISR_TUE0 (0x00000100) +#define MCF_SSI_ISR_TUE1 (0x00000200) +#define MCF_SSI_ISR_ROE0 (0x00000400) +#define MCF_SSI_ISR_ROE1 (0x00000800) +#define MCF_SSI_ISR_TDE0 (0x00001000) +#define MCF_SSI_ISR_TDE1 (0x00002000) +#define MCF_SSI_ISR_RDR0 (0x00004000) +#define MCF_SSI_ISR_RDR1 (0x00008000) +#define MCF_SSI_ISR_RXT (0x00010000) +#define MCF_SSI_ISR_CMDDU (0x00020000) +#define MCF_SSI_ISR_CMDAU (0x00040000) + +/* Bit definitions and macros for MCF_SSI_IER */ +#define MCF_SSI_IER_TFE0 (0x00000001) +#define MCF_SSI_IER_TFE1 (0x00000002) +#define MCF_SSI_IER_RFF0 (0x00000004) +#define MCF_SSI_IER_RFF1 (0x00000008) +#define MCF_SSI_IER_RLS (0x00000010) +#define MCF_SSI_IER_TLS (0x00000020) +#define MCF_SSI_IER_RFS (0x00000040) +#define MCF_SSI_IER_TFS (0x00000080) +#define MCF_SSI_IER_TUE0 (0x00000100) +#define MCF_SSI_IER_TUE1 (0x00000200) +#define MCF_SSI_IER_ROE0 (0x00000400) +#define MCF_SSI_IER_ROE1 (0x00000800) +#define MCF_SSI_IER_TDE0 (0x00001000) +#define MCF_SSI_IER_TDE1 (0x00002000) +#define MCF_SSI_IER_RDR0 (0x00004000) +#define MCF_SSI_IER_RDR1 (0x00008000) +#define MCF_SSI_IER_RXT (0x00010000) +#define MCF_SSI_IER_CMDU (0x00020000) +#define MCF_SSI_IER_CMDAU (0x00040000) +#define MCF_SSI_IER_TIE (0x00080000) +#define MCF_SSI_IER_TDMAE (0x00100000) +#define MCF_SSI_IER_RIE (0x00200000) +#define MCF_SSI_IER_RDMAE (0x00400000) + +/* Bit definitions and macros for MCF_SSI_TCR */ +#define MCF_SSI_TCR_TEFS (0x00000001) +#define MCF_SSI_TCR_TFSL (0x00000002) +#define MCF_SSI_TCR_TFSI (0x00000004) +#define MCF_SSI_TCR_TSCKP (0x00000008) +#define MCF_SSI_TCR_TSHFD (0x00000010) +#define MCF_SSI_TCR_TXDIR (0x00000020) +#define MCF_SSI_TCR_TFDIR (0x00000040) +#define MCF_SSI_TCR_TFEN0 (0x00000080) +#define MCF_SSI_TCR_TFEN1 (0x00000100) +#define MCF_SSI_TCR_TXBIT0 (0x00000200) + +/* Bit definitions and macros for MCF_SSI_RCR */ +#define MCF_SSI_RCR_REFS (0x00000001) +#define MCF_SSI_RCR_RFSL (0x00000002) +#define MCF_SSI_RCR_RFSI (0x00000004) +#define MCF_SSI_RCR_RSCKP (0x00000008) +#define MCF_SSI_RCR_RSHFD (0x00000010) +#define MCF_SSI_RCR_RFEN0 (0x00000080) +#define MCF_SSI_RCR_RFEN1 (0x00000100) +#define MCF_SSI_RCR_RXBIT0 (0x00000200) +#define MCF_SSI_RCR_RXEXT (0x00000400) + +/* Bit definitions and macros for MCF_SSI_CCR */ +#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)<<0) +#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define MCF_SSI_CCR_PSR (0x00020000) +#define MCF_SSI_CCR_DIV2 (0x00040000) + +/* Bit definitions and macros for MCF_SSI_FCSR */ +#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)<<0) +#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SSI_ACR */ +#define MCF_SSI_ACR_AC97EN (0x00000001) +#define MCF_SSI_ACR_FV (0x00000002) +#define MCF_SSI_ACR_TIF (0x00000004) +#define MCF_SSI_ACR_RD (0x00000008) +#define MCF_SSI_ACR_WR (0x00000010) +#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) + +/* Bit definitions and macros for MCF_SSI_ACADD */ +#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_ACDAT */ +#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_ATAG */ +#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_TMASK */ +#define MCF_SSI_TMASK_SSI_TMASK(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SSI_RMASK */ +#define MCF_SSI_RMASK_SSI_RMASK(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* +* +* Phase Locked Loop (PLL) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PLL_PODR (*(vuint8 *)(0xFC0C0000)) +#define MCF_PLL_PLLCR (*(vuint8 *)(0xFC0C0004)) +#define MCF_PLL_PMDR (*(vuint8 *)(0xFC0C0008)) +#define MCF_PLL_PFDR (*(vuint8 *)(0xFC0C000C)) + +/* Bit definitions and macros for MCF_PLL_PODR */ +#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) +#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) + +/* Bit definitions and macros for MCF_PLL_PLLCR */ +#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) +#define MCF_PLL_PLLCR_DITHEN (0x80) + +/* Bit definitions and macros for MCF_PLL_PMDR */ +#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PLL_PFDR */ +#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) + +/********************************************************************/ + +#endif /* __MCF532X_H__ */ diff --git a/bsps/m68k/include/mcf548x/MCD_dma.h b/bsps/m68k/include/mcf548x/MCD_dma.h new file mode 100644 index 0000000000..ea6f8863cb --- /dev/null +++ b/bsps/m68k/include/mcf548x/MCD_dma.h @@ -0,0 +1,362 @@ +/* + * File: MCD_dma.h + * Purpose: Main header file for multi-channel DMA API. + * + * Notes: + */ +#ifndef _MCD_API_H +#define _MCD_API_H + +/* + * Turn Execution Unit tasks ON (#define) or OFF (#undef) + */ +#define MCD_INCLUDE_EU + +/* + * Number of DMA channels + */ +#define NCHANNELS 16 + +/* + * Total number of variants + */ +#ifdef MCD_INCLUDE_EU +#define NUMOFVARIANTS 6 +#else +#define NUMOFVARIANTS 4 +#endif + +/* + * Define sizes of the various tables + */ +#define TASK_TABLE_SIZE (NCHANNELS*32) +#define VAR_TAB_SIZE (128) +#define CONTEXT_SAVE_SIZE (128) +#define FUNCDESC_TAB_SIZE (256) + +#ifdef MCD_INCLUDE_EU +#define FUNCDESC_TAB_NUM 16 +#else +#define FUNCDESC_TAB_NUM 1 +#endif + + +#ifndef DEFINESONLY + +/* + * Portability typedefs + */ +typedef int s32; +typedef unsigned int u32; +typedef short s16; +typedef unsigned short u16; +typedef char s8; +typedef unsigned char u8; + +/* + * These structures represent the internal registers of the + * multi-channel DMA + */ +struct dmaRegs_s { + u32 taskbar; /* task table base address register */ + u32 currPtr; + u32 endPtr; + u32 varTablePtr; + u16 dma_rsvd0; + u16 ptdControl; /* ptd control */ + u32 intPending; /* interrupt pending register */ + u32 intMask; /* interrupt mask register */ + u16 taskControl[16]; /* task control registers */ + u8 priority[32]; /* priority registers */ + u32 initiatorMux; /* initiator mux control */ + u32 taskSize0; /* task size control register 0. */ + u32 taskSize1; /* task size control register 1. */ + u32 dma_rsvd1; /* reserved */ + u32 dma_rsvd2; /* reserved */ + u32 debugComp1; /* debug comparator 1 */ + u32 debugComp2; /* debug comparator 2 */ + u32 debugControl; /* debug control */ + u32 debugStatus; /* debug status */ + u32 ptdDebug; /* priority task decode debug */ + u32 dma_rsvd3[31]; /* reserved */ +}; +typedef volatile struct dmaRegs_s dmaRegs; + +#endif + +/* + * PTD contrl reg bits + */ +#define PTD_CTL_TSK_PRI 0x8000 +#define PTD_CTL_COMM_PREFETCH 0x0001 + +/* + * Task Control reg bits and field masks + */ +#define TASK_CTL_EN 0x8000 +#define TASK_CTL_VALID 0x4000 +#define TASK_CTL_ALWAYS 0x2000 +#define TASK_CTL_INIT_MASK 0x1f00 +#define TASK_CTL_ASTRT 0x0080 +#define TASK_CTL_HIPRITSKEN 0x0040 +#define TASK_CTL_HLDINITNUM 0x0020 +#define TASK_CTL_ASTSKNUM_MASK 0x000f + +/* + * Priority reg bits and field masks + */ +#define PRIORITY_HLD 0x80 +#define PRIORITY_PRI_MASK 0x07 + +/* + * Debug Control reg bits and field masks + */ +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 +#define DBG_CTL_AUTO_ARM 0x00008000 +#define DBG_CTL_BREAK 0x00004000 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070 +#define DBG_CTL_EXT_BREAK 0x00000004 +#define DBG_CTL_INT_BREAK 0x00000002 + +/* + * PTD Debug reg selector addresses + * This reg must be written with a value to show the contents of + * one of the desired internal register. + */ +#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ +#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and + have initiators asserted */ + + +/* + * General return values + */ +#define MCD_OK 0 +#define MCD_ERROR -1 +#define MCD_TABLE_UNALIGNED -2 +#define MCD_CHANNEL_INVALID -3 + +/* + * MCD_initDma input flags + */ +#define MCD_RELOC_TASKS 0x00000001 +#define MCD_NO_RELOC_TASKS 0x00000000 +#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ + +/* + * MCD_dmaStatus Status Values for each channel + */ +#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ +#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ +#define MCD_PAUSED 4 /* DMA active but it is currently paused */ +#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ +#define MCD_DONE 6 /* the most recent DMA has completed. */ + + +/* + * MCD_startDma parameter defines + */ + +/* + * Constants for the funcDesc parameter + */ +/* Byte swapping: */ +#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ +#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ +#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of + each 32-bit data value being DMAed.*/ +#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each + 16-bit half of each 32-bit data value DMAed */ +#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ +#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ +/* CRCing: */ +#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ +#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ +#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ +#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ +#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ + +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) + +/* + * Constants for the flags parameter + */ +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ +#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ +#define MCD_TT_FLAGS_MASK 0x000000ff +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) + +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ +#define MCD_CHAIN_DMA /* TBD */ +#define MCD_EU_DMA /* TBD */ +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ + + +/* these flags are valid for MCD_startDma and the chained buffer descriptors */ +#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ +#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ +#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ +#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring + last byte of data in buffer */ +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum + prior to performing the DMA. */ + +/* Defines for the FEC buffer descriptor control/status word*/ +#define MCD_FEC_BUF_READY 0x8000 +#define MCD_FEC_WRAP 0x2000 +#define MCD_FEC_INTERRUPT 0x1000 +#define MCD_FEC_END_FRAME 0x0800 + + +/* + * Defines for general intuitiveness + */ + +#define MCD_TRUE 1 +#define MCD_FALSE 0 + +/* + * Three different cases for destination and source. + */ +#define MINUS1 -1 +#define ZERO 0 +#define PLUS1 1 + +#ifndef DEFINESONLY + +/* Task Table Entry struct*/ +typedef struct { + u32 TDTstart; /* task descriptor table start */ + u32 TDTend; /* task descriptor table end */ + u32 varTab; /* variable table start */ + u32 FDTandFlags; /* function descriptor table start and flags */ + volatile u32 descAddrAndStatus; + volatile u32 modifiedVarTab; + u32 contextSaveSpace; /* context save space start */ + u32 literalBases; +} TaskTableEntry; + + +/* Chained buffer descriptor */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + u32 flags; /* flags describing the DMA */ + u32 csumResult; /* checksum from checksumming performed since last checksum reset */ + s8 *srcAddr; /* the address to move data from */ + s8 *destAddr; /* the address to move data to */ + s8 *lastDestAddr; /* the last address written to */ + u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ + MCD_bufDesc *next; /* next buffer descriptor in chain */ + u32 info; /* private information about this descriptor; DMA does not affect it */ +}; + +/* Progress Query struct */ +typedef volatile struct MCD_XferProg_struct { + s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ + s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ + u32 dmaSize; /* the amount of data transferred for the current buffer */ + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ +} MCD_XferProg; + + +/* FEC buffer descriptor */ +typedef volatile struct MCD_bufDescFec_struct { + u16 statCtrl; + u16 length; + u32 dataPointer; +} MCD_bufDescFec; + + +/*************************************************************************/ +/* + * API function Prototypes - see MCD_dmaApi.c for further notes + */ + +/* + * MCD_startDma starts a particular kind of DMA . + */ +int MCD_startDma ( + int channel, /* the channel on which to run the DMA */ + s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ + s16 srcIncr, /* the amount to increment the source address per transfer */ + s8 *destAddr, /* the address to move data to */ + s16 destIncr, /* the amount to increment the destination address per transfer */ + u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ + u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ + u32 initiator, /* what device initiates the DMA */ + int priority, /* priority of the DMA */ + u32 flags, /* flags describing the DMA */ + u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +); + +/* + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA + * registers, relocating and creating the appropriate task structures, and + * setting up some global settings + */ +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); + +/* + * MCD_dmaStatus() returns the status of the DMA on the requested channel. + */ +int MCD_dmaStatus (int channel); + +/* + * MCD_XferProgrQuery() returns progress of DMA on requested channel + */ +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); + +/* + * MCD_killDma() halts the DMA on the requested channel, without any + * intention of resuming the DMA. + */ +int MCD_killDma (int channel); + +/* + * MCD_continDma() continues a DMA which as stopped due to encountering an + * unready buffer descriptor. + */ +int MCD_continDma (int channel); + +/* + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is + * running on that channel). + */ +int MCD_pauseDma (int channel); + +/* + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is + * running on that channel). + */ +int MCD_resumeDma (int channel); + +/* + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA + */ +int MCD_csumQuery (int channel, u32 *csum); + +/* + * MCD_getCodeSize provides the packed size required by the microcoded task + * and structures. + */ +int MCD_getCodeSize(void); + +/* + * MCD_getVersion provides a pointer to a version string and returns a + * version number. + */ +int MCD_getVersion(char **longVersion); + +/* macro for setting a location in the variable table */ +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, + so I'm avoiding surrounding it with "do {} while(0)" */ + +#endif /* DEFINESONLY */ + +#endif /* _MCD_API_H */ diff --git a/bsps/m68k/include/mcf548x/MCD_progCheck.h b/bsps/m68k/include/mcf548x/MCD_progCheck.h new file mode 100644 index 0000000000..e0f578fdaf --- /dev/null +++ b/bsps/m68k/include/mcf548x/MCD_progCheck.h @@ -0,0 +1,5 @@ + /* This file is autogenerated. Do not change */ +#define CURRBD 4 +#define DCOUNT 6 +#define DESTPTR 5 +#define SRCPTR 7 diff --git a/bsps/m68k/include/mcf548x/MCD_tasksInit.h b/bsps/m68k/include/mcf548x/MCD_tasksInit.h new file mode 100644 index 0000000000..daf871cd6d --- /dev/null +++ b/bsps/m68k/include/mcf548x/MCD_tasksInit.h @@ -0,0 +1,44 @@ +#ifndef MCD_TSK_INIT_H +#define MCD_TSK_INIT_H 1 + +/* + * Do not edit! + */ + + +/* + * Task 0 + */ +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 1 + */ +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 2 + */ +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 3 + */ +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 4 + */ +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 5 + */ +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); + +#endif /* MCD_TSK_INIT_H */ diff --git a/bsps/m68k/include/mcf548x/mcdma_glue.h b/bsps/m68k/include/mcf548x/mcdma_glue.h new file mode 100644 index 0000000000..de0621120f --- /dev/null +++ b/bsps/m68k/include/mcf548x/mcdma_glue.h @@ -0,0 +1,106 @@ +/*===============================================================*\ +| Project: RTEMS generic MFC548x BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2004-2009 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares glue functions to the Freescale Mcdma API | +\*===============================================================*/ +#ifndef _MCDMA_GLUE_H +#define _MCDMA_GLUE_H + +#include <rtems.h> +#include <mcf548x/mcf548x.h> + +#define MCDMA_CLR_PENDING(chan) (MCF548X_DMA_DIPR = (1 << (chan))) +#define MCDMA_GET_PENDING(chan) (MCF548X_DMA_DIPR & (1 << (chan))) + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_enable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| enable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno /* task number to enable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_disable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| disable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno /* task number to disable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_irq_install +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| install given function as mcdma interrupt handler | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int mcdma_taskno, /* task number for handler */ + void (*the_handler)(rtems_irq_hdl_param), /* function to call */ + void *the_param + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void mcdma_glue_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the mcdma module (if not yet done): | +| - load code | +| - initialize registers | +| - initialize bus arbiter | +| - initialize interrupt control | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + void *sram_base /* base address for SRAM, to be used for DMA task */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +#endif /* _MCDMA_GLUE_H */ diff --git a/bsps/m68k/include/mcf548x/mcf548x.h b/bsps/m68k/include/mcf548x/mcf548x.h new file mode 100644 index 0000000000..7a9dc73698 --- /dev/null +++ b/bsps/m68k/include/mcf548x/mcf548x.h @@ -0,0 +1,4056 @@ +/*===============================================================*\ +| Project: RTEMS generic mcf548x BSP | ++-----------------------------------------------------------------+ +| File: mcf548x.h | ++-----------------------------------------------------------------+ +| The file contains all register an bit definitions of the | +| generic MCF548x BSP. | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| | +| Parts of the code has been derived from the "dBUG source code" | +| package Freescale is providing for M548X EVBs. The usage of | +| the modified or unmodified code and it's integration into the | +| generic mcf548x BSP has been done according to the Freescale | +| license terms. | +| | +| The Freescale license terms can be reviewed in the file | +| | +| Freescale_license.txt | +| | ++-----------------------------------------------------------------+ +| | +| The generic mcf548x BSP has been developed on the basic | +| structures and modules of the av5282 BSP. | +| | ++-----------------------------------------------------------------+ +| | +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| | +| date history ID | +| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | +| 12.11.07 1.0 ras | +| | +\*===============================================================*/ + +#ifndef __MCF548X_H__ +#define __MCF548X_H__ + +#include <stdint.h> + +/*********************************************************************/ +extern char __MBAR[]; + +/********************************************************************* +* +* Cache Control Register (CACR) +* +*********************************************************************/ + +/* Bit definitions and macros for MCF548X_CACR */ +#define MCF548X_CACR_DEC (0x80000000) +#define MCF548X_CACR_DW (0x40000000) +#define MCF548X_CACR_DESB (0x20000000) +#define MCF548X_CACR_DDPI (0x10000000) +#define MCF548X_CACR_DHLCK (0x08000000) +#define MCF548X_CACR_DDCM(x) (((x)<<25)&0x06000000) +#define MCF548X_CACR_DCINVA (0x01000000) +#define MCF548X_CACR_DDSP (0x00800000) +#define MCF548X_CACR_BEC (0x00080000) +#define MCF548X_CACR_BCINVA (0x00040000) +#define MCF548X_CACR_IEC (0x00008000) +#define MCF548X_CACR_DNFB (0x00002000) +#define MCF548X_CACR_IDPI (0x00001000) +#define MCF548X_CACR_IHLCK (0x00000800) +#define MCF548X_CACR_IDCM (0x00000400) +#define MCF548X_CACR_ICINVA (0x00000100) +#define MCF548X_CACR_IDSP (0x00000080) +#define MCF548X_CACR_EUSP (0x00000020) +#define MCF548X_CACR_DF (0x00000010) + +/* Bit definitions and macros for MCF548X_CACR_DDCM (data cache mode) */ +#define DCACHE_ON_WRIGHTTHROUGH 0 +#define DCACHE_ON_COPYBACK 1 +#define DCACHE_OFF_PRECISE 2 +#define DCACHE_OFF_IMPRECISE 3 + +/********************************************************************* +* +* Access Control Registers (ACR0-3) +* +*********************************************************************/ + +/* Bit definitions and macros for MCF548X_ACRn */ +#define MCF548X_ACR_BA(x) ((x)&0xFF000000) +#define MCF548X_ACR_ADMSK_AMM(x) (((x)>=0x1000000) ? (((x)&0xFF000000)>>8) : (((x)&0x00FF0000)|0x00000400)) +#define MCF548X_ACR_E (0x00008000) +#define MCF548X_ACR_S(x) (((x)<<13)&0x00006000) +#define MCF548X_ACR_CM(x) (((x)<<5)&0x00000060) +#define MCF548X_ACR_SP (0x00000008) +#define MCF548X_ACR_W (0x00000004) + +/* Bit definitions and macros for MCF548X_ACR_S (supervisor/user access) */ +#define S_ACCESS_USER 0 +#define S_ACCESS_SUPV 1 +#define S_ACCESS_BOTH 2 + +/* Bit definitions and macros for MCF548X_ACR_CM (cache mode) */ +#define CM_ON_WRIGHTTHROUGH 0 +#define CM_ON_COPYBACK 1 +#define CM_OFF_PRECISE 2 +#define CM_OFF_IMPRECISE 3 + +/********************************************************************* +* +* System PLL Control Register (SPCR) +* +*********************************************************************/ + +/* Register read/write macro */ +#define MCF548X_PLL_SPCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000300))) + +/* Bit definitions and macros for MCF548X_PLL_SPCR (supervisor/user access) */ +#define MCF548X_PLL_SPCR_PLLK 0x80000000 +#define MCF548X_PLL_SPCR_COREN 0x00004000 +#define MCF548X_PLL_SPCR_CRYENB 0x00002000 +#define MCF548X_PLL_SPCR_CRYENA 0x00001000 +#define MCF548X_PLL_SPCR_CAN1EN 0x00000800 +#define MCF548X_PLL_SPCR_PSCEN 0x00000200 +#define MCF548X_PLL_SPCR_USBEN 0x00000080 +#define MCF548X_PLL_SPCR_FEC1EN 0x00000040 +#define MCF548X_PLL_SPCR_FEC0EN 0x00000020 +#define MCF548X_PLL_SPCR_DMAEN 0x00000010 +#define MCF548X_PLL_SPCR_CAN0EN 0x00000008 +#define MCF548X_PLL_SPCR_FBEN 0x00000004 +#define MCF548X_PLL_SPCR_PCIEN 0x00000002 +#define MCF548X_PLL_SPCR_MEMEN 0x00000001 + +/********************************************************************* +* +* XLB Arbiter Control (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_XLB_CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000240))) +#define MCF548X_XLB_ADRTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000258))) +#define MCF548X_XLB_DATTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00025C))) +#define MCF548X_XLB_BUSTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000260))) + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_FEC_EIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004))) +#define MCF548X_FEC_EIMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008))) +#define MCF548X_FEC_ECR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024))) +#define MCF548X_FEC_MMFR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040))) +#define MCF548X_FEC_MSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044))) +#define MCF548X_FEC_MIBC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064))) +#define MCF548X_FEC_RCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084))) +#define MCF548X_FEC_R_HASH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088))) +#define MCF548X_FEC_TCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4))) +#define MCF548X_FEC_PALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4))) +#define MCF548X_FEC_PAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8))) +#define MCF548X_FEC_OPD0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090EC))) +#define MCF548X_FEC_IAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118))) +#define MCF548X_FEC_IALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911C))) +#define MCF548X_FEC_GAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120))) +#define MCF548X_FEC_GALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124))) +#define MCF548X_FEC_FECTFWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144))) +#define MCF548X_FEC_FECRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184))) +#define MCF548X_FEC_FECRFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188))) +#define MCF548X_FEC_FECRFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918C))) +#define MCF548X_FEC_FECRLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190))) +#define MCF548X_FEC_FECRLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194))) +#define MCF548X_FEC_FECRFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198))) +#define MCF548X_FEC_FECRFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919C))) +#define MCF548X_FEC_FECRFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0))) +#define MCF548X_FEC_FECTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4))) +#define MCF548X_FEC_FECTFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8))) +#define MCF548X_FEC_FECTFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091AC))) +#define MCF548X_FEC_FECTLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0))) +#define MCF548X_FEC_FECTLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4))) +#define MCF548X_FEC_FECTFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8))) +#define MCF548X_FEC_FECTFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BC))) +#define MCF548X_FEC_FECTFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0))) +#define MCF548X_FEC_FRST0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4))) +#define MCF548X_FEC_CTCWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8))) +#define MCF548X_FEC_RMON_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200))) +#define MCF548X_FEC_RMON_T_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204))) +#define MCF548X_FEC_RMON_T_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208))) +#define MCF548X_FEC_RMON_T_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920C))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210))) +#define MCF548X_FEC_RMON_T_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214))) +#define MCF548X_FEC_RMON_T_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218))) +#define MCF548X_FEC_RMON_T_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921C))) +#define MCF548X_FEC_RMON_T_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220))) +#define MCF548X_FEC_RMON_T_COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224))) +#define MCF548X_FEC_RMON_T_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228))) +#define MCF548X_FEC_RMON_T_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922C))) +#define MCF548X_FEC_RMON_T_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230))) +#define MCF548X_FEC_RMON_T_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234))) +#define MCF548X_FEC_RMON_T_P512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238))) +#define MCF548X_FEC_RMON_T_P1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923C))) +#define MCF548X_FEC_RMON_T_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240))) +#define MCF548X_FEC_RMON_T_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244))) +#define MCF548X_FEC_IEEE_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248))) +#define MCF548X_FEC_IEEE_T_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924C))) +#define MCF548X_FEC_IEEE_T_1COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250))) +#define MCF548X_FEC_IEEE_T_MCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254))) +#define MCF548X_FEC_IEEE_T_DEF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258))) +#define MCF548X_FEC_IEEE_T_LCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925C))) +#define MCF548X_FEC_IEEE_T_EXCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260))) +#define MCF548X_FEC_IEEE_T_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264))) +#define MCF548X_FEC_IEEE_T_CSERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268))) +#define MCF548X_FEC_IEEE_T_SQE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926C))) +#define MCF548X_FEC_IEEE_T_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274))) +#define MCF548X_FEC_RMON_R_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284))) +#define MCF548X_FEC_RMON_R_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288))) +#define MCF548X_FEC_RMON_R_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928C))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290))) +#define MCF548X_FEC_RMON_R_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294))) +#define MCF548X_FEC_RMON_R_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298))) +#define MCF548X_FEC_RMON_R_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929C))) +#define MCF548X_FEC_RMON_R_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0))) +#define MCF548X_FEC_RMON_R_RESVD_00 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4))) +#define MCF548X_FEC_RMON_R_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8))) +#define MCF548X_FEC_RMON_R_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092AC))) +#define MCF548X_FEC_RMON_R_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0))) +#define MCF548X_FEC_RMON_R_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4))) +#define MCF548X_FEC_RMON_R_512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8))) +#define MCF548X_FEC_RMON_R_1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BC))) +#define MCF548X_FEC_RMON_R_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0))) +#define MCF548X_FEC_RMON_R_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4))) +#define MCF548X_FEC_IEEE_R_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8))) +#define MCF548X_FEC_IEEE_R_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CC))) +#define MCF548X_FEC_IEEE_R_CRC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0))) +#define MCF548X_FEC_IEEE_R_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4))) +#define MCF548X_FEC_IEEE_R_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8))) +#define MCF548X_FEC_IEEE_R_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DC))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0))) +#define MCF548X_FEC_EIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009804))) +#define MCF548X_FEC_EIMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009808))) +#define MCF548X_FEC_ECR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009824))) +#define MCF548X_FEC_MMFR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009840))) +#define MCF548X_FEC_MSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009844))) +#define MCF548X_FEC_MIBC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009864))) +#define MCF548X_FEC_RCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009884))) +#define MCF548X_FEC_R_HASH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009888))) +#define MCF548X_FEC_TCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098C4))) +#define MCF548X_FEC_PALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E4))) +#define MCF548X_FEC_PAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E8))) +#define MCF548X_FEC_OPD1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098EC))) +#define MCF548X_FEC_IAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009918))) +#define MCF548X_FEC_IALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00991C))) +#define MCF548X_FEC_GAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009920))) +#define MCF548X_FEC_GALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009924))) +#define MCF548X_FEC_FECTFWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009944))) +#define MCF548X_FEC_FECRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009984))) +#define MCF548X_FEC_FECRFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009988))) +#define MCF548X_FEC_FECRFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00998C))) +#define MCF548X_FEC_FECRLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009990))) +#define MCF548X_FEC_FECRLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009994))) +#define MCF548X_FEC_FECRFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009998))) +#define MCF548X_FEC_FECRFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00999C))) +#define MCF548X_FEC_FECRFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A0))) +#define MCF548X_FEC_FECTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A4))) +#define MCF548X_FEC_FECTFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A8))) +#define MCF548X_FEC_FECTFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099AC))) +#define MCF548X_FEC_FECTLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B0))) +#define MCF548X_FEC_FECTLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B4))) +#define MCF548X_FEC_FECTFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B8))) +#define MCF548X_FEC_FECTFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099BC))) +#define MCF548X_FEC_FECTFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C0))) +#define MCF548X_FEC_FRST1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C4))) +#define MCF548X_FEC_CTCWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C8))) +#define MCF548X_FEC_RMON_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A00))) +#define MCF548X_FEC_RMON_T_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A04))) +#define MCF548X_FEC_RMON_T_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A08))) +#define MCF548X_FEC_RMON_T_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A0C))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A10))) +#define MCF548X_FEC_RMON_T_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A14))) +#define MCF548X_FEC_RMON_T_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A18))) +#define MCF548X_FEC_RMON_T_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A1C))) +#define MCF548X_FEC_RMON_T_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A20))) +#define MCF548X_FEC_RMON_T_COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A24))) +#define MCF548X_FEC_RMON_T_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A28))) +#define MCF548X_FEC_RMON_T_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A2C))) +#define MCF548X_FEC_RMON_T_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A30))) +#define MCF548X_FEC_RMON_T_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A34))) +#define MCF548X_FEC_RMON_T_P512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A38))) +#define MCF548X_FEC_RMON_T_P1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A3C))) +#define MCF548X_FEC_RMON_T_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A40))) +#define MCF548X_FEC_RMON_T_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A44))) +#define MCF548X_FEC_IEEE_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A48))) +#define MCF548X_FEC_IEEE_T_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A4C))) +#define MCF548X_FEC_IEEE_T_1COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A50))) +#define MCF548X_FEC_IEEE_T_MCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A54))) +#define MCF548X_FEC_IEEE_T_DEF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A58))) +#define MCF548X_FEC_IEEE_T_LCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A5C))) +#define MCF548X_FEC_IEEE_T_EXCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A60))) +#define MCF548X_FEC_IEEE_T_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A64))) +#define MCF548X_FEC_IEEE_T_CSERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A68))) +#define MCF548X_FEC_IEEE_T_SQE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A6C))) +#define MCF548X_FEC_IEEE_T_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A70))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A74))) +#define MCF548X_FEC_RMON_R_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A84))) +#define MCF548X_FEC_RMON_R_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A88))) +#define MCF548X_FEC_RMON_R_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A8C))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A90))) +#define MCF548X_FEC_RMON_R_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A94))) +#define MCF548X_FEC_RMON_R_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A98))) +#define MCF548X_FEC_RMON_R_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A9C))) +#define MCF548X_FEC_RMON_R_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA0))) +#define MCF548X_FEC_RMON_R_RESVD_01 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA4))) +#define MCF548X_FEC_RMON_R_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA8))) +#define MCF548X_FEC_RMON_R_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AAC))) +#define MCF548X_FEC_RMON_R_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB0))) +#define MCF548X_FEC_RMON_R_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB4))) +#define MCF548X_FEC_RMON_R_512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB8))) +#define MCF548X_FEC_RMON_R_1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ABC))) +#define MCF548X_FEC_RMON_R_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC0))) +#define MCF548X_FEC_RMON_R_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC4))) +#define MCF548X_FEC_IEEE_R_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC8))) +#define MCF548X_FEC_IEEE_R_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ACC))) +#define MCF548X_FEC_IEEE_R_CRC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD0))) +#define MCF548X_FEC_IEEE_R_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD4))) +#define MCF548X_FEC_IEEE_R_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD8))) +#define MCF548X_FEC_IEEE_R_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ADC))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AE0))) +#define MCF548X_FEC_EIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004U+((x)*0x800)))) +#define MCF548X_FEC_EIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008U+((x)*0x800)))) +#define MCF548X_FEC_ECR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024U+((x)*0x800)))) +#define MCF548X_FEC_MMFR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040U+((x)*0x800)))) +#define MCF548X_FEC_MSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044U+((x)*0x800)))) +#define MCF548X_FEC_MIBC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064U+((x)*0x800)))) +#define MCF548X_FEC_RCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084U+((x)*0x800)))) +#define MCF548X_FEC_R_HASH(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088U+((x)*0x800)))) +#define MCF548X_FEC_TCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4U+((x)*0x800)))) +#define MCF548X_FEC_PALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4U+((x)*0x800)))) +#define MCF548X_FEC_PAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8U+((x)*0x800)))) +#define MCF548X_FEC_OPD(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090ECU+((x)*0x800)))) +#define MCF548X_FEC_IAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118U+((x)*0x800)))) +#define MCF548X_FEC_IALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911CU+((x)*0x800)))) +#define MCF548X_FEC_GAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120U+((x)*0x800)))) +#define MCF548X_FEC_GALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124U+((x)*0x800)))) +#define MCF548X_FEC_FECTFWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144U+((x)*0x800)))) +#define MCF548X_FEC_FECRFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184U+((x)*0x800)))) +#define MCF548X_FEC_FECRFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188U+((x)*0x800)))) +#define MCF548X_FEC_FECRFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918CU+((x)*0x800)))) +#define MCF548X_FEC_FECRLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190U+((x)*0x800)))) +#define MCF548X_FEC_FECRLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194U+((x)*0x800)))) +#define MCF548X_FEC_FECRFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198U+((x)*0x800)))) +#define MCF548X_FEC_FECRFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919CU+((x)*0x800)))) +#define MCF548X_FEC_FECRFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0U+((x)*0x800)))) +#define MCF548X_FEC_FECTFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4U+((x)*0x800)))) +#define MCF548X_FEC_FECTFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8U+((x)*0x800)))) +#define MCF548X_FEC_FECTFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091ACU+((x)*0x800)))) +#define MCF548X_FEC_FECTLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0U+((x)*0x800)))) +#define MCF548X_FEC_FECTLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4U+((x)*0x800)))) +#define MCF548X_FEC_FECTFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8U+((x)*0x800)))) +#define MCF548X_FEC_FECTFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BCU+((x)*0x800)))) +#define MCF548X_FEC_FECTFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0U+((x)*0x800)))) +#define MCF548X_FEC_FRST(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4U+((x)*0x800)))) +#define MCF548X_FEC_CTCWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240U+((x)*0x800)))) +#define MCF548X_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926CU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929CU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092ACU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BCU+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0U+((x)*0x800)))) +#define MCF548X_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CCU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8U+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DCU+((x)*0x800)))) +#define MCF548X_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0U+((x)*0x800)))) + +/* Bit definitions and macros for MCF548X_FEC_EIR */ +#define MCF548X_FEC_EIR_RFERR (0x00020000) +#define MCF548X_FEC_EIR_XFERR (0x00040000) +#define MCF548X_FEC_EIR_XFUN (0x00080000) +#define MCF548X_FEC_EIR_RL (0x00100000) +#define MCF548X_FEC_EIR_LC (0x00200000) +#define MCF548X_FEC_EIR_MII (0x00800000) +#define MCF548X_FEC_EIR_TXF (0x08000000) +#define MCF548X_FEC_EIR_GRA (0x10000000) +#define MCF548X_FEC_EIR_BABT (0x20000000) +#define MCF548X_FEC_EIR_BABR (0x40000000) +#define MCF548X_FEC_EIR_HBERR (0x80000000) +#define MCF548X_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF548X_FEC_EIMR */ +#define MCF548X_FEC_EIMR_RFERR (0x00020000) +#define MCF548X_FEC_EIMR_XFERR (0x00040000) +#define MCF548X_FEC_EIMR_XFUN (0x00080000) +#define MCF548X_FEC_EIMR_RL (0x00100000) +#define MCF548X_FEC_EIMR_LC (0x00200000) +#define MCF548X_FEC_EIMR_MII (0x00800000) +#define MCF548X_FEC_EIMR_TXF (0x08000000) +#define MCF548X_FEC_EIMR_GRA (0x10000000) +#define MCF548X_FEC_EIMR_BABT (0x20000000) +#define MCF548X_FEC_EIMR_BABR (0x40000000) +#define MCF548X_FEC_EIMR_HBERR (0x80000000) +#define MCF548X_FEC_EIMR_MASK_ALL (0x00000000) +#define MCF548X_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF548X_FEC_ECR */ +#define MCF548X_FEC_ECR_RESET (0x00000001) +#define MCF548X_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF548X_FEC_MMFR */ +#define MCF548X_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF548X_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF548X_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF548X_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF548X_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF548X_FEC_MMFR_ST_01 (0x40000000) +#define MCF548X_FEC_MMFR_OP_READ (0x20000000) +#define MCF548X_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF548X_FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for MCF548X_FEC_MSCR */ +#define MCF548X_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF548X_FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define MCF548X_FEC_MSCR_MII_SPEED_133 (0x1B<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_120 (0x18<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_66 (0xE<<1) +#define MCF548X_FEC_MSCR_MII_SPEED_60 (0xC<<1) + +/* Bit definitions and macros for MCF548X_FEC_MIBC */ +#define MCF548X_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF548X_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_RCR */ +#define MCF548X_FEC_RCR_LOOP (0x00000001) +#define MCF548X_FEC_RCR_DRT (0x00000002) +#define MCF548X_FEC_RCR_MII_MODE (0x00000004) +#define MCF548X_FEC_RCR_PROM (0x00000008) +#define MCF548X_FEC_RCR_BC_REJ (0x00000010) +#define MCF548X_FEC_RCR_FCE (0x00000020) +#define MCF548X_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_R_HASH */ +#define MCF548X_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) +#define MCF548X_FEC_R_HASH_MULTCAST (0x40000000) +#define MCF548X_FEC_R_HASH_FCE_DC (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_TCR */ +#define MCF548X_FEC_TCR_GTS (0x00000001) +#define MCF548X_FEC_TCR_HBC (0x00000002) +#define MCF548X_FEC_TCR_FDEN (0x00000004) +#define MCF548X_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF548X_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF548X_FEC_PAUR */ +#define MCF548X_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_OPD */ +#define MCF548X_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_FEC_FECTFWR */ +#define MCF548X_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) +#define MCF548X_FEC_FECTFWR_X_WMRK_64 (0x00000000) +#define MCF548X_FEC_FECTFWR_X_WMRK_128 (0x00000001) +#define MCF548X_FEC_FECTFWR_X_WMRK_192 (0x00000002) +#define MCF548X_FEC_FECTFWR_X_WMRK_256 (0x00000003) +#define MCF548X_FEC_FECTFWR_X_WMRK_320 (0x00000004) +#define MCF548X_FEC_FECTFWR_X_WMRK_384 (0x00000005) +#define MCF548X_FEC_FECTFWR_X_WMRK_448 (0x00000006) +#define MCF548X_FEC_FECTFWR_X_WMRK_512 (0x00000007) +#define MCF548X_FEC_FECTFWR_X_WMRK_576 (0x00000008) +#define MCF548X_FEC_FECTFWR_X_WMRK_640 (0x00000009) +#define MCF548X_FEC_FECTFWR_X_WMRK_704 (0x0000000A) +#define MCF548X_FEC_FECTFWR_X_WMRK_768 (0x0000000B) +#define MCF548X_FEC_FECTFWR_X_WMRK_832 (0x0000000C) +#define MCF548X_FEC_FECTFWR_X_WMRK_896 (0x0000000D) +#define MCF548X_FEC_FECTFWR_X_WMRK_960 (0x0000000E) +#define MCF548X_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) + +/* Bit definitions and macros for MCF548X_FEC_FECRFDR */ +#define MCF548X_FEC_FECRFDR_ADDR0 (((uintptr_t)__MBAR + (0x009184))) +#define MCF548X_FEC_FECRFDR_ADDR1 (((uintptr_t)__MBAR + (0x009984))) +#define MCF548X_FEC_FECRFDR_ADDR(x) (((uintptr_t)__MBAR + (0x009184U+(0x800*x)))) + +/* Bit definitions and macros for MCF548X_FEC_FECRFSR */ +#define MCF548X_FEC_FECRFSR_EMT (0x00010000) +#define MCF548X_FEC_FECRFSR_ALARM (0x00020000) +#define MCF548X_FEC_FECRFSR_FU (0x00040000) +#define MCF548X_FEC_FECRFSR_FR (0x00080000) +#define MCF548X_FEC_FECRFSR_OF (0x00100000) +#define MCF548X_FEC_FECRFSR_UF (0x00200000) +#define MCF548X_FEC_FECRFSR_RXW (0x00400000) +#define MCF548X_FEC_FECRFSR_FAE (0x00800000) +#define MCF548X_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_FECRFCR */ +#define MCF548X_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_FEC_FECRFCR_OF_MSK (0x00080000) +#define MCF548X_FEC_FECRFCR_UF_MSK (0x00100000) +#define MCF548X_FEC_FECRFCR_RXW_MSK (0x00200000) +#define MCF548X_FEC_FECRFCR_FAE_MSK (0x00400000) +#define MCF548X_FEC_FECRFCR_IP_MSK (0x00800000) +#define MCF548X_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_FEC_FECRFCR_FRM (0x08000000) +#define MCF548X_FEC_FECRFCR_TIMER (0x10000000) +#define MCF548X_FEC_FECRFCR_WFR (0x20000000) +#define MCF548X_FEC_FECRFCR_WCTL (0x40000000) + +/* Bit definitions and macros for MCF548X_FEC_FECRLRFP */ +#define MCF548X_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRLWFP */ +#define MCF548X_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFAR */ +#define MCF548X_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFRP */ +#define MCF548X_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECRFWP */ +#define MCF548X_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFDR */ +#define MCF548X_FEC_FECTFDR_TFCW_TC (0x04000000) +#define MCF548X_FEC_FECTFDR_TFCW_ABC (0x02000000) +#define MCF548X_FEC_FECTFDR_ADDR0 (((uintptr_t)__MBAR + (0x0091A4))) +#define MCF548X_FEC_FECTFDR_ADDR1 (((uintptr_t)__MBAR + (0x0099A4))) +#define MCF548X_FEC_FECTFDR_ADDR(x) (((uintptr_t)__MBAR + (0x0091A4U+(0x800*x)))) + +/* Bit definitions and macros for MCF548X_FEC_FECTFSR */ +#define MCF548X_FEC_FECTFSR_EMT (0x00010000) +#define MCF548X_FEC_FECTFSR_ALARM (0x00020000) +#define MCF548X_FEC_FECTFSR_FU (0x00040000) +#define MCF548X_FEC_FECTFSR_FR (0x00080000) +#define MCF548X_FEC_FECTFSR_OF (0x00100000) +#define MCF548X_FEC_FECTFSR_UP (0x00200000) +#define MCF548X_FEC_FECTFSR_FAE (0x00800000) +#define MCF548X_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_FEC_FECTFSR_TXW (0x40000000) +#define MCF548X_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_FEC_FECTFCR */ +#define MCF548X_FEC_FECTFCR_RESERVED (0x00200000) +#define MCF548X_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) +#define MCF548X_FEC_FECTFCR_TXW_MSK (0x00240000) +#define MCF548X_FEC_FECTFCR_OF_MSK (0x00280000) +#define MCF548X_FEC_FECTFCR_UF_MSK (0x00300000) +#define MCF548X_FEC_FECTFCR_FAE_MSK (0x00600000) +#define MCF548X_FEC_FECTFCR_IP_MSK (0x00A00000) +#define MCF548X_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) +#define MCF548X_FEC_FECTFCR_FRM (0x08200000) +#define MCF548X_FEC_FECTFCR_TIMER (0x10200000) +#define MCF548X_FEC_FECTFCR_WFR (0x20200000) +#define MCF548X_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF548X_FEC_FECTLRFP */ +#define MCF548X_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTLWFP */ +#define MCF548X_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFAR */ +#define MCF548X_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFRP */ +#define MCF548X_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FECTFWP */ +#define MCF548X_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_FEC_FRST */ +#define MCF548X_FEC_FRST_RST_CTL (0x01000000) +#define MCF548X_FEC_FRST_SW_RST (0x02000000) + +/* Bit definitions and macros for MCF548X_FEC_CTCWR */ +#define MCF548X_FEC_CTCWR_TFCW (0x01000000) +#define MCF548X_FEC_CTCWR_CRC (0x02000000) + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SIU_SBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000010))) +#define MCF548X_SIU_SECSACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000038))) +#define MCF548X_SIU_RSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000044))) +#define MCF548X_SIU_JTAGID (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000050))) + +/* Bit definitions and macros for MCF548X_SIU_SBCR */ +#define MCF548X_SIU_SBCR_PIN2DSPI (0x08000000) +#define MCF548X_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF548X_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF548X_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF548X_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF548X_SIU_SECSACR */ +#define MCF548X_SIU_SECSACR_SEQEN (0x00000001) + +/* Bit definitions and macros for MCF548X_SIU_RSR */ +#define MCF548X_SIU_RSR_RST (0x00000001) +#define MCF548X_SIU_RSR_RSTWD (0x00000002) +#define MCF548X_SIU_RSR_RSTJTG (0x00000008) + +/* Bit definitions and macros for MCF548X_SIU_JTAGID */ +#define MCF548X_SIU_JTAGID_REV (0xF0000000) +#define MCF548X_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF548X_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF548X_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF548X_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF548X_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF548X_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF548X_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF548X_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF548X_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF548X_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF548X_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF548X_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF548X_SIU_JTAGID_MCF5470 (0x0801701D) + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_CTM_CTCRF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00))) +#define MCF548X_CTM_CTCRF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F04))) +#define MCF548X_CTM_CTCRF2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F08))) +#define MCF548X_CTM_CTCRF3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F0C))) +#define MCF548X_CTM_CTCRFn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00U+((x)*0x004)))) +#define MCF548X_CTM_CTCRV4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10))) +#define MCF548X_CTM_CTCRV5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F14))) +#define MCF548X_CTM_CTCRV6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F18))) +#define MCF548X_CTM_CTCRV7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F1C))) +#define MCF548X_CTM_CTCRVn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10U+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_CTM_CTCRFn */ +#define MCF548X_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) +#define MCF548X_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) +#define MCF548X_CTM_CTCRFn_M (0x00800000) +#define MCF548X_CTM_CTCRFn_IM (0x01000000) +#define MCF548X_CTM_CTCRFn_I (0x80000000) +#define MCF548X_CTM_CTCRFn_PCT_100 (0x00000000) +#define MCF548X_CTM_CTCRFn_PCT_50 (0x00100000) +#define MCF548X_CTM_CTCRFn_PCT_25 (0x00200000) +#define MCF548X_CTM_CTCRFn_PCT_12p5 (0x00300000) +#define MCF548X_CTM_CTCRFn_PCT_6p25 (0x00400000) +#define MCF548X_CTM_CTCRFn_PCT_OFF (0x00500000) +#define MCF548X_CTM_CTCRFn_S_CLK_1 (0x00000000) +#define MCF548X_CTM_CTCRFn_S_CLK_2 (0x00010000) +#define MCF548X_CTM_CTCRFn_S_CLK_4 (0x00020000) +#define MCF548X_CTM_CTCRFn_S_CLK_8 (0x00030000) +#define MCF548X_CTM_CTCRFn_S_CLK_16 (0x00040000) +#define MCF548X_CTM_CTCRFn_S_CLK_32 (0x00050000) +#define MCF548X_CTM_CTCRFn_S_CLK_64 (0x00060000) +#define MCF548X_CTM_CTCRFn_S_CLK_128 (0x00070000) +#define MCF548X_CTM_CTCRFn_S_CLK_256 (0x00080000) + +/* Bit definitions and macros for MCF548X_CTM_CTCRVn */ +#define MCF548X_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) +#define MCF548X_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) +#define MCF548X_CTM_CTCRVn_M (0x08000000) +#define MCF548X_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) +#define MCF548X_CTM_CTCRVn_S_CLK_1 (0x00000000) +#define MCF548X_CTM_CTCRVn_S_CLK_2 (0x10000000) +#define MCF548X_CTM_CTCRVn_S_CLK_4 (0x20000000) +#define MCF548X_CTM_CTCRVn_S_CLK_8 (0x30000000) +#define MCF548X_CTM_CTCRVn_S_CLK_16 (0x40000000) +#define MCF548X_CTM_CTCRVn_S_CLK_32 (0x50000000) +#define MCF548X_CTM_CTCRVn_S_CLK_64 (0x60000000) +#define MCF548X_CTM_CTCRVn_S_CLK_128 (0x70000000) +#define MCF548X_CTM_CTCRVn_S_CLK_256 (0x80000000) +#define MCF548X_CTM_CTCRVn_PCT_100 (0x00000000) +#define MCF548X_CTM_CTCRVn_PCT_50 (0x01000000) +#define MCF548X_CTM_CTCRVn_PCT_25 (0x02000000) +#define MCF548X_CTM_CTCRVn_PCT_12p5 (0x03000000) +#define MCF548X_CTM_CTCRVn_PCT_6p25 (0x04000000) +#define MCF548X_CTM_CTCRVn_PCT_OFF (0x05000000) + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DSPI_DMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A00))) +#define MCF548X_DSPI_DTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A08))) +#define MCF548X_DSPI_DCTAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0C))) +#define MCF548X_DSPI_DCTAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A10))) +#define MCF548X_DSPI_DCTAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A14))) +#define MCF548X_DSPI_DCTAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A18))) +#define MCF548X_DSPI_DCTAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A1C))) +#define MCF548X_DSPI_DCTAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A20))) +#define MCF548X_DSPI_DCTAR6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A24))) +#define MCF548X_DSPI_DCTAR7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A28))) +#define MCF548X_DSPI_DCTARn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0CU+((x)*0x004)))) +#define MCF548X_DSPI_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A2C))) +#define MCF548X_DSPI_DIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A30))) +#define MCF548X_DSPI_DTFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A34))) +#define MCF548X_DSPI_DRFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A38))) +#define MCF548X_DSPI_DTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3C))) +#define MCF548X_DSPI_DTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A40))) +#define MCF548X_DSPI_DTFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A44))) +#define MCF548X_DSPI_DTFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A48))) +#define MCF548X_DSPI_DTFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3CU+((x)*0x004)))) +#define MCF548X_DSPI_DRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7C))) +#define MCF548X_DSPI_DRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A80))) +#define MCF548X_DSPI_DRFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A84))) +#define MCF548X_DSPI_DRFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A88))) +#define MCF548X_DSPI_DRFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7CU+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_DSPI_DMCR */ +#define MCF548X_DSPI_DMCR_HALT (0x00000001) +#define MCF548X_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define MCF548X_DSPI_DMCR_CRXF (0x00000400) +#define MCF548X_DSPI_DMCR_CTXF (0x00000800) +#define MCF548X_DSPI_DMCR_DRXF (0x00001000) +#define MCF548X_DSPI_DMCR_DTXF (0x00002000) +#define MCF548X_DSPI_DMCR_CSIS0 (0x00010000) +#define MCF548X_DSPI_DMCR_CSIS2 (0x00040000) +#define MCF548X_DSPI_DMCR_CSIS3 (0x00080000) +#define MCF548X_DSPI_DMCR_CSIS5 (0x00200000) +#define MCF548X_DSPI_DMCR_ROOE (0x01000000) +#define MCF548X_DSPI_DMCR_PCSSE (0x02000000) +#define MCF548X_DSPI_DMCR_MTFE (0x04000000) +#define MCF548X_DSPI_DMCR_FRZ (0x08000000) +#define MCF548X_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define MCF548X_DSPI_DMCR_CSCK (0x40000000) +#define MCF548X_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DTCR */ +#define MCF548X_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_DSPI_DCTARn */ +#define MCF548X_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) +#define MCF548X_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) +#define MCF548X_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) +#define MCF548X_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) +#define MCF548X_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) +#define MCF548X_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) +#define MCF548X_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) +#define MCF548X_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) +#define MCF548X_DSPI_DCTARn_LSBFE (0x01000000) +#define MCF548X_DSPI_DCTARn_CPHA (0x02000000) +#define MCF548X_DSPI_DCTARn_CPOL (0x04000000) +#define MCF548X_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) +#define MCF548X_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) +#define MCF548X_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) +#define MCF548X_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) +#define MCF548X_DSPI_DCTARn_PASC_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PASC_3CLK (0x00100000) +#define MCF548X_DSPI_DCTARn_PASC_5CLK (0x00200000) +#define MCF548X_DSPI_DCTARn_PASC_7CLK (0x00300000) +#define MCF548X_DSPI_DCTARn_PDT_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PDT_3CLK (0x00040000) +#define MCF548X_DSPI_DCTARn_PDT_5CLK (0x00080000) +#define MCF548X_DSPI_DCTARn_PDT_7CLK (0x000A0000) +#define MCF548X_DSPI_DCTARn_PBR_1CLK (0x00000000) +#define MCF548X_DSPI_DCTARn_PBR_3CLK (0x00010000) +#define MCF548X_DSPI_DCTARn_PBR_5CLK (0x00020000) +#define MCF548X_DSPI_DCTARn_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for MCF548X_DSPI_DSR */ +#define MCF548X_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) +#define MCF548X_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define MCF548X_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define MCF548X_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define MCF548X_DSPI_DSR_RFDF (0x00020000) +#define MCF548X_DSPI_DSR_RFOF (0x00080000) +#define MCF548X_DSPI_DSR_TFFF (0x02000000) +#define MCF548X_DSPI_DSR_TFUF (0x08000000) +#define MCF548X_DSPI_DSR_EOQF (0x10000000) +#define MCF548X_DSPI_DSR_TXRXS (0x40000000) +#define MCF548X_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DIRSR */ +#define MCF548X_DSPI_DIRSR_RFDFS (0x00010000) +#define MCF548X_DSPI_DIRSR_RFDFE (0x00020000) +#define MCF548X_DSPI_DIRSR_RFOFE (0x00080000) +#define MCF548X_DSPI_DIRSR_TFFFS (0x01000000) +#define MCF548X_DSPI_DIRSR_TFFFE (0x02000000) +#define MCF548X_DSPI_DIRSR_TFUFE (0x08000000) +#define MCF548X_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF548X_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DTFR */ +#define MCF548X_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_DSPI_DTFR_CS0 (0x00010000) +#define MCF548X_DSPI_DTFR_CS2 (0x00040000) +#define MCF548X_DSPI_DTFR_CS3 (0x00080000) +#define MCF548X_DSPI_DTFR_CS5 (0x00200000) +#define MCF548X_DSPI_DTFR_CTCNT (0x04000000) +#define MCF548X_DSPI_DTFR_EOQ (0x08000000) +#define MCF548X_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define MCF548X_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF548X_DSPI_DRFR */ +#define MCF548X_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF548X_DSPI_DTFDRn */ +#define MCF548X_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_DSPI_DRFDRn */ +#define MCF548X_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_EPORT_EPPAR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000F00))) +#define MCF548X_EPORT_EPDDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F04))) +#define MCF548X_EPORT_EPIER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F05))) +#define MCF548X_EPORT_EPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F08))) +#define MCF548X_EPORT_EPPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F09))) +#define MCF548X_EPORT_EPFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F0C))) + +/* Bit definitions and macros for MCF548X_EPORT_EPPAR */ +#define MCF548X_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF548X_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF548X_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF548X_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF548X_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF548X_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF548X_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF548X_EPORT_EPPAR_EPPAx_LEVEL (0) +#define MCF548X_EPORT_EPPAR_EPPAx_RISING (1) +#define MCF548X_EPORT_EPPAR_EPPAx_FALLING (2) +#define MCF548X_EPORT_EPPAR_EPPAx_BOTH (3) + +/* Bit definitions and macros for MCF548X_EPORT_EPDDR */ +#define MCF548X_EPORT_EPDDR_EPDD1 (0x02) +#define MCF548X_EPORT_EPDDR_EPDD2 (0x04) +#define MCF548X_EPORT_EPDDR_EPDD3 (0x08) +#define MCF548X_EPORT_EPDDR_EPDD4 (0x10) +#define MCF548X_EPORT_EPDDR_EPDD5 (0x20) +#define MCF548X_EPORT_EPDDR_EPDD6 (0x40) +#define MCF548X_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPIER */ +#define MCF548X_EPORT_EPIER_EPIE1 (0x02) +#define MCF548X_EPORT_EPIER_EPIE2 (0x04) +#define MCF548X_EPORT_EPIER_EPIE3 (0x08) +#define MCF548X_EPORT_EPIER_EPIE4 (0x10) +#define MCF548X_EPORT_EPIER_EPIE5 (0x20) +#define MCF548X_EPORT_EPIER_EPIE6 (0x40) +#define MCF548X_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPDR */ +#define MCF548X_EPORT_EPDR_EPD1 (0x02) +#define MCF548X_EPORT_EPDR_EPD2 (0x04) +#define MCF548X_EPORT_EPDR_EPD3 (0x08) +#define MCF548X_EPORT_EPDR_EPD4 (0x10) +#define MCF548X_EPORT_EPDR_EPD5 (0x20) +#define MCF548X_EPORT_EPDR_EPD6 (0x40) +#define MCF548X_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPPDR */ +#define MCF548X_EPORT_EPPDR_EPPD1 (0x02) +#define MCF548X_EPORT_EPPDR_EPPD2 (0x04) +#define MCF548X_EPORT_EPPDR_EPPD3 (0x08) +#define MCF548X_EPORT_EPPDR_EPPD4 (0x10) +#define MCF548X_EPORT_EPPDR_EPPD5 (0x20) +#define MCF548X_EPORT_EPPDR_EPPD6 (0x40) +#define MCF548X_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF548X_EPORT_EPFR */ +#define MCF548X_EPORT_EPFR_EPF1 (0x02) +#define MCF548X_EPORT_EPFR_EPF2 (0x04) +#define MCF548X_EPORT_EPFR_EPF3 (0x08) +#define MCF548X_EPORT_EPFR_EPF4 (0x10) +#define MCF548X_EPORT_EPFR_EPF5 (0x20) +#define MCF548X_EPORT_EPFR_EPF6 (0x40) +#define MCF548X_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* +* FlexBus Chip Selects (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_FBCS_CSAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500))) +#define MCF548X_FBCS_CSMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504))) +#define MCF548X_FBCS_CSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508))) +#define MCF548X_FBCS_CSAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00050C))) +#define MCF548X_FBCS_CSMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000510))) +#define MCF548X_FBCS_CSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000514))) +#define MCF548X_FBCS_CSAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000518))) +#define MCF548X_FBCS_CSMR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00051C))) +#define MCF548X_FBCS_CSCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000520))) +#define MCF548X_FBCS_CSAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000524))) +#define MCF548X_FBCS_CSMR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000528))) +#define MCF548X_FBCS_CSCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00052C))) +#define MCF548X_FBCS_CSAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000530))) +#define MCF548X_FBCS_CSMR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000534))) +#define MCF548X_FBCS_CSCR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000538))) +#define MCF548X_FBCS_CSAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00053C))) +#define MCF548X_FBCS_CSMR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000540))) +#define MCF548X_FBCS_CSCR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000544))) +#define MCF548X_FBCS_CSAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500U+((x)*0x00C)))) +#define MCF548X_FBCS_CSMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504U+((x)*0x00C)))) +#define MCF548X_FBCS_CSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508U+((x)*0x00C)))) + +/* Bit definitions and macros for MCF548X_FBCS_CSAR */ +#define MCF548X_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF548X_FBCS_CSMR */ +#define MCF548X_FBCS_CSMR_V (0x00000001) +#define MCF548X_FBCS_CSMR_WP (0x00000100) +#define MCF548X_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF548X_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF548X_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF548X_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF548X_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF548X_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF548X_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF548X_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF548X_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF548X_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF548X_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF548X_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF548X_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF548X_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF548X_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF548X_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF548X_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF548X_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF548X_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF548X_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF548X_FBCS_CSCR */ +#define MCF548X_FBCS_CSCR_BSTW (0x00000008) +#define MCF548X_FBCS_CSCR_BSTR (0x00000010) +#define MCF548X_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +#define MCF548X_FBCS_CSCR_AA (0x00000100) +#define MCF548X_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +#define MCF548X_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +#define MCF548X_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +#define MCF548X_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +#define MCF548X_FBCS_CSCR_SWSEN (0x00800000) +#define MCF548X_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +#define MCF548X_FBCS_CSCR_PS_8 (0x00000040) +#define MCF548X_FBCS_CSCR_PS_16 (0x00000080) +#define MCF548X_FBCS_CSCR_PS_32 (0x00000000) + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_GPIO_PODR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A00))) +#define MCF548X_GPIO_PODR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A01))) +#define MCF548X_GPIO_PODR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A02))) +#define MCF548X_GPIO_PODR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A04))) +#define MCF548X_GPIO_PODR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A05))) +#define MCF548X_GPIO_PODR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A06))) +#define MCF548X_GPIO_PODR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A07))) +#define MCF548X_GPIO_PODR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A08))) +#define MCF548X_GPIO_PODR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A09))) +#define MCF548X_GPIO_PODR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0A))) +#define MCF548X_GPIO_PODR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0C))) +#define MCF548X_GPIO_PODR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0D))) +#define MCF548X_GPIO_PODR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0E))) +#define MCF548X_GPIO_PDDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A10))) +#define MCF548X_GPIO_PDDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A11))) +#define MCF548X_GPIO_PDDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A12))) +#define MCF548X_GPIO_PDDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A14))) +#define MCF548X_GPIO_PDDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A15))) +#define MCF548X_GPIO_PDDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A16))) +#define MCF548X_GPIO_PDDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A17))) +#define MCF548X_GPIO_PDDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A18))) +#define MCF548X_GPIO_PDDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A19))) +#define MCF548X_GPIO_PDDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1A))) +#define MCF548X_GPIO_PDDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1C))) +#define MCF548X_GPIO_PDDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1D))) +#define MCF548X_GPIO_PDDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1E))) +#define MCF548X_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A20))) +#define MCF548X_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A21))) +#define MCF548X_GPIO_PPDSDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A22))) +#define MCF548X_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A24))) +#define MCF548X_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A25))) +#define MCF548X_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A26))) +#define MCF548X_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A27))) +#define MCF548X_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A28))) +#define MCF548X_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A29))) +#define MCF548X_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2A))) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2C))) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2D))) +#define MCF548X_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2E))) +#define MCF548X_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A30))) +#define MCF548X_GPIO_PCLRR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A31))) +#define MCF548X_GPIO_PCLRR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A32))) +#define MCF548X_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A34))) +#define MCF548X_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A35))) +#define MCF548X_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A36))) +#define MCF548X_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A37))) +#define MCF548X_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A38))) +#define MCF548X_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A39))) +#define MCF548X_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3A))) +#define MCF548X_GPIO_PCLRR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3C))) +#define MCF548X_GPIO_PCLRR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3D))) +#define MCF548X_GPIO_PCLRR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3E))) +#define MCF548X_GPIO_PAR_FBCTL (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A40))) +#define MCF548X_GPIO_PAR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A42))) +#define MCF548X_GPIO_PAR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A43))) +#define MCF548X_GPIO_PAR_FECI2CIRQ (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A44))) +#define MCF548X_GPIO_PAR_PCIBG (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A48))) +#define MCF548X_GPIO_PAR_PCIBR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A4A))) +#define MCF548X_GPIO_PAR_PSC3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4C))) +#define MCF548X_GPIO_PAR_PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4D))) +#define MCF548X_GPIO_PAR_PSC1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4E))) +#define MCF548X_GPIO_PAR_PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4F))) +#define MCF548X_GPIO_PAR_DSPI (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A50))) +#define MCF548X_GPIO_PAR_TIMER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A52))) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCTL */ +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCS */ +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_DMA */ +#define MCF548X_GPIO_PODR_DMA_PODR_DMA0 (0x01) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA1 (0x02) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA2 (0x04) +#define MCF548X_GPIO_PODR_DMA_PODR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0H */ +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0L */ +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1H */ +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1L */ +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_FECI2C */ +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBG */ +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) +#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBR */ +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) +#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC3PSC2 */ +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC1PSC0 */ +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PODR_DSPI */ +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCTL */ +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCS */ +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_DMA */ +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) +#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0H */ +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0L */ +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1H */ +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1L */ +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_FECI2C */ +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBG */ +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) +#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBR */ +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) +#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC3PSC2 */ +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC1PSC0 */ +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PDDR_DSPI */ +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCTL */ +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCS */ +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DMA */ +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) +#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0H */ +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0L */ +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1H */ +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1L */ +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FECI2C */ +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBG */ +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) +#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBR */ +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) +#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC3PSC2 */ +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC1PSC0 */ +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DSPI */ +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) +#define MCF548X_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCTL */ +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCS */ +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DMA */ +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) +#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0H */ +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0L */ +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1H */ +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1L */ +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) +#define MCF548X_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FECI2C */ +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF548X_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBG */ +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) +#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) +#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) +#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBR */ +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) +#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) +#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) +#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC3PSC2 */ +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC1PSC0 */ +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DSPI */ +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCTL */ +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TA (0x0004) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_FBCTL_PAR_OE (0x0040) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TBST (2) +#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TS (3) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) +#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCS */ +#define MCF548X_GPIO_PAR_FBCS_PAR_CS1 (0x02) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS2 (0x04) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS3 (0x08) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS4 (0x10) +#define MCF548X_GPIO_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_DMA */ +#define MCF548X_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) +#define MCF548X_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) +#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_DACK (3) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_TIN (2) +#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_FECI2CIRQ */ +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) +#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBG */ +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBR */ +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC3 */ +#define MCF548X_GPIO_PAR_PSC3_PAR_TXD3 (0x04) +#define MCF548X_GPIO_PAR_PSC3_PAR_RXD3 (0x08) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF548X_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC2 */ +#define MCF548X_GPIO_PAR_PSC2_PAR_TXD2 (0x04) +#define MCF548X_GPIO_PAR_PSC2_PAR_RXD2 (0x08) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC1 */ +#define MCF548X_GPIO_PAR_PSC1_PAR_TXD1 (0x04) +#define MCF548X_GPIO_PAR_PSC1_PAR_RXD1 (0x08) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC0 */ +#define MCF548X_GPIO_PAR_PSC0_PAR_TXD0 (0x04) +#define MCF548X_GPIO_PAR_PSC0_PAR_RXD0 (0x08) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_DSPI */ +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS5 (0x1000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) +#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) +#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) +#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) +#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) + +/* Bit definitions and macros for MCF548X_GPIO_PAR_TIMER */ +#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) +#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) +#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_GPT_GMS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800))) +#define MCF548X_GPT_GCIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804))) +#define MCF548X_GPT_GPWM0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808))) +#define MCF548X_GPT_GSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080C))) +#define MCF548X_GPT_GMS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000810))) +#define MCF548X_GPT_GCIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000814))) +#define MCF548X_GPT_GPWM1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000818))) +#define MCF548X_GPT_GSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00081C))) +#define MCF548X_GPT_GMS2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000820))) +#define MCF548X_GPT_GCIR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000824))) +#define MCF548X_GPT_GPWM2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000828))) +#define MCF548X_GPT_GSR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00082C))) +#define MCF548X_GPT_GMS3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000830))) +#define MCF548X_GPT_GCIR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000834))) +#define MCF548X_GPT_GPWM3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000838))) +#define MCF548X_GPT_GSR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00083C))) +#define MCF548X_GPT_GMS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800U+((x)*0x010)))) +#define MCF548X_GPT_GCIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804U+((x)*0x010)))) +#define MCF548X_GPT_GPWM(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808U+((x)*0x010)))) +#define MCF548X_GPT_GSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080CU+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_GPT_GMS */ +#define MCF548X_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) +#define MCF548X_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) +#define MCF548X_GPT_GMS_IEN (0x00000100) +#define MCF548X_GPT_GMS_OD (0x00000200) +#define MCF548X_GPT_GMS_SC (0x00000400) +#define MCF548X_GPT_GMS_CE (0x00001000) +#define MCF548X_GPT_GMS_WDEN (0x00008000) +#define MCF548X_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) +#define MCF548X_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) +#define MCF548X_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) +#define MCF548X_GPT_GMS_OCT_FRCLOW (0x00000000) +#define MCF548X_GPT_GMS_OCT_PULSEHI (0x00100000) +#define MCF548X_GPT_GMS_OCT_PULSELO (0x00200000) +#define MCF548X_GPT_GMS_OCT_TOGGLE (0x00300000) +#define MCF548X_GPT_GMS_ICT_ANY (0x00000000) +#define MCF548X_GPT_GMS_ICT_RISE (0x00010000) +#define MCF548X_GPT_GMS_ICT_FALL (0x00020000) +#define MCF548X_GPT_GMS_ICT_PULSE (0x00030000) +#define MCF548X_GPT_GMS_GPIO_INPUT (0x00000000) +#define MCF548X_GPT_GMS_GPIO_OUTLO (0x00000020) +#define MCF548X_GPT_GMS_GPIO_OUTHI (0x00000030) +#define MCF548X_GPT_GMS_TMS_DISABLE (0x00000000) +#define MCF548X_GPT_GMS_TMS_INCAPT (0x00000001) +#define MCF548X_GPT_GMS_TMS_OUTCAPT (0x00000002) +#define MCF548X_GPT_GMS_TMS_PWM (0x00000003) +#define MCF548X_GPT_GMS_TMS_GPIO (0x00000004) + +/* Bit definitions and macros for MCF548X_GPT_GCIR */ +#define MCF548X_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_GPT_GPWM */ +#define MCF548X_GPT_GPWM_LOAD (0x00000001) +#define MCF548X_GPT_GPWM_PWMOP (0x00000100) +#define MCF548X_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_GPT_GSR */ +#define MCF548X_GPT_GSR_CAPT (0x00000001) +#define MCF548X_GPT_GSR_COMP (0x00000002) +#define MCF548X_GPT_GSR_PWMP (0x00000004) +#define MCF548X_GPT_GSR_TEXP (0x00000008) +#define MCF548X_GPT_GSR_PIN (0x00000100) +#define MCF548X_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) +#define MCF548X_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_I2C_I2AR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F00))) +#define MCF548X_I2C_I2FDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F04))) +#define MCF548X_I2C_I2CR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F08))) +#define MCF548X_I2C_I2SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F0C))) +#define MCF548X_I2C_I2DR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F10))) +#define MCF548X_I2C_I2ICR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F20))) + +/* Bit definitions and macros for MCF548X_I2C_I2AR */ +#define MCF548X_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF548X_I2C_I2FDR */ +#define MCF548X_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF548X_I2C_I2CR */ +#define MCF548X_I2C_I2CR_RSTA (0x04) +#define MCF548X_I2C_I2CR_TXAK (0x08) +#define MCF548X_I2C_I2CR_MTX (0x10) +#define MCF548X_I2C_I2CR_MSTA (0x20) +#define MCF548X_I2C_I2CR_IIEN (0x40) +#define MCF548X_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF548X_I2C_I2SR */ +#define MCF548X_I2C_I2SR_RXAK (0x01) +#define MCF548X_I2C_I2SR_IIF (0x02) +#define MCF548X_I2C_I2SR_SRW (0x04) +#define MCF548X_I2C_I2SR_IAL (0x10) +#define MCF548X_I2C_I2SR_IBB (0x20) +#define MCF548X_I2C_I2SR_IAAS (0x40) +#define MCF548X_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF548X_I2C_I2ICR */ +#define MCF548X_I2C_I2ICR_IE (0x01) +#define MCF548X_I2C_I2ICR_RE (0x02) +#define MCF548X_I2C_I2ICR_TE (0x04) +#define MCF548X_I2C_I2ICR_BNBE (0x08) + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_INTC_IPRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000700))) +#define MCF548X_INTC_IPRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000704))) +#define MCF548X_INTC_IMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000708))) +#define MCF548X_INTC_IMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00070C))) +#define MCF548X_INTC_INTFRCH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000710))) +#define MCF548X_INTC_INTFRCL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000714))) +#define MCF548X_INTC_IRLR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000718))) +#define MCF548X_INTC_IACKLPR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000719))) +#define MCF548X_INTC_ICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740))) +#define MCF548X_INTC_ICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000741))) +#define MCF548X_INTC_ICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000742))) +#define MCF548X_INTC_ICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000743))) +#define MCF548X_INTC_ICR4 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000744))) +#define MCF548X_INTC_ICR5 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000745))) +#define MCF548X_INTC_ICR6 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000746))) +#define MCF548X_INTC_ICR7 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000747))) +#define MCF548X_INTC_ICR8 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000748))) +#define MCF548X_INTC_ICR9 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000749))) +#define MCF548X_INTC_ICR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074A))) +#define MCF548X_INTC_ICR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074B))) +#define MCF548X_INTC_ICR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074C))) +#define MCF548X_INTC_ICR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074D))) +#define MCF548X_INTC_ICR14 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074E))) +#define MCF548X_INTC_ICR15 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074F))) +#define MCF548X_INTC_ICR16 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000750))) +#define MCF548X_INTC_ICR17 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000751))) +#define MCF548X_INTC_ICR18 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000752))) +#define MCF548X_INTC_ICR19 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000753))) +#define MCF548X_INTC_ICR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000754))) +#define MCF548X_INTC_ICR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000755))) +#define MCF548X_INTC_ICR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000756))) +#define MCF548X_INTC_ICR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000757))) +#define MCF548X_INTC_ICR24 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000758))) +#define MCF548X_INTC_ICR25 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000759))) +#define MCF548X_INTC_ICR26 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075A))) +#define MCF548X_INTC_ICR27 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075B))) +#define MCF548X_INTC_ICR28 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075C))) +#define MCF548X_INTC_ICR29 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075D))) +#define MCF548X_INTC_ICR30 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075E))) +#define MCF548X_INTC_ICR31 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075F))) +#define MCF548X_INTC_ICR32 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000760))) +#define MCF548X_INTC_ICR33 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000761))) +#define MCF548X_INTC_ICR34 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000762))) +#define MCF548X_INTC_ICR35 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000763))) +#define MCF548X_INTC_ICR36 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000764))) +#define MCF548X_INTC_ICR37 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000765))) +#define MCF548X_INTC_ICR38 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000766))) +#define MCF548X_INTC_ICR39 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000767))) +#define MCF548X_INTC_ICR40 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000768))) +#define MCF548X_INTC_ICR41 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000769))) +#define MCF548X_INTC_ICR42 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076A))) +#define MCF548X_INTC_ICR43 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076B))) +#define MCF548X_INTC_ICR44 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076C))) +#define MCF548X_INTC_ICR45 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076D))) +#define MCF548X_INTC_ICR46 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076E))) +#define MCF548X_INTC_ICR47 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076F))) +#define MCF548X_INTC_ICR48 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000770))) +#define MCF548X_INTC_ICR49 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000771))) +#define MCF548X_INTC_ICR50 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000772))) +#define MCF548X_INTC_ICR51 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000773))) +#define MCF548X_INTC_ICR52 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000774))) +#define MCF548X_INTC_ICR53 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000775))) +#define MCF548X_INTC_ICR54 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000776))) +#define MCF548X_INTC_ICR55 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000777))) +#define MCF548X_INTC_ICR56 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000778))) +#define MCF548X_INTC_ICR57 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000779))) +#define MCF548X_INTC_ICR58 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077A))) +#define MCF548X_INTC_ICR59 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077B))) +#define MCF548X_INTC_ICR60 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077C))) +#define MCF548X_INTC_ICR61 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077D))) +#define MCF548X_INTC_ICR62 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077E))) +#define MCF548X_INTC_ICR63 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077F))) +#define MCF548X_INTC_ICRn(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740U+((x)*0x001)))) +#define MCF548X_INTC_SWIACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E0))) +#define MCF548X_INTC_L1IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4))) +#define MCF548X_INTC_L2IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E8))) +#define MCF548X_INTC_L3IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007EC))) +#define MCF548X_INTC_L4IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F0))) +#define MCF548X_INTC_L5IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F4))) +#define MCF548X_INTC_L6IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F8))) +#define MCF548X_INTC_L7IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007FC))) +#define MCF548X_INTC_LnIACK(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4U+((x)*0x004)))) + +/* Bit definitions and macros for MCF548X_INTC_IPRH */ +#define MCF548X_INTC_IPRH_INT32 (0x00000001) +#define MCF548X_INTC_IPRH_INT33 (0x00000002) +#define MCF548X_INTC_IPRH_INT34 (0x00000004) +#define MCF548X_INTC_IPRH_INT35 (0x00000008) +#define MCF548X_INTC_IPRH_INT36 (0x00000010) +#define MCF548X_INTC_IPRH_INT37 (0x00000020) +#define MCF548X_INTC_IPRH_INT38 (0x00000040) +#define MCF548X_INTC_IPRH_INT39 (0x00000080) +#define MCF548X_INTC_IPRH_INT40 (0x00000100) +#define MCF548X_INTC_IPRH_INT41 (0x00000200) +#define MCF548X_INTC_IPRH_INT42 (0x00000400) +#define MCF548X_INTC_IPRH_INT43 (0x00000800) +#define MCF548X_INTC_IPRH_INT44 (0x00001000) +#define MCF548X_INTC_IPRH_INT45 (0x00002000) +#define MCF548X_INTC_IPRH_INT46 (0x00004000) +#define MCF548X_INTC_IPRH_INT47 (0x00008000) +#define MCF548X_INTC_IPRH_INT48 (0x00010000) +#define MCF548X_INTC_IPRH_INT49 (0x00020000) +#define MCF548X_INTC_IPRH_INT50 (0x00040000) +#define MCF548X_INTC_IPRH_INT51 (0x00080000) +#define MCF548X_INTC_IPRH_INT52 (0x00100000) +#define MCF548X_INTC_IPRH_INT53 (0x00200000) +#define MCF548X_INTC_IPRH_INT54 (0x00400000) +#define MCF548X_INTC_IPRH_INT55 (0x00800000) +#define MCF548X_INTC_IPRH_INT56 (0x01000000) +#define MCF548X_INTC_IPRH_INT57 (0x02000000) +#define MCF548X_INTC_IPRH_INT58 (0x04000000) +#define MCF548X_INTC_IPRH_INT59 (0x08000000) +#define MCF548X_INTC_IPRH_INT60 (0x10000000) +#define MCF548X_INTC_IPRH_INT61 (0x20000000) +#define MCF548X_INTC_IPRH_INT62 (0x40000000) +#define MCF548X_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IPRL */ +#define MCF548X_INTC_IPRL_INT1 (0x00000002) +#define MCF548X_INTC_IPRL_INT2 (0x00000004) +#define MCF548X_INTC_IPRL_INT3 (0x00000008) +#define MCF548X_INTC_IPRL_INT4 (0x00000010) +#define MCF548X_INTC_IPRL_INT5 (0x00000020) +#define MCF548X_INTC_IPRL_INT6 (0x00000040) +#define MCF548X_INTC_IPRL_INT7 (0x00000080) +#define MCF548X_INTC_IPRL_INT8 (0x00000100) +#define MCF548X_INTC_IPRL_INT9 (0x00000200) +#define MCF548X_INTC_IPRL_INT10 (0x00000400) +#define MCF548X_INTC_IPRL_INT11 (0x00000800) +#define MCF548X_INTC_IPRL_INT12 (0x00001000) +#define MCF548X_INTC_IPRL_INT13 (0x00002000) +#define MCF548X_INTC_IPRL_INT14 (0x00004000) +#define MCF548X_INTC_IPRL_INT15 (0x00008000) +#define MCF548X_INTC_IPRL_INT16 (0x00010000) +#define MCF548X_INTC_IPRL_INT17 (0x00020000) +#define MCF548X_INTC_IPRL_INT18 (0x00040000) +#define MCF548X_INTC_IPRL_INT19 (0x00080000) +#define MCF548X_INTC_IPRL_INT20 (0x00100000) +#define MCF548X_INTC_IPRL_INT21 (0x00200000) +#define MCF548X_INTC_IPRL_INT22 (0x00400000) +#define MCF548X_INTC_IPRL_INT23 (0x00800000) +#define MCF548X_INTC_IPRL_INT24 (0x01000000) +#define MCF548X_INTC_IPRL_INT25 (0x02000000) +#define MCF548X_INTC_IPRL_INT26 (0x04000000) +#define MCF548X_INTC_IPRL_INT27 (0x08000000) +#define MCF548X_INTC_IPRL_INT28 (0x10000000) +#define MCF548X_INTC_IPRL_INT29 (0x20000000) +#define MCF548X_INTC_IPRL_INT30 (0x40000000) +#define MCF548X_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IMRH */ +#define MCF548X_INTC_IMRH_INT_MASK32 (0x00000001) +#define MCF548X_INTC_IMRH_INT_MASK33 (0x00000002) +#define MCF548X_INTC_IMRH_INT_MASK34 (0x00000004) +#define MCF548X_INTC_IMRH_INT_MASK35 (0x00000008) +#define MCF548X_INTC_IMRH_INT_MASK36 (0x00000010) +#define MCF548X_INTC_IMRH_INT_MASK37 (0x00000020) +#define MCF548X_INTC_IMRH_INT_MASK38 (0x00000040) +#define MCF548X_INTC_IMRH_INT_MASK39 (0x00000080) +#define MCF548X_INTC_IMRH_INT_MASK40 (0x00000100) +#define MCF548X_INTC_IMRH_INT_MASK41 (0x00000200) +#define MCF548X_INTC_IMRH_INT_MASK42 (0x00000400) +#define MCF548X_INTC_IMRH_INT_MASK43 (0x00000800) +#define MCF548X_INTC_IMRH_INT_MASK44 (0x00001000) +#define MCF548X_INTC_IMRH_INT_MASK45 (0x00002000) +#define MCF548X_INTC_IMRH_INT_MASK46 (0x00004000) +#define MCF548X_INTC_IMRH_INT_MASK47 (0x00008000) +#define MCF548X_INTC_IMRH_INT_MASK48 (0x00010000) +#define MCF548X_INTC_IMRH_INT_MASK49 (0x00020000) +#define MCF548X_INTC_IMRH_INT_MASK50 (0x00040000) +#define MCF548X_INTC_IMRH_INT_MASK51 (0x00080000) +#define MCF548X_INTC_IMRH_INT_MASK52 (0x00100000) +#define MCF548X_INTC_IMRH_INT_MASK53 (0x00200000) +#define MCF548X_INTC_IMRH_INT_MASK54 (0x00400000) +#define MCF548X_INTC_IMRH_INT_MASK55 (0x00800000) +#define MCF548X_INTC_IMRH_INT_MASK56 (0x01000000) +#define MCF548X_INTC_IMRH_INT_MASK57 (0x02000000) +#define MCF548X_INTC_IMRH_INT_MASK58 (0x04000000) +#define MCF548X_INTC_IMRH_INT_MASK59 (0x08000000) +#define MCF548X_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF548X_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF548X_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF548X_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IMRL */ +#define MCF548X_INTC_IMRL_MASKALL (0x00000001) +#define MCF548X_INTC_IMRL_INT_MASK1 (0x00000002) +#define MCF548X_INTC_IMRL_INT_MASK2 (0x00000004) +#define MCF548X_INTC_IMRL_INT_MASK3 (0x00000008) +#define MCF548X_INTC_IMRL_INT_MASK4 (0x00000010) +#define MCF548X_INTC_IMRL_INT_MASK5 (0x00000020) +#define MCF548X_INTC_IMRL_INT_MASK6 (0x00000040) +#define MCF548X_INTC_IMRL_INT_MASK7 (0x00000080) +#define MCF548X_INTC_IMRL_INT_MASK8 (0x00000100) +#define MCF548X_INTC_IMRL_INT_MASK9 (0x00000200) +#define MCF548X_INTC_IMRL_INT_MASK10 (0x00000400) +#define MCF548X_INTC_IMRL_INT_MASK11 (0x00000800) +#define MCF548X_INTC_IMRL_INT_MASK12 (0x00001000) +#define MCF548X_INTC_IMRL_INT_MASK13 (0x00002000) +#define MCF548X_INTC_IMRL_INT_MASK14 (0x00004000) +#define MCF548X_INTC_IMRL_INT_MASK15 (0x00008000) +#define MCF548X_INTC_IMRL_INT_MASK16 (0x00010000) +#define MCF548X_INTC_IMRL_INT_MASK17 (0x00020000) +#define MCF548X_INTC_IMRL_INT_MASK18 (0x00040000) +#define MCF548X_INTC_IMRL_INT_MASK19 (0x00080000) +#define MCF548X_INTC_IMRL_INT_MASK20 (0x00100000) +#define MCF548X_INTC_IMRL_INT_MASK21 (0x00200000) +#define MCF548X_INTC_IMRL_INT_MASK22 (0x00400000) +#define MCF548X_INTC_IMRL_INT_MASK23 (0x00800000) +#define MCF548X_INTC_IMRL_INT_MASK24 (0x01000000) +#define MCF548X_INTC_IMRL_INT_MASK25 (0x02000000) +#define MCF548X_INTC_IMRL_INT_MASK26 (0x04000000) +#define MCF548X_INTC_IMRL_INT_MASK27 (0x08000000) +#define MCF548X_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF548X_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF548X_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF548X_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_INTFRCH */ +#define MCF548X_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF548X_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF548X_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF548X_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF548X_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF548X_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF548X_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF548X_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF548X_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF548X_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF548X_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF548X_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF548X_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF548X_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF548X_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF548X_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF548X_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF548X_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF548X_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF548X_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF548X_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF548X_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF548X_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF548X_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF548X_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF548X_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF548X_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF548X_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF548X_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF548X_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF548X_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF548X_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_INTFRCL */ +#define MCF548X_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF548X_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF548X_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF548X_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF548X_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF548X_INTC_INTFRCL_INT6 (0x00000040) +#define MCF548X_INTC_INTFRCL_INT7 (0x00000080) +#define MCF548X_INTC_INTFRCL_INT8 (0x00000100) +#define MCF548X_INTC_INTFRCL_INT9 (0x00000200) +#define MCF548X_INTC_INTFRCL_INT10 (0x00000400) +#define MCF548X_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF548X_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF548X_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF548X_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF548X_INTC_INTFRCL_INT15 (0x00008000) +#define MCF548X_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF548X_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF548X_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF548X_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF548X_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF548X_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF548X_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF548X_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF548X_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF548X_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF548X_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF548X_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF548X_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF548X_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF548X_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF548X_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF548X_INTC_IRLR */ +#define MCF548X_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF548X_INTC_IACKLPR */ +#define MCF548X_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF548X_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF548X_INTC_ICRn */ +#define MCF548X_INTC_ICRn_IP(x) (((x)&0x07)<<0) +#define MCF548X_INTC_ICRn_IL(x) (((x)&0x07)<<3) + + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SDRAMC_SDRAMDS (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000004))) +#define MCF548X_SDRAMC_CS0CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020))) +#define MCF548X_SDRAMC_CS1CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000024))) +#define MCF548X_SDRAMC_CS2CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000028))) +#define MCF548X_SDRAMC_CS3CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00002C))) +#define MCF548X_SDRAMC_CSnCFG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020U+((x)*0x004)))) +#define MCF548X_SDRAMC_SDMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000100))) +#define MCF548X_SDRAMC_SDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000104))) +#define MCF548X_SDRAMC_SDCFG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000108))) +#define MCF548X_SDRAMC_SDCFG2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00010C))) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDRAMDS */ +#define MCF548X_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) +#define MCF548X_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) +#define MCF548X_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) +#define MCF548X_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) +#define MCF548X_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) +#define MCF548X_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) + +/* Bit definitions and macros for MCF548X_SDRAMC_CSnCFG */ +#define MCF548X_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) +#define MCF548X_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) +#define MCF548X_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDMR */ +#define MCF548X_SDRAMC_SDMR_CMD (0x00010000) +#define MCF548X_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define MCF548X_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) +#define MCF548X_SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define MCF548X_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCR */ +#define MCF548X_SDRAMC_SDCR_IPALL (0x00000002) +#define MCF548X_SDRAMC_SDCR_IREF (0x00000004) +#define MCF548X_SDRAMC_SDCR_BUFF (0x00000010) +#define MCF548X_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define MCF548X_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define MCF548X_SDRAMC_SDCR_DRIVE (0x00400000) +#define MCF548X_SDRAMC_SDCR_AP (0x00800000) +#define MCF548X_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define MCF548X_SDRAMC_SDCR_REF (0x10000000) +#define MCF548X_SDRAMC_SDCR_DDR (0x20000000) +#define MCF548X_SDRAMC_SDCR_CKE (0x40000000) +#define MCF548X_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG1 */ +#define MCF548X_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +#define MCF548X_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define MCF548X_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define MCF548X_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define MCF548X_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define MCF548X_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define MCF548X_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG2 */ +#define MCF548X_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +#define MCF548X_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define MCF548X_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define MCF548X_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SEC_EUACRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021000))) +#define MCF548X_SEC_EUACRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021004))) +#define MCF548X_SEC_EUASRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021028))) +#define MCF548X_SEC_EUASRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02102C))) +#define MCF548X_SEC_SIMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021008))) +#define MCF548X_SEC_SIMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02100C))) +#define MCF548X_SEC_SISRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021010))) +#define MCF548X_SEC_SISRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021014))) +#define MCF548X_SEC_SICRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021018))) +#define MCF548X_SEC_SICRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02101C))) +#define MCF548X_SEC_SIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021020))) +#define MCF548X_SEC_SMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021030))) +#define MCF548X_SEC_MEAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021038))) +#define MCF548X_SEC_CCCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02200C))) +#define MCF548X_SEC_CCCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02300C))) +#define MCF548X_SEC_CCPSRH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022010))) +#define MCF548X_SEC_CCPSRH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023010))) +#define MCF548X_SEC_CCPSRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022014))) +#define MCF548X_SEC_CCPSRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023014))) +#define MCF548X_SEC_CDPR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022044))) +#define MCF548X_SEC_CDPR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023044))) +#define MCF548X_SEC_FR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02204C))) +#define MCF548X_SEC_FR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02304C))) +#define MCF548X_SEC_AFRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028018))) +#define MCF548X_SEC_AFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028028))) +#define MCF548X_SEC_AFISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028030))) +#define MCF548X_SEC_AFIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028038))) +#define MCF548X_SEC_DRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A018))) +#define MCF548X_SEC_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A028))) +#define MCF548X_SEC_DISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A030))) +#define MCF548X_SEC_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A038))) +#define MCF548X_SEC_MDRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C018))) +#define MCF548X_SEC_MDSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C028))) +#define MCF548X_SEC_MDISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C030))) +#define MCF548X_SEC_MDIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C038))) +#define MCF548X_SEC_RNGRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E018))) +#define MCF548X_SEC_RNGSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E028))) +#define MCF548X_SEC_RNGISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E030))) +#define MCF548X_SEC_RNGIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E038))) +#define MCF548X_SEC_AESRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032018))) +#define MCF548X_SEC_AESSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032028))) +#define MCF548X_SEC_AESISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032030))) +#define MCF548X_SEC_AESIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032038))) + +/* Bit definitions and macros for MCF548X_SEC_EUACRH */ +#define MCF548X_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) +#define MCF548X_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) +#define MCF548X_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) +#define MCF548X_SEC_EUACRH_RNG_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_RNG_CHA0 (0x01000000) +#define MCF548X_SEC_EUACRH_RNG_CHA1 (0x02000000) +#define MCF548X_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_MDEU_CHA0 (0x00000100) +#define MCF548X_SEC_EUACRH_MDEU_CHA1 (0x00000200) +#define MCF548X_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRH_AFEU_CHA0 (0x00000001) +#define MCF548X_SEC_EUACRH_AFEU_CHA1 (0x00000002) + +/* Bit definitions and macros for MCF548X_SEC_EUACRL */ +#define MCF548X_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) +#define MCF548X_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) +#define MCF548X_SEC_EUACRL_DEU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRL_DEU_CHA0 (0x01000000) +#define MCF548X_SEC_EUACRL_DEU_CHA1 (0x02000000) +#define MCF548X_SEC_EUACRL_AESU_NOASSIGN (0x00000000) +#define MCF548X_SEC_EUACRL_AESU_CHA0 (0x00010000) +#define MCF548X_SEC_EUACRL_AESU_CHA1 (0x00020000) + +/* Bit definitions and macros for MCF548X_SEC_EUASRH */ +#define MCF548X_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) +#define MCF548X_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) +#define MCF548X_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SEC_EUASRL */ +#define MCF548X_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) +#define MCF548X_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SEC_SIMRH */ +#define MCF548X_SEC_SIMRH_AERR (0x08000000) +#define MCF548X_SEC_SIMRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SIMRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SIMRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SIMRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SIMRL */ +#define MCF548X_SEC_SIMRL_TEA (0x00000040) +#define MCF548X_SEC_SIMRL_DEUDN (0x00000100) +#define MCF548X_SEC_SIMRL_DEUERR (0x00000200) +#define MCF548X_SEC_SIMRL_AESUDN (0x00001000) +#define MCF548X_SEC_SIMRL_AESUERR (0x00002000) +#define MCF548X_SEC_SIMRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SIMRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SIMRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SIMRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SIMRL_RNGDN (0x01000000) +#define MCF548X_SEC_SIMRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SISRH */ +#define MCF548X_SEC_SISRH_AERR (0x08000000) +#define MCF548X_SEC_SISRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SISRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SISRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SISRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SISRL */ +#define MCF548X_SEC_SISRL_TEA (0x00000040) +#define MCF548X_SEC_SISRL_DEUDN (0x00000100) +#define MCF548X_SEC_SISRL_DEUERR (0x00000200) +#define MCF548X_SEC_SISRL_AESUDN (0x00001000) +#define MCF548X_SEC_SISRL_AESUERR (0x00002000) +#define MCF548X_SEC_SISRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SISRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SISRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SISRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SISRL_RNGDN (0x01000000) +#define MCF548X_SEC_SISRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SICRH */ +#define MCF548X_SEC_SICRH_AERR (0x08000000) +#define MCF548X_SEC_SICRH_CHA0DN (0x10000000) +#define MCF548X_SEC_SICRH_CHA0ERR (0x20000000) +#define MCF548X_SEC_SICRH_CHA1DN (0x40000000) +#define MCF548X_SEC_SICRH_CHA1ERR (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_SICRL */ +#define MCF548X_SEC_SICRL_TEA (0x00000040) +#define MCF548X_SEC_SICRL_DEUDN (0x00000100) +#define MCF548X_SEC_SICRL_DEUERR (0x00000200) +#define MCF548X_SEC_SICRL_AESUDN (0x00001000) +#define MCF548X_SEC_SICRL_AESUERR (0x00002000) +#define MCF548X_SEC_SICRL_MDEUDN (0x00010000) +#define MCF548X_SEC_SICRL_MDEUERR (0x00020000) +#define MCF548X_SEC_SICRL_AFEUDN (0x00100000) +#define MCF548X_SEC_SICRL_AFEUERR (0x00200000) +#define MCF548X_SEC_SICRL_RNGDN (0x01000000) +#define MCF548X_SEC_SICRL_RNGERR (0x02000000) + +/* Bit definitions and macros for MCF548X_SEC_SMCR */ +#define MCF548X_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) +#define MCF548X_SEC_SMCR_SWR (0x01000000) +#define MCF548X_SEC_SMCR_CURR_CHAN_1 (0x00000010) +#define MCF548X_SEC_SMCR_CURR_CHAN_2 (0x00000020) + +/* Bit definitions and macros for MCF548X_SEC_CCCRn */ +#define MCF548X_SEC_CCCRn_RST (0x00000001) +#define MCF548X_SEC_CCCRn_CDIE (0x00000002) +#define MCF548X_SEC_CCCRn_NT (0x00000004) +#define MCF548X_SEC_CCCRn_NE (0x00000008) +#define MCF548X_SEC_CCCRn_WE (0x00000010) +#define MCF548X_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) +#define MCF548X_SEC_CCCRn_BURST_SIZE_2 (0x00000000) +#define MCF548X_SEC_CCCRn_BURST_SIZE_8 (0x00000100) +#define MCF548X_SEC_CCCRn_BURST_SIZE_16 (0x00000200) +#define MCF548X_SEC_CCCRn_BURST_SIZE_24 (0x00000300) +#define MCF548X_SEC_CCCRn_BURST_SIZE_32 (0x00000400) +#define MCF548X_SEC_CCCRn_BURST_SIZE_40 (0x00000500) +#define MCF548X_SEC_CCCRn_BURST_SIZE_48 (0x00000600) +#define MCF548X_SEC_CCCRn_BURST_SIZE_56 (0x00000700) + +/* Bit definitions and macros for MCF548X_SEC_CCPSRHn */ +#define MCF548X_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF548X_SEC_CCPSRLn */ +#define MCF548X_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) +#define MCF548X_SEC_CCPSRLn_EUERR (0x00000100) +#define MCF548X_SEC_CCPSRLn_SERR (0x00000200) +#define MCF548X_SEC_CCPSRLn_DERR (0x00000400) +#define MCF548X_SEC_CCPSRLn_PERR (0x00001000) +#define MCF548X_SEC_CCPSRLn_TEA (0x00002000) +#define MCF548X_SEC_CCPSRLn_SD (0x00010000) +#define MCF548X_SEC_CCPSRLn_PD (0x00020000) +#define MCF548X_SEC_CCPSRLn_SRD (0x00040000) +#define MCF548X_SEC_CCPSRLn_PRD (0x00080000) +#define MCF548X_SEC_CCPSRLn_SG (0x00100000) +#define MCF548X_SEC_CCPSRLn_PG (0x00200000) +#define MCF548X_SEC_CCPSRLn_SR (0x00400000) +#define MCF548X_SEC_CCPSRLn_PR (0x00800000) +#define MCF548X_SEC_CCPSRLn_MO (0x01000000) +#define MCF548X_SEC_CCPSRLn_MI (0x02000000) +#define MCF548X_SEC_CCPSRLn_STAT (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AFRCR */ +#define MCF548X_SEC_AFRCR_SR (0x01000000) +#define MCF548X_SEC_AFRCR_MI (0x02000000) +#define MCF548X_SEC_AFRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AFSR */ +#define MCF548X_SEC_AFSR_RD (0x01000000) +#define MCF548X_SEC_AFSR_ID (0x02000000) +#define MCF548X_SEC_AFSR_IE (0x04000000) +#define MCF548X_SEC_AFSR_OFE (0x08000000) +#define MCF548X_SEC_AFSR_IFW (0x10000000) +#define MCF548X_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_AFISR */ +#define MCF548X_SEC_AFISR_DSE (0x00010000) +#define MCF548X_SEC_AFISR_KSE (0x00020000) +#define MCF548X_SEC_AFISR_CE (0x00040000) +#define MCF548X_SEC_AFISR_ERE (0x00080000) +#define MCF548X_SEC_AFISR_IE (0x00100000) +#define MCF548X_SEC_AFISR_OFU (0x02000000) +#define MCF548X_SEC_AFISR_IFO (0x04000000) +#define MCF548X_SEC_AFISR_IFE (0x10000000) +#define MCF548X_SEC_AFISR_OFE (0x20000000) +#define MCF548X_SEC_AFISR_AE (0x40000000) +#define MCF548X_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AFIMR */ +#define MCF548X_SEC_AFIMR_DSE (0x00010000) +#define MCF548X_SEC_AFIMR_KSE (0x00020000) +#define MCF548X_SEC_AFIMR_CE (0x00040000) +#define MCF548X_SEC_AFIMR_ERE (0x00080000) +#define MCF548X_SEC_AFIMR_IE (0x00100000) +#define MCF548X_SEC_AFIMR_OFU (0x02000000) +#define MCF548X_SEC_AFIMR_IFO (0x04000000) +#define MCF548X_SEC_AFIMR_IFE (0x10000000) +#define MCF548X_SEC_AFIMR_OFE (0x20000000) +#define MCF548X_SEC_AFIMR_AE (0x40000000) +#define MCF548X_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_DRCR */ +#define MCF548X_SEC_DRCR_SR (0x01000000) +#define MCF548X_SEC_DRCR_MI (0x02000000) +#define MCF548X_SEC_DRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_DSR */ +#define MCF548X_SEC_DSR_RD (0x01000000) +#define MCF548X_SEC_DSR_ID (0x02000000) +#define MCF548X_SEC_DSR_IE (0x04000000) +#define MCF548X_SEC_DSR_OFR (0x08000000) +#define MCF548X_SEC_DSR_IFW (0x10000000) +#define MCF548X_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_DISR */ +#define MCF548X_SEC_DISR_DSE (0x00010000) +#define MCF548X_SEC_DISR_KSE (0x00020000) +#define MCF548X_SEC_DISR_CE (0x00040000) +#define MCF548X_SEC_DISR_ERE (0x00080000) +#define MCF548X_SEC_DISR_IE (0x00100000) +#define MCF548X_SEC_DISR_KPE (0x00200000) +#define MCF548X_SEC_DISR_OFU (0x02000000) +#define MCF548X_SEC_DISR_IFO (0x04000000) +#define MCF548X_SEC_DISR_IFE (0x10000000) +#define MCF548X_SEC_DISR_OFE (0x20000000) +#define MCF548X_SEC_DISR_AE (0x40000000) +#define MCF548X_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_DIMR */ +#define MCF548X_SEC_DIMR_DSE (0x00010000) +#define MCF548X_SEC_DIMR_KSE (0x00020000) +#define MCF548X_SEC_DIMR_CE (0x00040000) +#define MCF548X_SEC_DIMR_ERE (0x00080000) +#define MCF548X_SEC_DIMR_IE (0x00100000) +#define MCF548X_SEC_DIMR_KPE (0x00200000) +#define MCF548X_SEC_DIMR_OFU (0x02000000) +#define MCF548X_SEC_DIMR_IFO (0x04000000) +#define MCF548X_SEC_DIMR_IFE (0x10000000) +#define MCF548X_SEC_DIMR_OFE (0x20000000) +#define MCF548X_SEC_DIMR_AE (0x40000000) +#define MCF548X_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_MDRCR */ +#define MCF548X_SEC_MDRCR_SR (0x01000000) +#define MCF548X_SEC_MDRCR_MI (0x02000000) +#define MCF548X_SEC_MDRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_MDSR */ +#define MCF548X_SEC_MDSR_RD (0x01000000) +#define MCF548X_SEC_MDSR_ID (0x02000000) +#define MCF548X_SEC_MDSR_IE (0x04000000) +#define MCF548X_SEC_MDSR_IFW (0x10000000) +#define MCF548X_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_MDISR */ +#define MCF548X_SEC_MDISR_DSE (0x00010000) +#define MCF548X_SEC_MDISR_KSE (0x00020000) +#define MCF548X_SEC_MDISR_CE (0x00040000) +#define MCF548X_SEC_MDISR_ERE (0x00080000) +#define MCF548X_SEC_MDISR_IE (0x00100000) +#define MCF548X_SEC_MDISR_IFO (0x04000000) +#define MCF548X_SEC_MDISR_AE (0x40000000) +#define MCF548X_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_MDIMR */ +#define MCF548X_SEC_MDIMR_DSE (0x00010000) +#define MCF548X_SEC_MDIMR_KSE (0x00020000) +#define MCF548X_SEC_MDIMR_CE (0x00040000) +#define MCF548X_SEC_MDIMR_ERE (0x00080000) +#define MCF548X_SEC_MDIMR_IE (0x00100000) +#define MCF548X_SEC_MDIMR_IFO (0x04000000) +#define MCF548X_SEC_MDIMR_AE (0x40000000) +#define MCF548X_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGRCR */ +#define MCF548X_SEC_RNGRCR_SR (0x01000000) +#define MCF548X_SEC_RNGRCR_MI (0x02000000) +#define MCF548X_SEC_RNGRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGSR */ +#define MCF548X_SEC_RNGSR_RD (0x01000000) +#define MCF548X_SEC_RNGSR_O (0x02000000) +#define MCF548X_SEC_RNGSR_IE (0x04000000) +#define MCF548X_SEC_RNGSR_OFR (0x08000000) +#define MCF548X_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGISR */ +#define MCF548X_SEC_RNGISR_IE (0x00100000) +#define MCF548X_SEC_RNGISR_OFU (0x02000000) +#define MCF548X_SEC_RNGISR_AE (0x40000000) +#define MCF548X_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_RNGIMR */ +#define MCF548X_SEC_RNGIMR_IE (0x00100000) +#define MCF548X_SEC_RNGIMR_OFU (0x02000000) +#define MCF548X_SEC_RNGIMR_AE (0x40000000) +#define MCF548X_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AESRCR */ +#define MCF548X_SEC_AESRCR_SR (0x01000000) +#define MCF548X_SEC_AESRCR_MI (0x02000000) +#define MCF548X_SEC_AESRCR_RI (0x04000000) + +/* Bit definitions and macros for MCF548X_SEC_AESSR */ +#define MCF548X_SEC_AESSR_RD (0x01000000) +#define MCF548X_SEC_AESSR_ID (0x02000000) +#define MCF548X_SEC_AESSR_IE (0x04000000) +#define MCF548X_SEC_AESSR_OFR (0x08000000) +#define MCF548X_SEC_AESSR_IFW (0x10000000) +#define MCF548X_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF548X_SEC_AESISR */ +#define MCF548X_SEC_AESISR_DSE (0x00010000) +#define MCF548X_SEC_AESISR_KSE (0x00020000) +#define MCF548X_SEC_AESISR_CE (0x00040000) +#define MCF548X_SEC_AESISR_ERE (0x00080000) +#define MCF548X_SEC_AESISR_IE (0x00100000) +#define MCF548X_SEC_AESISR_OFU (0x02000000) +#define MCF548X_SEC_AESISR_IFO (0x04000000) +#define MCF548X_SEC_AESISR_IFE (0x10000000) +#define MCF548X_SEC_AESISR_OFE (0x20000000) +#define MCF548X_SEC_AESISR_AE (0x40000000) +#define MCF548X_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF548X_SEC_AESIMR */ +#define MCF548X_SEC_AESIMR_DSE (0x00010000) +#define MCF548X_SEC_AESIMR_KSE (0x00020000) +#define MCF548X_SEC_AESIMR_CE (0x00040000) +#define MCF548X_SEC_AESIMR_ERE (0x00080000) +#define MCF548X_SEC_AESIMR_IE (0x00100000) +#define MCF548X_SEC_AESIMR_OFU (0x02000000) +#define MCF548X_SEC_AESIMR_IFO (0x04000000) +#define MCF548X_SEC_AESIMR_IFE (0x10000000) +#define MCF548X_SEC_AESIMR_OFE (0x20000000) +#define MCF548X_SEC_AESIMR_AE (0x40000000) +#define MCF548X_SEC_AESIMR_ME (0x80000000) + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SLT_SLTCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900))) +#define MCF548X_SLT_SCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904))) +#define MCF548X_SLT_SCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908))) +#define MCF548X_SLT_SSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090C))) +#define MCF548X_SLT_SLTCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000910))) +#define MCF548X_SLT_SCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000914))) +#define MCF548X_SLT_SCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000918))) +#define MCF548X_SLT_SSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00091C))) +#define MCF548X_SLT_SLTCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900U+((x)*0x010)))) +#define MCF548X_SLT_SCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904U+((x)*0x010)))) +#define MCF548X_SLT_SCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908U+((x)*0x010)))) +#define MCF548X_SLT_SSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090CU+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_SLT_SCR */ +#define MCF548X_SLT_SCR_TEN (0x01000000) +#define MCF548X_SLT_SCR_IEN (0x02000000) +#define MCF548X_SLT_SCR_RUN (0x04000000) + +/* Bit definitions and macros for MCF548X_SLT_SSR */ +#define MCF548X_SLT_SSR_ST (0x01000000) +#define MCF548X_SLT_SSR_BE (0x02000000) + + +/********************************************************************* +* +* Universal Serial Bus (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_USB_USBAISR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B000))) +#define MCF548X_USB_USBAIMR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B001))) +#define MCF548X_USB_EPINFO (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B003))) +#define MCF548X_USB_CFGR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B004))) +#define MCF548X_USB_CFGAR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B005))) +#define MCF548X_USB_SPEEDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B006))) +#define MCF548X_USB_FRMNUMR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B00E))) +#define MCF548X_USB_EPTNR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B010))) +#define MCF548X_USB_IFUR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B014))) +#define MCF548X_USB_IFR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040))) +#define MCF548X_USB_IFR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B042))) +#define MCF548X_USB_IFR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B044))) +#define MCF548X_USB_IFR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B046))) +#define MCF548X_USB_IFR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B048))) +#define MCF548X_USB_IFR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04A))) +#define MCF548X_USB_IFR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04C))) +#define MCF548X_USB_IFR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04E))) +#define MCF548X_USB_IFR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B050))) +#define MCF548X_USB_IFR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B052))) +#define MCF548X_USB_IFR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B054))) +#define MCF548X_USB_IFR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B056))) +#define MCF548X_USB_IFR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B058))) +#define MCF548X_USB_IFR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05A))) +#define MCF548X_USB_IFR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05C))) +#define MCF548X_USB_IFR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05E))) +#define MCF548X_USB_IFR16 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B060))) +#define MCF548X_USB_IFR17 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B062))) +#define MCF548X_USB_IFR18 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B064))) +#define MCF548X_USB_IFR19 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B066))) +#define MCF548X_USB_IFR20 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B068))) +#define MCF548X_USB_IFR21 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06A))) +#define MCF548X_USB_IFR22 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06C))) +#define MCF548X_USB_IFR23 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06E))) +#define MCF548X_USB_IFR24 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B070))) +#define MCF548X_USB_IFR25 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B072))) +#define MCF548X_USB_IFR26 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B074))) +#define MCF548X_USB_IFR27 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B076))) +#define MCF548X_USB_IFR28 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B078))) +#define MCF548X_USB_IFR29 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07A))) +#define MCF548X_USB_IFR30 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07C))) +#define MCF548X_USB_IFR31 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07E))) +#define MCF548X_USB_IFRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040U+((x)*0x002)))) +#define MCF548X_USB_PPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B080))) +#define MCF548X_USB_DPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B082))) +#define MCF548X_USB_CRCECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B084))) +#define MCF548X_USB_BSECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B086))) +#define MCF548X_USB_PIDECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B088))) +#define MCF548X_USB_FRMECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08A))) +#define MCF548X_USB_TXPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08C))) +#define MCF548X_USB_CNTOVR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B08E))) +#define MCF548X_USB_EP0ACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B101))) +#define MCF548X_USB_EP0MPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B102))) +#define MCF548X_USB_EP0IFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B104))) +#define MCF548X_USB_EP0SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B105))) +#define MCF548X_USB_BMRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B106))) +#define MCF548X_USB_BRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B107))) +#define MCF548X_USB_WVALUER (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B108))) +#define MCF548X_USB_WINDEXR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10A))) +#define MCF548X_USB_WLENGTH (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10C))) +#define MCF548X_USB_EP1OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131))) +#define MCF548X_USB_EP2OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B161))) +#define MCF548X_USB_EP3OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B191))) +#define MCF548X_USB_EP4OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C1))) +#define MCF548X_USB_EP5OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F1))) +#define MCF548X_USB_EP6OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B221))) +#define MCF548X_USB_EPnOUTACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132))) +#define MCF548X_USB_EP2OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B162))) +#define MCF548X_USB_EP3OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B192))) +#define MCF548X_USB_EP4OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1C2))) +#define MCF548X_USB_EP5OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1F2))) +#define MCF548X_USB_EP6OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B222))) +#define MCF548X_USB_EPnOUTMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134))) +#define MCF548X_USB_EP2OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B164))) +#define MCF548X_USB_EP3OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B194))) +#define MCF548X_USB_EP4OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C4))) +#define MCF548X_USB_EP5OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F4))) +#define MCF548X_USB_EP6OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B224))) +#define MCF548X_USB_EPnOUTIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135))) +#define MCF548X_USB_EP2OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B165))) +#define MCF548X_USB_EP3OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B195))) +#define MCF548X_USB_EP4OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C5))) +#define MCF548X_USB_EP5OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F5))) +#define MCF548X_USB_EP6OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B225))) +#define MCF548X_USB_EPnOUTSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135U+((x)*0x030)))) +#define MCF548X_USB_EP1OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13E))) +#define MCF548X_USB_EP2OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B16E))) +#define MCF548X_USB_EP3OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B19E))) +#define MCF548X_USB_EP4OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1CE))) +#define MCF548X_USB_EP5OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1FE))) +#define MCF548X_USB_EP6OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B22E))) +#define MCF548X_USB_EPnOUTSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13EU+((x)*0x030)))) +#define MCF548X_USB_EP1INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149))) +#define MCF548X_USB_EP2INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B179))) +#define MCF548X_USB_EP3INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1A9))) +#define MCF548X_USB_EP4INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1D9))) +#define MCF548X_USB_EP5INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B209))) +#define MCF548X_USB_EP6INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B239))) +#define MCF548X_USB_EPnINACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149U+((x)*0x030)))) +#define MCF548X_USB_EP1INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14A))) +#define MCF548X_USB_EP2INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B17A))) +#define MCF548X_USB_EP3INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1AA))) +#define MCF548X_USB_EP4INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1DA))) +#define MCF548X_USB_EP5INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B20A))) +#define MCF548X_USB_EP6INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B23A))) +#define MCF548X_USB_EPnINMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14AU+((x)*0x030)))) +#define MCF548X_USB_EP1INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14C))) +#define MCF548X_USB_EP2INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17C))) +#define MCF548X_USB_EP3INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AC))) +#define MCF548X_USB_EP4INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DC))) +#define MCF548X_USB_EP5INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20C))) +#define MCF548X_USB_EP6INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23C))) +#define MCF548X_USB_EPnINIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14CU+((x)*0x030)))) +#define MCF548X_USB_EP1INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14D))) +#define MCF548X_USB_EP2INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17D))) +#define MCF548X_USB_EP3INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AD))) +#define MCF548X_USB_EP4INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DD))) +#define MCF548X_USB_EP5INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20D))) +#define MCF548X_USB_EP6INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23D))) +#define MCF548X_USB_EPnINSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14DU+((x)*0x030)))) +#define MCF548X_USB_EP1INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15A))) +#define MCF548X_USB_EP2INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B18A))) +#define MCF548X_USB_EP3INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1BA))) +#define MCF548X_USB_EP4INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1EA))) +#define MCF548X_USB_EP5INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B21A))) +#define MCF548X_USB_EP6INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B24A))) +#define MCF548X_USB_EPnINSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15AU+((x)*0x030)))) +#define MCF548X_USB_USBSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B400))) +#define MCF548X_USB_USBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B404))) +#define MCF548X_USB_DRAMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B408))) +#define MCF548X_USB_DRAMDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B40C))) +#define MCF548X_USB_USBISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B410))) +#define MCF548X_USB_USBIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B414))) +#define MCF548X_USB_EP0STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440))) +#define MCF548X_USB_EP1STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B470))) +#define MCF548X_USB_EP2STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A0))) +#define MCF548X_USB_EP3STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D0))) +#define MCF548X_USB_EP4STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B500))) +#define MCF548X_USB_EP5STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B530))) +#define MCF548X_USB_EP6STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B560))) +#define MCF548X_USB_EPnSTAT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440U+((x)*0x030)))) +#define MCF548X_USB_EP0ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444))) +#define MCF548X_USB_EP1ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B474))) +#define MCF548X_USB_EP2ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A4))) +#define MCF548X_USB_EP3ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D4))) +#define MCF548X_USB_EP4ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B504))) +#define MCF548X_USB_EP5ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B534))) +#define MCF548X_USB_EP6ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B564))) +#define MCF548X_USB_EPnISR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444U+((x)*0x030)))) +#define MCF548X_USB_EP0IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448))) +#define MCF548X_USB_EP1IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B478))) +#define MCF548X_USB_EP2IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A8))) +#define MCF548X_USB_EP3IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D8))) +#define MCF548X_USB_EP4IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B508))) +#define MCF548X_USB_EP5IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B538))) +#define MCF548X_USB_EP6IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B568))) +#define MCF548X_USB_EPnIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448U+((x)*0x030)))) +#define MCF548X_USB_EP0FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44C))) +#define MCF548X_USB_EP1FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B47C))) +#define MCF548X_USB_EP2FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4AC))) +#define MCF548X_USB_EP3FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4DC))) +#define MCF548X_USB_EP4FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B50C))) +#define MCF548X_USB_EP5FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B53C))) +#define MCF548X_USB_EP6FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B56C))) +#define MCF548X_USB_EPnFRCFGR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44CU+((x)*0x030)))) +#define MCF548X_USB_EP0FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450))) +#define MCF548X_USB_EP1FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B480))) +#define MCF548X_USB_EP2FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B0))) +#define MCF548X_USB_EP3FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E0))) +#define MCF548X_USB_EP4FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B510))) +#define MCF548X_USB_EP5FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B540))) +#define MCF548X_USB_EP6FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B570))) +#define MCF548X_USB_EPnFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450U+((x)*0x030)))) +#define MCF548X_USB_EP0FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454))) +#define MCF548X_USB_EP1FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B484))) +#define MCF548X_USB_EP2FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B4))) +#define MCF548X_USB_EP3FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E4))) +#define MCF548X_USB_EP4FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B514))) +#define MCF548X_USB_EP5FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B544))) +#define MCF548X_USB_EP6FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B574))) +#define MCF548X_USB_EPnFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454U+((x)*0x030)))) +#define MCF548X_USB_EP0FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458))) +#define MCF548X_USB_EP1FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B488))) +#define MCF548X_USB_EP2FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B8))) +#define MCF548X_USB_EP3FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E8))) +#define MCF548X_USB_EP4FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B518))) +#define MCF548X_USB_EP5FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B548))) +#define MCF548X_USB_EP6FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B578))) +#define MCF548X_USB_EPnFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458U+((x)*0x030)))) +#define MCF548X_USB_EP0FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45C))) +#define MCF548X_USB_EP1FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B48C))) +#define MCF548X_USB_EP2FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4BC))) +#define MCF548X_USB_EP3FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4EC))) +#define MCF548X_USB_EP4FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B51C))) +#define MCF548X_USB_EP5FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B54C))) +#define MCF548X_USB_EP6FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B57C))) +#define MCF548X_USB_EPnFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45CU+((x)*0x030)))) +#define MCF548X_USB_EP0FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460))) +#define MCF548X_USB_EP1FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B490))) +#define MCF548X_USB_EP2FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C0))) +#define MCF548X_USB_EP3FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F0))) +#define MCF548X_USB_EP4FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B520))) +#define MCF548X_USB_EP5FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B550))) +#define MCF548X_USB_EP6FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B580))) +#define MCF548X_USB_EPnFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460U+((x)*0x030)))) +#define MCF548X_USB_EP0FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464))) +#define MCF548X_USB_EP1FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B494))) +#define MCF548X_USB_EP2FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C4))) +#define MCF548X_USB_EP3FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F4))) +#define MCF548X_USB_EP4FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B524))) +#define MCF548X_USB_EP5FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B554))) +#define MCF548X_USB_EP6FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B584))) +#define MCF548X_USB_EPnFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464U+((x)*0x030)))) +#define MCF548X_USB_EP0LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468))) +#define MCF548X_USB_EP1LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B498))) +#define MCF548X_USB_EP2LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C8))) +#define MCF548X_USB_EP3LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F8))) +#define MCF548X_USB_EP4LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B528))) +#define MCF548X_USB_EP5LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B558))) +#define MCF548X_USB_EP6LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B588))) +#define MCF548X_USB_EPnLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468U+((x)*0x030)))) +#define MCF548X_USB_EP0LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46C))) +#define MCF548X_USB_EP1LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B49C))) +#define MCF548X_USB_EP2LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4CC))) +#define MCF548X_USB_EP3LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4FC))) +#define MCF548X_USB_EP4LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B52C))) +#define MCF548X_USB_EP5LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B55C))) +#define MCF548X_USB_EP6LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B58C))) +#define MCF548X_USB_EPnLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46CU+((x)*0x030)))) + +/* Bit definitions and macros for MCF548X_USB_USBAISR */ +#define MCF548X_USB_USBAISR_SETUP (0x01) +#define MCF548X_USB_USBAISR_IN (0x02) +#define MCF548X_USB_USBAISR_OUT (0x04) +#define MCF548X_USB_USBAISR_EPHALT (0x08) +#define MCF548X_USB_USBAISR_TRANSERR (0x10) +#define MCF548X_USB_USBAISR_ACK (0x20) +#define MCF548X_USB_USBAISR_CTROVFL (0x40) +#define MCF548X_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF548X_USB_USBAIMR */ +#define MCF548X_USB_USBAIMR_SETUPEN (0x01) +#define MCF548X_USB_USBAIMR_INEN (0x02) +#define MCF548X_USB_USBAIMR_OUTEN (0x04) +#define MCF548X_USB_USBAIMR_EPHALTEN (0x08) +#define MCF548X_USB_USBAIMR_TRANSERREN (0x10) +#define MCF548X_USB_USBAIMR_ACKEN (0x20) +#define MCF548X_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF548X_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPINFO */ +#define MCF548X_USB_EPINFO_EPDIR (0x01) +#define MCF548X_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) + +/* Bit definitions and macros for MCF548X_USB_CFGAR */ +#define MCF548X_USB_CFGAR_RESERVED (0xA0) +#define MCF548X_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF548X_USB_SPEEDR */ +#define MCF548X_USB_SPEEDR_HS (0x01) +#define MCF548X_USB_SPEEDR_FS (0x02) + +/* Bit definitions and macros for MCF548X_USB_FRMNUMR */ +#define MCF548X_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPTNR */ +#define MCF548X_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) +#define MCF548X_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) +#define MCF548X_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) +#define MCF548X_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) +#define MCF548X_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) +#define MCF548X_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) +#define MCF548X_USB_EPTNR_EPnT1 (0) +#define MCF548X_USB_EPTNR_EPnT2 (1) +#define MCF548X_USB_EPTNR_EPnT3 (2) + +/* Bit definitions and macros for MCF548X_USB_IFUR */ +#define MCF548X_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) +#define MCF548X_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) + +/* Bit definitions and macros for MCF548X_USB_IFRn */ +#define MCF548X_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) +#define MCF548X_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) + +/* Bit definitions and macros for MCF548X_USB_CNTOVR */ +#define MCF548X_USB_CNTOVR_PPCNT (0x01) +#define MCF548X_USB_CNTOVR_DPCNT (0x02) +#define MCF548X_USB_CNTOVR_CRCECNT (0x04) +#define MCF548X_USB_CNTOVR_BSECNT (0x08) +#define MCF548X_USB_CNTOVR_PIDECNT (0x10) +#define MCF548X_USB_CNTOVR_FRMECNT (0x20) +#define MCF548X_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF548X_USB_EP0ACR */ +#define MCF548X_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) +#define MCF548X_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF548X_USB_EP0ACR_TTYPE_ISOC (1) +#define MCF548X_USB_EP0ACR_TTYPE_BULK (2) +#define MCF548X_USB_EP0ACR_TTYPE_INT (3) + +/* Bit definitions and macros for MCF548X_USB_EP0MPSR */ +#define MCF548X_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EP0SR */ +#define MCF548X_USB_EP0SR_HALT (0x01) +#define MCF548X_USB_EP0SR_ACTIVE (0x02) +#define MCF548X_USB_EP0SR_PSTALL (0x04) +#define MCF548X_USB_EP0SR_CCOMP (0x08) +#define MCF548X_USB_EP0SR_TXZERO (0x20) +#define MCF548X_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_BMRTR */ +#define MCF548X_USB_BMRTR_DIR (0x80) +#define MCF548X_USB_BMRTR_TYPE_STANDARD (0x00) +#define MCF548X_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF548X_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF548X_USB_BMRTR_REC_DEVICE (0x00) +#define MCF548X_USB_BMRTR_REC_INTERFACE (0x01) +#define MCF548X_USB_BMRTR_REC_ENDPOINT (0x02) +#define MCF548X_USB_BMRTR_REC_OTHER (0x03) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTACR */ +#define MCF548X_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTMPSR */ +#define MCF548X_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTSR */ +#define MCF548X_USB_EPnOUTSR_HALT (0x01) +#define MCF548X_USB_EPnOUTSR_ACTIVE (0x02) +#define MCF548X_USB_EPnOUTSR_PSTALL (0x04) +#define MCF548X_USB_EPnOUTSR_CCOMP (0x08) +#define MCF548X_USB_EPnOUTSR_TXZERO (0x20) +#define MCF548X_USB_EPnOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPnOUTSFR */ +#define MCF548X_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnINACR */ +#define MCF548X_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnINMPSR */ +#define MCF548X_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +#define MCF548X_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) + +/* Bit definitions and macros for MCF548X_USB_EPnINSR */ +#define MCF548X_USB_EPnINSR_HALT (0x01) +#define MCF548X_USB_EPnINSR_ACTIVE (0x02) +#define MCF548X_USB_EPnINSR_PSTALL (0x04) +#define MCF548X_USB_EPnINSR_CCOMP (0x08) +#define MCF548X_USB_EPnINSR_TXZERO (0x20) +#define MCF548X_USB_EPnINSR_INT (0x80) + +/* Bit definitions and macros for MCF548X_USB_EPnINSFR */ +#define MCF548X_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_USBSR */ +#define MCF548X_USB_USBSR_SUSP (0x00000080) +#define MCF548X_USB_USBSR_ISOERREP (0x0000000F) + +/* Bit definitions and macros for MCF548X_USB_USBCR */ +#define MCF548X_USB_USBCR_RESUME (0x00000001) +#define MCF548X_USB_USBCR_APPLOCK (0x00000002) +#define MCF548X_USB_USBCR_RST (0x00000004) +#define MCF548X_USB_USBCR_RAMEN (0x00000008) +#define MCF548X_USB_USBCR_RAMSPLIT (0x00000020) + +/* Bit definitions and macros for MCF548X_USB_DRAMCR */ +#define MCF548X_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) +#define MCF548X_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) +#define MCF548X_USB_DRAMCR_BSY (0x40000000) +#define MCF548X_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_DRAMDR */ +#define MCF548X_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF548X_USB_USBISR */ +#define MCF548X_USB_USBISR_ISOERR (0x00000001) +#define MCF548X_USB_USBISR_FTUNLCK (0x00000002) +#define MCF548X_USB_USBISR_SUSP (0x00000004) +#define MCF548X_USB_USBISR_RES (0x00000008) +#define MCF548X_USB_USBISR_UPDSOF (0x00000010) +#define MCF548X_USB_USBISR_RSTSTOP (0x00000020) +#define MCF548X_USB_USBISR_SOF (0x00000040) +#define MCF548X_USB_USBISR_MSOF (0x00000080) + +/* Bit definitions and macros for MCF548X_USB_USBIMR */ +#define MCF548X_USB_USBIMR_ISOERR (0x00000001) +#define MCF548X_USB_USBIMR_FTUNLCK (0x00000002) +#define MCF548X_USB_USBIMR_SUSP (0x00000004) +#define MCF548X_USB_USBIMR_RES (0x00000008) +#define MCF548X_USB_USBIMR_UPDSOF (0x00000010) +#define MCF548X_USB_USBIMR_RSTSTOP (0x00000020) +#define MCF548X_USB_USBIMR_SOF (0x00000040) +#define MCF548X_USB_USBIMR_MSOF (0x00000080) + +/* Bit definitions and macros for MCF548X_USB_EPnSTAT */ +#define MCF548X_USB_EPnSTAT_RST (0x00000001) +#define MCF548X_USB_EPnSTAT_FLUSH (0x00000002) +#define MCF548X_USB_EPnSTAT_DIR (0x00000080) +#define MCF548X_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) + +/* Bit definitions and macros for MCF548X_USB_EPnISR */ +#define MCF548X_USB_EPnISR_EOF (0x00000001) +#define MCF548X_USB_EPnISR_EOT (0x00000004) +#define MCF548X_USB_EPnISR_FIFOLO (0x00000010) +#define MCF548X_USB_EPnISR_FIFOHI (0x00000020) +#define MCF548X_USB_EPnISR_ERR (0x00000040) +#define MCF548X_USB_EPnISR_EMT (0x00000080) +#define MCF548X_USB_EPnISR_FU (0x00000100) + +/* Bit definitions and macros for MCF548X_USB_EPnIMR */ +#define MCF548X_USB_EPnIMR_EOF (0x00000001) +#define MCF548X_USB_EPnIMR_EOT (0x00000004) +#define MCF548X_USB_EPnIMR_FIFOLO (0x00000010) +#define MCF548X_USB_EPnIMR_FIFOHI (0x00000020) +#define MCF548X_USB_EPnIMR_ERR (0x00000040) +#define MCF548X_USB_EPnIMR_EMT (0x00000080) +#define MCF548X_USB_EPnIMR_FU (0x00000100) + +/* Bit definitions and macros for MCF548X_USB_EPnFRCFGR */ +#define MCF548X_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) +#define MCF548X_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) + +/* Bit definitions and macros for MCF548X_USB_EPnFSR */ +#define MCF548X_USB_EPnFSR_EMT (0x00010000) +#define MCF548X_USB_EPnFSR_ALRM (0x00020000) +#define MCF548X_USB_EPnFSR_FR (0x00040000) +#define MCF548X_USB_EPnFSR_FU (0x00080000) +#define MCF548X_USB_EPnFSR_OF (0x00100000) +#define MCF548X_USB_EPnFSR_UF (0x00200000) +#define MCF548X_USB_EPnFSR_RXW (0x00400000) +#define MCF548X_USB_EPnFSR_FAE (0x00800000) +#define MCF548X_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) +#define MCF548X_USB_EPnFSR_TXW (0x40000000) +#define MCF548X_USB_EPnFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_EPnFCR */ +#define MCF548X_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_USB_EPnFCR_TXWMSK (0x00040000) +#define MCF548X_USB_EPnFCR_OFMSK (0x00080000) +#define MCF548X_USB_EPnFCR_UFMSK (0x00100000) +#define MCF548X_USB_EPnFCR_RXWMSK (0x00200000) +#define MCF548X_USB_EPnFCR_FAEMSK (0x00400000) +#define MCF548X_USB_EPnFCR_IPMSK (0x00800000) +#define MCF548X_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_USB_EPnFCR_FRM (0x08000000) +#define MCF548X_USB_EPnFCR_TMR (0x10000000) +#define MCF548X_USB_EPnFCR_WFR (0x20000000) +#define MCF548X_USB_EPnFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF548X_USB_EPnFAR */ +#define MCF548X_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnFRP */ +#define MCF548X_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnFWP */ +#define MCF548X_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnLRFP */ +#define MCF548X_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_USB_EPnLWFP */ +#define MCF548X_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PSC_MR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600))) +#define MCF548X_PSC_SR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604))) +#define MCF548X_PSC_CSR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604))) +#define MCF548X_PSC_CR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608))) +#define MCF548X_PSC_RB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_8BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_16BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_TB_AC970 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) +#define MCF548X_PSC_IPCR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) +#define MCF548X_PSC_ACR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) +#define MCF548X_PSC_ISR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) +#define MCF548X_PSC_IMR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) +#define MCF548X_PSC_CTUR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618))) +#define MCF548X_PSC_CTLR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861C))) +#define MCF548X_PSC_IP0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634))) +#define MCF548X_PSC_OPSET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638))) +#define MCF548X_PSC_OPRESET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863C))) +#define MCF548X_PSC_SICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640))) +#define MCF548X_PSC_IRCR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644))) +#define MCF548X_PSC_IRCR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648))) +#define MCF548X_PSC_IRSDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864C))) +#define MCF548X_PSC_IRMDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650))) +#define MCF548X_PSC_IRFDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654))) +#define MCF548X_PSC_RFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658))) +#define MCF548X_PSC_TFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865C))) +#define MCF548X_PSC_RFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664))) +#define MCF548X_PSC_TFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684))) +#define MCF548X_PSC_RFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668))) +#define MCF548X_PSC_TFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688))) +#define MCF548X_PSC_RFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866E))) +#define MCF548X_PSC_TFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868E))) +#define MCF548X_PSC_RFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672))) +#define MCF548X_PSC_TFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692))) +#define MCF548X_PSC_RFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676))) +#define MCF548X_PSC_TFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696))) +#define MCF548X_PSC_RLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867A))) +#define MCF548X_PSC_TLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869A))) +#define MCF548X_PSC_RLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867E))) +#define MCF548X_PSC_TLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869E))) +#define MCF548X_PSC_MR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008700))) +#define MCF548X_PSC_SR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008704))) +#define MCF548X_PSC_CSR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008704))) +#define MCF548X_PSC_CR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008708))) +#define MCF548X_PSC_RB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_8BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_16BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_TB_AC971 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) +#define MCF548X_PSC_IPCR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) +#define MCF548X_PSC_ACR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) +#define MCF548X_PSC_ISR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) +#define MCF548X_PSC_IMR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) +#define MCF548X_PSC_CTUR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008718))) +#define MCF548X_PSC_CTLR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00871C))) +#define MCF548X_PSC_IP1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008734))) +#define MCF548X_PSC_OPSET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008738))) +#define MCF548X_PSC_OPRESET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00873C))) +#define MCF548X_PSC_SICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008740))) +#define MCF548X_PSC_IRCR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008744))) +#define MCF548X_PSC_IRCR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008748))) +#define MCF548X_PSC_IRSDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00874C))) +#define MCF548X_PSC_IRMDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008750))) +#define MCF548X_PSC_IRFDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008754))) +#define MCF548X_PSC_RFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008758))) +#define MCF548X_PSC_TFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00875C))) +#define MCF548X_PSC_RFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008764))) +#define MCF548X_PSC_TFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008784))) +#define MCF548X_PSC_RFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008768))) +#define MCF548X_PSC_TFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008788))) +#define MCF548X_PSC_RFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00876E))) +#define MCF548X_PSC_TFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00878E))) +#define MCF548X_PSC_RFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008772))) +#define MCF548X_PSC_TFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008792))) +#define MCF548X_PSC_RFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008776))) +#define MCF548X_PSC_TFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008796))) +#define MCF548X_PSC_RLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877A))) +#define MCF548X_PSC_TLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879A))) +#define MCF548X_PSC_RLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877E))) +#define MCF548X_PSC_TLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879E))) +#define MCF548X_PSC_MR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008800))) +#define MCF548X_PSC_SR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008804))) +#define MCF548X_PSC_CSR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008804))) +#define MCF548X_PSC_CR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008808))) +#define MCF548X_PSC_RB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_8BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_16BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_TB_AC972 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) +#define MCF548X_PSC_IPCR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) +#define MCF548X_PSC_ACR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) +#define MCF548X_PSC_ISR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) +#define MCF548X_PSC_IMR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) +#define MCF548X_PSC_CTUR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008818))) +#define MCF548X_PSC_CTLR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00881C))) +#define MCF548X_PSC_IP2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008834))) +#define MCF548X_PSC_OPSET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008838))) +#define MCF548X_PSC_OPRESET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00883C))) +#define MCF548X_PSC_SICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008840))) +#define MCF548X_PSC_IRCR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008844))) +#define MCF548X_PSC_IRCR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008848))) +#define MCF548X_PSC_IRSDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00884C))) +#define MCF548X_PSC_IRMDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008850))) +#define MCF548X_PSC_IRFDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008854))) +#define MCF548X_PSC_RFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008858))) +#define MCF548X_PSC_TFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00885C))) +#define MCF548X_PSC_RFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008864))) +#define MCF548X_PSC_TFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008884))) +#define MCF548X_PSC_RFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008868))) +#define MCF548X_PSC_TFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008888))) +#define MCF548X_PSC_RFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00886E))) +#define MCF548X_PSC_TFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00888E))) +#define MCF548X_PSC_RFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008872))) +#define MCF548X_PSC_TFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008892))) +#define MCF548X_PSC_RFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008876))) +#define MCF548X_PSC_TFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008896))) +#define MCF548X_PSC_RLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887A))) +#define MCF548X_PSC_TLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889A))) +#define MCF548X_PSC_RLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887E))) +#define MCF548X_PSC_TLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889E))) +#define MCF548X_PSC_MR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008900))) +#define MCF548X_PSC_SR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008904))) +#define MCF548X_PSC_CSR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008904))) +#define MCF548X_PSC_CR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008908))) +#define MCF548X_PSC_RB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_8BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_16BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_TB_AC973 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) +#define MCF548X_PSC_IPCR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) +#define MCF548X_PSC_ACR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) +#define MCF548X_PSC_ISR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) +#define MCF548X_PSC_IMR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) +#define MCF548X_PSC_CTUR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008918))) +#define MCF548X_PSC_CTLR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00891C))) +#define MCF548X_PSC_IP3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008934))) +#define MCF548X_PSC_OPSET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008938))) +#define MCF548X_PSC_OPRESET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00893C))) +#define MCF548X_PSC_SICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008940))) +#define MCF548X_PSC_IRCR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008944))) +#define MCF548X_PSC_IRCR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008948))) +#define MCF548X_PSC_IRSDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00894C))) +#define MCF548X_PSC_IRMDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008950))) +#define MCF548X_PSC_IRFDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008954))) +#define MCF548X_PSC_RFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008958))) +#define MCF548X_PSC_TFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00895C))) +#define MCF548X_PSC_RFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008964))) +#define MCF548X_PSC_TFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008984))) +#define MCF548X_PSC_RFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008968))) +#define MCF548X_PSC_TFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008988))) +#define MCF548X_PSC_RFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00896E))) +#define MCF548X_PSC_TFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00898E))) +#define MCF548X_PSC_RFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008972))) +#define MCF548X_PSC_TFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008992))) +#define MCF548X_PSC_RFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008976))) +#define MCF548X_PSC_TFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008996))) +#define MCF548X_PSC_RLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897A))) +#define MCF548X_PSC_TLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899A))) +#define MCF548X_PSC_RLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897E))) +#define MCF548X_PSC_TLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899E))) +#define MCF548X_PSC_MR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600U+((x)*0x100)))) +#define MCF548X_PSC_SR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) +#define MCF548X_PSC_CSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) +#define MCF548X_PSC_CR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608U+((x)*0x100)))) +#define MCF548X_PSC_RB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_8BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_16BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_TB_AC97(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) +#define MCF548X_PSC_IPCR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) +#define MCF548X_PSC_ACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) +#define MCF548X_PSC_ISR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) +#define MCF548X_PSC_IMR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) +#define MCF548X_PSC_CTUR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618U+((x)*0x100)))) +#define MCF548X_PSC_CTLR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861CU+((x)*0x100)))) +#define MCF548X_PSC_IP(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634U+((x)*0x100)))) +#define MCF548X_PSC_OPSET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638U+((x)*0x100)))) +#define MCF548X_PSC_OPRESET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863CU+((x)*0x100)))) +#define MCF548X_PSC_SICR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640U+((x)*0x100)))) +#define MCF548X_PSC_IRCR1(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644U+((x)*0x100)))) +#define MCF548X_PSC_IRCR2(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648U+((x)*0x100)))) +#define MCF548X_PSC_IRSDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864CU+((x)*0x100)))) +#define MCF548X_PSC_IRMDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650U+((x)*0x100)))) +#define MCF548X_PSC_IRFDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654U+((x)*0x100)))) +#define MCF548X_PSC_RFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658U+((x)*0x100)))) +#define MCF548X_PSC_TFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865CU+((x)*0x100)))) +#define MCF548X_PSC_RFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664U+((x)*0x100)))) +#define MCF548X_PSC_TFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684U+((x)*0x100)))) +#define MCF548X_PSC_RFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668U+((x)*0x100)))) +#define MCF548X_PSC_TFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688U+((x)*0x100)))) +#define MCF548X_PSC_RFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866EU+((x)*0x100)))) +#define MCF548X_PSC_TFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868EU+((x)*0x100)))) +#define MCF548X_PSC_RFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672U+((x)*0x100)))) +#define MCF548X_PSC_TFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692U+((x)*0x100)))) +#define MCF548X_PSC_RFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676U+((x)*0x100)))) +#define MCF548X_PSC_TFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696U+((x)*0x100)))) +#define MCF548X_PSC_RLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867AU+((x)*0x100)))) +#define MCF548X_PSC_TLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869AU+((x)*0x100)))) +#define MCF548X_PSC_RLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867EU+((x)*0x100)))) +#define MCF548X_PSC_TLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869EU+((x)*0x100)))) + +/* Bit definitions and macros for MCF548X_PSC_MR */ +#define MCF548X_PSC_MR_BC(x) (((x)&0x03)<<0) +#define MCF548X_PSC_MR_PT (0x04) +#define MCF548X_PSC_MR_PM(x) (((x)&0x03)<<3) +#define MCF548X_PSC_MR_ERR (0x20) +#define MCF548X_PSC_MR_RXIRQ (0x40) +#define MCF548X_PSC_MR_RXRTS (0x80) +#define MCF548X_PSC_MR_SB(x) (((x)&0x0F)<<0) +#define MCF548X_PSC_MR_TXCTS (0x10) +#define MCF548X_PSC_MR_TXRTS (0x20) +#define MCF548X_PSC_MR_CM(x) (((x)&0x03)<<6) +#define MCF548X_PSC_MR_PM_MULTI_ADDR (0x1C) +#define MCF548X_PSC_MR_PM_MULTI_DATA (0x18) +#define MCF548X_PSC_MR_PM_NONE (0x10) +#define MCF548X_PSC_MR_PM_FORCE_HI (0x0C) +#define MCF548X_PSC_MR_PM_FORCE_LO (0x08) +#define MCF548X_PSC_MR_PM_ODD (0x04) +#define MCF548X_PSC_MR_PM_EVEN (0x00) +#define MCF548X_PSC_MR_BC_5 (0x00) +#define MCF548X_PSC_MR_BC_6 (0x01) +#define MCF548X_PSC_MR_BC_7 (0x02) +#define MCF548X_PSC_MR_BC_8 (0x03) +#define MCF548X_PSC_MR_CM_NORMAL (0x00) +#define MCF548X_PSC_MR_CM_ECHO (0x40) +#define MCF548X_PSC_MR_CM_LOCAL_LOOP (0x80) +#define MCF548X_PSC_MR_CM_REMOTE_LOOP (0xC0) +#define MCF548X_PSC_MR_SB_STOP_BITS_1 (0x07) +#define MCF548X_PSC_MR_SB_STOP_BITS_15 (0x08) +#define MCF548X_PSC_MR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF548X_PSC_SR */ +#define MCF548X_PSC_SR_ERR (0x0040) +#define MCF548X_PSC_SR_CDE_DEOF (0x0080) +#define MCF548X_PSC_SR_RXRDY (0x0100) +#define MCF548X_PSC_SR_FU (0x0200) +#define MCF548X_PSC_SR_TXRDY (0x0400) +#define MCF548X_PSC_SR_TXEMP_URERR (0x0800) +#define MCF548X_PSC_SR_OE (0x1000) +#define MCF548X_PSC_SR_PE_CRCERR (0x2000) +#define MCF548X_PSC_SR_FE_PHYERR (0x4000) +#define MCF548X_PSC_SR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_CSR */ +#define MCF548X_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) +#define MCF548X_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) +#define MCF548X_PSC_CSR_RCSEL_SYS_CLK (0xD0) +#define MCF548X_PSC_CSR_RCSEL_CTM16 (0xE0) +#define MCF548X_PSC_CSR_RCSEL_CTM (0xF0) +#define MCF548X_PSC_CSR_TCSEL_SYS_CLK (0x0D) +#define MCF548X_PSC_CSR_TCSEL_CTM16 (0x0E) +#define MCF548X_PSC_CSR_TCSEL_CTM (0x0F) + +/* Bit definitions and macros for MCF548X_PSC_CR */ +#define MCF548X_PSC_CR_RXC(x) (((x)&0x03)<<0) +#define MCF548X_PSC_CR_TXC(x) (((x)&0x03)<<2) +#define MCF548X_PSC_CR_MISC(x) (((x)&0x07)<<4) +#define MCF548X_PSC_CR_NONE (0x00) +#define MCF548X_PSC_CR_STOP_BREAK (0x70) +#define MCF548X_PSC_CR_START_BREAK (0x60) +#define MCF548X_PSC_CR_BKCHGINT (0x50) +#define MCF548X_PSC_CR_RESET_ERROR (0x40) +#define MCF548X_PSC_CR_RESET_TX (0x30) +#define MCF548X_PSC_CR_RESET_RX (0x20) +#define MCF548X_PSC_CR_RESET_MR (0x10) +#define MCF548X_PSC_CR_TX_DISABLED (0x08) +#define MCF548X_PSC_CR_TX_ENABLED (0x04) +#define MCF548X_PSC_CR_RX_DISABLED (0x02) +#define MCF548X_PSC_CR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF548X_PSC_TB_8BIT */ +#define MCF548X_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) +#define MCF548X_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) +#define MCF548X_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) +#define MCF548X_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PSC_TB_16BIT */ +#define MCF548X_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PSC_TB_AC97 */ +#define MCF548X_PSC_TB_AC97_SOF (0x00000800) +#define MCF548X_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for MCF548X_PSC_IPCR */ +#define MCF548X_PSC_IPCR_RESERVED (0x0C) +#define MCF548X_PSC_IPCR_CTS (0x0D) +#define MCF548X_PSC_IPCR_D_CTS (0x1C) +#define MCF548X_PSC_IPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF548X_PSC_ACR */ +#define MCF548X_PSC_ACR_IEC0 (0x01) +#define MCF548X_PSC_ACR_CTMS(x) (((x)&0x07)<<4) +#define MCF548X_PSC_ACR_BRG (0x80) + +/* Bit definitions and macros for MCF548X_PSC_ISR */ +#define MCF548X_PSC_ISR_ERR (0x0040) +#define MCF548X_PSC_ISR_DEOF (0x0080) +#define MCF548X_PSC_ISR_TXRDY (0x0100) +#define MCF548X_PSC_ISR_RXRDY_FU (0x0200) +#define MCF548X_PSC_ISR_DB (0x0400) +#define MCF548X_PSC_ISR_IPC (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_IMR */ +#define MCF548X_PSC_IMR_ERR (0x0040) +#define MCF548X_PSC_IMR_DEOF (0x0080) +#define MCF548X_PSC_IMR_TXRDY (0x0100) +#define MCF548X_PSC_IMR_RXRDY_FU (0x0200) +#define MCF548X_PSC_IMR_DB (0x0400) +#define MCF548X_PSC_IMR_IPC (0x8000) + +/* Bit definitions and macros for MCF548X_PSC_IP */ +#define MCF548X_PSC_IP_CTS (0x01) +#define MCF548X_PSC_IP_TGL (0x40) +#define MCF548X_PSC_IP_LWPR_B (0x80) + +/* Bit definitions and macros for MCF548X_PSC_OPSET */ +#define MCF548X_PSC_OPSET_RTS (0x01) + +/* Bit definitions and macros for MCF548X_PSC_OPRESET */ +#define MCF548X_PSC_OPRESET_RTS (0x01) + +/* Bit definitions and macros for MCF548X_PSC_SICR */ +#define MCF548X_PSC_SICR_SIM(x) (((x)&0x07)<<0) +#define MCF548X_PSC_SICR_SHDIR (0x10) +#define MCF548X_PSC_SICR_DTS (0x20) +#define MCF548X_PSC_SICR_AWR (0x40) +#define MCF548X_PSC_SICR_ACRB (0x80) +#define MCF548X_PSC_SICR_SIM_UART (0x00) +#define MCF548X_PSC_SICR_SIM_MODEM8 (0x01) +#define MCF548X_PSC_SICR_SIM_MODEM16 (0x02) +#define MCF548X_PSC_SICR_SIM_AC97 (0x03) +#define MCF548X_PSC_SICR_SIM_SIR (0x04) +#define MCF548X_PSC_SICR_SIM_MIR (0x05) +#define MCF548X_PSC_SICR_SIM_FIR (0x06) + +/* Bit definitions and macros for MCF548X_PSC_IRCR1 */ +#define MCF548X_PSC_IRCR1_SPUL (0x01) +#define MCF548X_PSC_IRCR1_SIPEN (0x02) +#define MCF548X_PSC_IRCR1_FD (0x04) + +/* Bit definitions and macros for MCF548X_PSC_IRCR2 */ +#define MCF548X_PSC_IRCR2_NXTEOF (0x01) +#define MCF548X_PSC_IRCR2_ABORT (0x02) +#define MCF548X_PSC_IRCR2_SIPREQ (0x04) + +/* Bit definitions and macros for MCF548X_PSC_IRMDR */ +#define MCF548X_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF548X_PSC_IRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF548X_PSC_IRFDR */ +#define MCF548X_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFCNT */ +#define MCF548X_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFCNT */ +#define MCF548X_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFSR */ +#define MCF548X_PSC_RFSR_EMT (0x0001) +#define MCF548X_PSC_RFSR_ALARM (0x0002) +#define MCF548X_PSC_RFSR_FU (0x0004) +#define MCF548X_PSC_RFSR_FRMRY (0x0008) +#define MCF548X_PSC_RFSR_OF (0x0010) +#define MCF548X_PSC_RFSR_UF (0x0020) +#define MCF548X_PSC_RFSR_RXW (0x0040) +#define MCF548X_PSC_RFSR_FAE (0x0080) +#define MCF548X_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF548X_PSC_RFSR_TAG (0x1000) +#define MCF548X_PSC_RFSR_TXW (0x4000) +#define MCF548X_PSC_RFSR_IP (0x8000) +#define MCF548X_PSC_RFSR_FRM_BYTE0 (0x0800) +#define MCF548X_PSC_RFSR_FRM_BYTE1 (0x0400) +#define MCF548X_PSC_RFSR_FRM_BYTE2 (0x0200) +#define MCF548X_PSC_RFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF548X_PSC_TFSR */ +#define MCF548X_PSC_TFSR_EMT (0x0001) +#define MCF548X_PSC_TFSR_ALARM (0x0002) +#define MCF548X_PSC_TFSR_FU (0x0004) +#define MCF548X_PSC_TFSR_FRMRY (0x0008) +#define MCF548X_PSC_TFSR_OF (0x0010) +#define MCF548X_PSC_TFSR_UF (0x0020) +#define MCF548X_PSC_TFSR_RXW (0x0040) +#define MCF548X_PSC_TFSR_FAE (0x0080) +#define MCF548X_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF548X_PSC_TFSR_TAG (0x1000) +#define MCF548X_PSC_TFSR_TXW (0x4000) +#define MCF548X_PSC_TFSR_IP (0x8000) +#define MCF548X_PSC_TFSR_FRM_BYTE0 (0x0800) +#define MCF548X_PSC_TFSR_FRM_BYTE1 (0x0400) +#define MCF548X_PSC_TFSR_FRM_BYTE2 (0x0200) +#define MCF548X_PSC_TFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF548X_PSC_RFCR */ +#define MCF548X_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_RFCR_TXW_MSK (0x00040000) +#define MCF548X_PSC_RFCR_OF_MSK (0x00080000) +#define MCF548X_PSC_RFCR_UF_MSK (0x00100000) +#define MCF548X_PSC_RFCR_RXW_MSK (0x00200000) +#define MCF548X_PSC_RFCR_FAE_MSK (0x00400000) +#define MCF548X_PSC_RFCR_IP_MSK (0x00800000) +#define MCF548X_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_PSC_RFCR_FRMEN (0x08000000) +#define MCF548X_PSC_RFCR_TIMER (0x10000000) +#define MCF548X_PSC_RFCR_WRITETAG (0x20000000) +#define MCF548X_PSC_RFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF548X_PSC_TFCR */ +#define MCF548X_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PSC_TFCR_TXW_MSK (0x00040000) +#define MCF548X_PSC_TFCR_OF_MSK (0x00080000) +#define MCF548X_PSC_TFCR_UF_MSK (0x00100000) +#define MCF548X_PSC_TFCR_RXW_MSK (0x00200000) +#define MCF548X_PSC_TFCR_FAE_MSK (0x00400000) +#define MCF548X_PSC_TFCR_IP_MSK (0x00800000) +#define MCF548X_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF548X_PSC_TFCR_FRMEN (0x08000000) +#define MCF548X_PSC_TFCR_TIMER (0x10000000) +#define MCF548X_PSC_TFCR_WRITETAG (0x20000000) +#define MCF548X_PSC_TFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF548X_PSC_RFAR */ +#define MCF548X_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFAR */ +#define MCF548X_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFRP */ +#define MCF548X_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFRP */ +#define MCF548X_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RFWP */ +#define MCF548X_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TFWP */ +#define MCF548X_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RLRFP */ +#define MCF548X_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TLRFP */ +#define MCF548X_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_RLWFP */ +#define MCF548X_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF548X_PSC_TLWFP */ +#define MCF548X_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) + + +/********************************************************************* +* +* 32KByte System SRAM (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_SRAM_SSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC0))) +#define MCF548X_SRAM_TCCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC4))) +#define MCF548X_SRAM_TCCRDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC8))) +#define MCF548X_SRAM_TCCRDW (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFCC))) +#define MCF548X_SRAM_TCCRSEC (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFD0))) + +/* Bit definitions and macros for MCF548X_SRAM_SSCR */ +#define MCF548X_SRAM_SSCR_INLV (0x00010000) + +/* Bit definitions and macros for MCF548X_SRAM_TCCR */ +#define MCF548X_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRDR */ +#define MCF548X_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRDW */ +#define MCF548X_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_SRAM_TCCRSEC */ +#define MCF548X_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) +#define MCF548X_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) +#define MCF548X_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) +#define MCF548X_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PCI_PCIIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B00))) +#define MCF548X_PCI_PCISCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B04))) +#define MCF548X_PCI_PCICCRIR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B08))) +#define MCF548X_PCI_PCICR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B0C))) +#define MCF548X_PCI_PCIBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B10))) +#define MCF548X_PCI_PCIBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B14))) +#define MCF548X_PCI_PCICR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B3C))) +#define MCF548X_PCI_PCIGSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B60))) +#define MCF548X_PCI_PCITBATR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B64))) +#define MCF548X_PCI_PCITBATR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B68))) +#define MCF548X_PCI_PCITCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B6C))) +#define MCF548X_PCI_PCIIW0BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B70))) +#define MCF548X_PCI_PCIIW1BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B74))) +#define MCF548X_PCI_PCIIW2BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B78))) +#define MCF548X_PCI_PCIIWCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B80))) +#define MCF548X_PCI_PCIICR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B84))) +#define MCF548X_PCI_PCIISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B88))) +#define MCF548X_PCI_PCICAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000BF8))) +#define MCF548X_PCI_PCITPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008400))) +#define MCF548X_PCI_PCITSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008404))) +#define MCF548X_PCI_PCITTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008408))) +#define MCF548X_PCI_PCITER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00840C))) +#define MCF548X_PCI_PCITNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008410))) +#define MCF548X_PCI_PCITLWR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008414))) +#define MCF548X_PCI_PCITDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008418))) +#define MCF548X_PCI_PCITSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00841C))) +#define MCF548X_PCI_PCITFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008440))) +#define MCF548X_PCI_PCITFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008444))) +#define MCF548X_PCI_PCITFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008448))) +#define MCF548X_PCI_PCITFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00844C))) +#define MCF548X_PCI_PCITFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008450))) +#define MCF548X_PCI_PCITFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008454))) +#define MCF548X_PCI_PCIRPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008480))) +#define MCF548X_PCI_PCIRSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008484))) +#define MCF548X_PCI_PCIRTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008488))) +#define MCF548X_PCI_PCIRER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00848C))) +#define MCF548X_PCI_PCIRNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008490))) +#define MCF548X_PCI_PCIRDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008498))) +#define MCF548X_PCI_PCIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00849C))) +#define MCF548X_PCI_PCIRFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C0))) +#define MCF548X_PCI_PCIRFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C4))) +#define MCF548X_PCI_PCIRFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C8))) +#define MCF548X_PCI_PCIRFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084CC))) +#define MCF548X_PCI_PCIRFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D0))) +#define MCF548X_PCI_PCIRFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D4))) + +/* Bit definitions and macros for MCF548X_PCI_PCIIDR */ +#define MCF548X_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCISCR */ +#define MCF548X_PCI_PCISCR_M (0x00000002) +#define MCF548X_PCI_PCISCR_B (0x00000004) +#define MCF548X_PCI_PCISCR_SP (0x00000008) +#define MCF548X_PCI_PCISCR_MW (0x00000010) +#define MCF548X_PCI_PCISCR_PER (0x00000040) +#define MCF548X_PCI_PCISCR_S (0x00000100) +#define MCF548X_PCI_PCISCR_F (0x00000200) +#define MCF548X_PCI_PCISCR_C (0x00100000) +#define MCF548X_PCI_PCISCR_66M (0x00200000) +#define MCF548X_PCI_PCISCR_R (0x00400000) +#define MCF548X_PCI_PCISCR_FC (0x00800000) +#define MCF548X_PCI_PCISCR_DP (0x01000000) +#define MCF548X_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) +#define MCF548X_PCI_PCISCR_TS (0x08000000) +#define MCF548X_PCI_PCISCR_TR (0x10000000) +#define MCF548X_PCI_PCISCR_MA (0x20000000) +#define MCF548X_PCI_PCISCR_SE (0x40000000) +#define MCF548X_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCICCRIR */ +#define MCF548X_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) + +/* Bit definitions and macros for MCF548X_PCI_PCICR1 */ +#define MCF548X_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) +#define MCF548X_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIBAR0 */ +#define MCF548X_PCI_PCIBAR0_IO (0x00000001) +#define MCF548X_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) +#define MCF548X_PCI_PCIBAR0_PREF (0x00000008) +#define MCF548X_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF548X_PCI_PCIBAR1 */ +#define MCF548X_PCI_PCIBAR1_IO (0x00000001) +#define MCF548X_PCI_PCIBAR1_PREF (0x00000008) +#define MCF548X_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF548X_PCI_PCICR2 */ +#define MCF548X_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIGSCR */ +#define MCF548X_PCI_PCIGSCR_PR (0x00000001) +#define MCF548X_PCI_PCIGSCR_SEE (0x00001000) +#define MCF548X_PCI_PCIGSCR_PEE (0x00002000) +#define MCF548X_PCI_PCIGSCR_SE (0x10000000) +#define MCF548X_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITBATR0 */ +#define MCF548X_PCI_PCITBATR0_EN (0x00000001) +#define MCF548X_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF548X_PCI_PCITBATR1 */ +#define MCF548X_PCI_PCITBATR1_EN (0x00000001) +#define MCF548X_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF548X_PCI_PCITCR */ +#define MCF548X_PCI_PCITCR_P (0x00010000) +#define MCF548X_PCI_PCITCR_LD (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW0BTAR */ +#define MCF548X_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW1BTAR */ +#define MCF548X_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIW2BTAR */ +#define MCF548X_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) +#define MCF548X_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIIWCR */ +#define MCF548X_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) +#define MCF548X_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) +#define MCF548X_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) +#define MCF548X_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) +#define MCF548X_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) + +/* Bit definitions and macros for MCF548X_PCI_PCIICR */ +#define MCF548X_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) +#define MCF548X_PCI_PCIICR_TAE (0x01000000) +#define MCF548X_PCI_PCIICR_IAE (0x02000000) +#define MCF548X_PCI_PCIICR_REE (0x04000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIISR */ +#define MCF548X_PCI_PCIISR_TA (0x01000000) +#define MCF548X_PCI_PCIISR_IA (0x02000000) +#define MCF548X_PCI_PCIISR_RE (0x04000000) + +/* Bit definitions and macros for MCF548X_PCI_PCICAR */ +#define MCF548X_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) +#define MCF548X_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) +#define MCF548X_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITPSR */ +#define MCF548X_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCITTCR */ +#define MCF548X_PCI_PCITTCR_DI (0x00000001) +#define MCF548X_PCI_PCITTCR_W (0x00000010) +#define MCF548X_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCITER */ +#define MCF548X_PCI_PCITER_NE (0x00010000) +#define MCF548X_PCI_PCITER_IAE (0x00020000) +#define MCF548X_PCI_PCITER_TAE (0x00040000) +#define MCF548X_PCI_PCITER_RE (0x00080000) +#define MCF548X_PCI_PCITER_SE (0x00100000) +#define MCF548X_PCI_PCITER_FEE (0x00200000) +#define MCF548X_PCI_PCITER_ME (0x01000000) +#define MCF548X_PCI_PCITER_BE (0x08000000) +#define MCF548X_PCI_PCITER_CM (0x10000000) +#define MCF548X_PCI_PCITER_RF (0x40000000) +#define MCF548X_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITDCR */ +#define MCF548X_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCITSR */ +#define MCF548X_PCI_PCITSR_IA (0x00010000) +#define MCF548X_PCI_PCITSR_TA (0x00020000) +#define MCF548X_PCI_PCITSR_RE (0x00040000) +#define MCF548X_PCI_PCITSR_SE (0x00080000) +#define MCF548X_PCI_PCITSR_FE (0x00100000) +#define MCF548X_PCI_PCITSR_BE1 (0x00200000) +#define MCF548X_PCI_PCITSR_BE2 (0x00400000) +#define MCF548X_PCI_PCITSR_BE3 (0x00800000) +#define MCF548X_PCI_PCITSR_NT (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCITFSR */ +#define MCF548X_PCI_PCITFSR_EMT (0x00010000) +#define MCF548X_PCI_PCITFSR_ALARM (0x00020000) +#define MCF548X_PCI_PCITFSR_FU (0x00040000) +#define MCF548X_PCI_PCITFSR_FR (0x00080000) +#define MCF548X_PCI_PCITFSR_OF (0x00100000) +#define MCF548X_PCI_PCITFSR_UF (0x00200000) +#define MCF548X_PCI_PCITFSR_RXW (0x00400000) + +/* Bit definitions and macros for MCF548X_PCI_PCITFCR */ +#define MCF548X_PCI_PCITFCR_OF_MSK (0x00080000) +#define MCF548X_PCI_PCITFCR_UF_MSK (0x00100000) +#define MCF548X_PCI_PCITFCR_RXW_MSK (0x00200000) +#define MCF548X_PCI_PCITFCR_FAE_MSK (0x00400000) +#define MCF548X_PCI_PCITFCR_IP_MSK (0x00800000) +#define MCF548X_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCITFAR */ +#define MCF548X_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCITFRPR */ +#define MCF548X_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCITFWPR */ +#define MCF548X_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRPSR */ +#define MCF548X_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCIRTCR */ +#define MCF548X_PCI_PCIRTCR_DI (0x00000001) +#define MCF548X_PCI_PCIRTCR_W (0x00000010) +#define MCF548X_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +#define MCF548X_PCI_PCIRTCR_FB (0x00001000) +#define MCF548X_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +#define MCF548X_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIRER */ +#define MCF548X_PCI_PCIRER_NE (0x00010000) +#define MCF548X_PCI_PCIRER_IAE (0x00020000) +#define MCF548X_PCI_PCIRER_TAE (0x00040000) +#define MCF548X_PCI_PCIRER_RE (0x00080000) +#define MCF548X_PCI_PCIRER_SE (0x00100000) +#define MCF548X_PCI_PCIRER_FEE (0x00200000) +#define MCF548X_PCI_PCIRER_ME (0x01000000) +#define MCF548X_PCI_PCIRER_BE (0x08000000) +#define MCF548X_PCI_PCIRER_CM (0x10000000) +#define MCF548X_PCI_PCIRER_FE (0x20000000) +#define MCF548X_PCI_PCIRER_RF (0x40000000) +#define MCF548X_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRDCR */ +#define MCF548X_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +#define MCF548X_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF548X_PCI_PCIRSR */ +#define MCF548X_PCI_PCIRSR_IA (0x00010000) +#define MCF548X_PCI_PCIRSR_TA (0x00020000) +#define MCF548X_PCI_PCIRSR_RE (0x00040000) +#define MCF548X_PCI_PCIRSR_SE (0x00080000) +#define MCF548X_PCI_PCIRSR_FE (0x00100000) +#define MCF548X_PCI_PCIRSR_BE1 (0x00200000) +#define MCF548X_PCI_PCIRSR_BE2 (0x00400000) +#define MCF548X_PCI_PCIRSR_BE3 (0x00800000) +#define MCF548X_PCI_PCIRSR_NT (0x01000000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFSR */ +#define MCF548X_PCI_PCIRFSR_EMT (0x00010000) +#define MCF548X_PCI_PCIRFSR_ALARM (0x00020000) +#define MCF548X_PCI_PCIRFSR_FU (0x00040000) +#define MCF548X_PCI_PCIRFSR_FR (0x00080000) +#define MCF548X_PCI_PCIRFSR_OF (0x00100000) +#define MCF548X_PCI_PCIRFSR_UF (0x00200000) +#define MCF548X_PCI_PCIRFSR_RXW (0x00400000) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFCR */ +#define MCF548X_PCI_PCIRFCR_OF_MSK (0x00080000) +#define MCF548X_PCI_PCIRFCR_UF_MSK (0x00100000) +#define MCF548X_PCI_PCIRFCR_RXW_MSK (0x00200000) +#define MCF548X_PCI_PCIRFCR_FAE_MSK (0x00400000) +#define MCF548X_PCI_PCIRFCR_IP_MSK (0x00800000) +#define MCF548X_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFAR */ +#define MCF548X_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFRPR */ +#define MCF548X_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) + +/* Bit definitions and macros for MCF548X_PCI_PCIRFWPR */ +#define MCF548X_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) + + +/********************************************************************* +* +* PCI Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_PCIARB_PACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C00))) +#define MCF548X_PCIARB_PASR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C04))) + +/* Bit definitions and macros for MCF548X_PCIARB_PACR */ +#define MCF548X_PCIARB_PACR_INTMPRI (0x00000001) +#define MCF548X_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) +#define MCF548X_PCIARB_PACR_INTMINTEN (0x00010000) +#define MCF548X_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) +#define MCF548X_PCIARB_PACR_PKMD (0x40000000) +#define MCF548X_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF548X_PCIARB_PASR */ +#define MCF548X_PCIARB_PASR_ITLMBK (0x00010000) +#define MCF548X_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) + + +/********************************************************************* +* +* Multi-Channel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DMA_TASKBAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008000))) +#define MCF548X_DMA_CP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008004))) +#define MCF548X_DMA_EP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008008))) +#define MCF548X_DMA_VP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00800C))) +#define MCF548X_DMA_DIPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008014))) +#define MCF548X_DMA_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008018))) +#define MCF548X_DMA_TCR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801C))) +#define MCF548X_DMA_TCR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801E))) +#define MCF548X_DMA_TCR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008020))) +#define MCF548X_DMA_TCR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008022))) +#define MCF548X_DMA_TCR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008024))) +#define MCF548X_DMA_TCR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008026))) +#define MCF548X_DMA_TCR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008028))) +#define MCF548X_DMA_TCR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802A))) +#define MCF548X_DMA_TCR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802C))) +#define MCF548X_DMA_TCR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802E))) +#define MCF548X_DMA_TCR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008030))) +#define MCF548X_DMA_TCR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008032))) +#define MCF548X_DMA_TCR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008034))) +#define MCF548X_DMA_TCR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008036))) +#define MCF548X_DMA_TCR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008038))) +#define MCF548X_DMA_TCR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00803A))) +#define MCF548X_DMA_TCRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801CU+((x)*0x002)))) +#define MCF548X_DMA_IMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00805C))) +#define MCF548X_DMA_PTDDBG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008080))) + +/* Bit definitions and macros for MCF548X_DMA_DIPR */ +#define MCF548X_DMA_DIPR_TASK0 (0x00000001) +#define MCF548X_DMA_DIPR_TASK1 (0x00000002) +#define MCF548X_DMA_DIPR_TASK2 (0x00000004) +#define MCF548X_DMA_DIPR_TASK3 (0x00000008) +#define MCF548X_DMA_DIPR_TASK4 (0x00000010) +#define MCF548X_DMA_DIPR_TASK5 (0x00000020) +#define MCF548X_DMA_DIPR_TASK6 (0x00000040) +#define MCF548X_DMA_DIPR_TASK7 (0x00000080) +#define MCF548X_DMA_DIPR_TASK8 (0x00000100) +#define MCF548X_DMA_DIPR_TASK9 (0x00000200) +#define MCF548X_DMA_DIPR_TASK10 (0x00000400) +#define MCF548X_DMA_DIPR_TASK11 (0x00000800) +#define MCF548X_DMA_DIPR_TASK12 (0x00001000) +#define MCF548X_DMA_DIPR_TASK13 (0x00002000) +#define MCF548X_DMA_DIPR_TASK14 (0x00004000) +#define MCF548X_DMA_DIPR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF548X_DMA_DIMR */ +#define MCF548X_DMA_DIMR_TASK0 (0x00000001) +#define MCF548X_DMA_DIMR_TASK1 (0x00000002) +#define MCF548X_DMA_DIMR_TASK2 (0x00000004) +#define MCF548X_DMA_DIMR_TASK3 (0x00000008) +#define MCF548X_DMA_DIMR_TASK4 (0x00000010) +#define MCF548X_DMA_DIMR_TASK5 (0x00000020) +#define MCF548X_DMA_DIMR_TASK6 (0x00000040) +#define MCF548X_DMA_DIMR_TASK7 (0x00000080) +#define MCF548X_DMA_DIMR_TASK8 (0x00000100) +#define MCF548X_DMA_DIMR_TASK9 (0x00000200) +#define MCF548X_DMA_DIMR_TASK10 (0x00000400) +#define MCF548X_DMA_DIMR_TASK11 (0x00000800) +#define MCF548X_DMA_DIMR_TASK12 (0x00001000) +#define MCF548X_DMA_DIMR_TASK13 (0x00002000) +#define MCF548X_DMA_DIMR_TASK14 (0x00004000) +#define MCF548X_DMA_DIMR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF548X_DMA_IMCR */ +#define MCF548X_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) +#define MCF548X_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) +#define MCF548X_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) +#define MCF548X_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) +#define MCF548X_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) +#define MCF548X_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) +#define MCF548X_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) +#define MCF548X_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) +#define MCF548X_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) +#define MCF548X_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) +#define MCF548X_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) +#define MCF548X_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) +#define MCF548X_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) +#define MCF548X_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) +#define MCF548X_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) +#define MCF548X_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) +#define MCF548X_DMA_IMCR_SRC16_FEC0RX (0x00000000) +#define MCF548X_DMA_IMCR_SRC17_FEC0TX (0x00000000) +#define MCF548X_DMA_IMCR_SRC18_FEC0RX (0x00000020) +#define MCF548X_DMA_IMCR_SRC19_FEC0TX (0x00000080) +#define MCF548X_DMA_IMCR_SRC20_FEC1RX (0x00000100) +#define MCF548X_DMA_IMCR_SRC21_DREQ1 (0x00000000) +#define MCF548X_DMA_IMCR_SRC21_FEC1TX (0x00000400) +#define MCF548X_DMA_IMCR_SRC22_FEC0RX (0x00001000) +#define MCF548X_DMA_IMCR_SRC23_FEC0TX (0x00004000) +#define MCF548X_DMA_IMCR_SRC24_CTM0 (0x00010000) +#define MCF548X_DMA_IMCR_SRC24_FEC1RX (0x00020000) +#define MCF548X_DMA_IMCR_SRC25_CTM1 (0x00040000) +#define MCF548X_DMA_IMCR_SRC25_FEC1TX (0x00080000) +#define MCF548X_DMA_IMCR_SRC26_USBEP4 (0x00000000) +#define MCF548X_DMA_IMCR_SRC26_CTM2 (0x00200000) +#define MCF548X_DMA_IMCR_SRC27_USBEP5 (0x00000000) +#define MCF548X_DMA_IMCR_SRC27_CTM3 (0x00800000) +#define MCF548X_DMA_IMCR_SRC28_USBEP6 (0x00000000) +#define MCF548X_DMA_IMCR_SRC28_CTM4 (0x01000000) +#define MCF548X_DMA_IMCR_SRC28_DREQ1 (0x02000000) +#define MCF548X_DMA_IMCR_SRC28_PSC2RX (0x03000000) +#define MCF548X_DMA_IMCR_SRC29_DREQ1 (0x04000000) +#define MCF548X_DMA_IMCR_SRC29_CTM5 (0x08000000) +#define MCF548X_DMA_IMCR_SRC29_PSC2TX (0x0C000000) +#define MCF548X_DMA_IMCR_SRC30_FEC1RX (0x00000000) +#define MCF548X_DMA_IMCR_SRC30_CTM6 (0x10000000) +#define MCF548X_DMA_IMCR_SRC30_PSC3RX (0x30000000) +#define MCF548X_DMA_IMCR_SRC31_FEC1TX (0x00000000) +#define MCF548X_DMA_IMCR_SRC31_CTM7 (0x80000000) +#define MCF548X_DMA_IMCR_SRC31_PSC3TX (0xC0000000) + + +/********************************************************************* +* +* Multi-Channel DMA External Requests (DMA_EREQ) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF548X_DMA_EREQ_EREQBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00))) +#define MCF548X_DMA_EREQ_EREQMASK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04))) +#define MCF548X_DMA_EREQ_EREQCTRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08))) +#define MCF548X_DMA_EREQ_EREQBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D10))) +#define MCF548X_DMA_EREQ_EREQMASK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D14))) +#define MCF548X_DMA_EREQ_EREQCTRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D18))) +#define MCF548X_DMA_EREQ_EREQBAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00U+((x)*0x010)))) +#define MCF548X_DMA_EREQ_EREQMASK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04U+((x)*0x010)))) +#define MCF548X_DMA_EREQ_EREQCTRL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08U+((x)*0x010)))) + +/* Bit definitions and macros for MCF548X_DMA_EREQ_EREQCTRL */ +#define MCF548X_DMA_EREQ_EREQCTRL_EN (0x00000001) +#define MCF548X_DMA_EREQ_EREQCTRL_SYNC (0x00000002) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) +#define MCF548X_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) +#define MCF548X_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) +#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) +#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) + +/*********************************************************************/ + +#endif /* __MCF548X_H__ */ diff --git a/bsps/m68k/include/mvme16x_hw.h b/bsps/m68k/include/mvme16x_hw.h new file mode 100644 index 0000000000..2ac595a0fa --- /dev/null +++ b/bsps/m68k/include/mvme16x_hw.h @@ -0,0 +1,274 @@ +/** + * @file + * + * @ingroup m68k_mvme + * + * @brief MVME16x IO definitions + */ + +/* mvme16x_hw.h + * + * This include file contains all MVME16x board IO definitions + * and was derived by combining the common items in the + * mvme162 and mvme167 BSPs. + * + * COPYRIGHT (c) 1989-2000. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __MVME16xHW_h +#define __MVME16xHW_h + +#include <bsp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup m68k_mvme MVME16X IO Support + * + * @ingroup m68k_shared + * + * @brief IO Support Package + */ + +struct rtems_bsdnet_ifconfig; +int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach + +/* + * This is NOT the base address of local RAM! + * This is the base local address of the VMEbus short I/O space. A local + * access to this space results in a A16 VMEbus I/O cycle. This base address + * is NOT configurable on the MVME167, although the types of VMEbus short I/O + * cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address + * range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The + * GCSRs of other boards are accessible only through the VMEbus short I/O + * space. See pages 2-45 and 2-7. + */ +#define BOARD_BASE_ADDRESS 0xFFFF0000 + +/* + * This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of + * other MVMEs in the group, i.e. it represents the offset of the GCSRs in the + * VMEbus short I/O space. It also should represent the group address of this + * MVME167! The group address is configurable, and must match the address + * programmed into the MVME167 through the 167Bug monitor. 0xCC is the address + * recommended by Motorola. It is arbitrary. + * See pages 2-42 and 2-97 to 2-104. + */ +#define GROUP_BASE_ADDRESS 0x0000CC00 + +/* + * Representation of the VMEchip2 LCSR. + * Could be made more detailed. + */ + +typedef volatile struct { + unsigned long slave_adr[2]; + unsigned long slave_trn[2]; + unsigned long slave_ctl; + unsigned long mastr_adr[4]; + unsigned long mastr_trn; + unsigned long mastr_att; + unsigned long mastr_ctl; + unsigned long dma_ctl_1; + unsigned long dma_ctl_2; + unsigned long dma_loc_cnt; + unsigned long dma_vme_cnt; + unsigned long dma_byte_cnt; + unsigned long dma_adr_cnt; + unsigned long dma_status; + unsigned long to_ctl; + unsigned long timer_cmp_1; + unsigned long timer_cnt_1; + unsigned long timer_cmp_2; + unsigned long timer_cnt_2; + unsigned long board_ctl; + unsigned long prescaler_cnt; + unsigned long intr_stat; + unsigned long intr_ena; + unsigned long intr_soft_set; + unsigned long intr_clear; + unsigned long intr_level[4]; + unsigned long vector_base; +} lcsr_regs; + +/* + * Base address of VMEchip2 LCSR + * Not configurable on the MVME167. + * XXX what about 162? + */ +#define lcsr ((lcsr_regs * const) 0xFFF40000) + +/* + * Vector numbers for the interrupts from the VMEchip2. Use the values + * "recommended" by Motorola. + * See pages 2-70 to 2-92, and table 2-3. + */ + +/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */ +#define MASK_INT 0x00800000 + +/* The content of VBR0 corresponds to "X" in table 2-3 */ +#define VBR0 0x6 + +/* The content of VBR1 corresponds to "Y" in table 2-3 */ +#define VBR1 0x7 + +/* + * Representation of the PCCchip2 + */ +typedef volatile struct pccchip2_regs_ { + unsigned char chip_id; /* 0xFFF42000 */ + unsigned char chip_revision; /* 0xFFF42001 */ + unsigned char gen_control; /* 0xFFF42002 */ + unsigned char vector_base; /* 0xFFF42003 */ + unsigned long timer_cmp_1; /* 0xFFF42004 */ + unsigned long timer_cnt_1; /* 0xFFF42008 */ + unsigned long timer_cmp_2; /* 0xFFF4200C */ + unsigned long timer_cnt_2; /* 0xFFF42010 */ + unsigned char LSB_prescaler_count;/* 0xFFF42014 */ + unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ + unsigned char timer_ctl_2; /* 0xFFF42016 */ + unsigned char timer_ctl_1; /* 0xFFF42017 */ + unsigned char gpi_int_ctl; /* 0xFFF42018 */ + unsigned char gpio_ctl; /* 0xFFF42019 */ + unsigned char timer_int_ctl_2; /* 0xFFF4201A */ + unsigned char timer_int_ctl_1; /* 0xFFF4201B */ + unsigned char SCC_error; /* 0xFFF4201C */ + unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ + unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ + unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ + unsigned char reserved1[3]; + unsigned char modem_piack; /* 0xFFF42023 */ + unsigned char reserved2; + unsigned char tx_piack; /* 0xFFF42025 */ + unsigned char reserved3; + unsigned char rx_piack; /* 0xFFF42027 */ + unsigned char LANC_error; /* 0xFFF42028 */ + unsigned char reserved4; + unsigned char LANC_int_ctl; /* 0xFFF4202A */ + unsigned char LANC_berr_ctl; /* 0xFFF4202B */ + unsigned char SCSI_error; /* 0xFFF4202C */ + unsigned char reserved5[2]; + unsigned char SCSI_int_ctl; /* 0xFFF4202F */ + unsigned char print_ack_int_ctl; /* 0xFFF42030 */ + unsigned char print_fault_int_ctl;/* 0xFFF42031 */ + unsigned char print_sel_int_ctl; /* 0xFFF42032 */ + unsigned char print_pe_int_ctl; /* 0xFFF42033 */ + unsigned char print_busy_int_ctl; /* 0xFFF42034 */ + unsigned char reserved6; + unsigned char print_input_status; /* 0xFFF42036 */ + unsigned char print_ctl; /* 0xFFF42037 */ + unsigned char chip_speed; /* 0xFFF42038 */ + unsigned char reserved7; + unsigned char print_data; /* 0xFFF4203A */ + unsigned char reserved8[3]; + unsigned char int_level; /* 0xFFF4203E */ + unsigned char int_mask; /* 0xFFF4203F */ +} pccchip2_regs; + +/* + * Base address of the PCCchip2. + * This is not configurable in the MVME167. + */ +#define pccchip2 ((pccchip2_regs * const) 0xFFF42000) + +/* + * On the MVME162, we have the mcchip and the pccchip2 on + * the 167. They are similar but different enough where + * we have to reconcile them later. + */ + +/* + * Vector numbers for the interrupts from the PCCchip2. Use the values + * "recommended" by Motorola. + * See page 3-15. + */ +#define PCCCHIP2_VBR 0x5 + +/* + * The following registers are located in the VMEbus short + * IO space and respond to address modifier codes $29 and $2D. + * On FORCE CPU use address gcsr_vme and device /dev/vme16d32. + */ + +typedef volatile struct { + unsigned char chip_revision; + unsigned char chip_id; + unsigned char lmsig; + unsigned char board_scr; + unsigned short gpr[6]; +} gcsr_regs; + +#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS)) +#define gcsr ((gcsr_regs * const) 0xFFF40100) + +/* + * Representation of 82596CA LAN controller: Memory Map + */ +typedef volatile struct i82596_regs_ { + unsigned short port_lower; /* 0xFFF46000 */ + unsigned short port_upper; /* 0xFFF46002 */ + unsigned long chan_attn; /* 0xFFF46004 */ +} i82596_regs; + +/* + * Base address of the 82596. + */ + +#define i82596 ((i82596_regs * const) 0xFFF46000) + +/* + * Representation of initialization data in NVRAM + */ + +#if defined(mvme167) +typedef volatile struct nvram_config_ { + unsigned char cache_mode; /* 0xFFFC0000 */ + unsigned char console_mode; /* 0xFFFC0001 */ + unsigned char console_printk_port; /* 0xFFFC0002 */ + unsigned char pad1; /* 0xFFFC0003 */ + unsigned long ipaddr; /* 0xFFFC0004 */ + unsigned long netmask; /* 0xFFFC0008 */ + unsigned char enaddr[6]; /* 0xFFFC000C */ + unsigned short processor_id; /* 0xFFFC0012 */ + unsigned long rma_start; /* 0xFFFC0014 */ + unsigned long vma_start; /* 0xFFFC0018 */ + unsigned long ramsize; /* 0xFFFC001C */ +} nvram_config; + +/* + * Pointer to the base of User Area NVRAM + */ + +#define nvram ((nvram_config * const) 0xFFFC0000) + +#endif + +/* + * Flag to indicate if J1-4 is on (and parameters should be + * sought in User Area NVRAM) + * + * NOTE: If NVRAM has bad settings, the you want to disable this + * on the MVME167. + */ +#if defined(mvme167) + #define NVRAM_CONFIGURE \ + ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) ) +#else + #define NVRAM_CONFIGURE 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5206elite/headers.am b/bsps/m68k/mcf5206elite/headers.am new file mode 100644 index 0000000000..1faf6942f8 --- /dev/null +++ b/bsps/m68k/mcf5206elite/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/ds1307.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2c.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/i2cdrv.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/nvram.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5206elite/include/tm27.h diff --git a/bsps/m68k/mcf5206elite/include/bsp.h b/bsps/m68k/mcf5206elite/include/bsp.h new file mode 100644 index 0000000000..47c7e8c745 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/bsp.h @@ -0,0 +1,181 @@ +/* + * Board Support Package for MCF5206eLITE evaluation board + * BSP definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H +#define LIBBSP_M68K_MCF5206ELITE_BSP_H + +#include "mcf5206/mcf5206e.h" + +/*** Board resources allocation ***/ + +/* + * To achieve some compatibility with dBUG monitor, we use the same + * memory resources allocation as it is used in dBUG. + * + * If this definitions will be changed, change the linker script also. + */ + +/* Memory mapping */ +/* CS0: Boot Flash */ +#define BSP_MEM_ADDR_FLASH (0xFFE00000) +#define BSP_MEM_SIZE_FLASH (1*1024*1024) +#define BSP_MEM_MASK_FLASH (MCF5206E_CSMR_MASK_1M) + +/* CS2: External SRAM */ +#define BSP_MEM_ADDR_ESRAM (0x30000000) +#define BSP_MEM_SIZE_ESRAM (1*1024*1024) +#define BSP_MEM_MASK_ESRAM (MCF5206E_CSMR_MASK_1M) + +/* CS3: General-Purpose I/O register */ +#define BSP_MEM_ADDR_GPIO (0x40000000) +#define BSP_MEM_SIZE_GPIO (64*1024) +#define BSP_MEM_MASK_GPIO (MCF5206E_CSMR_MASK_64K) + +/* DRAM0: Dynamic RAM */ +#define BSP_MEM_ADDR_DRAM (0x00000000) +#define BSP_MEM_SIZE_DRAM (16*1024*1024) +#define BSP_MEM_MASK_DRAM (MCF5206E_DCMR_MASK_16M) + +/* On-chip SRAM */ +#define BSP_MEM_ADDR_SRAM (0x20000000) +#define BSP_MEM_SIZE_SRAM (8*1024) + +/* On-chip peripherial registers */ +#define BSP_MEM_ADDR_IMM (0x10000000) +#define BSP_MEM_SIZE_IMM (1*1024) +#define MBAR BSP_MEM_ADDR_IMM + +/* Interrupt vector assignment */ +#define BSP_INTVEC_AVEC1 (25) +#define BSP_INTLVL_AVEC1 (1) +#define BSP_INTPRIO_AVEC1 (3) + +#define BSP_INTVEC_AVEC2 (26) +#define BSP_INTLVL_AVEC2 (2) +#define BSP_INTPRIO_AVEC2 (3) + +#define BSP_INTVEC_AVEC3 (27) +#define BSP_INTLVL_AVEC3 (3) +#define BSP_INTPRIO_AVEC3 (3) + +#define BSP_INTVEC_AVEC4 (28) +#define BSP_INTLVL_AVEC4 (4) +#define BSP_INTPRIO_AVEC4 (3) + +#define BSP_INTVEC_AVEC5 (29) +#define BSP_INTLVL_AVEC5 (5) +#define BSP_INTPRIO_AVEC5 (3) + +#define BSP_INTVEC_AVEC6 (30) +#define BSP_INTLVL_AVEC6 (6) +#define BSP_INTPRIO_AVEC6 (3) + +#define BSP_INTVEC_AVEC7 (31) +#define BSP_INTLVL_AVEC7 (7) +#define BSP_INTPRIO_AVEC7 (3) + +#define BSP_INTVEC_TIMER1 (BSP_INTVEC_AVEC5) +#define BSP_INTLVL_TIMER1 (BSP_INTLVL_AVEC5) +#define BSP_INTPRIO_TIMER1 (2) + +#define BSP_INTVEC_TIMER2 (BSP_INTVEC_AVEC6) +#define BSP_INTLVL_TIMER2 (BSP_INTLVL_AVEC6) +#define BSP_INTPRIO_TIMER2 (2) + +#define BSP_INTVEC_MBUS (BSP_INTVEC_AVEC4) +#define BSP_INTLVL_MBUS (BSP_INTLVL_AVEC4) +#define BSP_INTPRIO_MBUS (2) + +#define BSP_INTVEC_UART1 (64) +#define BSP_INTLVL_UART1 (4) +#define BSP_INTPRIO_UART1 (0) + +#define BSP_INTVEC_UART2 (65) +#define BSP_INTLVL_UART2 (4) +#define BSP_INTPRIO_UART2 (1) + +#define BSP_INTVEC_DMA0 (66) +#define BSP_INTLVL_DMA0 (3) +#define BSP_INTPRIO_DMA0 (1) + +#define BSP_INTVEC_DMA1 (67) +#define BSP_INTLVL_DMA1 (3) +#define BSP_INTPRIO_DMA1 (2) + +/* Location of DS1307 Real-Time Clock/NVRAM chip */ +#define DS1307_I2C_BUS_NUMBER (0) + +#ifndef ASM + +#include <bspopts.h> +#include <rtems.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* System frequency */ +#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY) +extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */ + +/* MBUS I2C bus clock default frequency */ +#define BSP_MBUS_FREQUENCY (16000) + +/* Number of I2C buses supported in this board */ +#define I2C_NUMBER_OF_BUSES (1) + +/* I2C bus selection */ +#define I2C_SELECT_BUS(bus) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { register uint32_t _delay=(microseconds); \ + register uint32_t _tmp=123; \ + __asm__ volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for BSP methods that cross file boundaries + */ +void Init5206e(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/m68k/mcf5206elite/include/ds1307.h b/bsps/m68k/mcf5206elite/include/ds1307.h new file mode 100644 index 0000000000..8e5636a0c8 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/ds1307.h @@ -0,0 +1,41 @@ +/* + * This file contains the definitions for Dallas Semiconductor + * DS1307/DS1308 serial real-time clock/NVRAM. + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTC_DS1307__ +#define __RTC_DS1307__ + +#define DS1307_I2C_ADDRESS (0xD0) /* I2C bus address assigned to DS1307 */ + +#define DS1307_SECOND (0x00) +#define DS1307_SECOND_HALT (0x80) /* High bit is a Clock Halt bit */ +#define DS1307_MINUTE (0x01) +#define DS1307_HOUR (0x02) +#define DS1307_HOUR_12 (0x40) /* 12-hour mode */ +#define DS1307_HOUR_PM (0x20) /* PM in 12-hour mode */ +#define DS1307_DAY_OF_WEEK (0x03) +#define DS1307_DAY (0x04) +#define DS1307_MONTH (0x05) +#define DS1307_YEAR (0x06) +#define DS1307_CONTROL (0x07) +#define DS1307_CONTROL_OUT (0x80) /* Output control */ +#define DS1307_CONTROL_SQWE (0x10) /* Sqware Wave Enable */ +#define DS1307_CONTROL_RS_1 (0x00) /* Rate select: 1 Hz */ +#define DS1307_CONTROL_RS_4096 (0x01) /* Rate select: 4096 Hz */ +#define DS1307_CONTROL_RS_8192 (0x02) /* Rate select: 8192 Hz */ +#define DS1307_CONTROL_RS_32768 (0x03) /* Rate select; 32768 Hz */ + +#define DS1307_NVRAM_START (0x08) /* Start location of non-volatile memory */ +#define DS1307_NVRAM_END (0x3F) /* End location of non-volatile memory */ +#define DS1307_NVRAM_SIZE (56) /* Size of non-volatile memory */ + +#endif __RTC_DS1307__ diff --git a/bsps/m68k/mcf5206elite/include/i2c.h b/bsps/m68k/mcf5206elite/include/i2c.h new file mode 100644 index 0000000000..8bec067a3a --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/i2c.h @@ -0,0 +1,243 @@ +/* + * Generic I2C bus interface for RTEMS + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTEMS__I2C_H__ +#define __RTEMS__I2C_H__ + +#include <rtems.h> +#include <bsp.h> +/* This header file define the generic interface to i2c buses available in + * system. This interface may be used by user applications or i2c-device + * drivers (like RTC, NVRAM, etc). + * + * Functions i2c_initialize and i2c_transfer declared in this header usually + * implemented in particular board support package. Usually this + * implementation is a simple wrapper or multiplexor to I2C controller + * driver which is available in system. It may be generic "software + * controller" I2C driver which control SDA and SCL signals directly (if SDA + * and SCL is general-purpose I/O pins), or driver for hardware I2C + * controller (standalone or integrated with processors: MBus controller in + * ColdFire processors, I2C controller in PowerQUICC and so on). + * + * i2c_transfer is a very generic low-level function. Higher-level function + * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. + */ + +/* I2C Bus Number type */ +typedef uint32_t i2c_bus_number; + +/* I2C device address */ +typedef uint16_t i2c_address; + +/* I2C error codes generated during message transfer */ +typedef enum i2c_message_status { + I2C_SUCCESSFUL = 0, + I2C_TIMEOUT, + I2C_NO_DEVICE, + I2C_ARBITRATION_LOST, + I2C_NO_ACKNOWLEDGE, + I2C_NO_DATA, + I2C_RESOURCE_NOT_AVAILABLE +} i2c_message_status; + +/* I2C Message */ +typedef struct i2c_message { + i2c_address addr; /* I2C slave device address */ + uint16_t flags; /* message flags (see below) */ + i2c_message_status status; /* message transfer status code */ + uint16_t len; /* Number of bytes to read or write */ + uint8_t *buf; /* pointer to data array */ +} i2c_message; + +/* I2C message flag */ +#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ +#define I2C_MSG_WR (0x02) /* transfer direction for this message + from master to slave */ +#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message + is failed */ +/* Type for function which is called when transfer over I2C bus is finished */ +typedef void (*i2c_transfer_done) (void *arg); + +/* i2c_initialize -- + * I2C driver initialization. This function usually called on device + * driver initialization state, before initialization task. All I2C + * buses are initialized; reasonable slow data transfer rate is + * selected for each bus. + * + * PARAMETERS: + * major - I2C device major number + * minor - I2C device minor number + * arg - RTEMS driver initialization argument + * + * RETURNS: + * RTEMS status code + */ +rtems_device_driver +i2c_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* i2c_select_clock_rate -- + * select I2C bus clock rate for specified bus. Some bus controller do not + * allow to select arbitrary clock rate; in this case nearest possible + * slower clock rate is selected. + * + * PARAMETERS: + * bus - I2C bus number + * bps - data transfer rate for this bytes in bits per second + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, + * RTEMS_INVALID_NUMBER, if wrong bus number is specified, + * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection + * or specified data transfer rate could not be used. + */ +rtems_status_code +i2c_select_clock_rate(i2c_bus_number bus, int bps); + +/* i2c_transfer -- + * Initiate multiple-messages transfer over specified I2C bus or + * put request into queue if bus or some other resource is busy. (This + * is non-blocking function). + * + * PARAMETERS: + * bus - I2C bus number + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code if something failed. + */ +rtems_status_code +i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void * done_arg_ptr); + +/* i2c_transfer_wait -- + * Initiate I2C bus transfer and block until this transfer will be + * finished. This function wait the semaphore if system in + * SYSTEM_STATE_UP state, or poll done flag in other states. + * + * PARAMETERS: + * bus - I2C bus number + * msg - pointer to transfer messages array + * nmsg - number of messages in transfer + * + * RETURNS: + * I2C_SUCCESSFUL, if transfer finished successfully, + * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, + * value of status field of first error-finished message in transfer, + * if something wrong. + */ +i2c_message_status +i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); + +/* i2c_poll -- + * Poll I2C bus controller for events and hanle it. This function is + * used when I2C driver operates in poll-driven mode. + * + * PARAMETERS: + * bus - bus number to be polled + * + * RETURNS: + * none + */ +void +i2c_poll(i2c_bus_number bus); + +/* i2c_write -- + * Send single message over specified I2C bus to addressed device and + * wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - data to be sent to device + * size - data buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrbyte -- + * Send single one-byte long message over specified I2C bus to + * addressed device and wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - byte message to be sent to device + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); + +/* i2c_read -- + * receive single message over specified I2C bus from addressed device. + * This call will wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - buffer for received message + * size - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrrd -- + * Send message over I2C bus to specified device and receive message + * from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * bufw - data to be sent to device + * sizew - send data buffer size + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, + void *bufr, int sizer); + +/* i2c_wbrd -- + * Send one-byte message over I2C bus to specified device and receive + * message from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - one-byte message to be sent over I2C bus + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, + void *bufr, int sizer); + +#endif diff --git a/bsps/m68k/mcf5206elite/include/i2cdrv.h b/bsps/m68k/mcf5206elite/include/i2cdrv.h new file mode 100644 index 0000000000..4b4a1ec141 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/i2cdrv.h @@ -0,0 +1,35 @@ +/* + * i2cdrv.h -- I2C bus driver prototype and definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __I2CDRV_H__ +#define __I2CDRV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_DRIVER_TABLE_ENTRY \ + { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL } + +/* i2cdrv_initialize -- + * I2C driver initialization (rtems I/O driver primitive) + */ +rtems_device_driver +i2cdrv_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __I2CDRV_H__ */ diff --git a/bsps/m68k/mcf5206elite/include/nvram.h b/bsps/m68k/mcf5206elite/include/nvram.h new file mode 100644 index 0000000000..fd75db2363 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/nvram.h @@ -0,0 +1,71 @@ +/* + * nvram.h -- DS1307-based non-volatile memory device driver. + * + * This driver support file-like operations to 56-bytes long non-volatile + * memory of DS1307 I2C real-time clock chip. + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __DRIVER__NVRAM_H__ +#define __DRIVER__NVRAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_DRIVER_TABLE_ENTRY \ + { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ + nvram_driver_read, nvram_driver_write, NULL } + +/* nvram_driver_initialize -- + * Non-volatile memory device driver initialization. + */ +rtems_device_driver +nvram_driver_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_open -- + * Non-volatile memory device driver open primitive. + */ +rtems_device_driver +nvram_driver_open(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_close -- + * Non-volatile memory device driver close primitive. + */ +rtems_device_driver +nvram_driver_close(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_read -- + * Non-volatile memory device driver read primitive. + */ +rtems_device_driver +nvram_driver_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_write -- + * Non-volatile memory device driver write primitive. + */ +rtems_device_driver +nvram_driver_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __VFDDRV_H__ */ diff --git a/bsps/m68k/mcf5206elite/include/tm27.h b/bsps/m68k/mcf5206elite/include/tm27.h new file mode 100644 index 0000000000..2abef68311 --- /dev/null +++ b/bsps/m68k/mcf5206elite/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5206elite + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #2"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf52235/headers.am b/bsps/m68k/mcf52235/headers.am new file mode 100644 index 0000000000..b536b21164 --- /dev/null +++ b/bsps/m68k/mcf52235/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf52235/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf52235/include/tm27.h diff --git a/bsps/m68k/mcf52235/include/bsp.h b/bsps/m68k/mcf52235/include/bsp.h new file mode 100644 index 0000000000..ef3b928a24 --- /dev/null +++ b/bsps/m68k/mcf52235/include/bsp.h @@ -0,0 +1,87 @@ +/** + * @file + * + * @ingroup m68k_mcf52235 + * + * @brief Global BSP definitions + */ + +/* + * mcf52235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF52235_BSP_H +#define LIBBSP_M68K_MCF52235_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf5223x/mcf5223x.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Declare base address of peripherals area */ +#define __IPSBAR ((vuint8 *) 0x40000000) + +/***************************************************************************/ +/** Network driver configuration **/ + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* externals */ + +/* constants */ + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init52235(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @defgroup m68k_mcf52235 MCF52235 Support + * + * @ingroup bsp_m68k + * + * @brief MCF52235 Support Package + */ diff --git a/bsps/m68k/mcf52235/include/tm27.h b/bsps/m68k/mcf52235/include/tm27.h new file mode 100644 index 0000000000..b4b62ef721 --- /dev/null +++ b/bsps/m68k/mcf52235/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf52235 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5225x/headers.am b/bsps/m68k/mcf5225x/headers.am new file mode 100644 index 0000000000..200bebf9b5 --- /dev/null +++ b/bsps/m68k/mcf5225x/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5225x/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5225x/include/tm27.h diff --git a/bsps/m68k/mcf5225x/include/bsp.h b/bsps/m68k/mcf5225x/include/bsp.h new file mode 100644 index 0000000000..8b8d40f485 --- /dev/null +++ b/bsps/m68k/mcf5225x/include/bsp.h @@ -0,0 +1,90 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MCF5225X_BSP_H +#define LIBBSP_M68K_MCF5225X_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf5225x/mcf5225x.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Declare base address of peripherals area */ +#define __IPSBAR ((vuint8 *) 0x40000000) + +/***************************************************************************/ +/** Network driver configuration **/ + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define ports for console and DPU specific for BLUETOOTH and STATIONS */ +#define STATIONS_PORT 0 +#define CONSOLE_PORT 1 +#define BLUETOOTH_PORT 2 + +/* externals */ + +/* constants */ + +/* miscellaneous stuff assumed to exist */ + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5225x(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5225x/include/tm27.h b/bsps/m68k/mcf5225x/include/tm27.h new file mode 100644 index 0000000000..fcf1c4f8aa --- /dev/null +++ b/bsps/m68k/mcf5225x/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5225x + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5235/headers.am b/bsps/m68k/mcf5235/headers.am new file mode 100644 index 0000000000..e00b25f46c --- /dev/null +++ b/bsps/m68k/mcf5235/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5235/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5235/include/tm27.h diff --git a/bsps/m68k/mcf5235/include/bsp.h b/bsps/m68k/mcf5235/include/bsp.h new file mode 100644 index 0000000000..14a6b04034 --- /dev/null +++ b/bsps/m68k/mcf5235/include/bsp.h @@ -0,0 +1,70 @@ +/* + * mcf5235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF5235_BSP_H +#define LIBBSP_M68K_MCF5235_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf5235/mcf5235.h> /* internal MCF5235 modules */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t get_CPU_clock_speed(void); +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5235(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5235/include/tm27.h b/bsps/m68k/mcf5235/include/tm27.h new file mode 100644 index 0000000000..92a85c789a --- /dev/null +++ b/bsps/m68k/mcf5235/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5235 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mcf5329/headers.am b/bsps/m68k/mcf5329/headers.am new file mode 100644 index 0000000000..c1ee57ae55 --- /dev/null +++ b/bsps/m68k/mcf5329/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mcf5329/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mcf5329/include/tm27.h diff --git a/bsps/m68k/mcf5329/include/bsp.h b/bsps/m68k/mcf5329/include/bsp.h new file mode 100644 index 0000000000..7670e7a2d9 --- /dev/null +++ b/bsps/m68k/mcf5329/include/bsp.h @@ -0,0 +1,70 @@ +/* + * mcf52235 BSP header file + */ + +#ifndef LIBBSP_M68K_MCF5329_BSP_H +#define LIBBSP_M68K_MCF5329_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> +#include <rtems.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf532x/mcf532x.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); +uint32_t bsp_get_BUS_clock_speed(void); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 + +#define PIT3_IRQ_LEVEL 4 + +#define UART0_IRQ_LEVEL 3 +#define UART1_IRQ_LEVEL 3 +#define UART2_IRQ_LEVEL 3 + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void Init5329(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mcf5329/include/tm27.h b/bsps/m68k/mcf5329/include/tm27.h new file mode 100644 index 0000000000..33376540ac --- /dev/null +++ b/bsps/m68k/mcf5329/include/tm27.h @@ -0,0 +1,35 @@ +/* + * @file + * @ingroup m68k_mcf5329 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mrm332/headers.am b/bsps/m68k/mrm332/headers.am new file mode 100644 index 0000000000..84ad4ec522 --- /dev/null +++ b/bsps/m68k/mrm332/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/mrm332.h +include_HEADERS += ../../../../../../bsps/m68k/mrm332/include/tm27.h diff --git a/bsps/m68k/mrm332/include/bsp.h b/bsps/m68k/mrm332/include/bsp.h new file mode 100644 index 0000000000..6d4f7b8eb2 --- /dev/null +++ b/bsps/m68k/mrm332/include/bsp.h @@ -0,0 +1,90 @@ +/* bsp.h + * + * This include file contains all mrm board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_MRM332_BSP_H +#define LIBBSP_M68K_MRM332_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <rtems/bspIo.h> +#include <mrm332.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONSOLE_SCI + +/* externals */ + +extern char _etext[]; +extern char _copy_start[]; +extern char _edata[]; +extern char _clear_start[]; +extern char end[]; +extern bool _copy_data_from_rom; + +/* constants */ + +#ifdef __START_C__ +#define STACK_SIZE "#0x800" +#else +#define STACK_SIZE 0x800 +#endif + +/* macros */ + +#define RAW_PUTS(str) \ + { register char *ptr = str; \ + while (*ptr) SCI_output_char(*ptr++); \ + } + +#define RAW_PUTI(n) { \ + register int i, j; \ + \ + RAW_PUTS("0x"); \ + for (i=28;i>=0;i -= 4) { \ + j = (n>>i) & 0xf; \ + SCI_output_char( (j>9 ? j-10+'a' : j+'0') ); \ + } \ + } + +/* miscellaneous stuff assumed to exist */ + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +extern int stack_size; +extern int stack_start; + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +void Spurious_Initialize(void); + +void _UART_flush(void); + +void outbyte(char); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mrm332/include/mrm332.h b/bsps/m68k/mrm332/include/mrm332.h new file mode 100644 index 0000000000..1b8672752d --- /dev/null +++ b/bsps/m68k/mrm332/include/mrm332.h @@ -0,0 +1,71 @@ +/* mrm332.h + */ + +#ifndef _MRM332_H_ +#define _MRM332_H_ + +/* SIM_MM (SIM Module Mapping) determines the location of the control + register block. When MM=0, register addresses range fom 0x7ff000 to + 0x7FFFFF. When MM=1, register addresses range from 0xfff000 to + 0xffffff. */ +#define SIM_MM 1 + +/* Interrupt related definitions */ +#define SIM_IARB 15 +#define QSM_IARB 10 + +#define MRM_PIV 64 +#define ISRL_PIT 4 /* zero disables PIT */ + +#define EFI_QIVR 66 /* 66=>SCI and 67=>QSPI interrupt */ +#define ISRL_QSPI 0 + +#define EFI_SPINT 24 /* spurious interrupt */ +#define EFI_INT1 25 /* CTS interrupt */ +#define ISRL_SCI 6 + +/* System Clock definitions */ +#define XTAL 32768.0 /* crystal frequency in Hz */ + +/* Specify the CPU frequency. Do not specify a faster clock than your */ +/* CPU is rated for! */ +#if 0 +/* Default MRM clock rate (8.388688 MHz) set by CPU32: */ +#define MRM_W 0 /* system clock parameters */ +#define MRM_X 0 +#define MRM_Y 0x3f +#endif + +#if 0 +/* 16.77722 MHz: */ +#define MRM_W 1 /* system clock parameters */ +#define MRM_X 1 +#define MRM_Y 0x0f +#endif + +#if 1 +/* 25.16582 MHz: */ +#define MRM_W 1 /* system clock parameters */ +#define MRM_X 1 +#define MRM_Y 0x17 +#define SET_EDIV +#endif + +#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X))) +#define SCI_BAUD 19200 /* RS232 Baud Rate */ + +/* macros/functions */ + +#ifndef ASM + +/* + * This prototype really should have the noreturn attribute but + * that causes a warning. Not sure how to fix that. + */ +/* static void reboot(void) __attribute__ ((noreturn)); */ +static void reboot(void); +__inline__ static void reboot() {__asm__ ("trap #15; .word 0x0063");} + +#endif /* ASM */ + +#endif /* _MRM_H_ */ diff --git a/bsps/m68k/mrm332/include/tm27.h b/bsps/m68k/mrm332/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/m68k/mrm332/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/m68k/mvme147/headers.am b/bsps/m68k/mvme147/headers.am new file mode 100644 index 0000000000..c6b61dd0e1 --- /dev/null +++ b/bsps/m68k/mvme147/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme147/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme147/include/tm27.h diff --git a/bsps/m68k/mvme147/include/bsp.h b/bsps/m68k/mvme147/include/bsp.h new file mode 100644 index 0000000000..9cf3fbf5a8 --- /dev/null +++ b/bsps/m68k/mvme147/include/bsp.h @@ -0,0 +1,117 @@ +/* bsp.h + * + * This include file contains all MVME147 board IO definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * MVME147 port for TNI - Telecom Bretagne + * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) + * May 1996 + */ + +#ifndef LIBBSP_M68K_MVME147_BSP_H +#define LIBBSP_M68K_MVME147_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +#define RAM_START 0x00005000 +#define RAM_END 0x00400000 + + /* MVME 147 Peripheral controller chip + see MVME147/D1, 3.4 */ + +struct pcc_map { + /* 32 bit registers */ + uint32_t dma_table_address; /* 0xfffe1000 */ + uint32_t dma_data_address; /* 0xfffe1004 */ + uint32_t dma_bytecount; /* 0xfffe1008 */ + uint32_t dma_data_holding; /* 0xfffe100c */ + + /* 16 bit registers */ + uint16_t timer1_preload; /* 0xfffe1010 */ + uint16_t timer1_count; /* 0xfffe1012 */ + uint16_t timer2_preload; /* 0xfffe1014 */ + uint16_t timer2_count; /* 0xfffe1016 */ + + /* 8 bit registers */ + uint8_t timer1_int_control; /* 0xfffe1018 */ + uint8_t timer1_control; /* 0xfffe1019 */ + uint8_t timer2_int_control; /* 0xfffe101a */ + uint8_t timer2_control; /* 0xfffe101b */ + + uint8_t acfail_int_control; /* 0xfffe101c */ + uint8_t watchdog_control; /* 0xfffe101d */ + + uint8_t printer_int_control; /* 0xfffe101e */ + uint8_t printer_control; /* 0xfffe102f */ + + uint8_t dma_int_control; /* 0xfffe1020 */ + uint8_t dma_control; /* 0xfffe1021 */ + uint8_t bus_error_int_control; /* 0xfffe1022 */ + uint8_t dma_status; /* 0xfffe1023 */ + uint8_t abort_int_control; /* 0xfffe1024 */ + uint8_t table_address_function_code; /* 0xfffe1025 */ + uint8_t serial_port_int_control; /* 0xfffe1026 */ + uint8_t general_purpose_control; /* 0xfffe1027 */ + uint8_t lan_int_control; /* 0xfffe1028 */ + uint8_t general_purpose_status; /* 0xfffe1029 */ + uint8_t scsi_port_int_control; /* 0xfffe102a */ + uint8_t slave_base_address; /* 0xfffe102b */ + uint8_t software_int_1_control; /* 0xfffe102c */ + uint8_t int_base_vector; /* 0xfffe102d */ + uint8_t software_int_2_control; /* 0xfffe102e */ + uint8_t revision_level; /* 0xfffe102f */ +}; + +#define pcc ((volatile struct pcc_map * const) 0xfffe1000) + +#define z8530 0xfffe3001 + +/* interrupt vectors - see MVME146/D1 4.14 */ +#define PCC_BASE_VECTOR 0x40 /* First user int */ +#define SCC_VECTOR PCC_BASE_VECTOR+3 +#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 +#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 +#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 +#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 + +#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ +#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ + +#if (USE_CHANNEL_A == 1) +#define CONSOLE_CONTROL 0xfffe3002 +#define CONSOLE_DATA 0xfffe3003 +#elif (USE_CHANNEL_B == 1) +#define CONSOLE_CONTROL 0xfffe3000 +#define CONSOLE_DATA 0xfffe3001 +#endif + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme147/include/tm27.h b/bsps/m68k/mvme147/include/tm27.h new file mode 100644 index 0000000000..5b548a888a --- /dev/null +++ b/bsps/m68k/mvme147/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme147 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Use the MPCSR vector for the MVME147 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), \ + SOFT_1_VECTOR, 1 ) + +#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c + /* generate level 4 sotware int. */ + +#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme147s/headers.am b/bsps/m68k/mvme147s/headers.am new file mode 100644 index 0000000000..d42fd64a42 --- /dev/null +++ b/bsps/m68k/mvme147s/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme147s/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme147s/include/tm27.h diff --git a/bsps/m68k/mvme147s/include/bsp.h b/bsps/m68k/mvme147s/include/bsp.h new file mode 100644 index 0000000000..3a4803fec2 --- /dev/null +++ b/bsps/m68k/mvme147s/include/bsp.h @@ -0,0 +1,192 @@ +/* bsp.h + * + * This include file contains all MVME147 board IO definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * MVME147 port for TNI - Telecom Bretagne + * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) + * May 1996 + */ + +#ifndef LIBBSP_M68K_MVME147S_BSP_H +#define LIBBSP_M68K_MVME147S_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +#define RAM_START 0x00007000 +#define RAM_END 0x003e0000 +#define DRAM_END 0x00400000 + /* We leave 128k for the shared memory */ + + /* MVME 147 Peripheral controller chip + see MVME147/D1, 3.4 */ + +struct pcc_map { + /* 32 bit registers */ + uint32_t dma_table_address; /* 0xfffe1000 */ + uint32_t dma_data_address; /* 0xfffe1004 */ + uint32_t dma_bytecount; /* 0xfffe1008 */ + uint32_t dma_data_holding; /* 0xfffe100c */ + + /* 16 bit registers */ + uint16_t timer1_preload; /* 0xfffe1010 */ + uint16_t timer1_count; /* 0xfffe1012 */ + uint16_t timer2_preload; /* 0xfffe1014 */ + uint16_t timer2_count; /* 0xfffe1016 */ + + /* 8 bit registers */ + uint8_t timer1_int_control; /* 0xfffe1018 */ + uint8_t timer1_control; /* 0xfffe1019 */ + uint8_t timer2_int_control; /* 0xfffe101a */ + uint8_t timer2_control; /* 0xfffe101b */ + + uint8_t acfail_int_control; /* 0xfffe101c */ + uint8_t watchdog_control; /* 0xfffe101d */ + + uint8_t printer_int_control; /* 0xfffe101e */ + uint8_t printer_control; /* 0xfffe102f */ + + uint8_t dma_int_control; /* 0xfffe1020 */ + uint8_t dma_control; /* 0xfffe1021 */ + uint8_t bus_error_int_control; /* 0xfffe1022 */ + uint8_t dma_status; /* 0xfffe1023 */ + uint8_t abort_int_control; /* 0xfffe1024 */ + uint8_t table_address_function_code; /* 0xfffe1025 */ + uint8_t serial_port_int_control; /* 0xfffe1026 */ + uint8_t general_purpose_control; /* 0xfffe1027 */ + uint8_t lan_int_control; /* 0xfffe1028 */ + uint8_t general_purpose_status; /* 0xfffe1029 */ + uint8_t scsi_port_int_control; /* 0xfffe102a */ + uint8_t slave_base_address; /* 0xfffe102b */ + uint8_t software_int_1_control; /* 0xfffe102c */ + uint8_t int_base_vector; /* 0xfffe102d */ + uint8_t software_int_2_control; /* 0xfffe102e */ + uint8_t revision_level; /* 0xfffe102f */ +}; + +#define pcc ((volatile struct pcc_map * const) 0xfffe1000) + +/* VME chip configuration registers */ + +struct vme_lcsr_map { + uint8_t unused_1; + uint8_t system_controller; /* 0xfffe2001 */ + uint8_t unused_2; + uint8_t vme_bus_requester; /* 0xfffe2003 */ + uint8_t unused_3; + uint8_t master_configuration; /* 0xfffe2005 */ + uint8_t unused_4; + uint8_t slave_configuration; /* 0xfffe2007 */ + uint8_t unused_5; + uint8_t timer_configuration; /* 0xfffe2009 */ + uint8_t unused_6; + uint8_t slave_address_modifier; /* 0xfffe200b */ + uint8_t unused_7; + uint8_t master_address_modifier; /* 0xfffe200d */ + uint8_t unused_8; + uint8_t interrupt_handler_mask; /* 0xfffe200f */ + uint8_t unused_9; + uint8_t utility_interrupt_mask; /* 0xfffe2011 */ + uint8_t unused_10; + uint8_t utility_interrupt_vector; /* 0xfffe2013 */ + uint8_t unused_11; + uint8_t interrupt_request; /* 0xfffe2015 */ + uint8_t unused_12; + uint8_t vme_bus_status_id; /* 0xfffe2017 */ + uint8_t unused_13; + uint8_t bus_error_status; /* 0xfffe2019 */ + uint8_t unused_14; + uint8_t gcsr_base_address; /* 0xfffe201b */ +}; + +#define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000) + +struct vme_gcsr_map { + uint8_t unused_1; + uint8_t global_0; /* 0xfffe2021 */ + uint8_t unused_2; + uint8_t global_1; /* 0xfffe2023 */ + uint8_t unused_3; + uint8_t board_identification; /* 0xfffe2025 */ + uint8_t unused_4; + uint8_t general_purpose_0; /* 0xfffe2027 */ + uint8_t unused_5; + uint8_t general_purpose_1; /* 0xfffe2029 */ + uint8_t unused_6; + uint8_t general_purpose_2; /* 0xfffe202b */ + uint8_t unused_7; + uint8_t general_purpose_3; /* 0xfffe202d */ + uint8_t unused_8; + uint8_t general_purpose_4; /* 0xfffe202f */ +}; + +#define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020) + +#define z8530 0xfffe3001 + +/* interrupt vectors - see MVME147/D1 4.14 */ +#define PCC_BASE_VECTOR 0x40 /* First user int */ +#define SCC_VECTOR PCC_BASE_VECTOR+3 +#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 +#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 +#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 +#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 + +#define VME_BASE_VECTOR 0x50 +#define VME_SIGLP_VECTOR VME_BASE_VECTOR+1 + +#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ +#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ + +#if (USE_CHANNEL_A == 1) +#define CONSOLE_CONTROL 0xfffe3002 +#define CONSOLE_DATA 0xfffe3003 +#elif (USE_CHANNEL_B == 1) +#define CONSOLE_CONTROL 0xfffe3000 +#define CONSOLE_DATA 0xfffe3001 +#endif + +#define FOREVER 1 /* infinite loop */ + +#ifdef M147_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme147s/include/tm27.h b/bsps/m68k/mvme147s/include/tm27.h new file mode 100644 index 0000000000..48ae0f459a --- /dev/null +++ b/bsps/m68k/mvme147s/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme147s + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Use the MPCSR vector for the MVME147 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), \ + SOFT_1_VECTOR, 1 ) + +#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c + /* generate level 4 sotware int. */ + +#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme162/headers.am b/bsps/m68k/mvme162/headers.am new file mode 100644 index 0000000000..5456150cf5 --- /dev/null +++ b/bsps/m68k/mvme162/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/page_table.h +include_HEADERS += ../../../../../../bsps/m68k/mvme162/include/tm27.h diff --git a/bsps/m68k/mvme162/include/bsp.h b/bsps/m68k/mvme162/include/bsp.h new file mode 100644 index 0000000000..3645a31086 --- /dev/null +++ b/bsps/m68k/mvme162/include/bsp.h @@ -0,0 +1,204 @@ +/* + * This include file contains all MVME162fx board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + */ + +#ifndef LIBBSP_M68K_MVME162_BSP_H +#define LIBBSP_M68K_MVME162_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#include <mvme16x_hw.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------*/ + +typedef volatile struct { + + unsigned char chipID; + unsigned char chipREV; + unsigned char gen_control; + unsigned char vector_base; + + unsigned long timer_cmp_1; + unsigned long timer_cnt_1; + unsigned long timer_cmp_2; + unsigned long timer_cnt_2; + + unsigned char LSB_prescaler_count; + unsigned char prescaler_clock_adjust; + unsigned char time_ctl_2; + unsigned char time_ctl_1; + + unsigned char time_int_ctl_4; + unsigned char time_int_ctl_3; + unsigned char time_int_ctl_2; + unsigned char time_int_ctl_1; + + unsigned char dram_err_int_ctl; + unsigned char SCC_int_ctl; + unsigned char time_ctl_4; + unsigned char time_ctl_3; + + unsigned short DRAM_space_base; + unsigned short SRAM_space_base; + + unsigned char DRAM_size; + unsigned char DRAM_SRAM_opt; + unsigned char SRAM_size; + unsigned char reserved; + + unsigned char LANC_error; + unsigned char reserved1; + unsigned char LANC_int_ctl; + unsigned char LANC_berr_ctl; + + unsigned char SCSI_error; + unsigned char general_inputs; + unsigned char MVME_162_version; + unsigned char SCSI_int_ctl; + + unsigned long timer_cmp_3; + unsigned long timer_cnt_3; + unsigned long timer_cmp_4; + unsigned long timer_cnt_4; + + unsigned char bus_clk; + unsigned char PROM_acc_time_ctl; + unsigned char FLASH_acc_time_ctl; + unsigned char ABORT_int_ctl; + + unsigned char RESET_ctl; + unsigned char watchdog_timer_ctl; + unsigned char acc_watchdog_time_base_sel; + unsigned char reserved2; + + unsigned char DRAM_ctl; + unsigned char reserved4; + unsigned char MPU_status; + unsigned char reserved3; + + unsigned long prescaler_count; + +} mcchip_regs; + +#define mcchip ((mcchip_regs * const) 0xFFF42000) + +/*----------------------------------------------------------------*/ + +/* + * SCC Z8523(0) defines and macros + * ------------------------------- + * Prototypes for the low-level serial io are also included here, + * because such stuff is bsp-specific (yet). The function bodies + * are in console.c + * + * NOTE from Eric Vaitl <evaitl@viasat.com>: + * + * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a + * bug in the MC2 chip (revision 1) such that the SCC data register is + * not accessible, it has to be accessed indirectly through the SCC + * control register. + */ + +enum {portB, portA}; + +extern bool char_ready(int port, char *ch); +extern char char_wait(int port); +extern void char_put(int port, char ch); + +#define TX_BUFFER_EMPTY 0x04 +#define RX_DATA_AVAILABLE 0x01 +#define SCC_VECTOR 0x40 + +typedef volatile struct { + unsigned char pad1; + volatile unsigned char csr; + unsigned char pad2; + volatile unsigned char buf; +} scc_regs; + +#define scc ((scc_regs * const) 0xFFF45000) + +#define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) +#define ZREAD0(port) (scc[port].csr) + +#define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) +#define ZREADD(port) (scc[port].csr=0x08, scc[port].csr ) + +#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) +#define ZWRITED(port, v) (scc[port].csr = 0x08, \ + scc[port].csr = (unsigned char)(v)) +/*----------------------------------------------------------------*/ + +#ifdef M162_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +/* + * This value is the default address location of the 162Bug vector table + * and is also the default start address of the boards DRAM. This value + * may be different for your specific board based on a number of factors: + * + * Default DRAM address: 0x00000000 + * Default SRAM address: 0xFFE00000 + * + * o If no DRAM can be found by the 162Bug program, it will use SRAM. + * o The default SRAM address may be different if SRAM mezzanine boards + * are installed on the main board. + * o Both the DRAM and SRAM addresses can be modified by changing the + * appropriate values in NVRAM using the ENV command at the 162Bug + * prompt. + * + * If your board has different values than the defaults, change the value + * of the following define. + * + */ +#define MOT_162BUG_VEC_ADDRESS 0x00000000 + +extern rtems_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Prototypes for methods in the BSP that cross file boundaries. + */ +bool char_ready(int port, char *ch); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme162/include/page_table.h b/bsps/m68k/mvme162/include/page_table.h new file mode 100644 index 0000000000..09b93a49bd --- /dev/null +++ b/bsps/m68k/mvme162/include/page_table.h @@ -0,0 +1,27 @@ +/* + * This file was submitted by Eric Vaitl <vaitl@viasat.com> and + * supports page table initialization. + */ + +#ifndef PAGE_TABLE_H +#define PAGE_TABLE_H + +extern void page_table_teardown(void); +extern void page_table_init(void); +extern int page_table_map(void *addr, unsigned long size, int cache_type); + +enum { + CACHE_WRITE_THROUGH, + CACHE_COPYBACK, + CACHE_NONE_SERIALIZED, + CACHE_NONE +}; +enum { + PTM_SUCCESS, + PTM_BAD_ADDR, + PTM_BAD_SIZE, + PTM_BAD_CACHE, + PTM_NO_TABLE_SPACE +}; + +#endif diff --git a/bsps/m68k/mvme162/include/tm27.h b/bsps/m68k/mvme162/include/tm27.h new file mode 100644 index 0000000000..750408d009 --- /dev/null +++ b/bsps/m68k/mvme162/include/tm27.h @@ -0,0 +1,39 @@ +/* + * @file + * @ingroup m68k_mvme162 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: We use software interrupt 0 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ + lcsr->intr_level[2] |= 3; \ + lcsr->intr_ena |= 0x100; + +#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 + +#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/mvme167/headers.am b/bsps/m68k/mvme167/headers.am new file mode 100644 index 0000000000..23b9370680 --- /dev/null +++ b/bsps/m68k/mvme167/headers.am @@ -0,0 +1,7 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/page_table.h +include_HEADERS += ../../../../../../bsps/m68k/mvme167/include/tm27.h diff --git a/bsps/m68k/mvme167/include/bsp.h b/bsps/m68k/mvme167/include/bsp.h new file mode 100644 index 0000000000..d04b4f3952 --- /dev/null +++ b/bsps/m68k/mvme167/include/bsp.h @@ -0,0 +1,318 @@ +/** + * @file + * + * Following defines must reflect the setup of the particular MVME167. + * All page references are to the MVME166/MVME167/MVME187 Single Board + * Computer Programmer's Reference Guide (MVME187PG/D2) with the April + * 1993 supplements/addenda (MVME187PG/D2A1). + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS file: + * Copyright (c) 1998, National Research Council of Canada + */ + +#ifndef LIBBSP_M68K_MVME167_BSP_H +#define LIBBSP_M68K_MVME167_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <rtems/bspIo.h> + +#include <mvme16x_hw.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* GCSR is in mvme16x_hw.h */ +/* LCSR is in mvme16x_hw.h */ +/* i82596 is in mvme16x_hw.h */ +/* NVRAM is in mvme16x_hw.h */ + +#if 0 +/* + * Representation of the PCCchip2 + */ +typedef volatile struct pccchip2_regs_ { + unsigned char chip_id; /* 0xFFF42000 */ + unsigned char chip_revision; /* 0xFFF42001 */ + unsigned char gen_control; /* 0xFFF42002 */ + unsigned char vector_base; /* 0xFFF42003 */ + unsigned long timer_cmp_1; /* 0xFFF42004 */ + unsigned long timer_cnt_1; /* 0xFFF42008 */ + unsigned long timer_cmp_2; /* 0xFFF4200C */ + unsigned long timer_cnt_2; /* 0xFFF42010 */ + unsigned char LSB_prescaler_count;/* 0xFFF42014 */ + unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ + unsigned char timer_ctl_2; /* 0xFFF42016 */ + unsigned char timer_ctl_1; /* 0xFFF42017 */ + unsigned char gpi_int_ctl; /* 0xFFF42018 */ + unsigned char gpio_ctl; /* 0xFFF42019 */ + unsigned char timer_int_ctl_2; /* 0xFFF4201A */ + unsigned char timer_int_ctl_1; /* 0xFFF4201B */ + unsigned char SCC_error; /* 0xFFF4201C */ + unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ + unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ + unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ + unsigned char reserved1[3]; + unsigned char modem_piack; /* 0xFFF42023 */ + unsigned char reserved2; + unsigned char tx_piack; /* 0xFFF42025 */ + unsigned char reserved3; + unsigned char rx_piack; /* 0xFFF42027 */ + unsigned char LANC_error; /* 0xFFF42028 */ + unsigned char reserved4; + unsigned char LANC_int_ctl; /* 0xFFF4202A */ + unsigned char LANC_berr_ctl; /* 0xFFF4202B */ + unsigned char SCSI_error; /* 0xFFF4202C */ + unsigned char reserved5[2]; + unsigned char SCSI_int_ctl; /* 0xFFF4202F */ + unsigned char print_ack_int_ctl; /* 0xFFF42030 */ + unsigned char print_fault_int_ctl;/* 0xFFF42031 */ + unsigned char print_sel_int_ctl; /* 0xFFF42032 */ + unsigned char print_pe_int_ctl; /* 0xFFF42033 */ + unsigned char print_busy_int_ctl; /* 0xFFF42034 */ + unsigned char reserved6; + unsigned char print_input_status; /* 0xFFF42036 */ + unsigned char print_ctl; /* 0xFFF42037 */ + unsigned char chip_speed; /* 0xFFF42038 */ + unsigned char reserved7; + unsigned char print_data; /* 0xFFF4203A */ + unsigned char reserved8[3]; + unsigned char int_level; /* 0xFFF4203E */ + unsigned char int_mask; /* 0xFFF4203F */ +} pccchip2_regs; + +/* + * Base address of the PCCchip2. + * This is not configurable in the MVME167. + */ +#define pccchip2 ((pccchip2_regs * const) 0xFFF42000) + +#endif +/* + * The MVME167 is equiped with one or two MEMC040 memory controllers at + * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers + * were initialized by 167Bug. + */ +typedef volatile struct memc040_regs_ { + unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */ + unsigned char reserved1[3]; + unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */ + unsigned char reserved2[3]; + unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */ + unsigned char reserved3[3]; + unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */ + unsigned char reserved4[3]; + unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */ + unsigned char reserved5[3]; + unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */ + unsigned char reserved6[3]; + unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */ + unsigned char reserved7[3]; + unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */ +} memc040_regs; + +/* + * Base address of the MEMC040s. + * This is not configurable in the MVME167. + */ +#define memc040_1 ((memc040_regs * const) 0xFFF43000) +#define memc040_2 ((memc040_regs * const) 0xFFF43100) + +/* + * The MVME167 may be equiped with error-correcting RAM cards. In this case, + * each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port + * assumes that these controllers, if present, are initialized by 167Bug. + * They do not appear to hold information of interest at this time, so they + * are not described. However, each MCECC pair lives at the same address as + * the MEMC040 is replaces. The first eight registers of the MCECC are + * nearly identical to the ones of the MEMC040, and the memc040_X structures + * can be used to read those first eight registers. + */ + +/* + * Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller + */ +typedef volatile struct cd2401_regs_ { + unsigned char reserved1[7]; + unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */ + unsigned char reserved2; + unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */ + unsigned char reserved3[6]; + unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */ + unsigned char ier; /* 0xFFF45011 - Interrupt Enable */ + unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */ + unsigned char ccr; /* 0xFFF45013 - Channel Command */ + unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */ + unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */ + unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */ + unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */ + unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */ + unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */ + unsigned char csr; /* 0xFFF4501A - Channel Status */ + unsigned char cmr; /* 0xFFF4501B - Channel Mode */ + union { + struct { + unsigned char schr4; /* 0xFFF4501C - Special Character 4 */ + unsigned char schr3; /* 0xFFF4501D - Special Character 3 */ + unsigned char schr2; /* 0xFFF4501E - Special Character 2 */ + unsigned char schr1; /* 0xFFF4501F - Special Character 1 */ + } async; + struct { + unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */ + unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */ + unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */ + unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */ + } sync; + } u1; + unsigned char reserved4[2]; + unsigned char scrh; /* 0xFFF45022 - Special Character Range High */ + unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */ + union { + struct { + unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */ + } w; + struct { + unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */ + unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */ + } b; + } u2; + unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */ + unsigned char reserved5[2]; + union { + struct { + unsigned char ttr; /* 0xFFF45029 - Transmit Timer */ + } async; + struct { + unsigned char gt2; /* 0xFFF45029 - General Timer 2 */ + } sync; + } u3; + union { + struct { + unsigned short gt1; /* 0xFFF4502A - General Timer 1 */ + } w; + struct { + unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */ + unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */ + } b; + } u4; + unsigned char reserved6[2]; + unsigned char lnxt; /* 0xFF4502E - LNext Character */ + unsigned char reserved7; + unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */ + unsigned char reserved8[7]; + unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */ + unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */ + unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */ + unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */ + unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */ + unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */ + unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */ + unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */ + unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */ + unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */ + unsigned short reserved9; + unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */ + unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */ + unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */ + unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */ + unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */ + unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */ + unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */ + unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */ + unsigned short reserved10; + unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */ + unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */ + unsigned char reserved11[32]; + unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */ + unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */ + unsigned char reserved12[2]; + unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */ + unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */ + unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */ + union { + struct { + unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */ + } w; + struct { + unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */ + unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */ + } b; + } u5; + unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */ + unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */ + unsigned char reserved13[2]; + unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */ + unsigned char reserved14[49]; + unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */ + unsigned char reserved15[2]; + unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */ + unsigned char reserved16[4]; + unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */ + unsigned char reserved17[2]; + unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */ + unsigned char reserved18[10]; + unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */ + unsigned char reserved19[3]; + unsigned char tpr; /* 0xFFF450DA - Timer Period */ + unsigned char reserved20[3]; + unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */ + unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */ + unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */ + unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */ + unsigned char stk; /* 0xFFF450E2 - Stack */ + unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */ + unsigned char reserved21[8]; + unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */ + unsigned char rir; /* 0xFFF450ED - Receive Interrupt */ + unsigned char car; /* 0xFFF450EE - Channel Access */ + unsigned char mir; /* 0xFFF450EF - Model Interrupt */ + unsigned char reserved22[6]; + unsigned char dmr; /* 0xFFF450F6 - DMA Mode */ + unsigned char reserved23; + unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */ +} cd2401_regs; + +/* + * Base address of the CD2401. + * This is not configurable in the MVME167. + */ +#define cd2401 ((cd2401_regs * const) 0xFFF45000) + +/* CD2401 is clocked at 20 MHz */ +#define CD2401_CLK_RATE 20000000 + +/* BSP-wide functions */ + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef M167_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +extern void *M68Kvec[]; /* vector table address */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/mvme167/include/page_table.h b/bsps/m68k/mvme167/include/page_table.h new file mode 100644 index 0000000000..2db5591729 --- /dev/null +++ b/bsps/m68k/mvme167/include/page_table.h @@ -0,0 +1,43 @@ +/* page_table.h + * + * This file was submitted by Eric Vaitl <vaitl@viasat.com> and + * supports page table initialization. + * + * For now, we only use the transparent translation registers. Page tables + * may be set up in the future. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modifications of respective RTEMS files: + * Copyright (c) 1998, National Research Council of Canada + */ + +#ifndef __PAGE_TABLE_H +#define __PAGE_TABLE_H + +#include <rtems.h> + +void page_table_teardown( void ); +void page_table_init( void ); + +enum { + CACHE_WRITE_THROUGH, + CACHE_COPYBACK, + CACHE_NONE_SERIALIZED, + CACHE_NONE +}; + +enum { + PTM_SUCCESS, + PTM_BAD_ADDR, + PTM_BAD_SIZE, + PTM_BAD_CACHE, + PTM_NO_TABLE_SPACE +}; + +#endif diff --git a/bsps/m68k/mvme167/include/tm27.h b/bsps/m68k/mvme167/include/tm27.h new file mode 100644 index 0000000000..5b65311794 --- /dev/null +++ b/bsps/m68k/mvme167/include/tm27.h @@ -0,0 +1,38 @@ +/* + * @file + * @ingroup m68k_mvme167 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: We use software interrupt 0 + */ +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ + lcsr->intr_level[2] |= 3; \ + lcsr->intr_ena |= 0x100 + +#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 + +#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/m68k/uC5282/headers.am b/bsps/m68k/uC5282/headers.am new file mode 100644 index 0000000000..5757c0d98e --- /dev/null +++ b/bsps/m68k/uC5282/headers.am @@ -0,0 +1,6 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/m68k/uC5282/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/m68k/uC5282/include/tm27.h diff --git a/bsps/m68k/uC5282/include/bsp.h b/bsps/m68k/uC5282/include/bsp.h new file mode 100644 index 0000000000..a887cc0385 --- /dev/null +++ b/bsps/m68k/uC5282/include/bsp.h @@ -0,0 +1,175 @@ +/* + * uC5282 BSP header file + * + * Author: W. Eric Norum <norume@aps.anl.gov> + * + * COPYRIGHT (c) 2005. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_M68K_UC5282_BSP_H +#define LIBBSP_M68K_UC5282_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <rtems/bspIo.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ +/** BSP Configuration **/ +/* + * Uncomment to use instruction/data cache + * Leave commented to use instruction-only cache + */ +#define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ + +/***************************************************************************/ +/** Network driver configuration **/ +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* functions */ + +typedef struct { + unsigned int l; + void *v; +} bsp_mnode_t; + +#define RTEMS_BSP_PGM_ERASE_FIRST 0x1 +#define RTEMS_BSP_PGM_RESET_AFTER 0x2 +#define RTEMS_BSP_PGM_EXEC_AFTER 0x4 +#define RTEMS_BSP_PGM_HALT_AFTER 0x8 + +uint32_t bsp_get_CPU_clock_speed(void); +rtems_status_code bsp_allocate_interrupt(int level, int priority); +int bsp_sysReset(int flags); +int bsp_program(bsp_mnode_t *chain, int flags); +unsigned const char *bsp_gethwaddr(int a); +const char *bsp_getbenv(const char *a); +int bsp_flash_erase_range(volatile unsigned short *flashptr, int start, int end); +int bsp_flash_write_range(volatile unsigned short *flashptr, bsp_mnode_t *chain, int offset); + +rtems_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +/* + * Fake VME support + * This makes it easier to use EPICS driver support on this BSP. + */ +#define VME_AM_STD_SUP_ASCENDING 0x3f +#define VME_AM_STD_SUP_PGM 0x3e +#define VME_AM_STD_USR_ASCENDING 0x3b +#define VME_AM_STD_USR_PGM 0x3a +#define VME_AM_STD_SUP_DATA 0x3d +#define VME_AM_STD_USR_DATA 0x39 +#define VME_AM_EXT_SUP_ASCENDING 0x0f +#define VME_AM_EXT_SUP_PGM 0x0e +#define VME_AM_EXT_USR_ASCENDING 0x0b +#define VME_AM_EXT_USR_PGM 0x0a +#define VME_AM_EXT_SUP_DATA 0x0d +#define VME_AM_EXT_USR_DATA 0x09 +#define VME_AM_SUP_SHORT_IO 0x2d +#define VME_AM_USR_SHORT_IO 0x29 + +/* + * 'Extended' BSP support + */ +rtems_status_code bspExtInit(void); +typedef void (*BSP_VME_ISR_t)(void *usrArg, unsigned long vector); +BSP_VME_ISR_t BSP_getVME_isr(unsigned long vector, void **parg); +int BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); +int BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); +int BSP_enableVME_int_lvl(unsigned int level); +int BSP_disableVME_int_lvl(unsigned int level); +int BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr); + +/* + * This BSP provides its own IDLE task to override the RTEMS one. + * So we prototype it and define the constant confdefs.h expects + * to configure a BSP specific one. + */ +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* + * The custom IDLE task keeps some idle statistics. + */ +int bsp_cpu_load_percentage(void); + +/* + * This is a helper method to determine the cause of a reset. + */ +void bsp_reset_cause(char *buf, size_t capacity); + +/* + * SRAM. The BSP uses SRAM for maintaining some clock-driver data + * and for ethernet descriptors (and the initial stack during + * early boot). + */ + +typedef struct mcf5282BufferDescriptor_ { + volatile uint16_t status; + uint16_t length; + volatile void *buffer; +} mcf5282BufferDescriptor_t; + +extern struct { + uint32_t idle_counter; + uint32_t filtered_idle; + uint32_t max_idle_count; + uint32_t pitc_per_tick; + uint32_t nsec_per_pitc; + uint32_t pad[3]; /* align to 16-bytes for descriptors */ + mcf5282BufferDescriptor_t fec_descriptors[]; + /* buffer descriptors are allocated from here */ + + /* initial stack is at top of SRAM (start.S) */ +} __SRAMBASE; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/m68k/uC5282/include/tm27.h b/bsps/m68k/uC5282/include/tm27.h new file mode 100644 index 0000000000..9a24da3755 --- /dev/null +++ b/bsps/m68k/uC5282/include/tm27.h @@ -0,0 +1,40 @@ +/* + * @file + * @ingroup m68k_uC5282 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * Author: W. Eric Norum <norume@aps.anl.gov> + * + * COPYRIGHT (c) 2005-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif |