diff options
Diffstat (limited to 'bsps/include/dev')
24 files changed, 4853 insertions, 127 deletions
diff --git a/bsps/include/dev/clock/VERSION b/bsps/include/dev/clock/VERSION new file mode 100644 index 0000000000..1ccbe7c216 --- /dev/null +++ b/bsps/include/dev/clock/VERSION @@ -0,0 +1,24 @@ +The information in this file describes the source of +bsps/include/dev/clock/xttcps_hw.h. + +Import from: + +https://github.com/Xilinx/embeddedsw.git + +commit 5330a64c8efd14f0eef09befdbb8d3d738c33ec2 +Refs: <xilinx_v2022.2> +Author: Nicole Baze <nicole.baze@xilinx.com> +AuthorDate: Mon Oct 3 13:27:19 2022 -0700 +Commit: Siva Addepalli <sivaprasad.addepalli@xilinx.com> +CommitDate: Fri Oct 7 10:26:16 2022 +0530 + + xilpm: versal: server: Fix bug in AIE2 zeroization + + There is a bug in AIE2 zeriozation function when polling for memory + zeroization complete. Currently the entire memory register is being + checked against zero but instead we need to check the bits specific + to the memory tiles. This patch updates the zeroization check by + adding a mask so that only the desired bits are checked for zero. + + Signed-off-by: Nicole Baze <nicole.baze@xilinx.com> + Acked-by: Jesus De Haro <jesus.de-haro@xilinx.com> diff --git a/bsps/include/dev/clock/xttcps_hw.h b/bsps/include/dev/clock/xttcps_hw.h new file mode 100644 index 0000000000..4d40ab445b --- /dev/null +++ b/bsps/include/dev/clock/xttcps_hw.h @@ -0,0 +1,210 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* @addtogroup ttcps_v3_15 +* @{ +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ------------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK, +* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to +* mask 16 bit values for zynq and 32 bit values for +* zynq ultrascale+mpsoc " +* </pre> +* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#ifdef __rtems__ +#include <xil_system.h> +#endif + +/************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif +#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (u32)(RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/i2c/cadence-i2c-regs.h b/bsps/include/dev/i2c/cadence-i2c-regs.h index 7d7c3b284a..0318b9850a 100644 --- a/bsps/include/dev/i2c/cadence-i2c-regs.h +++ b/bsps/include/dev/i2c/cadence-i2c-regs.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2014 embedded brains GmbH + * Copyright (C) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/dev/i2c/cadence-i2c.h b/bsps/include/dev/i2c/cadence-i2c.h index aff97237a4..1aba2b7ad0 100644 --- a/bsps/include/dev/i2c/cadence-i2c.h +++ b/bsps/include/dev/i2c/cadence-i2c.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2014 embedded brains GmbH + * Copyright (C) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index 398fd8bceb..c3615a12a0 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -1,23 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC IRQ + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H @@ -25,12 +39,17 @@ #include <bsp.h> #include <dev/irq/arm-gic.h> -#include <rtems/score/processormask.h> #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + #define ARM_GIC_IRQ_SGI_0 0 #define ARM_GIC_IRQ_SGI_1 1 #define ARM_GIC_IRQ_SGI_2 2 @@ -72,16 +91,6 @@ rtems_status_code arm_gic_irq_get_group( gic_group *group ); -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets); static inline rtems_status_code arm_gic_irq_generate_software_irq( @@ -100,9 +109,13 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( return sc; } +#ifdef RTEMS_SMP uint32_t arm_gic_irq_processor_count(void); void arm_gic_irq_initialize_secondary_cpu(void); +#endif + +/** @} */ #ifdef __cplusplus } diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h index 5da43f83b4..c03a7a7a07 100644 --- a/bsps/include/dev/irq/arm-gic-regs.h +++ b/bsps/include/dev/irq/arm-gic-regs.h @@ -1,23 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Register definitions + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) memory-mapped registers. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H @@ -25,6 +39,12 @@ #include <bsp/utility.h> +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + typedef struct { uint32_t iccicr; #define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4) @@ -212,4 +232,6 @@ typedef struct { uint32_t icspigrpmodr[64]; } gic_sgi_ppi; +/** @} */ + #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h index 167310660d..70e76c7603 100644 --- a/bsps/include/dev/irq/arm-gic-tm27.h +++ b/bsps/include/dev/irq/arm-gic-tm27.h @@ -1,23 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC TM27 Support + * @brief This header file provides the TM27 support for the ARM Generic + * Interrupt Controller (GIC). */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -27,11 +41,11 @@ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H #define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H -#include <assert.h> - #include <bsp.h> #include <bsp/irq.h> +#include <rtems/score/assert.h> + #define MUST_WAIT_FOR_INTERRUPT 1 #ifndef ARM_GIC_TM27_IRQ_LOW @@ -42,50 +56,66 @@ #define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 #endif +#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW + #define ARM_GIC_TM27_PRIO_LOW 0x80 #define ARM_GIC_TM27_PRIO_HIGH 0x00 -static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { - rtems_status_code sc = rtems_interrupt_handler_install( + static rtems_interrupt_entry entry_low; + static rtems_interrupt_entry entry_high; + rtems_status_code sc; + + rtems_interrupt_entry_initialize( + &entry_low, + handler, + NULL, + "tm27 low" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_LOW, - "tm27 low", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_low ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_LOW, ARM_GIC_TM27_PRIO_LOW ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); - sc = rtems_interrupt_handler_install( + rtems_interrupt_entry_initialize( + &entry_high, + handler, + NULL, + "tm27 high" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_HIGH, - "tm27 high", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_high ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_HIGH, ARM_GIC_TM27_PRIO_HIGH ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Cause_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_LOW, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Clear_tm27_intr(void) @@ -95,11 +125,13 @@ static inline void Clear_tm27_intr(void) static inline void Lower_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_HIGH, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } #endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h index 23c70e7b0e..4e418de68f 100644 --- a/bsps/include/dev/irq/arm-gic.h +++ b/bsps/include/dev/irq/arm-gic.h @@ -1,23 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Support + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_H @@ -32,11 +46,14 @@ extern "C" { #endif /* __cplusplus */ /** - * @defgroup arm_gic ARM GIC + * @defgroup DevIRQGIC ARM Generic Interrupt Controller (GIC) Support + * + * @ingroup RTEMSImplClassicIntr * - * @ingroup RTEMSBSPsARMShared + * @brief This group contains the Interrupt Manager implementation parts + * specific to the ARM Generic Interrupt Controller. * - * @brief ARM_GIC Support Package + * @{ */ #define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) @@ -235,6 +252,8 @@ static inline void gic_id_set_handling_model( dist->icdicfr[i] = icdicfr; } +/* @} */ + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h new file mode 100644 index 0000000000..8829c32384 --- /dev/null +++ b/bsps/include/dev/irq/arm-gicv3.h @@ -0,0 +1,403 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup DevIRQGIC + * + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support specific to the GICv3. + */ + +/* + * Copyright (C) 2022 embedded brains GmbH & Co. KG + * Copyright (C) 2019 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_DEV_IRQ_ARM_GICV3_H +#define _RTEMS_DEV_IRQ_ARM_GICV3_H + +#include <dev/irq/arm-gic.h> +#include <dev/irq/arm-gic-arch.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + +#define PRIORITY_DEFAULT 127 + +#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23) +#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23) +#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) +#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15) +#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15) +#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15) +#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7) +#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7) +#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7) + +#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55) +#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55) +#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55) +#define ICC_SGIR_IRM BSP_BIT32(40) +#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39) +#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39) +#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39) +#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27) +#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27) +#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27) +#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23) +#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23) +#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) +#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15) +#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15) +#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15) + +#ifdef ARM_MULTILIB_ARCH_V4 +/* cpuif->iccicr */ +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" + +/* cpuif->iccpmr */ +#define ICC_PMR "p15, 0, %0, c4, c6, 0" + +/* cpuif->iccbpr */ +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" + +/* cpuif->icciar */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" + +/* cpuif->icceoir */ +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" + +#define ICC_SRE "p15, 0, %0, c12, c12, 5" + +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" + +#define MPIDR "p15, 0, %0, c0, c0, 5" + +#define READ_SR(SR_NAME) \ +({ \ + uint32_t value; \ + __asm__ volatile("mrc " SR_NAME : "=r" (value) ); \ + value; \ +}) + +#define WRITE_SR(SR_NAME, VALUE) \ + __asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) ); + +#define ICC_SGI1 "p15, 0, %Q0, %R0, c12" +#define WRITE64_SR(SR_NAME, VALUE) \ + __asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) ); + +#else /* ARM_MULTILIB_ARCH_V4 */ + +/* AArch64 GICv3 registers are not named in GCC */ +#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0" +#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0" +#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0" +#define ICC_IGRPEN0 ICC_IGRPEN0_EL1 +#define ICC_IGRPEN1 ICC_IGRPEN1_EL1 +#define ICC_PMR "S3_0_C4_C6_0, %0" +#define ICC_EOIR1 "S3_0_C12_C12_1, %0" +#define ICC_SRE "S3_0_C12_C12_5, %0" +#define ICC_BPR0 "S3_0_C12_C8_3, %0" +#define ICC_BPR1 "S3_0_C12_C12_3, %0" +#define ICC_CTLR "S3_0_C12_C12_4, %0" +#define ICC_IAR1 "%0, S3_0_C12_C12_0" +#define MPIDR "%0, mpidr_el1" +#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39) +#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39) +#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39) + +#define ICC_SGI1 "S3_0_C12_C11_5, %0" +#define WRITE64_SR(SR_NAME, VALUE) \ + __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) ); +#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE) + +#define READ_SR(SR_NAME) \ +({ \ + uint64_t value; \ + __asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \ + value; \ +}) + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index) +{ + return (volatile gic_redist *) + ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000); +} + +static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index) +{ + return (volatile gic_sgi_ppi *) + ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000); +} + +static inline void gicv3_sgi_ppi_enable( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + /* Set G1NS */ + sgi_ppi->icspigrpr[0] |= 1U << vector; + sgi_ppi->icspigrpmodr[0] &= ~(1U << vector); + + /* Set enable */ + sgi_ppi->icspiser[0] = 1U << vector; +} + +static inline void gicv3_sgi_ppi_disable( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + sgi_ppi->icspicer[0] = 1U << vector; +} + +static inline bool gicv3_sgi_ppi_is_enabled( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + return (sgi_ppi->icspiser[0] & (1U << vector)) != 0; +} + +static inline void gicv3_sgi_ppi_set_priority( + rtems_vector_number vector, + uint8_t priority, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + sgi_ppi->icspiprior[vector] = priority; +} + +static inline uint8_t gicv3_sgi_ppi_get_priority( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + return sgi_ppi->icspiprior[vector]; +} + +static inline bool gicv3_sgi_ppi_is_pending( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + return (sgi_ppi->icspispendr[0] & (1U << vector)) != 0; +} + +static inline void gicv3_ppi_set_pending( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + sgi_ppi->icspispendr[0] = 1U << vector; +} + +static inline void gicv3_ppi_clear_pending( + rtems_vector_number vector, + uint32_t cpu_index +) +{ + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + + sgi_ppi->icspicpendr[0] = 1U << vector; +} + +static inline void gicv3_trigger_sgi( + rtems_vector_number vector, + uint32_t targets +) +{ +#ifndef ARM_MULTILIB_ARCH_V4 + uint64_t mpidr; +#else + uint32_t mpidr; +#endif + mpidr = READ_SR(MPIDR); + uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) + | ICC_SGIR_INTID(vector) + | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) + | ICC_SGIR_CPU_TARGET_LIST(targets); +#ifndef ARM_MULTILIB_ARCH_V4 + value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr)); +#endif + WRITE64_SR(ICC_SGI1, value); +} + +static inline uint32_t gicv3_get_id_count(volatile gic_dist *dist) +{ + uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); + + id_count = 32 * (id_count + 1); + id_count = id_count <= 1020 ? id_count : 1020; + + return id_count; +} + +static void gicv3_init_dist(volatile gic_dist *dist) +{ + uint32_t id_count = gicv3_get_id_count(dist); + uint32_t id; + + dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S + | GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS + | GIC_DIST_ICDDCR_ENABLE_GRP0; + + for (id = 0; id < id_count; id += 32) { + /* Disable all interrupts */ + dist->icdicer[id / 32] = 0xffffffff; + + /* Set G1NS */ + dist->icdigr[id / 32] = 0xffffffff; + dist->icdigmr[id / 32] = 0; + } + + for (id = 0; id < id_count; ++id) { + gic_id_set_priority(dist, id, PRIORITY_DEFAULT); + } + + for (id = 32; id < id_count; ++id) { + gic_id_set_targets(dist, id, 0x01); + } +} + +static void gicv3_init_cpu_interface(uint32_t cpu_index) +{ + /* Initialize Interrupt Controller System Register Enable Register */ +#ifdef BSP_ARM_GIC_ICC_SRE + WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE); +#endif + + /* Initialize Interrupt Controller Interrupt Priority Mask Register */ +#ifdef BSP_ARM_GIC_ICC_PMR + WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR); +#endif + + /* Initialize Interrupt Controller Binary Point Register 0 */ +#ifdef BSP_ARM_GIC_ICC_BPR0 + WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0); +#endif + + /* Initialize Interrupt Controller Binary Point Register 1 */ +#ifdef BSP_ARM_GIC_ICC_BPR1 + WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1); +#endif + + volatile gic_redist *redist = gicv3_get_redist(cpu_index); + uint32_t waker = redist->icrwaker; + uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP; + waker &= ~waker_mask; + redist->icrwaker = waker; + + volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); + /* Set G1NS */ + sgi_ppi->icspigrpr[0] = 0xffffffff; + sgi_ppi->icspigrpmodr[0] = 0; + for (int id = 0; id < 32; id++) { + sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; + } + + /* Initialize Interrupt Controller Interrupt Group Enable 0 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN0 + WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0); +#endif + + /* Initialize Interrupt Controller Interrupt Group Enable 1 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN1 + WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1); +#endif + + /* Initialize Interrupt Controller Control Register */ +#ifdef BSP_ARM_GIC_ICC_CTRL + WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL); +#endif +} + +static inline void gicv3_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_raise = true; + + if ( vector <= ARM_GIC_IRQ_SGI_LAST ) { + /* + * It is implementation-defined whether implemented SGIs are permanently + * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and + * GICD_ICENABLER0. + */ + attributes->can_raise_on = true; + attributes->cleared_by_acknowledge = true; + attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL; + } else { + attributes->can_disable = true; + attributes->can_clear = true; + attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL; + + if ( vector > ARM_GIC_IRQ_PPI_LAST ) { + /* SPI */ + attributes->can_get_affinity = true; + attributes->can_set_affinity = true; + } + } +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_DEV_IRQ_ARM_GICV3_H */ diff --git a/bsps/include/dev/nand/xnandpsu.h b/bsps/include/dev/nand/xnandpsu.h new file mode 100644 index 0000000000..ac9496a745 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu.h @@ -0,0 +1,642 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu.h +* @addtogroup Overview +* @{ +* @details +* +* This file implements a driver to support Arasan NAND controller +* present in Zynq Ultrascale Mp. +* +* <b>Driver Initialization</b> +* +* The function call XNandPsu_CfgInitialize() should be called by the application +* before any other function in the driver. The initialization function takes +* device specific data (like device id, instance id, and base address) and +* initializes the XNandPsu instance with the device specific data. +* +* <b>Device Geometry</b> +* +* NAND flash device is memory device and it is segmented into areas called +* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device +* can have multiple LUN. LUN is sequential raw of multiple blocks of the same +* size. A block is the smallest erasable unit of data within the Flash array of +* a LUN. The size of each block is based on a power of 2. There is no +* restriction on the number of blocks within the LUN. A block contains a number +* of pages. A page is the smallest addressable unit for read and program +* operations. The arrangement of LUN, blocks, and pages is referred to by this +* module as the part's geometry. +* +* The cells within the part can be programmed from a logic 1 to a logic 0 +* and not the other way around. To change a cell back to a logic 1, the +* entire block containing that cell must be erased. When a block is erased +* all bytes contain the value 0xFF. The number of times a block can be +* erased is finite. Eventually the block will wear out and will no longer +* be capable of erasure. As of this writing, the typical flash block can +* be erased 100,000 or more times. +* +* The jobs done by this driver typically are: +* - 8-bit operational mode +* - Read, Write, and Erase operation +* +* <b>Write Operation</b> +* +* The write call can be used to write a minimum of one byte and a maximum +* entire flash. If the address offset specified to write is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The write is blocking in nature in that +* the control is returned back to user only after the write operation is +* completed successfully or an error is reported. +* +* <b>Read Operation</b> +* +* The read call can be used to read a minimum of one byte and maximum of +* entire flash. If the address offset specified to read is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The read is blocking in nature in that +* the control is returned back to user only after the read operation is +* completed successfully or an error is reported. +* +* <b>Erase Operation</b> +* +* The erase operations are provided to erase a Block in the Flash memory. The +* erase call is blocking in nature in that the control is returned back to user +* only after the erase operation is completed successfully or an error is +* reported. +* +* @note Driver has been renamed to nandpsu after change in +* naming convention. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads, +* mutual exclusion, virtual memory, cache control, or HW write protection +* management must be satisfied by the layer above this driver. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 2.0 sb 01/12/2015 Removed Null checks for Buffer passed +* as parameter to Read API's +* - XNandPsu_Read() +* - XNandPsu_ReadPage +* Modified +* - XNandPsu_SetFeature() +* - XNandPsu_GetFeature() +* and made them public. +* Removed Failure Return for BCF Error check in +* XNandPsu_ReadPage() and added BCH_Error counter +* in the instance pointer structure. +* Added XNandPsu_Prepare_Cmd API +* Replaced +* - XNandPsu_IntrStsEnable +* - XNandPsu_IntrStsClear +* - XNandPsu_IntrClear +* - XNandPsu_SetProgramReg +* with XNandPsu_WriteReg call +* Modified xnandpsu.c file API's with above changes. +* Corrected the program command for Set Feature API. +* Modified +* - XNandPsu_OnfiReadStatus +* - XNandPsu_GetFeature +* - XNandPsu_SetFeature +* to add support for DDR mode. +* Changed Convention for SLC/MLC +* SLC --> HAMMING +* MLC --> BCH +* SlcMlc --> IsBCH +* Added support for writing BBT signature and version +* in page section by enabling XNANDPSU_BBT_NO_OOB. +* Removed extra DMA mode initialization from +* the XNandPsu_CfgInitialize API. +* Modified +* - XNandPsu_SetEccAddrSize +* ECC address now is calculated based upon the +* size of spare area +* Modified Block Erase API, removed clearing of +* packet register before erase. +* Clearing Data Interface Register before +* XNandPsu_OnfiReset call. +* Modified XNandPsu_ChangeTimingMode API supporting +* SDR and NVDDR interface for timing modes 0 to 5. +* Modified Bbt Signature and Version Offset value for +* Oob and No-Oob region. +* 1.0 kpc 17/06/2015 Increased the timeout for complete event to avoid +* timeout errors for erase operation on slower devices. +* 1.1 mi 09/16/16 Removed compilation warnings with extra compiler flags. +* 1.1 nsk 11/07/16 Change memcpy to Xil_MemCpy, CR#960462 +* 1.2 nsk 01/19/17 Fix for the failure of reading nand first redundant +* parameter page. CR#966603 +* ms 02/12/17 Fix for the compilation warning in _g.c file. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified Comment lines in nandpsu_example.c to +* follow doxygen rules. +* 1.2 nsk 08/08/17 Added support to import example in SDK +* 1.4 nsk 04/10/18 Added ICCARM compiler support. CR#997552. +* 1.5 mus 11/08/18 Updated BBT signature array size in +* XNandPsu_BbtDesc structure to fix the compilation +* warnings. +# 1.6 sd 06/02/20 Added Clock support +* 1.6 sd 20/03/20 Added compilation flag +* 1.8 sg 03/18/21 Added validation check for parameter page. +* 1.9 akm 07/15/21 Initialize NandInstPtr with Data Interface & Timing mode info. +* 1.10 akm 10/20/21 Fix gcc warnings. +* 1.10 akm 12/21/21 Validate input parameters before use. +* 1.10 akm 01/05/22 Remove assert checks form static and internal APIs. +* 1.11 akm 03/31/22 Fix unused parameter warning. +* 1.11 akm 03/31/22 Fix misleading-indentation warning. +* +* </pre> +* +******************************************************************************/ + +#ifndef XNANDPSU_H /* prevent circular inclusions */ +#define XNANDPSU_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include <string.h> +#include "xstatus.h" +#include "xil_assert.h" +#include "xnandpsu_hw.h" +#include "xnandpsu_onfi.h" +#include "xil_cache.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif +/************************** Constant Definitions *****************************/ + +#define XNANDPSU_DEBUG + +#ifdef __rtems__ +#define XNANDPSU_MAX_TARGETS 2U /**< ce_n0, ce_n1 */ +#else +#define XNANDPSU_MAX_TARGETS 1U /**< ce_n0, ce_n1 */ +#endif +#define XNANDPSU_MAX_PKT_SIZE 0x7FFU /**< Max packet size */ +#define XNANDPSU_MAX_PKT_COUNT 0xFFFU /**< Max packet count */ + +#define XNANDPSU_PAGE_SIZE_512 512U /**< 512 bytes page */ +#define XNANDPSU_PAGE_SIZE_2K 2048U /**< 2K bytes page */ +#define XNANDPSU_PAGE_SIZE_4K 4096U /**< 4K bytes page */ +#define XNANDPSU_PAGE_SIZE_8K 8192U /**< 8K bytes page */ +#define XNANDPSU_PAGE_SIZE_16K 16384U /**< 16K bytes page */ +#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */ +#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */ + +#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */ +#define XNANDPSU_BCH 0x2U /**< BCH Flash */ + +#define XNANDPSU_MAX_BLOCKS 16384U /**< Max number of Blocks */ +#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND + flash page of 16K */ +#define XNANDPSU_MAX_LUNS 8U /**< Max number of LUNs */ +#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U /**< Max number pages per block */ + +#define XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U + +#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U) + +#define XNANDPSU_MAX_TIMING_MODE 5 + +#ifdef __rtems__ +#define XNANDPSU_PAGE_CACHE_UNAVAILABLE -2 +#define XNANDPSU_PAGE_CACHE_NONE -1 +#endif + +/** + * The XNandPsu_Config structure contains configuration information for NAND + * controller. + */ +typedef struct { + u16 DeviceId; /**< Instance ID of NAND flash controller */ + u32 BaseAddress; /**< Base address of NAND flash controller */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +#if defined (XCLOCKING) + u32 RefClk; /**< Input clocks */ +#endif +} XNandPsu_Config; + +/** + * The XNandPsu_DataInterface enum contains flash operating mode. + */ +typedef enum { + XNANDPSU_SDR = 0U, /**< Single Data Rate */ + XNANDPSU_NVDDR /**< Double Data Rate */ +} XNandPsu_DataInterface; + +/** + * XNandPsu_TimingMode enum contains timing modes. + */ +typedef enum { + XNANDPSU_SDR0 = 0U, + XNANDPSU_SDR1, + XNANDPSU_SDR2, + XNANDPSU_SDR3, + XNANDPSU_SDR4, + XNANDPSU_SDR5, + XNANDPSU_NVDDR0, + XNANDPSU_NVDDR1, + XNANDPSU_NVDDR2, + XNANDPSU_NVDDR3, + XNANDPSU_NVDDR4, + XNANDPSU_NVDDR5 +} XNandPsu_TimingMode; + +/** + * The XNandPsu_SWMode enum contains the driver operating mode. + */ +typedef enum { + XNANDPSU_POLLING = 0, /**< Polling */ + XNANDPSU_INTERRUPT /**< Interrupt */ +} XNandPsu_SWMode; + +/** + * The XNandPsu_DmaMode enum contains the controller MDMA mode. + */ +typedef enum { + XNANDPSU_PIO = 0, /**< PIO Mode */ + XNANDPSU_SDMA, /**< SDMA Mode */ + XNANDPSU_MDMA /**< MDMA Mode */ +} XNandPsu_DmaMode; + +/** + * The XNandPsu_EccMode enum contains ECC functionality. + */ +typedef enum { + XNANDPSU_NONE = 0, + XNANDPSU_HWECC, + XNANDPSU_EZNAND, + XNANDPSU_ONDIE +} XNandPsu_EccMode; + +/** + * Bad block table descriptor + */ +typedef struct { + u32 PageOffset[XNANDPSU_MAX_TARGETS]; + /**< Page offset where BBT resides */ + u32 SigOffset; /**< Signature offset in Spare area */ + u32 VerOffset; /**< Offset of BBT version */ + u32 SigLength; /**< Length of the signature */ + u32 MaxBlocks; /**< Max blocks to search for BBT */ + char Signature[5]; /**< BBT signature */ + u8 Version[XNANDPSU_MAX_TARGETS]; + /**< BBT version */ + u32 Valid; /**< BBT descriptor is valid or not */ +} XNandPsu_BbtDesc; + +/** + * Bad block pattern + */ +typedef struct { + u32 Options; /**< Options to search the bad block pattern */ + u32 Offset; /**< Offset to search for specified pattern */ + u32 Length; /**< Number of bytes to check the pattern */ + u8 Pattern[2]; /**< Pattern format to search for */ +} XNandPsu_BadBlockPattern; + +/** + * The XNandPsu_Geometry structure contains the ONFI geometry information. + */ +typedef struct { + /* Parameter page information */ + u32 BytesPerPage; /**< Number of bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 RowAddrCycles; /**< Row address cycles */ + u8 ColAddrCycles; /**< Column address cycles */ + u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */ + u8 NumBitsECC; /**< Number of bits ECC correctability */ + u32 EccCodeWordSize; /**< ECC codeword size */ + /* Driver specific information */ + u32 BlockSize; /**< Block size */ + u32 NumTargetPages; /**< Total number of pages in a Target */ + u32 NumTargetBlocks; /**< Total number of blocks in a Target */ + u64 TargetSize; /**< Target size in bytes */ + u8 NumTargets; /**< Number of targets present */ + u32 NumPages; /**< Total number of pages */ + u32 NumBlocks; /**< Total number of blocks */ + u64 DeviceSize; /**< Total flash size in bytes */ +} XNandPsu_Geometry; + +/** + * The XNandPsu_Features structure contains the ONFI features information. + */ +typedef struct { + u32 NvDdr; + u32 EzNand; + u32 OnDie; + u32 ExtPrmPage; +} XNandPsu_Features; + +/** + * The XNandPsu_EccMatrix structure contains ECC features information. + */ +typedef struct { + u16 PageSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; + u16 EccAddr; + u16 EccSize; +} XNandPsu_EccMatrix; + +/** + * The XNandPsu_EccCfg structure contains ECC configuration. + */ +typedef struct { + u16 EccAddr; + u16 EccSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; +} XNandPsu_EccCfg; + +/** + * The XNandPsu structure contains the driver instance data. The user is + * required to allocate a variable of this type for the NAND controller. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u32 IsReady; /**< Device is initialized and ready */ + XNandPsu_Config Config; + u32 Ecc_Stat_PerPage_flips; /**< Ecc Correctable Error Counter for Current Page */ + u32 Ecc_Stats_total_flips; /**< Total Ecc Errors Corrected */ + XNandPsu_DataInterface DataInterface; + XNandPsu_TimingMode TimingMode; + XNandPsu_SWMode Mode; /**< Driver operating mode */ + XNandPsu_DmaMode DmaMode; /**< MDMA mode enabled/disabled */ + XNandPsu_EccMode EccMode; /**< ECC Mode */ + XNandPsu_EccCfg EccCfg; /**< ECC configuration */ + XNandPsu_Geometry Geometry; /**< Flash geometry */ + XNandPsu_Features Features; /**< ONFI features */ +#ifdef __rtems__ + int32_t PartialDataPageIndex; /**< Cached page index */ +#endif +#ifdef __ICCARM__ + u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE]; /**< Partial read/write buffer */ +#pragma pack(pop) +#else + u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64))); +#endif + /* Bad block table definitions */ + XNandPsu_BbtDesc BbtDesc; /**< Bad block table descriptor */ + XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */ + XNandPsu_BadBlockPattern BbPattern; /**< Bad block pattern to + search */ + u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2]; /**< Bad block table array */ +} XNandPsu; + +/******************* Macro Definitions (Inline Functions) *******************/ + +/*****************************************************************************/ +/** + * This macro sets the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) | (BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) & ~(BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears and updates the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param Mask is the bitmask. + * @param Value is the register value to write. + * + * @note C-style signature: + * void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr, + * u32 RegOffset, u32 Mask, u32 Val) + * + *****************************************************************************/ +#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\ + (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value)))) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro clears bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigClear(InstancePtr, Mask) \ + XNandPsu_ClrBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Status Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_STS_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro checks for the ONFI ID. + * + * @param Buff is the buffer holding ONFI ID + * + * @note none. + * + *****************************************************************************/ +#define IS_ONFI(Buff) \ + ((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \ + ((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I') + +/************************** Function Prototypes *****************************/ + +s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length); + +s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *SrcBuf); + +s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *DestBuf); + +s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block); + +s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr, + XNandPsu_DataInterface NewIntf, + XNandPsu_TimingMode NewMode); + +s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr); + +s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block); + +#ifdef __rtems__ +#include <stdbool.h> +/*****************************************************************************/ +/** +* This function changes the marking of a block in the RAM based Bad Block Table(BBT). It +* also updates the Bad Block Table(BBT) in the flash if necessary. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @param Block is the block number. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +******************************************************************************/ +s32 XNandPsu_MarkBlock(XNandPsu *InstancePtr, u32 Block, u8 BlockMark); + +/*****************************************************************************/ +/** +* This function changes the marking of a block in the RAM based Bad Block Table(BBT). It +* does not update the Bad Block Table(BBT) in the flash. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @param Block is the block number. +* +* @return +* - true if the BBT needs updating. +* - false if the BBT does not need updating. +* +******************************************************************************/ +bool XNandPsu_StageBlockMark(XNandPsu *InstancePtr, u32 Block, u8 BlockMark); + +/*****************************************************************************/ +/** +* This function updates the primary and mirror Bad Block Table(BBT) in the +* flash. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +******************************************************************************/ +s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target); +#endif + +void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_EnableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, + u8 DmaMode, u8 AddrCycles); + +/* XNandPsu_LookupConfig in xnandpsu_sinit.c */ +XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID); + + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_bbm.h b/bsps/include/dev/nand/xnandpsu_bbm.h new file mode 100644 index 0000000000..b6b39dc990 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_bbm.h @@ -0,0 +1,180 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_bbm.h +* @addtogroup Overview +* @{ +* +* This file implements the Bad Block Management(BBM) functionality. This is +* similar to the Bad Block Management which is a part of the MTD subsystem in +* Linux. The factory marked bad blocks are scanned initially and a Bad Block +* Table(BBT) is created in the memory. This table is also written to the flash +* so that upon reboot, the BBT is read back from the flash and loaded into the +* memory instead of scanning every time. The Bad Block Table(BBT) is written +* into one of the the last four blocks in the flash memory. The last four +* blocks are marked as Reserved so that user can't erase/program those blocks. +* +* There are two bad block tables, a primary table and a mirror table. The +* tables are versioned and incrementing version number is used to detect and +* recover from interrupted updates. Each table is stored in a separate block, +* beginning in the first page of that block. Only two blocks would be necessary +* in the absence of bad blocks within the last four; the range of four provides +* a little slack in case one or two of those blocks is bad. These blocks are +* marked as reserved and cannot be programmed by the user. A NAND Flash device +* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block +* table signature is written into the spare data area of the pages containing +* bad block table so that upon rebooting the bad block table signature is +* searched and the bad block table is loaded into RAM. The signature is "Bbt0" +* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The +* version offset follows the signature offset in the spare data area. The +* version number increments on every update to the bad block table and the +* version wraps at 0xff. +* +* Each block in the Bad Block Table(BBT) is represented by 2 bits. +* The two bits are encoded as follows in RAM BBT. +* 0'b00 -> Good Block +* 0'b01 -> Block is bad due to wear +* 0'b10 -> Reserved block +* 0'b11 -> Factory marked bad block +* +* While writing to the flash the two bits are encoded as follows. +* 0'b00 -> Factory marked bad block +* 0'b01 -> Reserved block +* 0'b10 -> Block is bad due to wear +* 0'b11 -> Good Block +* +* The user can check for the validity of the block using the API +* XNandPsu_IsBlockBad and take the action based on the return value. Also user +* can update the bad block table using XNandPsu_MarkBlockBad API. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 2.0 sb 01/12/2015 Added support for writing BBT signature and version +* in page section by enabling XNANDPSU_BBT_NO_OOB. +* Modified Bbt Signature and Version Offset value for +* Oob and No-Oob region. +* </pre> +* +******************************************************************************/ +#ifndef XNANDPSU_BBM_H /* prevent circular inclusions */ +#define XNANDPSU_BBM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xnandpsu.h" + +/************************** Constant Definitions *****************************/ +/* Block definitions for RAM based Bad Block Table (BBT) */ +#define XNANDPSU_BLOCK_GOOD 0x0U /**< Block is good */ +#define XNANDPSU_BLOCK_BAD 0x1U /**< Block is bad */ +#define XNANDPSU_BLOCK_RESERVED 0x2U /**< Reserved block */ +#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U /**< Factory marked bad + block */ +/* Block definitions for FLASH based Bad Block Table (BBT) */ +#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U /**< Block is good */ +#define XNANDPSU_FLASH_BLOCK_BAD 0x2U /**< Block is bad */ +#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U /**< Reserved block */ +#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U /**< Factory marked bad + block */ + +#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U /**< Scan the + second page + for bad block + information + */ +#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U /**< Page offset of Bad + Block Table Desc */ +#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U /**< Bad Block Table + signature offset */ +#define XNANDPSU_BBT_DESC_VER_OFFSET 12U /**< Bad block Table + version offset */ +#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U /**< Bad Block Table + signature offset in + page memory */ +#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U /**< Bad block Table + version offset in + page memory */ +#define XNANDPSU_BBT_DESC_SIG_LEN 4U /**< Bad block Table + signature length */ +#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U /**< Bad block Table + max blocks */ + +#define XNANDPSU_BBT_BLOCK_SHIFT 2U /**< Block shift value + for a block in BBT */ +#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U /**< Num of blocks in + one BBT entry */ +#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U /**< Bad block pattern + offset in a page */ +#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U /**< Bad block pattern + offset in a large + page */ +#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PATTERN 0xFFU /**< Bad block pattern + to search in a page + */ +#define XNANDPSU_BLOCK_TYPE_MASK 0x03U /**< Block type mask */ +#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U /**< Block shift mask + for a Bad Block Table + entry byte */ + +#define XNANDPSU_ONDIE_SIG_OFFSET 0x4U +#define XNANDPSU_ONDIE_VER_OFFSET 0x14U + +#define XNANDPSU_BBT_VERSION_LENGTH 1U +#define XNANDPSU_BBT_SIG_LENGTH 4U + +#define XNANDPSU_BBT_BUF_LENGTH ((XNANDPSU_MAX_BLOCKS >> \ + XNANDPSU_BBT_BLOCK_SHIFT) + \ + (XNANDPSU_BBT_DESC_SIG_OFFSET + \ + XNANDPSU_BBT_SIG_LENGTH + \ + XNANDPSU_BBT_VERSION_LENGTH)) +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro returns the Block shift value corresponding to a Block. +* +* @param Block is the block number. +* +* @return Block shift value +* +* @note None. +* +*****************************************************************************/ +#define XNandPsu_BbtBlockShift(Block) \ + (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr); + +s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_hw.h b/bsps/include/dev/nand/xnandpsu_hw.h new file mode 100644 index 0000000000..e3a648b136 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_hw.h @@ -0,0 +1,483 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_hw.h +* @addtogroup Overview +* @{ +* +* This file contains identifiers and low-level macros/functions for the Arasan +* NAND flash controller driver. +* +* See xnandpsu.h for more information. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First Release +* 2.0 sb 11/04/2014 Changed XNANDPSU_ECC_SLC_MLC_MASK to +* XNANDPSU_ECC_HAMMING_BCH_MASK. +* 1.7 akm 09/03/20 Updated the Makefile to support parallel make +* execution. +* </pre> +* +******************************************************************************/ + +#ifndef XNANDPSU_HW_H /* prevent circular inclusions */ +#define XNANDPSU_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/************************** Register Offset Definitions **********************/ + +#define XNANDPSU_PKT_OFFSET 0x00U /**< Packet Register */ +#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U /**< Memory Address + Register 1 */ +#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U /**< Memory Address + Register 2 */ +#define XNANDPSU_CMD_OFFSET 0x0CU /**< Command Register */ +#define XNANDPSU_PROG_OFFSET 0x10U /**< Program Register */ +#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status + Enable Register */ +#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal + Enable Register */ +#define XNANDPSU_INTR_STS_OFFSET 0x1CU /**< Interrupt Status + Register */ +#define XNANDPSU_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status + Register */ +#define XNANDPSU_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */ +#define XNANDPSU_TIMING_OFFSET 0x2CU /**< Timing Register */ +#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port + Register */ +#define XNANDPSU_ECC_OFFSET 0x34U /**< ECC Register */ +#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count + Register */ +#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command + Register */ +#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit + Register */ +#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit + Register */ +#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit + Register */ +#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit + Register */ +#define XNANDPSU_CPU_REL_OFFSET 0x58U /**< CPU Release Register */ +#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit + Register */ +#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit + Register */ +#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit + Register */ +#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit + Register */ +#define XNANDPSU_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */ +#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0 + Register */ +#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1 + Register */ +#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary + Register */ +#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration + Register */ + +/** @name Packet Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */ +#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/ +#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */ +/* @} */ + +/** @name Memory Address Register 1 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address + Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block + Address Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */ +/* @} */ + +/** @name Memory Address Register 2 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address + */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode + Value */ +#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash + Connection Mode */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select + shift */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U +/* @} */ + +/** @name Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle + Command */ +#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle + Command */ +#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */ +#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable + Mode */ +#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of + Address Cycles */ +#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */ +#define XNANDPSU_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command + Shift */ +#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */ +#define XNANDPSU_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */ +#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address + Cycles Shift */ +#define XNANDPSU_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */ +/* @} */ + +/** @name Program Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PROG_RD_MASK 0x00000001U /**< Read */ +#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */ +#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */ +#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U /**< Read Status */ +#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */ +#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */ +#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U /**< Read ID */ +#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param + Page */ +#define XNANDPSU_PROG_RST_MASK 0x00000100U /**< Reset */ +#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */ +#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */ +#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique + ID */ +#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status + Enhanced */ +#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read + Interleaved */ +#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read + Column + Enhanced */ +#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back + Interleaved */ +#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache + Start */ +#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache + Sequential */ +#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache + Random */ +#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache + End */ +#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data + Move */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row + Address */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row + Address End */ +#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */ +#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced + Program Page + Register Clear */ +#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */ +#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */ +/* @} */ + +/** @name Interrupt Status Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Status + Enable, + BCH Detect + Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Status + Enable */ +/* @} */ + +/** @name Interrupt Signal Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Signal + Enable, + BCH Detect + Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Signal + Enable */ +/* @} */ + +/** @name Interrupt Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write + Ready */ +#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read + Ready */ +#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete */ +#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error */ +#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error, + BCH Detect + Error */ +#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Interrupt + */ +#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB */ +/* @} */ + +/** @name Interrupt bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write + Ready Status + Enable */ +#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read + Ready Status + Enable */ +#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete Status + Enable */ +#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error + Status Enable */ +#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error + Status Enable, + BCH Detect Error + Status Enable */ +#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status + Enable */ +#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status + Enable */ +/* @} */ + +/** @name ID2 Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */ +/* @} */ + +/** @name Flash Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status + Value */ +/* @} */ + +/** @name Timing Register bit definitions and masks + * @{ + */ +#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column + setup time */ +#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device + */ +#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data + transaction value + */ +#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch + enable to Data + loading time */ +/* @} */ + +/** @name ECC Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */ +#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */ +#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH + support */ +/* @} */ + +/** @name ECC Error Count Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet + bound error + count */ +#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page + bound error + count */ +/* @} */ + +/** @name ECC Spare Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC + spare + command */ +#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number + of ECC/ + spare + address + cycles */ +/* @} */ + +/** @name Data Interface Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */ +#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data + Interface */ +#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */ +#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */ +/* @} */ + +/** @name DMA Buffer Boundary Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer + boundary */ +#define XNANDPSU_DMA_BUF_BND_4K 0x0U +#define XNANDPSU_DMA_BUF_BND_8K 0x1U +#define XNANDPSU_DMA_BUF_BND_16K 0x2U +#define XNANDPSU_DMA_BUF_BND_32K 0x3U +#define XNANDPSU_DMA_BUF_BND_64K 0x4U +#define XNANDPSU_DMA_BUF_BND_128K 0x5U +#define XNANDPSU_DMA_BUF_BND_256K 0x6U +#define XNANDPSU_DMA_BUF_BND_512K 0x7U +/* @} */ + +/** @name Slave DMA Configuration Register bit definitions and masks + * @{ + */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave + DMA + Transfer + Direction + */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave + DMA + Transfer + Count */ +#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave + DMA + Burst + Size */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA + Timeout + Counter + Value */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave + DMA + Enable */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the base address of controller registers. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XNandPsu_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddress is the the base address of controller registers. +* @param RegOffset is the register offset to be written. +* @param Data is the the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(((BaseAddress) + (RegOffset)), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_HW_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_onfi.h b/bsps/include/dev/nand/xnandpsu_onfi.h new file mode 100644 index 0000000000..97ea3c404e --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_onfi.h @@ -0,0 +1,316 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_onfi.h +* @addtogroup Overview +* @{ +* +* This file defines all the ONFI 3.1 specific commands and values. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 1.4 nsk 04/10/2018 Added ICCARM compiler support. +* </pre> +* +******************************************************************************/ +#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */ +#define XNANDPSU_ONFI_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +/* Standard ONFI 3.1 Commands */ +/* ONFI 3.1 Mandatory Commands */ +#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */ +#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column + (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column + (2nd cycle) */ +#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */ +#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */ +#define ONFI_CMD_RD_STS 0x70U /**< Read Status */ +#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */ +#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */ +#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */ +#define ONFI_CMD_RD_ID 0x90U /**< Read ID */ +#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */ +#define ONFI_CMD_RST 0xFFU /**< Reset */ +/* ONFI 3.1 Optional Commands */ +#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read + (1st cycle) */ +#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read + (2nd cycle) */ +#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read + (1st cycle) */ +#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read + (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column + Enhanced (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column + Enhanced (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random + (1st cycle) */ +#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random + (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */ +#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */ +#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase + (1st cycle) */ +#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase + (2nd cycle) */ +#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */ +#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved + (2nd cycle) */ +#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program + (1st cycle) */ +#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program + (2nd cycle) */ +#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program + (1st cycle) */ +#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program + (2nd cycle) */ +#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program + (1st cycle) */ +#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program + (2nd cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback + Program (1st cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback + Program (2nd cycle) */ +#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move + (1st cycle) */ +#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move + (2nd cycle) */ +#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */ +#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */ +#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */ +#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */ +#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */ +#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */ +#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */ +#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */ +#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */ +#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */ + +/* ONFI Status Register bit offsets */ +#define ONFI_STS_FAIL 0x01U /**< FAIL */ +#define ONFI_STS_FAILC 0x02U /**< FAILC */ +#define ONFI_STS_CSP 0x08U /**< CSP */ +#define ONFI_STS_VSP 0x10U /**< VSP */ +#define ONFI_STS_ARDY 0x20U /**< ARDY */ +#define ONFI_STS_RDY 0x40U /**< RDY */ +#define ONFI_STS_WP 0x80U /**< WP_n */ + +/* ONFI constants */ +#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */ +#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */ +#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory + parameter pages */ +#define ONFI_SIG_LEN 4U /**< Signature Length */ +#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */ + +#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */ +#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */ +#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address + cycles */ + +#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page + address cycles */ + +/** + * This enum defines the ONFI 3.1 commands. + */ +enum OnfiCommandList { + READ=0, /**< Read */ + MULTIPLANE_READ, /**< Multiplane Read */ + COPYBACK_READ, /**< Copyback Read */ + CHANGE_READ_COLUMN, /**< Change Read Column */ + CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */ + READ_CACHE_RANDOM, /**< Read Cache Random */ + READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */ + READ_CACHE_END, /**< Read Cache End */ + BLOCK_ERASE, /**< Block Erase */ + MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */ + READ_STATUS, /**< Read Status */ + READ_STATUS_ENHANCED, /**< Read Status Enhanced */ + PAGE_PROGRAM, /**< Page Program */ + MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */ + PAGE_CACHE_PROGRAM, /**< Page Cache Program */ + COPYBACK_PROGRAM, /**< Copyback Program */ + MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */ + SMALL_DATA_MOVE, /**< Small Data Move */ + CHANGE_WRITE_COLUMN, /**< Change Write Column */ + CHANGE_ROW_ADDR, /**< Change Row Address */ + READ_ID, /**< Read ID */ + VOLUME_SELECT, /**< Volume Select */ + ODT_CONFIGURE, /**< ODT Configure */ + READ_PARAM_PAGE, /**< Read Parameter Page */ + READ_UNIQUE_ID, /**< Read Unique ID */ + GET_FEATURES, /**< Get Features */ + SET_FEATURES, /**< Set Features */ + LUN_GET_FEATURES, /**< LUN Get Features */ + LUN_SET_FEATURES, /**< LUN Set Features */ + RESET_LUN, /**< Reset LUN */ + SYN_RESET, /**< Synchronous Reset */ + RESET, /**< Reset */ + MAX_CMDS /**< Dummy Command */ +}; + +/**************************** Type Definitions *******************************/ +/* Parameter page structure of ONFI 3.1 specification. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + /* Revision information and features block */ + u8 Signature[4]; /**< Parameter page signature */ + u16 Revision; /**< Revision Number */ + u16 Features; /**< Features supported */ + u16 OptionalCmds; /**< Optional commands supported */ + u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced + command support */ + u8 Reserved0; /**< Reserved (11) */ + u16 ExtParamPageLen; /**< Extended Parameter Page Length */ + u8 NumOfParamPages; /**< Number of Parameter Pages */ + u8 Reserved1[17]; /**< Reserved (15-31) */ + /* Manufacturer information block */ + u8 DeviceManufacturer[12]; /**< Device manufacturer */ + u8 DeviceModel[20]; /**< Device model */ + u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */ + u8 DateCode[2]; /**< Date code */ + u8 Reserved2[13]; /**< Reserved (67-79) */ + /* Memory organization block */ + u32 BytesPerPage; /**< Number of data bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 BytesPerPartialPage; /**< Number of data bytes per + partial page */ + u16 SpareBytesPerPartialPage; /**< Number of spare bytes per + partial page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 AddrCycles; /**< Number of address cycles */ + u8 BitsPerCell; /**< Number of bits per cell */ + u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */ + u16 BlockEndurance; /**< Block endurance */ + u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at + beginning of target */ + u16 BlockEnduranceGVB; /**< Block endurance for guaranteed + valid block */ + u8 ProgramsPerPage; /**< Number of programs per page */ + u8 PartialProgAttr; /**< Partial programming attributes */ + u8 EccBits; /**< Number of bits ECC + correctability */ + u8 PlaneAddrBits; /**< Number of plane address bits */ + u8 PlaneOperationAttr; /**< Multi-plane operation + attributes */ + u8 EzNandSupport; /**< EZ NAND support */ + u8 Reserved3[12]; /**< Reserved (116 - 127) */ + /* Electrical parameters block */ + u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */ + u16 SDRTimingMode; /**< SDR Timing mode support */ + u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */ + u16 TProg; /**< Maximum page program time */ + u16 TBers; /**< Maximum block erase time */ + u16 TR; /**< Maximum page read time */ + u16 TCcs; /**< Maximum change column setup + time */ + u8 NVDDRTimingMode; /**< NVDDR timing mode support */ + u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */ + u8 SynFeatures; /**< NVDDR/NVDDR2 features */ + u16 ClkInputPinCap; /**< CLK input pin capacitance */ + u16 IOPinCap; /**< I/O pin capacitance */ + u16 InputPinCap; /**< Input pin capacitance typical */ + u8 InputPinCapMax; /**< Input pin capacitance maximum */ + u8 DrvStrength; /**< Driver strength support */ + u16 TMr; /**< Maximum multi-plane read time */ + u16 TAdl; /**< Program page register clear + enhancement value */ + u16 TEr; /**< Typical page read time for + EZ NAND */ + u8 NVDDR2Features; /**< NVDDR2 Features */ + u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */ + u8 Reserved4[4]; /**< Reserved (160 - 163) */ + /* Vendor block */ + u16 VendorRevisionNum; /**< Vendor specific revision number */ + u8 VendorSpecific[88]; /**< Vendor specific */ + u16 Crc; /**< Integrity CRC */ +#ifdef __ICCARM__ +} OnfiParamPage; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiParamPage; +#endif + +/* ONFI extended parameter page structure. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u16 Crc; + u8 Sig[4]; + u8 Reserved1[10]; + u8 Section0Type; + u8 Section0Len; + u8 Section1Type; + u8 Section1Len; + u8 ResSection[12]; + u8 SectionData[256]; +#ifdef __ICCARM__ +} OnfiExtPrmPage; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiExtPrmPage; +#endif + +/* Driver extended parameter page information. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u8 NumEccBits; + u8 CodeWordSize; + u16 MaxBadBlocks; + u16 BlockEndurance; + u16 Reserved; +#ifdef __ICCARM__ +} OnfiExtEccBlock; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiExtEccBlock; +#endif + +typedef struct { + u8 Command1; /**< Command Cycle 1 */ + u8 Command2; /**< Command Cycle 2 */ +} OnfiCmdFormat; + +extern const OnfiCmdFormat OnfiCmd[MAX_CMDS]; + +/************************** Function Prototypes ******************************/ + +u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length); + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_ONFI_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/serial/arm-pl011-regs.h b/bsps/include/dev/serial/arm-pl011-regs.h index afe80a6262..d6ea9ae11a 100644 --- a/bsps/include/dev/serial/arm-pl011-regs.h +++ b/bsps/include/dev/serial/arm-pl011-regs.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,17 +9,28 @@ */ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H diff --git a/bsps/include/dev/serial/arm-pl011.h b/bsps/include/dev/serial/arm-pl011.h index c7e65656a3..a22fa1ac06 100644 --- a/bsps/include/dev/serial/arm-pl011.h +++ b/bsps/include/dev/serial/arm-pl011.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,17 +9,28 @@ */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_PL011_H diff --git a/bsps/include/dev/serial/zynq-uart-regs.h b/bsps/include/dev/serial/zynq-uart-regs.h index 8b6e7d513b..5e872d16c3 100644 --- a/bsps/include/dev/serial/zynq-uart-regs.h +++ b/bsps/include/dev/serial/zynq-uart-regs.h @@ -7,7 +7,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2013 embedded brains GmbH + * Copyright (C) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,6 +43,8 @@ #include <bsp/utility.h> +#define ZYNQ_UART_DEFAULT_BAUD 115200 + #define ZYNQ_UART_FIFO_DEPTH 64 typedef struct zynq_uart { @@ -158,6 +160,24 @@ typedef struct zynq_uart { #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) } zynq_uart; +void zynq_uart_initialize(volatile zynq_uart *regs); + +int zynq_uart_read_char_polled(volatile zynq_uart *regs); + +void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c); + +/** + * Flush TX FIFO and wait until it is empty. Used in bsp_reset. + */ +void zynq_uart_reset_tx_flush(volatile zynq_uart *regs); + +int zynq_cal_baud_rate( + uint32_t baudrate, + uint32_t* brgr, + uint32_t* bauddiv, + uint32_t modereg +); + /** @} */ #endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ diff --git a/bsps/include/dev/serial/zynq-uart-zynq.h b/bsps/include/dev/serial/zynq-uart-zynq.h new file mode 100644 index 0000000000..169037b33a --- /dev/null +++ b/bsps/include/dev/serial/zynq-uart-zynq.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup zynq_uart + * + * @brief This header file provides interfaces with respect to the Zynq + * platform. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQ_H +#define _DEV_SERIAL_ZYNQ_UART_ZYNQ_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup zynq_uart + * + * @{ + */ + +/** + * @brief This constant defines the Xilinx Zynq UART 0 base address. + */ +#define ZYNQ_UART_0_BASE_ADDR 0xe0000000 + +/** + * @brief This constant defines the Xilinx Zynq UART 1 base address. + */ +#define ZYNQ_UART_1_BASE_ADDR 0xe0001000 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQ_H */ diff --git a/bsps/include/dev/serial/zynq-uart-zynqmp.h b/bsps/include/dev/serial/zynq-uart-zynqmp.h new file mode 100644 index 0000000000..9f29003053 --- /dev/null +++ b/bsps/include/dev/serial/zynq-uart-zynqmp.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup zynq_uart + * + * @brief This header file provides interfaces with respect to the Zynq + * UltraScale+ MPSoC and RFSoC platforms. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H +#define _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup zynq_uart + * + * @{ + */ + +/** + * @brief This constant defines the Xilinx Zynq UART 0 base address. + */ +#define ZYNQ_UART_0_BASE_ADDR 0xff000000 + +/** + * @brief This constant defines the Xilinx Zynq UART 1 base address. + */ +#define ZYNQ_UART_1_BASE_ADDR 0xff010000 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H */ diff --git a/bsps/include/dev/serial/zynq-uart.h b/bsps/include/dev/serial/zynq-uart.h index b21e16f6de..002adcdbd6 100644 --- a/bsps/include/dev/serial/zynq-uart.h +++ b/bsps/include/dev/serial/zynq-uart.h @@ -7,7 +7,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2013, XXX embedded brains GmbH + * Copyright (C) 2013, XXX embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,7 +34,7 @@ #ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H #define LIBBSP_ARM_XILINX_ZYNQ_UART_H -#include <rtems/termiostypes.h> +#include <rtems/termiosdevice.h> #ifdef __cplusplus extern "C" { @@ -59,29 +59,6 @@ typedef struct { extern const rtems_termios_device_handler zynq_uart_handler; -#define ZYNQ_UART_DEFAULT_BAUD 115200 - -void zynq_uart_initialize(rtems_termios_device_context *base); - -int zynq_uart_read_polled(rtems_termios_device_context *base); - -void zynq_uart_write_polled( - rtems_termios_device_context *base, - char c -); - -/** - * Flush TX FIFO and wait until it is empty. Used in bsp_reset. - */ -void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); - -int zynq_cal_baud_rate( - uint32_t baudrate, - uint32_t* brgr, - uint32_t* bauddiv, - uint32_t modereg -); - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/dev/spi/xqspipsu-flash-helper.h b/bsps/include/dev/spi/xqspipsu-flash-helper.h new file mode 100644 index 0000000000..e689660881 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu-flash-helper.h @@ -0,0 +1,192 @@ +/****************************************************************************** +* Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include "xqspipsu.h" + +int QspiPsu_NOR_Initialize( + XQspiPsu *QspiPsuInstancePtr, + u16 QspiPsuIntrId +); + +/*****************************************************************************/ +/** + * + * This function erases the sectors in the serial Flash connected to the + * QSPIPSU interface. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the first sector which needs to + * be erased. + * @param ByteCount contains the total size to be erased. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Erase( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount +); + +/*****************************************************************************/ +/** + * + * This function writes to the serial Flash connected to the QSPIPSU interface. + * All the data put into the buffer must be in the same page of the device with + * page boundaries being on 256 byte boundaries. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address to write data to in the Flash. + * @param ByteCount contains the number of bytes to write. + * @param WriteBfrPtr is pointer to the write buffer (which is to be transmitted) + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Write_Page( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 *WriteBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function writes to the serial Flash connected to the QSPIPSU interface. + * Writes will be broken into device page sized and aligned writes as necessary. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address to write data to in the Flash. + * @param ByteCount contains the number of bytes to write. + * @param WriteBfrPtr is pointer to the write buffer (which is to be transmitted) + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Write( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 *WriteBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function performs a read. Default setting is in DMA mode. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the first sector which needs to + * be erased. + * @param ByteCount contains the total size to be erased. + * @param ReadBfrPtr is pointer to the read buffer to which valid received data + * should be written + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Read( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 **ReadBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function performs a read of the ECC Status Register for a given address. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the ECC unit for which the ECCSR + * needs to be read. The ECC unit contains 16 bytes of user data + * and all bytes in an ECC unit will return the same ECCSR. + * @param ReadBfrPtr is a pointer to a single byte to which the ECCSR will + * be written. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note Only the three least significant bits of the returned byte are + * meaningful. If all bits are 0, ECC is enabled for this unit and + * no errors have been encountered. + * Bit 0 is 1: ECC is disabled for the requested unit. + * Bit 1 is 1: A single bit error has been corrected in user data. + * Bit 2 is 1: A single bit error has been found in the ECC data + * and may indicate user data corruption. + * + ******************************************************************************/ +int QspiPsu_NOR_Read_Ecc( + XQspiPsu *QspiPsuPtr, + u32 Address, + u8 *ReadBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function returns the size of attached flash parts. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * + * @return The size of attached flash in bytes. + * + ******************************************************************************/ +u32 QspiPsu_NOR_Get_Device_Size(XQspiPsu *QspiPsuPtr); + +/*****************************************************************************/ +/** + * + * This function returns the sector size of attached flash parts. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * + * @return The sector size of attached flash in bytes. + * + ******************************************************************************/ +u32 QspiPsu_NOR_Get_Sector_Size(XQspiPsu *QspiPsuPtr); + +/*****************************************************************************/ +/** + * + * This function performs a read of the RDID configuration space. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param ReadBfrPtr is a pointer to a buffer to be filled with + * configuration data. + * @param ReadLen is the total length of the configuration space to read. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + ******************************************************************************/ +int QspiPsu_NOR_RDID(XQspiPsu *QspiPsuPtr, u8 *ReadBfrPtr, u32 ReadLen); + +/*****************************************************************************/ +/** + * + * This function performs a read of the SFDP configuration space. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param ReadBfrPtr is a pointer to a buffer to be filled with + * configuration data. + * @param ReadLen is the total length of the configuration space to read. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + ******************************************************************************/ +int QspiPsu_NOR_RDSFDP( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 **ReadBfrPtr +); diff --git a/bsps/include/dev/spi/xqspipsu.h b/bsps/include/dev/spi/xqspipsu.h new file mode 100644 index 0000000000..92d38eb0c8 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu.h @@ -0,0 +1,570 @@ +/****************************************************************************** +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** + * + * @file xqspipsu.h + * @addtogroup Overview + * @{ + * @details + * + * This section explains the implementation the functions required to use the + * QSPIPSU hardware to perform a transfer. These are accessible to the user + * via xqspipsu.h. + * + * Generic QSPI interface allows for communication to any QSPI slave device. + * GQSPI contains a GENFIFO into which the bus transfers required are to be + * pushed with appropriate configuration. The controller provides TX and RX + * FIFO's and a DMA to be used for RX transfers. The controller executes each + * GENFIFO entry noting the configuration and places data on the bus as required + * + * The different options in GENFIFO are as follows: + * - IMM_DATA : Can be one byte of data to be transmitted, number of clocks or + * number of bytes in transfer. + * - DATA_XFER : Indicates that data/clocks need to be transmitted or received. + * - EXPONENT : e when 2^e bytes are involved in transfer. + * - SPI_MODE : SPI/Dual SPI/Quad SPI + * - CS : Lower or Upper CS or Both + * - Bus : Lower or Upper Bus or Both + * - TX : When selected, controller transmits data in IMM or fetches number of + * bytes mentioned form TX FIFO. If not selected, dummies are pumped. + * - RX : When selected, controller receives and fills the RX FIFO/allows RX DMA + * of requested number of bytes. If not selected, RX data is discarded. + * - Stripe : Byte stripe over lower and upper bus or not. + * - Poll : Polls response to match for to a set value (used along with POLL_CFG + * registers) and then proceeds to next GENFIFO entry. + * This feature is not currently used in the driver. + * + * GENFIFO has manual and auto start options. + * All DMA requests need a 4-byte aligned destination address buffer and + * size of transfer should also be a multiple of 4. + * This driver supports DMA RX and IO RX. + * + * <b>Initialization & Configuration</b> + * + * This driver uses the GQSPI controller with RX DMA. It supports both + * interrupt and polled transfers. Manual start of GENFIFO is used. + * XQspiPsu_CfgInitialize() initializes the instance variables. + * Additional setting can be done using SetOptions/ClearOptions functions + * and SelectSlave function. + * + * <b>Transfer</b> + * + * Polled or Interrupt transfers can be done. The transfer function needs the + * message(s) to be transmitted in the form of an array of type XQspiPsu_Msg. + * This is supposed to contain the byte count and any TX/RX buffers as required. + * Flags can be used indicate further information such as whether the message + * should be striped. The transfer functions form and write GENFIFO entries, + * check the status of the transfer and report back to the application + * when done. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- --- -------- -----------------------------------------------. + * 1.0 hk 08/21/14 First release + * sk 03/13/15 Added IO mode support. + * hk 03/18/15 Switch to I/O mode before clearing RX FIFO. + * Clear and disable DMA interrupts/status in abort. + * Use DMA DONE bit instead of BUSY as recommended. + * sk 04/24/15 Modified the code according to MISRAC-2012. + * sk 06/17/15 Removed NULL checks for Rx/Tx buffers. As + * writing/reading from 0x0 location is permitted. + * 1.1 sk 04/12/16 Added debug message prints. + * 1.2 nsk 07/01/16 Added LQSPI support + * Modified XQspiPsu_Select() macro in xqspipsu.h + * Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h + * Added required macros in xqspipsu_hw.h + * Modified XQspiPsu_SetOptions() to support + * LQSPI options and updated OptionsTable in + * xqspipsu_options.c + * rk 07/15/16 Added support for TapDelays at different frequencies. + * nsk 08/05/16 Added example support PollData and PollTimeout + * Added XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h + * Added XQspiPsu_Create_PollConfigData and + * XQspiPsu_PollData() functions in xqspipsu.c + * 1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel + * configuration. Updated XQspiPsu_PollData() and + * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c + * and also modified the polldata example + * ms 03/17/17 Added readme.txt file in examples folder for doxygen + * generation. + * ms 04/05/17 Modified Comment lines in functions of qspipsu + * examples to recognize it as documentation block + * and modified filename tag to include them in + * doxygen examples. + * 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000) + * while booting images from QSPI + * 1.5 tjs 08/08/17 Added index.html file for importing examples + * from system.mss + * 1.5 nsk 08/14/17 Added CCI support + * 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands. + * 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot + * and linux For CR-984966 + * 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625 + * 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase + * commands. + * 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642 + * 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724 + * 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367 + * 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) + * 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) + * Added XQspiPsu_SetWP() in xqspipsu_options.c + * Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and + * also added write protect example. + * 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) + * 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write + * enable command. CR-998478 + * 1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064. + * 1.8 tjs 06/26/18 Added an example for accessing 64bit dma within + * 32 bit application. CR#1004701 + * 1.8 tjs 06/26/18 Removed checkpatch warnings + * 1.8 tjs 07/09/19 Fixed cppcheck, doxygen and gcc warnings. + * 1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is + * greater than 32 bit address space. (CR#1006862) + * 1.8 tjs 07/18/18 Added support for the low density ISSI flash parts. + * 1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data + * transfer length up to 255 for reducing the extra loop. + * 1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075) + * 1.9 tjs 04/17/18 Updated register addresses as per the latest revision + * of versal (CR#999610) + * 1.9 aru 01/17/19 Fixed the violations for MISRAC-2012 + * in safety mode .Done changes such as added U suffix, + * Declared pointer param as const. + * 1.9 nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the + * address is of only 32bit (CR#1020031) + * 1.9 nsk 02/01/19 Added QSPI idling support + * + * 1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ, + * 100MHZ and 150MHZ frequencies(CR#1023187) + * 1.9 nsk 03/27/19 Update 64bit dma support + * (CR#1018102). + * 1.9 akm 04/03/19 Fixed data alignment warnings on IAR compiler. + * 1.9 akm 04/03/19 Fixed compilation error in XQspiPsu_LqspiRead() + * function on IAR compiler. + * 1.10 sk 08/20/19 Fixed issues in poll timeout feature. + * 1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and + * 150MHZ frequencies in Versal. + * 1.10 akm 09/05/19 Added Multi Die Erase and Muti Die Read support. + * 1.11 akm 11/07/19 Removed LQSPI register access in Versal. + * 1.11 akm 11/15/19 Fixed Coverity deadcode warning in + * XQspipsu_Calculate_Tapdelay(). + * 1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone() + * APIs for non-blocking transfer. + * 1.11 sd 01/02/20 Added clocking support + * 1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and + * interrupts in XQspiPsu_CfgInitialize() API. + * 1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return + * XST_DEVICE_IS_STARTED instead of asserting, when the + * instance is already configured(CR#1058525). + * 1.12 akm 09/02/20 Updated the Makefile to support parallel make execution. + * 1.13 akm 01/04/21 Fix MISRA-C violations. + * 1.13 sne 04/23/21 Fixed doxygen warnings. + * 1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs. + * 1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer. + * + * </pre> + * + ******************************************************************************/ + +#ifndef XQSPIPSU_H_ /**< prevent circular inclusions */ +#define XQSPIPSU_H_ /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspipsu_hw.h" +#include "xil_cache.h" +#include "xil_mem.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPIPSU device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPsu_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent, + u32 ByteCount); + +/** + * This typedef contains configuration information for a flash message. + */ +typedef struct { + u8 *TxBfrPtr; /**< Tx Buffer pointer */ + u8 *RxBfrPtr; /**< Rx Buffer pointer */ + u32 ByteCount; /**< Byte Count */ + u32 BusWidth; /**< Bus Width */ + u32 Flags; /**< Flags */ + u8 PollData; /**< Poll Data */ + u32 PollTimeout;/**< Poll Timeout */ + u8 PollStatusCmd; /**< Poll Status command */ + u8 PollBusMask; /**< Poll Bus mask */ + u64 RxAddr64bit; /**< 64 bit Rx address */ + u8 Xfer64bit; /**< 64 bit Tx address */ +} XQspiPsu_Msg; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ + u8 BusWidth; /**< Bus width available on board */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +#if defined (XCLOCKING) + u32 RefClk; /**< Input clocks */ +#endif +} XQspiPsu_Config; + +/** + * The XQspiPsu driver instance data. The user is required to allocate a + * variable of this type for every QSPIPSU device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPsu_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + u64 RecvBuffer; /**< Buffer Address to receive (state) */ + u8 *GenFifoBufferPtr; /**< Gen FIFO entries */ + s32 TxBytes; /**< Number of bytes to transfer (state) */ + s32 RxBytes; /**< Number of bytes left to transfer(state) */ + s32 GenFifoEntries; /**< Number of Gen FIFO entries remaining */ +#ifdef __rtems__ + volatile +#endif + u32 IsBusy; /**< A transfer is in progress (state) */ + u32 ReadMode; /**< DMA or IO mode */ + u32 GenFifoCS; /**< Gen FIFO chip selection */ + u32 GenFifoBus; /**< Gen FIFO bus */ + s32 NumMsg; /**< Number of messages */ + s32 MsgCnt; /**< Message Count */ + s32 IsUnaligned; /**< Unaligned information */ + u8 IsManualstart; /**< Manual start information */ + XQspiPsu_Msg *Msg; /**< Message */ + XQspiPsu_StatusHandler StatusHandler; /**< Status Handler */ + void *StatusRef; /**< Callback reference for status handler */ +} XQspiPsu; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/** + * Definitions for Intel, STM, Winbond and Spansion Serial Flash Device + * geometry. + */ +#define BYTES256_PER_PAGE 256U /**< 256 Bytes per Page */ +#define BYTES512_PER_PAGE 512U /**< 512 Bytes per Page */ +#define BYTES1024_PER_PAGE 1024U /**< 1024 Bytes per Page */ +#define PAGES16_PER_SECTOR 16U /**< 16 Pages per Sector */ +#define PAGES128_PER_SECTOR 128U /**< 128 Pages per Sector */ +#define PAGES256_PER_SECTOR 256U /**< 256 Pages per Sector */ +#define PAGES512_PER_SECTOR 512U /**< 512 Pages per Sector */ +#define PAGES1024_PER_SECTOR 1024U /**< 1024 Pages per Sector */ +#define NUM_OF_SECTORS2 2U /**< 2 Sectors */ +#define NUM_OF_SECTORS4 4U /**< 4 Sectors */ +#define NUM_OF_SECTORS8 8U /**< 8 Sector */ +#define NUM_OF_SECTORS16 16U /**< 16 Sectors */ +#define NUM_OF_SECTORS32 32U /**< 32 Sectors */ +#define NUM_OF_SECTORS64 64U /**< 64 Sectors */ +#define NUM_OF_SECTORS128 128U /**< 128 Sectors */ +#define NUM_OF_SECTORS256 256U /**< 256 Sectors */ +#define NUM_OF_SECTORS512 512U /**< 512 Sectors */ +#define NUM_OF_SECTORS1024 1024U /**< 1024 Sectors */ +#define NUM_OF_SECTORS2048 2048U /**< 2048 Sectors */ +#define NUM_OF_SECTORS4096 4096U /**< 4096 Sectors */ +#define NUM_OF_SECTORS8192 8192U /**< 8192 Sectors */ +#define SECTOR_SIZE_64K 0X10000U /**< 64K Sector */ +#define SECTOR_SIZE_128K 0X20000U /**< 128K Sector */ +#define SECTOR_SIZE_256K 0X40000U /**< 256K Sector */ +#define SECTOR_SIZE_512K 0X80000U /**< 512K Sector */ + + +#define XQSPIPSU_READMODE_DMA 0x0U /**< DMA read mode */ +#define XQSPIPSU_READMODE_IO 0x1U /**< IO read mode */ + +#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U /**< Select lower flash */ +#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U /**< Select upper flash */ +#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U /**< Select both flash */ + +#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U /**< Select lower bus flash */ +#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U /**< Select upper bus flash */ +#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U /**< Select both bus flash */ + +#define XQSPIPSU_SELECT_MODE_SPI 0x1U /**< Select SPI mode */ +#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U /**< Select dual SPI mode */ +#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U /**< Select quad SPI mode */ + +#define XQSPIPSU_GENFIFO_CS_SETUP 0x05U /**< Chip select setup in GENFIO */ +#define XQSPIPSU_GENFIFO_CS_HOLD 0x04U /**< Chip select hold in GENFIFO */ + +#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U /**< Clk Active low option */ +#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U /**< Clk phase 1 option */ +#define XQSPIPSU_MANUAL_START_OPTION 0x8U /**< Manual start option */ +#if !defined (versal) +#define XQSPIPSU_LQSPI_MODE_OPTION 0x20U /**< LQSPI mode option */ + +#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U /**< LQSPI less Than 16 MB */ +#endif + +#define XQSPIPSU_GENFIFO_EXP_START 0x100U /**< Genfifo start */ + +#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U /**< DMA bytes max */ + +#define XQSPIPSU_CLK_PRESCALE_2 0x00U /**< Clock prescale 2 */ +#define XQSPIPSU_CLK_PRESCALE_4 0x01U /**< Clock prescale 4 */ +#define XQSPIPSU_CLK_PRESCALE_8 0x02U /**< Clock prescale 8 */ +#define XQSPIPSU_CLK_PRESCALE_16 0x03U /**< Clock prescale 16 */ +#define XQSPIPSU_CLK_PRESCALE_32 0x04U /**< Clock prescale 32 */ +#define XQSPIPSU_CLK_PRESCALE_64 0x05U /**< Clock prescale 64 */ +#define XQSPIPSU_CLK_PRESCALE_128 0x06U /**< Clock prescale 128 */ +#define XQSPIPSU_CLK_PRESCALE_256 0x07U /**< Clock prescale 256 */ +#define XQSPIPSU_CR_PRESC_MAXIMUM 7U /**< Prescale max */ + +#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U /**< Single mode connection */ +#define XQSPIPSU_CONNECTION_MODE_STACKED 1U /**< Stacked mode connection */ +#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U /**< Parallel mode connection */ + +/*QSPI Frequencies*/ +#define XQSPIPSU_FREQ_37_5MHZ 37500000U /**< Frequency 375 Mhz */ +#define XQSPIPSU_FREQ_40MHZ 40000000U /**< Frequency 40 Mhz */ +#define XQSPIPSU_FREQ_100MHZ 100000000U /**< Frequency 100 Mhz */ +#define XQSPIPSU_FREQ_150MHZ 150000000U /**< Frequency 150 Mhz */ + +/* Add more flags as required */ +#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U /**< Stripe Msg flag */ +#define XQSPIPSU_MSG_FLAG_RX 0x2U /**< Rx Msg flag */ +#define XQSPIPSU_MSG_FLAG_TX 0x4U /**< Tx Msg flag */ +#define XQSPIPSU_MSG_FLAG_POLL 0x8U /**< POLL Msg flag */ + +#define XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U /**< Rx address over 32 bit */ + +#define XQSPIPSU_SET_WP 1 /**< GQSPI configuration to toggle WP of flash */ + +/** + * select QSPI controller + */ +#define XQspiPsu_Select(InstancePtr, Mask) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_SEL_OFFSET, (Mask)) + +/** + * Enable QSPI Controller + */ +#define XQspiPsu_Enable(InstancePtr) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) + +/** + * Disable QSPI controller */ +#define XQspiPsu_Disable(InstancePtr) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_EN_OFFSET, 0x0U) + +/** + * Read Configuration register of LQSPI Controller + */ +#if !defined (versal) +#define XQspiPsu_GetLqspiConfigReg(InstancePtr) \ + XQspiPsu_In32((XQSPIPS_BASEADDR) + \ + XQSPIPSU_LQSPI_CR_OFFSET) +#endif + +/*****************************************************************************/ +/** + * + * This function enables the manual start option + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_ManualStartEnable(XQspiPsu *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_ManualStartEnable\r\n"); +#endif + + if (InstancePtr->IsManualstart == (u8)TRUE) { +#ifdef DEBUG + xil_printf("\nManual Start\r\n"); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET, + XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) | + XQSPIPSU_CFG_START_GEN_FIFO_MASK); + } +} +/*****************************************************************************/ +/** + * + * This function writes the GENFIFO entry to assert CS. + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_GenFifoEntryCSAssert(const XQspiPsu *InstancePtr) +{ + u32 GenFifoEntry; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n"); +#endif + + GenFifoEntry = 0x0U; + GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoCS | + InstancePtr->GenFifoBus | XQSPIPSU_GENFIFO_CS_SETUP); +#ifdef DEBUG + xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); +} + +/*****************************************************************************/ +/** + * + * This function writes the GENFIFO entry to de-assert CS. + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_GenFifoEntryCSDeAssert(const XQspiPsu *InstancePtr) +{ + u32 GenFifoEntry; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n"); +#endif + + GenFifoEntry = 0x0U; + GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoBus | + XQSPIPSU_GENFIFO_CS_HOLD); +#ifdef DEBUG + xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); +} + +/*****************************************************************************/ +/** + * + * This is a stub for the status callback. The stub is here in case the upper + * layers forget to set the handler. + * + * @param CallBackRef is a pointer to the upper layer callback reference + * @param StatusEvent is the event that just occurred. + * @param ByteCount is the number of bytes transferred up until the event + * occurred. + * + * @return None. + * + * @note None. + * + ******************************************************************************/ +static inline void StubStatusHandler(const void *CallBackRef, u32 StatusEvent, + u32 ByteCount) +{ + (const void) CallBackRef; + (void) StatusEvent; + (void) ByteCount; + + Xil_AssertVoidAlways(); +} +/************************** Function Prototypes ******************************/ + +/* Initialization and reset */ +XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId); +s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, + const XQspiPsu_Config *ConfigPtr, + UINTPTR EffectiveAddr); +void XQspiPsu_Reset(XQspiPsu *InstancePtr); +void XQspiPsu_Abort(XQspiPsu *InstancePtr); + +/* Transfer functions and handlers */ +s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr); +void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef, + XQspiPsu_StatusHandler FuncPointer); + +/* Non blocking Transfer functions */ +s32 XQspiPsu_StartDmaTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_CheckDmaDone(XQspiPsu *InstancePtr); + +/* Configuration functions */ +s32 XQspiPsu_SetClkPrescaler(const XQspiPsu *InstancePtr, u8 Prescaler); +void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus); +s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options); +s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); +u32 XQspiPsu_GetOptions(const XQspiPsu *InstancePtr); +s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); +void XQspiPsu_SetWP(const XQspiPsu *InstancePtr, u8 Value); +void XQspiPsu_WriteProtectToggle(const XQspiPsu *InstancePtr, u32 Toggle); +void XQspiPsu_Idle(const XQspiPsu *InstancePtr); + +/************************** Variable Prototypes ******************************/ + +/** + * This table contains configuration information for each QSPIPSU device + * in the system. + */ +#ifndef __rtems__ +extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]; +#endif /* __rtems__ */ + +#ifdef __cplusplus +} +#endif + + +#endif /* XQSPIPSU_H_ */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_control.h b/bsps/include/dev/spi/xqspipsu_control.h new file mode 100644 index 0000000000..76b0a8ce7c --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_control.h @@ -0,0 +1,102 @@ +/****************************************************************************** +* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** + * + * @file xqspipsu_control.h + * @addtogroup Overview + * @{ + * + * This is the header file for the implementation of QSPIPSU driver. + * Generic QSPI interface allows for communication to any QSPI slave device. + * GQSPI contains a GENFIFO into which the bus transfers required are to be + * pushed with appropriate configuration. The controller provides TX and RX + * FIFO's and a DMA to be used for RX transfers. The controller executes each + * GENFIFO entry noting the configuration and places data on the bus as required + * + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- --- -------- -----------------------------------------------. + * 1.11 akm 03/09/20 First release + * 1.13 akm 01/04/21 Fix MISRA-C violations. + * 1.15 akm 03/03/22 Enable tapdelay settings for applications on + * Microblaze platform. + * + * </pre> + * + ******************************************************************************/ + +/** @cond INTERNAL */ +#ifndef XQSPIPSU_CONTROL_H_ /**< prevent circular inclusions */ +#define XQSPIPSU_CONTROL_H_ /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xqspipsu.h" + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__) +#define TAPDLY_BYPASS_VALVE_40MHZ 0x01U +#define TAPDLY_BYPASS_VALVE_100MHZ 0x01U +#define USE_DLY_LPBK 0x01U +#define USE_DATA_DLY_ADJ 0x01U +#define DATA_DLY_ADJ_DLY 0X02U +#define LPBK_DLY_ADJ_DLY0 0X02U +#define LPBK_DLY_ADJ_DLY1 0X02U +#endif + +#ifdef __MICROBLAZE__ +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */ +#endif +/************************** Function Prototypes ******************************/ +void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 StatusReg); +void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg); +void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr, + XQspiPsu_Msg *Msg); +void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr, + XQspiPsu_Msg *Msg); +void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 *GenFifoEntry); +void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 *GenFifoEntry); +u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr, + const XQspiPsu_Msg *FlashMsg); +void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg); +u32 XQspiPsu_SelectSpiMode(u8 SpiMode); +void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr); +void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size); +void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size); + +#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__) +s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass, + u32 LPBKDelay, u32 Datadelay); +s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler); +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* XQSPIPSU_CONTROL_H_ */ +/** @endcond */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_flash_config.h b/bsps/include/dev/spi/xqspipsu_flash_config.h new file mode 100644 index 0000000000..0b04fffc28 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_flash_config.h @@ -0,0 +1,357 @@ +/****************************************************************************** +* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspipsu_flash_config.h +* +* +* This file contains flash configuration table and flash related defines. +* This file should be included in the example files and compiled along with +* the examples (*.c). +* +* @note +* +* None. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.12 akm 07/07/20 First release +* 1.12 akm 07/07/20 Add support for Macronix flash(MX66U2G45G, MX66L2G45G) +* and ISSI flash(IS25LP01G, IS25WP01G) parts. +* 1.13 akm 12/10/20 Set Read command as per the qspi bus width. +* 1.14 akm 07/16/21 Enable Quad Mode for Winbond flashes. +* 1.15 akm 11/19/21 Fix read/write failures on Spansion flash parts. +* +*</pre> +* + ******************************************************************************/ + +#ifndef XQSPIPSU_FLASH_CONFIG_H_ /* prevent circular inclusions */ +#define XQSPIPSU_FLASH_CONFIG_H_ /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" /* SDK generated parameters */ +#include "xqspipsu.h" /* QSPIPSU device driver */ + +/************************** Constant Definitions *****************************/ + +/* + * The following constants define the commands which may be sent to the Flash + * device. + */ +#define WRITE_STATUS_CMD 0x01 +#define WRITE_CMD 0x02 +#define READ_CMD 0x03 +#define WRITE_DISABLE_CMD 0x04 +#define READ_STATUS_CMD 0x05 +#define WRITE_ENABLE_CMD 0x06 +#define VOLATILE_WRITE_ENABLE_CMD 0x50 +#define QUAD_MODE_ENABLE_BIT 0x06 +#define FAST_READ_CMD 0x0B +#define DUAL_READ_CMD 0x3B +#define QUAD_READ_CMD 0x6B +#define BULK_ERASE_CMD 0xC7 +#define SEC_ERASE_CMD 0xD8 +#define READ_ID 0x9F +#define READ_SFDP 0x5A +#define READ_CONFIG_CMD 0x35 +#define WRITE_CONFIG_CMD 0x01 +#define ENTER_4B_ADDR_MODE 0xB7 +#define EXIT_4B_ADDR_MODE 0xE9 +#define EXIT_4B_ADDR_MODE_ISSI 0x29 +/* 4-byte address opcodes */ +#define READ_CMD_4B 0x13 +#define FAST_READ_CMD_4B 0x0C +#define DUAL_READ_CMD_4B 0x3C +#define QUAD_READ_CMD_4B 0x6C +#define WRITE_CMD_4B 0x12 +#define SEC_ERASE_CMD_4B 0xDC + +#define BANK_REG_RD 0x16 +#define BANK_REG_WR 0x17 +#define READ_ECCSR 0x18 +/* Bank register is called Extended Address Register in Micron */ +#define EXTADD_REG_RD 0xC8 +#define EXTADD_REG_WR 0xC5 +#define DIE_ERASE_CMD 0xC4 +#define READ_FLAG_STATUS_CMD 0x70 + +#define WRITE_STATUS_REG_2_CMD 0x31 +#define READ_STATUS_REG_2_CMD 0x35 +#define WB_QUAD_MODE_ENABLE_BIT 0x01 + +/* + * The following constants define the offsets within a FlashBuffer data + * type for each kind of data. Note that the read data offset is not the + * same as the write data because the QSPIPSU driver is designed to allow full + * duplex transfers such that the number of bytes received is the number + * sent and received. + */ +#define COMMAND_OFFSET 0 /* Flash instruction */ +#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */ +#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */ +#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */ +#define ADDRESS_4_OFFSET 4 /* LSB byte of address to read or write + * when 4 byte address + */ +#define DATA_OFFSET 5 /* Start of Data for Read/Write */ +#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad + * reads + */ +#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and + * quad reads + */ +#define DUMMY_CLOCKS 8 /* Number of dummy bytes for fast, dual and + * quad reads + */ +#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */ +#define BULK_ERASE_SIZE 1 /* Bulk Erase command size */ +#define SEC_ERASE_SIZE 4 /* Sector Erase command + Sector address */ +#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank + * value + */ +#define RD_CFG_SIZE 2 /* 1 byte Configuration register + RD CFG + * command + */ +#define WR_CFG_SIZE 3 /* WRR command + 1 byte each Status and + * Config Reg + */ +#define DIE_ERASE_SIZE 4 /* Die Erase command + Die address */ + +/* + * The following constants specify the extra bytes which are sent to the + * Flash on the QSPIPSu interface, that are not data, but control information + * which includes the command and address + */ +#define OVERHEAD_SIZE 4 + +/* + * Base address of Flash1 + */ +#define FLASH1BASE 0x0000000 + +/* + * Sixteen MB + */ +#define SIXTEENMB 0x1000000 + + +/* + * Mask for quad enable bit in Flash configuration register + */ +#define FLASH_QUAD_EN_MASK 0x02 + +#define FLASH_SRWD_MASK 0x80 + +/* + * Bank mask + */ +#define BANKMASK 0xF000000 + +/* + * Bus width + */ +#define BUSWIDTH_SINGLE 0 +#define BUSWIDTH_DOUBLE 1 + +/* + * Identification of Flash + * Micron: + * Byte 0 is Manufacturer ID; + * Byte 1 is first byte of Device ID - 0xBB or 0xBA + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + * Spansion: + * Byte 0 is Manufacturer ID; + * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02 + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + */ +#define MICRON_ID_BYTE0 0x20 +#define SPANSION_ID_BYTE0 0x01 +#define WINBOND_ID_BYTE0 0xEF +#define MACRONIX_ID_BYTE0 0xC2 +#define ISSI_ID_BYTE0 0x9D + +/**************************** Type Definitions *******************************/ + +typedef struct{ + u32 jedec_id; /* JEDEC ID */ + + u32 SectSize; /* Individual sector size or combined sector + * size in case of parallel config + */ + u32 NumSect; /* Total no. of sectors in one/two + * flash devices + */ + u32 PageSize; /* Individual page size or + * combined page size in case of parallel + * config + */ + u32 NumPage; /* Total no. of pages in one/two flash + * devices + */ + u32 FlashDeviceSize; /* This is the size of one flash device + * NOT the combination of both devices, + * if present + */ + u32 SectMask; /* Mask to get sector start address */ + u8 NumDie; /* No. of die forming a single flash */ +} FlashInfo; + +/************************** Variable Definitions *****************************/ +FlashInfo Flash_Config_Table[] = { + /* Spansion */ + /*s25fl064l*/ + {0x016017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*s25fl128l*/ + {0x016018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*s25fl256l*/ + {0x016019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*s25fl512s*/ + {0x010220, SECTOR_SIZE_256K, NUM_OF_SECTORS256, BYTES512_PER_PAGE, + 0x20000, 0x4000000, 0xFFFC0000, 1}, + /* Spansion 1Gbit is handled as 512Mbit stacked */ + /* Micron */ + /*n25q128a11*/ + {0x20bb18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*n25q128a13*/ + {0x20ba18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*n25q256ax1*/ + {0x20bb19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*n25q256a*/ + {0x20ba19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*mt25qu512a*/ + {0x20bb20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*n25q512ax3*/ + {0x20ba20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*n25q00a*/ + {0x20bb21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*n25q00*/ + {0x20ba21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mt25qu02g*/ + {0x20bb22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /*mt25ql02g*/ + {0x20ba22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /* Winbond */ + /*w25q128fw*/ + {0xef6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*w25q128jv*/ + {0xef7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*w25h02jv*/ + {0xef9022, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /* Macronix */ + /*mx66l1g45g*/ + {0xc2201b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66l1g55g*/ + {0xc2261b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66u1g45g*/ + {0xc2253b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66l2g45g*/ + {0xc2201c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 1}, + /*mx66u2g45g*/ + {0xc2253c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 1}, + /* ISSI */ + /*is25wp080d*/ + {0x9d7014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE, + 0x1000, 0x100000, 0xFFFF0000, 1}, + /*is25lp080d*/ + {0x9d6014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE, + 0x1000, 0x100000, 0xFFFF0000, 1}, + /*is25wp016d*/ + {0x9d7015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE, + 0x2000, 0x200000, 0xFFFF0000, 1}, + /*is25lp016d*/ + {0x9d6015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE, + 0x2000, 0x200000, 0xFFFF0000, 1}, + /*is25wp032*/ + {0x9d7016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE, + 0x4000, 0x400000, 0xFFFF0000, 1}, + /*is25lp032*/ + {0x9d6016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE, + 0x4000, 0x400000, 0xFFFF0000, 1}, + /*is25wp064*/ + {0x9d7017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*is25lp064*/ + {0x9d6017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*is25wp128*/ + {0x9d7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*is25lp128*/ + {0x9d6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*is25lp256d*/ + {0x9d6019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*is25wp256d*/ + {0x9d7019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*is25lp512m*/ + {0x9d601a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*is25wp512m*/ + {0x9d701a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*is25lp01g*/ + {0x9d601b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 1}, + /*is25wp01g*/ + {0x9d701b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 1} +}; + +static INLINE u32 CalculateFCTIndex(u32 ReadId, u32 *FCTIndex) +{ + u32 Index; + + for (Index = 0; Index < sizeof(Flash_Config_Table)/sizeof(Flash_Config_Table[0]); + Index++) { + if (ReadId == Flash_Config_Table[Index].jedec_id) { + *FCTIndex = Index; + return XST_SUCCESS; + } + } + + return XST_FAILURE; +} + +#ifdef __cplusplus +} +#endif + +#endif /* XQSPIPSU_FLASH_CONFIG_H_ */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_hw.h b/bsps/include/dev/spi/xqspipsu_hw.h new file mode 100644 index 0000000000..a798f9bb89 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_hw.h @@ -0,0 +1,1006 @@ +/****************************************************************************** +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xqspipsu_hw.h +* @addtogroup Overview +* @{ +* +* This file contains low level access functions using the base address +* directly without an instance. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- -----------------------------------------------. +* 1.0 hk 08/21/14 First release +* hk 03/18/15 Add DMA status register masks required. +* sk 04/24/15 Modified the code according to MISRAC-2012. +* 1.2 nsk 07/01/16 Added LQSPI supported Masks +* rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. +* 1.9 tjs 04/17/18 Updated register addresses as per the latest revision +* of versal (CR#999610) +* 1.9 aru 01/17/19 Fixed the violations for MISRAC-2012 +* in safety mode .Done changes such as added U suffix +* 1.11 akm 11/07/19 Removed LQSPI register access in Versal. +* 1.15 akm 12/02/21 Fix Doxygen warnings. +* +* </pre> +* +******************************************************************************/ +#ifndef XQSPIPSU_HW_H /**< prevent circular inclusions */ +#define XQSPIPSU_HW_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ +/** + * @name Device Base Address + * Below macros gives QSPI, QSPIPSU base address. + * @{ + */ +/** + * QSPI Base Address + */ +#if defined (versal) +#define XQSPIPS_BASEADDR 0XF1030000U +#else +#define XQSPIPS_BASEADDR 0XFF0F0000U +#endif + +#if defined (versal) +#define XQSPIPSU_BASEADDR 0XF1030100U +#else +#define XQSPIPSU_BASEADDR 0xFF0F0100U +#endif +#define XQSPIPSU_OFFSET 0x100U +/** @} */ + +/** + * @name XQSPIPS Enable Register information + * QSPIPSU Enable Register + * @{ + */ +/** + * Register: XQSPIPS_EN_REG + */ +#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U ) +#define XQSPIPS_EN_SHIFT 0U +#define XQSPIPS_EN_WIDTH 1U +#define XQSPIPS_EN_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU configuration Register information + * This register contains bits for configuring GQSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_CFG + */ +#define XQSPIPSU_CFG_OFFSET 0X00000000U + +#define XQSPIPSU_CFG_MODE_EN_SHIFT 30U +#define XQSPIPSU_CFG_MODE_EN_WIDTH 2U +#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U +#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U + +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U + +#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U +#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U +#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U + +#define XQSPIPSU_CFG_ENDIAN_SHIFT 26U +#define XQSPIPSU_CFG_ENDIAN_WIDTH 1U +#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U + +#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U +#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U +#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U + +#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19U +#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1U +#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U + +#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U +#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U +#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U + +#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2U +#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1U +#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U + +#define XQSPIPSU_CFG_CLK_POL_SHIFT 1U +#define XQSPIPSU_CFG_CLK_POL_WIDTH 1U +#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU LQSPI Register information + * This register contains bits for configuring LQSPI + * @{ + */ +/** + * Register: XQSPIPSU_LQSPI + */ +#if !defined (versal) +#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U +#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U /**< LQSPI mode enable */ +#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U /**< Both memories or one */ +#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U /**< Separate memory bus */ +#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U /**< Upper memory page */ +#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U /**< Upper memory page */ +#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U /**< Enable mode bits */ +#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U /**< Mode on */ +#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U /**< Default LQSPI CR value */ +#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U /**< Default 4 Byte LQSPI CR value */ +#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U /**< Default LQSPI CFG value */ +#endif +/** @} */ + +/** + * @name XQSPIPSU Interrupt Status Register information + * QSPIPSU Interrupt Status Register + * @{ + */ +/** + * Register: XQSPIPSU_ISR + */ +#define XQSPIPSU_ISR_OFFSET 0X00000004U + +#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_ISR_RXFULL_SHIFT 5U +#define XQSPIPSU_ISR_RXFULL_WIDTH 1U +#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_ISR_TXFULL_SHIFT 3U +#define XQSPIPSU_ISR_TXFULL_WIDTH 1U +#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U + +#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Interrupt Enable Register information + * This register bits for enabling interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IER + */ +#define XQSPIPSU_IER_OFFSET 0X00000008U + +#define XQSPIPSU_IER_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IER_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IER_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IER_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IER_RXFULL_SHIFT 5U +#define XQSPIPSU_IER_RXFULL_WIDTH 1U +#define XQSPIPSU_IER_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IER_TXFULL_SHIFT 3U +#define XQSPIPSU_IER_TXFULL_WIDTH 1U +#define XQSPIPSU_IER_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Interrupt Disable Register information + * This register bits for disabling interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IDR + */ +#define XQSPIPSU_IDR_OFFSET 0X0000000CU + +#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IDR_RXFULL_SHIFT 5U +#define XQSPIPSU_IDR_RXFULL_WIDTH 1U +#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IDR_TXFULL_SHIFT 3U +#define XQSPIPSU_IDR_TXFULL_WIDTH 1U +#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U + +#define XQSPIPSU_IDR_ALL_MASK 0X0FBEU +/** @} */ + +/** + * @name XQSPIPSU Interrupt Mask Register information + * This register bits for masking interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IMR + */ +#define XQSPIPSU_IMR_OFFSET 0X00000010U + +#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IMR_RXFULL_SHIFT 5U +#define XQSPIPSU_IMR_RXFULL_WIDTH 1U +#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IMR_TXFULL_SHIFT 3U +#define XQSPIPSU_IMR_TXFULL_WIDTH 1U +#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Enable Register information + * This register bits for enabling QSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_EN_REG + */ +#define XQSPIPSU_EN_OFFSET 0X00000014U + +#define XQSPIPSU_EN_SHIFT 0U +#define XQSPIPSU_EN_WIDTH 1U +#define XQSPIPSU_EN_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU TX Data Register information + * This register bits for configuring TXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_TXD + */ +#define XQSPIPSU_TXD_OFFSET 0X0000001CU + +#define XQSPIPSU_TXD_SHIFT 0U +#define XQSPIPSU_TXD_WIDTH 32U +#define XQSPIPSU_TXD_MASK 0XFFFFFFFFU + +#define XQSPIPSU_TXD_DEPTH 64 +/** @} */ + +/** + * @name XQSPIPSU RX Data Register information + * This register bits for configuring RXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_RXD + */ +#define XQSPIPSU_RXD_OFFSET 0X00000020U + +#define XQSPIPSU_RXD_SHIFT 0U +#define XQSPIPSU_RXD_WIDTH 32U +#define XQSPIPSU_RXD_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU TX/RX Threshold Register information + * This register bits for configuring TX/RX Threshold + * @{ + */ +/** + * Register: XQSPIPSU_TX_THRESHOLD + */ +#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U + +#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U +#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU +#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U + +#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU + +#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U +#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU +#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U + +#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U +/** @} */ + +/** + * @name XQSPIPSU GPIO Register information + * @{ + */ +/** + * Register: XQSPIPSU_GPIO + */ +#define XQSPIPSU_GPIO_OFFSET 0X00000030U + +#define XQSPIPSU_GPIO_WP_N_SHIFT 0U +#define XQSPIPSU_GPIO_WP_N_WIDTH 1U +#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU Loopback Master Clock Delay Adjustment Register information + * This register contains bits for configuring loopback + * @{ + */ +/** + * Register: XQSPIPSU_LPBK_DLY_ADJ + */ +#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U + +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U +/** @} */ + +/** + * @name XQSPIPSU GEN_FIFO Register information + * This register contains bits for configuring GENFIFO + * @{ + */ +/** + * Register: XQSPIPSU_GEN_FIFO + */ +#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U + +#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U +#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U +#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU +/** @} */ + +/** + * @name XQSPIPSU Select Register information + * This register contains bits for selection GQSPI/LQSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_SEL + */ +#define XQSPIPSU_SEL_OFFSET 0X00000044U + +#define XQSPIPSU_SEL_SHIFT 0U +#define XQSPIPSU_SEL_WIDTH 1U +#if !defined (versal) +#define XQSPIPSU_SEL_LQSPI_MASK 0X0U +#endif +#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU FIFO Control Register information + * This register contains bits for controlling TXFIFO and RXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_FIFO_CTRL + */ +#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU + +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U + +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U + +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU GENFIFO Threshold Register information + * This register contains bits for configuring GENFIFO threshold + * @{ + */ +/** + * Register: XQSPIPSU_GF_THRESHOLD + */ +#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U + +#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U +#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU +#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U +/** @} */ + +/** + * @name XQSPIPSU Poll configuration Register information + * This register contains bits for configuring Poll feature + * @{ + */ +/** + * Register: XQSPIPSU_POLL_CFG + */ +#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U + +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U + +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U + +#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U +#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U +#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U + +#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U +#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U +#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU + +#define XQSPIPSU_P_TO_OFFSET 0X00000058U + +#define XQSPIPSU_P_TO_VALUE_SHIFT 0U +#define XQSPIPSU_P_TO_VALUE_WIDTH 32U +#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU Transfer Status Register information + * This register contains bits for transfer status + * @{ + */ +/** + * Register: XQSPIPSU_XFER_STS + */ +#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU + +#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U +#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U +#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU GEN_FIFO Snapshot Register information + * This register contains bits for configuring GENFIFO + * @{ + */ +/** + * Register: XQSPIPSU_GF_SNAPSHOT + */ +#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U + +#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0U +#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20U +#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU +/** @} */ + +/** + * @name XQSPIPSU Receive Data Copy Register information + * @{ + */ +/** + * Register: XQSPIPSU_RX_COPY + */ +#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U + +#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8U +#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8U +#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U + +#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0U +#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8U +#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU +/** @} */ + +/** + * @name XQSPIPSU Module Identification Register information + * @{ + */ +/** + * Register: XQSPIPSU_MOD_ID + */ +#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU + +#define XQSPIPSU_MOD_ID_SHIFT 0U +#define XQSPIPSU_MOD_ID_WIDTH 32U +#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU DMA Transfer Register information + * This register contains bits for configuring DMA + * @{ + */ +/** + * Register: XQSPIPSU_QSPIDMA_DST_ADDR + */ +#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U + +#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU + +#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U + +#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U +#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU + +#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U + +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U + +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U + +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU + +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U + +#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU +#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU + +#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U + +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU + +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U + +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU + +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU + +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU Generic FIFO masks information + * Generic FIFO masks information + * @{ + */ +/** + * Generic FIFO masks + */ +#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU +#define XQSPIPSU_GENFIFO_DATA_XFER 0x100U +#define XQSPIPSU_GENFIFO_EXP 0x200U +#define XQSPIPSU_GENFIFO_MODE_SPI 0x400U +#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U +#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U +#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U +#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U +#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U +#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U +#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */ +#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */ +#define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */ +#define XQSPIPSU_GENFIFO_STRIPE 0x40000U +#define XQSPIPSU_GENFIFO_POLL 0x80000U +/** @} */ + +/** + * @name XQSPIPSU RX Data Delay Register information + * @{ + */ +/** + * QSPI Data delay register + */ +#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U + +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U + +#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U +#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U +#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U +/** @} */ + +/** + * @name TAPDLY Bypass register information + * @{ + */ +/** + * Tapdelay Bypass register + */ + +#if defined versal +#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU +#else +#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U +#endif + +#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U +#if !defined (versal) +#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U +#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U +#endif + +#if defined versal +#define IOU_TAPDLY_RESET_STATE 0x4U +#else +#define IOU_TAPDLY_RESET_STATE 0x7U +#endif +/** @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPsu_In32 Xil_In32 /**< Read the 32 bit register value */ +#define XQspiPsu_Out32 Xil_Out32 /**< Write the 32 bit register value */ + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset) +* +******************************************************************************/ +#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + + +#ifdef __cplusplus +} +#endif + + +#endif /**< XQSPIPSU_H */ +/** @} */ |