diff options
Diffstat (limited to 'bsps/include/dev/irq')
| -rw-r--r-- | bsps/include/dev/irq/arm-gic-irq.h | 55 | ||||
| -rw-r--r-- | bsps/include/dev/irq/arm-gic-regs.h | 42 | ||||
| -rw-r--r-- | bsps/include/dev/irq/arm-gic-tm27.h | 90 | ||||
| -rw-r--r-- | bsps/include/dev/irq/arm-gic.h | 45 | ||||
| -rw-r--r-- | bsps/include/dev/irq/arm-gicv3.h | 73 |
5 files changed, 220 insertions, 85 deletions
diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index e0a96c781a..c3615a12a0 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC IRQ + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H @@ -19,12 +39,17 @@ #include <bsp.h> #include <dev/irq/arm-gic.h> -#include <rtems/score/processormask.h> #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + #define ARM_GIC_IRQ_SGI_0 0 #define ARM_GIC_IRQ_SGI_1 1 #define ARM_GIC_IRQ_SGI_2 2 @@ -66,16 +91,6 @@ rtems_status_code arm_gic_irq_get_group( gic_group *group ); -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets); static inline rtems_status_code arm_gic_irq_generate_software_irq( @@ -94,9 +109,13 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( return sc; } +#ifdef RTEMS_SMP uint32_t arm_gic_irq_processor_count(void); void arm_gic_irq_initialize_secondary_cpu(void); +#endif + +/** @} */ #ifdef __cplusplus } diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h index 5827411c3b..c03a7a7a07 100644 --- a/bsps/include/dev/irq/arm-gic-regs.h +++ b/bsps/include/dev/irq/arm-gic-regs.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Register definitions + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) memory-mapped registers. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H @@ -19,6 +39,12 @@ #include <bsp/utility.h> +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + typedef struct { uint32_t iccicr; #define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4) @@ -206,4 +232,6 @@ typedef struct { uint32_t icspigrpmodr[64]; } gic_sgi_ppi; +/** @} */ + #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h index d7aeefb529..70e76c7603 100644 --- a/bsps/include/dev/irq/arm-gic-tm27.h +++ b/bsps/include/dev/irq/arm-gic-tm27.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC TM27 Support + * @brief This header file provides the TM27 support for the ARM Generic + * Interrupt Controller (GIC). */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -21,11 +41,11 @@ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H #define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H -#include <assert.h> - #include <bsp.h> #include <bsp/irq.h> +#include <rtems/score/assert.h> + #define MUST_WAIT_FOR_INTERRUPT 1 #ifndef ARM_GIC_TM27_IRQ_LOW @@ -36,50 +56,66 @@ #define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 #endif +#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW + #define ARM_GIC_TM27_PRIO_LOW 0x80 #define ARM_GIC_TM27_PRIO_HIGH 0x00 -static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { - rtems_status_code sc = rtems_interrupt_handler_install( + static rtems_interrupt_entry entry_low; + static rtems_interrupt_entry entry_high; + rtems_status_code sc; + + rtems_interrupt_entry_initialize( + &entry_low, + handler, + NULL, + "tm27 low" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_LOW, - "tm27 low", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_low ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_LOW, ARM_GIC_TM27_PRIO_LOW ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); - sc = rtems_interrupt_handler_install( + rtems_interrupt_entry_initialize( + &entry_high, + handler, + NULL, + "tm27 high" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_HIGH, - "tm27 high", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_high ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_HIGH, ARM_GIC_TM27_PRIO_HIGH ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Cause_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_LOW, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Clear_tm27_intr(void) @@ -89,11 +125,13 @@ static inline void Clear_tm27_intr(void) static inline void Lower_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_HIGH, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } #endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h index eba519c749..4e418de68f 100644 --- a/bsps/include/dev/irq/arm-gic.h +++ b/bsps/include/dev/irq/arm-gic.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Support + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_H @@ -26,11 +46,14 @@ extern "C" { #endif /* __cplusplus */ /** - * @defgroup arm_gic ARM GIC + * @defgroup DevIRQGIC ARM Generic Interrupt Controller (GIC) Support * - * @ingroup RTEMSBSPsARMShared + * @ingroup RTEMSImplClassicIntr * - * @brief ARM_GIC Support Package + * @brief This group contains the Interrupt Manager implementation parts + * specific to the ARM Generic Interrupt Controller. + * + * @{ */ #define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) @@ -229,6 +252,8 @@ static inline void gic_id_set_handling_model( dist->icdicfr[i] = icdicfr; } +/* @} */ + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h index a79368ebdf..8829c32384 100644 --- a/bsps/include/dev/irq/arm-gicv3.h +++ b/bsps/include/dev/irq/arm-gicv3.h @@ -3,13 +3,14 @@ /** * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief This header file contains interfaces to access an Arm GICv3. + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support specific to the GICv3. */ /* - * Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2022 embedded brains GmbH & Co. KG * Copyright (C) 2019 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without @@ -44,6 +45,12 @@ extern "C" { #endif +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + #define PRIORITY_DEFAULT 127 #define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23) @@ -116,13 +123,16 @@ extern "C" { #else /* ARM_MULTILIB_ARCH_V4 */ /* AArch64 GICv3 registers are not named in GCC */ -#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0" -#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0" +#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0" +#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0" #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0" +#define ICC_IGRPEN0 ICC_IGRPEN0_EL1 +#define ICC_IGRPEN1 ICC_IGRPEN1_EL1 #define ICC_PMR "S3_0_C4_C6_0, %0" #define ICC_EOIR1 "S3_0_C12_C12_1, %0" #define ICC_SRE "S3_0_C12_C12_5, %0" #define ICC_BPR0 "S3_0_C12_C8_3, %0" +#define ICC_BPR1 "S3_0_C12_C12_3, %0" #define ICC_CTLR "S3_0_C12_C12_4, %0" #define ICC_IAR1 "%0, S3_0_C12_C12_0" #define MPIDR "%0, mpidr_el1" @@ -300,25 +310,27 @@ static void gicv3_init_dist(volatile gic_dist *dist) } } -/* - * A better way to access these registers than special opcodes - */ -#define isb() __asm __volatile("isb" : : : "memory") +static void gicv3_init_cpu_interface(uint32_t cpu_index) +{ + /* Initialize Interrupt Controller System Register Enable Register */ +#ifdef BSP_ARM_GIC_ICC_SRE + WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE); +#endif -#define WRITE_SPECIALREG(reg, _val) \ - __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) + /* Initialize Interrupt Controller Interrupt Priority Mask Register */ +#ifdef BSP_ARM_GIC_ICC_PMR + WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR); +#endif -#define gic_icc_write(reg, val) \ -do { \ - WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \ - isb(); \ -} while (0) + /* Initialize Interrupt Controller Binary Point Register 0 */ +#ifdef BSP_ARM_GIC_ICC_BPR0 + WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0); +#endif -static void gicv3_init_cpu_interface(uint32_t cpu_index) -{ - uint32_t sre_value = 0x7; - WRITE_SR(ICC_SRE, sre_value); - WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff)); + /* Initialize Interrupt Controller Binary Point Register 1 */ +#ifdef BSP_ARM_GIC_ICC_BPR1 + WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1); +#endif volatile gic_redist *redist = gicv3_get_redist(cpu_index); uint32_t waker = redist->icrwaker; @@ -334,9 +346,20 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index) sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; } - /* Enable interrupt groups 0 and 1 */ - gic_icc_write(IGRPEN1, 1); - WRITE_SR(ICC_CTLR, 0x0); + /* Initialize Interrupt Controller Interrupt Group Enable 0 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN0 + WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0); +#endif + + /* Initialize Interrupt Controller Interrupt Group Enable 1 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN1 + WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1); +#endif + + /* Initialize Interrupt Controller Control Register */ +#ifdef BSP_ARM_GIC_ICC_CTRL + WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL); +#endif } static inline void gicv3_get_attributes( @@ -371,6 +394,8 @@ static inline void gicv3_get_attributes( } } +/** @} */ + #ifdef __cplusplus } #endif |