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-rw-r--r--bsps/i386/include/bsp/apic.h125
-rw-r--r--bsps/i386/include/bsp/irq.h96
-rw-r--r--bsps/i386/include/bsp/irq_asm.h45
-rw-r--r--bsps/i386/include/bsp/realmode_int.h97
-rw-r--r--bsps/i386/include/bsp/smp-imps.h245
-rw-r--r--bsps/i386/include/bsp/tty_drv.h104
-rw-r--r--bsps/i386/include/i386_io.h73
-rw-r--r--bsps/i386/include/libcpu/byteorder.h31
-rw-r--r--bsps/i386/include/libcpu/cpuModel.h51
-rw-r--r--bsps/i386/include/libcpu/page.h39
-rw-r--r--bsps/i386/include/uart.h191
11 files changed, 1097 insertions, 0 deletions
diff --git a/bsps/i386/include/bsp/apic.h b/bsps/i386/include/bsp/apic.h
new file mode 100644
index 0000000000..9ae103b963
--- /dev/null
+++ b/bsps/i386/include/bsp/apic.h
@@ -0,0 +1,125 @@
+/**
+ * @file
+ * @ingroup i386_apic
+ * @brief Local and I/O APIC definitions
+ */
+
+/*
+ * Author: Erich Boleyn <erich@uruk.org>
+ * http://www.uruk.org/~erich/
+ *
+ * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @defgroup i386_apci
+ * @ingroup i386_pci
+ * @brief Intel Architecture local and I/O APIC definitions
+ * @{
+ */
+
+/*
+ * Header file for Intel Architecture local and I/O APIC definitions.
+ *
+ * This file was created from information in the Intel Pentium Pro
+ * Family Developer's Manual, Volume 3: Operating System Writer's
+ * Manual, order number 242692-001, which can be ordered from the
+ * Intel literature center.
+ */
+
+#ifndef _APIC_H
+#define _APIC_H
+
+/*
+ * APIC Defines.
+ */
+
+/*
+ * Recommendation: Don't use this except for MSI interrupt delivery.
+ * In general, the "Destination Mode" can be used to control this, since
+ * it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC
+ * version for AMD Opteron.
+ */
+#define APIC_BCAST_ID 0xFF
+
+/*
+ * APIC register definitions
+ */
+
+/*
+ * Shared defines for I/O and local APIC definitions
+ */
+/** @brief APIC version register */
+#define APIC_VERSION(x) ((x) & 0xFF)
+#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF)
+/** @brief APIC id register */
+#define APIC_ID(x) ((x) >> 24)
+#define APIC_VER_NEW 0x10
+
+#define IOAPIC_REGSEL 0
+#define IOAPIC_RW 0x10
+#define IOAPIC_ID 0
+#define IOAPIC_VER 1
+#define IOAPIC_REDIR 0x10
+
+#define LAPIC_ID 0x20
+#define LAPIC_VER 0x30
+#define LAPIC_TPR 0x80
+#define LAPIC_APR 0x90
+#define LAPIC_PPR 0xA0
+#define LAPIC_EOI 0xB0
+#define LAPIC_LDR 0xD0
+#define LAPIC_DFR 0xE0
+#define LAPIC_SPIV 0xF0
+#define LAPIC_SPIV_ENABLE_APIC 0x100
+#define LAPIC_ISR 0x100
+#define LAPIC_TMR 0x180
+#define LAPIC_IRR 0x200
+#define LAPIC_ESR 0x280
+#define LAPIC_ICR 0x300
+#define LAPIC_ICR_DS_SELF 0x40000
+#define LAPIC_ICR_DS_ALLINC 0x80000
+#define LAPIC_ICR_DS_ALLEX 0xC0000
+#define LAPIC_ICR_TM_LEVEL 0x8000
+#define LAPIC_ICR_LEVELASSERT 0x4000
+#define LAPIC_ICR_STATUS_PEND 0x1000
+#define LAPIC_ICR_DM_LOGICAL 0x800
+#define LAPIC_ICR_DM_LOWPRI 0x100
+#define LAPIC_ICR_DM_SMI 0x200
+#define LAPIC_ICR_DM_NMI 0x400
+#define LAPIC_ICR_DM_INIT 0x500
+#define LAPIC_ICR_DM_SIPI 0x600
+#define LAPIC_LVTT 0x320
+#define LAPIC_LVTPC 0x340
+#define LAPIC_LVT0 0x350
+#define LAPIC_LVT1 0x360
+#define LAPIC_LVTE 0x370
+#define LAPIC_TICR 0x380
+#define LAPIC_TCCR 0x390
+#define LAPIC_TDCR 0x3E0
+
+#endif /* _APIC_H */
+
+/** @} */
diff --git a/bsps/i386/include/bsp/irq.h b/bsps/i386/include/bsp/irq.h
new file mode 100644
index 0000000000..f7e673c8a7
--- /dev/null
+++ b/bsps/i386/include/bsp/irq.h
@@ -0,0 +1,96 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief Interrupt handlers
+ */
+
+/* irq.h
+ *
+ * This include file describe the data structure and the functions implemented
+ * by rtems to write interrupt handlers.
+ *
+ * CopyRight (C) 1998 valette@crf.canon.fr
+ *
+ * This code is heavilly inspired by the public specification of STREAM V2
+ * that can be found at :
+ *
+ * <http://www.chorus.com/Documentation/index.html> by following
+ * the STREAM API Specification Document link.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/**
+ * @defgroup i386_irq Interrupt handlers
+ * @ingroup i386_shared
+ * @brief Data structure and the functions to write interrupt handlers
+ * @{
+ */
+
+#ifndef _IRQ_H_
+#define _IRQ_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief
+ * Include some preprocessor value also used by assember code
+ */
+
+#include <bsp/irq_asm.h>
+#include <rtems.h>
+#define BSP_SHARED_HANDLER_SUPPORT 1
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/*-------------------------------------------------------------------------+
+| Constants
++--------------------------------------------------------------------------*/
+
+/** @brief Base vector for our IRQ handlers. */
+#define BSP_IRQ_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE
+#define BSP_IRQ_LINES_NUMBER 16
+#define BSP_IRQ_MAX_ON_i8259A (BSP_IRQ_LINES_NUMBER - 1)
+
+/*
+ * Define the number of valid vectors. This is different to the number of IRQ
+ * signals supported. Use this value to allocation vector data or range check.
+ */
+#define BSP_IRQ_VECTOR_NUMBER 17
+#define BSP_IRQ_VECTOR_LOWEST_OFFSET 0
+#define BSP_IRQ_VECTOR_MAX_OFFSET (BSP_IRQ_VECTOR_NUMBER - 1)
+
+/** @brief
+ * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE
+ * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE
+ * 2) The same name should be defined on all architecture
+ * so that handler connection can be unchanged.
+ */
+#define BSP_PERIODIC_TIMER 0 /* fixed on all builds of PC */
+#define BSP_KEYBOARD 1 /* fixed on all builds of PC */
+#define BSP_UART_COM2_IRQ 3 /* fixed for ISA bus */
+#define BSP_UART_COM1_IRQ 4 /* fixed for ISA bus */
+#define BSP_UART_COM3_IRQ 5
+#define BSP_UART_COM4_IRQ 6
+#define BSP_RT_TIMER1 8
+#define BSP_RT_TIMER3 10
+#define BSP_SMP_IPI 16 /* not part of the ATPIC */
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_IRQ_VECTOR_LOWEST_OFFSET
+#define BSP_INTERRUPT_VECTOR_MAX BSP_IRQ_VECTOR_MAX_OFFSET
+
+/** @brief
+ * Type definition for RTEMS managed interrupts
+ */
+typedef unsigned short rtems_i8259_masks;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IRQ_H_ */
diff --git a/bsps/i386/include/bsp/irq_asm.h b/bsps/i386/include/bsp/irq_asm.h
new file mode 100644
index 0000000000..05cb4e6cc3
--- /dev/null
+++ b/bsps/i386/include/bsp/irq_asm.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ * @ingroup i386_irq
+ * @brief
+ */
+
+/* irq_asm.h
+ *
+ * This include file has defines to represent some contant used
+ * to program and manage the Intel 8259 interrupt controller
+ *
+ *
+ * COPYRIGHT (c) 1998 valette@crf.canon.fr
+ *
+ * Copyright (c) 2016 Chris Johns <chrisj@rtems.org>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+#ifndef __I8259S_H__
+#define __I8259S_H__
+
+#define BSP_ASM_IRQ_VECTOR_BASE 0x20
+ /** @brief PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< Master PIC command register
+#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< Slave PIC command register
+#define PIC_MASTER_IMR_IO_PORT 0x21 ///< Master PIC Interrupt Mask Register
+#define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< Slave PIC Interrupt Mask Register
+
+ /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI 0x60 ///< End of Specific Interrupt (EOSI)
+#define PIC_EOI 0x20 ///< Generic End of Interrupt (EOI)
+
+/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
+#define PIC_OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */
+#define PIC_OCW3_RR 0x02 /* register read */
+#define PIC_OCW3_P 0x04 /* poll mode command */
+/* 0x08 must be 1 to select OCW3 vs OCW2 */
+#define PIC_OCW3_SEL 0x08 /* must be 1 */
+/* 0x10 must be 0 to select OCW3 vs ICW1 */
+#define PIC_OCW3_SMM 0x20 /* special mode mask */
+#define PIC_OCW3_ESMM 0x40 /* enable SMM */
+
+#endif
diff --git a/bsps/i386/include/bsp/realmode_int.h b/bsps/i386/include/bsp/realmode_int.h
new file mode 100644
index 0000000000..e8a1e36d01
--- /dev/null
+++ b/bsps/i386/include/bsp/realmode_int.h
@@ -0,0 +1,97 @@
+/**
+ * @file realmode_int.h
+ *
+ * @ingroup i386_shared
+ *
+ * @brief Definitioins supporting real mode interrupt calls.
+ *
+ * Interface allows calling given interrupt number with content of the
+ * registers defined. For passing or receiving higher amounts of the data
+ * there is a buffer accessible from real mode available. Real mode pointer
+ * to this buffer is passed to the interrupt in the registers.
+ */
+
+/*
+ * Copyright (C) 2014 Jan Doležal (dolezj21@fel.cvut.cz)
+ * CTU in Prague.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _REALMODE_INT_H
+#define _REALMODE_INT_H
+
+#include <rtems/score/cpu.h>
+#include <stdint.h>
+
+#ifndef ASM /* ASM */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* --- BIOS service interrupt number --- */
+/* number of interrupt servicing video functions */
+#define INTERRUPT_NO_VIDEO_SERVICES 0x10
+
+/**
+ * @brief Used for passing and retrieving registers content to/from real mode
+ * interrupt call.
+ */
+typedef struct {
+ uint32_t reg_eax;
+ uint32_t reg_ebx;
+ uint32_t reg_ecx;
+ uint32_t reg_edx;
+ uint32_t reg_esi;
+ uint32_t reg_edi;
+ uint16_t reg_ds;
+ uint16_t reg_es;
+ uint16_t reg_fs;
+ uint16_t reg_gs;
+} RTEMS_PACKED i386_realmode_interrupt_registers;
+
+/**
+ * @brief Returns buffer and its size usable with real mode interrupt call.
+ *
+ * Provides position to real mode buffer. It is buffer
+ * accessible from real mode context - it is located below
+ * address ~0x100000 in order for it to be accessible
+ * This buffer is meant to be pointed to by segReg:GenPurpReg
+ * and through this get bigger portion of an information to/from
+ * interrupt service routine than just by using register.
+ *
+ * @param[out] size pointer to variable, where the size of buffer
+ * will be filled
+ * @retval pointer to buffer
+ */
+extern void *i386_get_default_rm_buffer(uint16_t *size);
+
+/**
+ * @brief Call to real mode interrupt with specified int NO and processor
+ * registers.
+ *
+ * This function allows calling interrupts in real mode and to set processor
+ * registers as desired before interrupt call is made and to retrieve the
+ * registers content after call was made.
+ *
+ * @param[in] interrupt_number interrupt number to be called
+ * @param[in] ir pointer to structure containing registers to be passed to
+ * interrupt and to retrieve register content after call was made.
+ * @retval 0 call failed (GDT too small or pagin is on)
+ * @retval 1 call successful
+ */
+extern int i386_real_interrupt_call(
+ uint8_t interrupt_number,
+ i386_realmode_interrupt_registers *ir
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* _REALMODE_INT_H */
diff --git a/bsps/i386/include/bsp/smp-imps.h b/bsps/i386/include/bsp/smp-imps.h
new file mode 100644
index 0000000000..60e688547b
--- /dev/null
+++ b/bsps/i386/include/bsp/smp-imps.h
@@ -0,0 +1,245 @@
+/**
+ * @file
+ * @ingroup i386_smp
+ * @brief Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control
+ */
+
+/*
+ * Author: Erich Boleyn <erich@uruk.org>
+ * http://www.uruk.org/~erich/
+ *
+ * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Header file implementing Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
+ * with hooks for running correctly on a standard PC without the hardware.
+ *
+ * This file was created from information in the Intel MPS version 1.4
+ * document, order number 242016-004, which can be ordered from the
+ * Intel literature center.
+ */
+
+/*
+ * This file is based upon code by Eric Boleyn as documented above.
+ * RTEMS support was added and minimal other changes were made.
+ * This should make it easier to compare this file with the original
+ * version.
+ *
+ * COPYRIGHT (c) 2011.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/**
+ * @defgroup i386_smp SMP
+ * @ingroup i386_shared
+ * @brief
+ * Header file implementing Intel MultiProcessor Specification (MPS)
+ * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
+ * with hooks for running correctly on a standard PC without the hardware.
+ */
+
+#ifndef _SMP_IMPS_H
+#define _SMP_IMPS_H
+
+/* make sure "apic.h" is included */
+#ifndef _APIC_H
+#error Must include "apic.h" before "smp-imps.h"
+#endif /* !_APIC_H */
+
+/*
+ * Defines used.
+ */
+
+#define IMPS_READ(x) (*((volatile unsigned *) (x)))
+#define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y))
+
+#ifdef IMPS_DEBUG
+#define IMPS_DEBUG_PRINT(x) KERNEL_PRINT(x)
+#else /* !IMPS_DEBUG */
+#define IMPS_DEBUG_PRINT(x)
+#endif /* !IMPS_DEBUG */
+
+#define IMPS_MAX_CPUS APIC_BCAST_ID
+
+/** @brief
+ * This is the value that must be in the "sig" member of the MP
+ * Floating Pointer Structure.
+ */
+#define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24))
+#define IMPS_FPS_IMCRP_BIT 0x80
+#define IMPS_FPS_DEFAULT_MAX 7
+
+/** @brief
+ * This is the value that must be in the "sig" member of the MP
+ * Configuration Table Header.
+ */
+#define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24))
+
+/** @brief
+ * These are the "type" values for Base MP Configuration Table entries.
+ */
+#define IMPS_FLAG_ENABLED 1
+#define IMPS_BCT_PROCESSOR 0
+#define IMPS_CPUFLAG_BOOT 2
+#define IMPS_BCT_BUS 1
+#define IMPS_BCT_IOAPIC 2
+#define IMPS_BCT_IO_INTERRUPT 3
+#define IMPS_BCT_LOCAL_INTERRUPT 4
+#define IMPS_INT_INT 0
+#define IMPS_INT_NMI 1
+#define IMPS_INT_SMI 2
+#define IMPS_INT_EXTINT 3
+
+
+/*
+ * Typedefs and data item definitions done here.
+ */
+
+typedef struct imps_fps imps_fps; ///< MP floating pointer structure
+typedef struct imps_cth imps_cth; ///< MP configuration table header
+typedef struct imps_processor imps_processor;
+typedef struct imps_bus imps_bus;
+typedef struct imps_ioapic imps_ioapic;
+typedef struct imps_interrupt imps_interrupt;
+
+
+/*
+ * Data structures defined here
+ */
+
+/** @brief
+ * MP Floating Pointer Structure (fps)
+ *
+ * Look at page 4-3 of the MP spec for the starting definitions of
+ * this structure.
+ */
+struct imps_fps
+{
+ unsigned sig;
+ imps_cth *cth_ptr;
+ unsigned char length;
+ unsigned char spec_rev;
+ unsigned char checksum;
+ unsigned char feature_info[5];
+};
+
+/** @brief
+ * MP Configuration Table Header (cth)
+ *
+ * Look at page 4-5 of the MP spec for the starting definitions of
+ * this structure.
+ */
+struct imps_cth
+{
+ unsigned sig;
+ unsigned short base_length;
+ unsigned char spec_rev;
+ unsigned char checksum;
+ char oem_id[8];
+ char prod_id[12];
+ unsigned oem_table_ptr;
+ unsigned short oem_table_size;
+ unsigned short entry_count;
+ unsigned lapic_addr;
+ unsigned short extended_length;
+ unsigned char extended_checksum;
+ char reserved[1];
+};
+
+/** @brief
+ * Base MP Configuration Table Types. They are sorted according to
+ * type (i.e. all of type 0 come first, etc.). Look on page 4-6 for
+ * the start of the descriptions.
+ */
+
+struct imps_processor
+{
+ unsigned char type; ///< must be 0
+ unsigned char apic_id;
+ unsigned char apic_ver;
+ unsigned char flags;
+ unsigned signature;
+ unsigned features;
+ char reserved[8];
+};
+
+struct imps_bus
+{
+ unsigned char type; ///< must be 1
+ unsigned char id;
+ char bus_type[6];
+};
+
+struct imps_ioapic
+{
+ unsigned char type; ///< must be 2
+ unsigned char id;
+ unsigned char ver;
+ unsigned char flags;
+ unsigned addr;
+};
+
+struct imps_interrupt
+{
+ unsigned char type; ///< must be 3 or 4
+ unsigned char int_type;
+ unsigned short flags;
+ unsigned char source_bus_id;
+ unsigned char source_bus_irq;
+ unsigned char dest_apic_id;
+ unsigned char dest_apic_intin;
+};
+
+/*
+ * Exported globals here.
+ */
+
+/** @brief
+ * These map from virtual cpu numbers to APIC id's and back.
+ */
+extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
+extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
+
+/** @brief base address of application processor reset code at 0x70000 */
+extern char _binary_appstart_bin_start[];
+extern char _binary_appstart_bin_size[];
+
+/*
+ * Defines that use variables
+ */
+#define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x))))
+#define IMPS_LAPIC_WRITE(x, y) \
+ (*((volatile unsigned *) (imps_lapic_addr+(x))) = (y))
+
+#endif /* !_SMP_IMPS_H */
+
+/** @} */
diff --git a/bsps/i386/include/bsp/tty_drv.h b/bsps/i386/include/bsp/tty_drv.h
new file mode 100644
index 0000000000..cbfb346f22
--- /dev/null
+++ b/bsps/i386/include/bsp/tty_drv.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ * @ingroup i386_tty
+ * @brief ttySx driver
+ */
+
+#ifndef __tty_drv__
+#define __tty_drv__
+/***************************************************************************
+ *
+ * Copyright (c) 1999 ConnectTel, Inc. All Rights Reserved.
+ *
+ * MODULE DESCRIPTION: Prototype routines for the ttySx driver.
+ *
+ * by: Rosimildo da Silva:
+ * rdasilva@connecttel.com
+ * http://www.connecttel.com
+ *
+ ****************************************************************************/
+
+/**
+ * @defgroup i386_tty ttSx
+ * @ingroup i386_comm
+ * @brief i386 tySx driver
+ * @{
+ */
+
+/* functions */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief ttyS1 entry points */
+rtems_device_driver tty1_initialize(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty1_open(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty1_control(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+/** @brief tty1 & tty2 shared entry points */
+rtems_device_driver tty_close(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty_read(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty_write(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+/** @brief tty2 entry points */
+rtems_device_driver tty2_initialize(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty2_open(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+rtems_device_driver tty2_control(
+ rtems_device_major_number,
+ rtems_device_minor_number,
+ void *
+);
+
+#define TTY1_DRIVER_TABLE_ENTRY \
+ { tty1_initialize, tty1_open, tty_close, \
+ tty_read, tty_write, tty1_control }
+
+#define TTY2_DRIVER_TABLE_ENTRY \
+ { tty2_initialize, tty2_open, tty_close, \
+ tty_read, tty_write, tty2_control }
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __tty_drv__ */
diff --git a/bsps/i386/include/i386_io.h b/bsps/i386/include/i386_io.h
new file mode 100644
index 0000000000..1308d58b6b
--- /dev/null
+++ b/bsps/i386/include/i386_io.h
@@ -0,0 +1,73 @@
+/**
+ * @file
+ * @ingroup i386_io
+ * @brief I/O
+ */
+
+/*
+ * Copyright (c) 2000 - Rosimildo da Silva. All Rights Reserved.
+ *
+ * MODULE DESCRIPTION:
+ *
+ * IO Functions for the PC platform equivalent to DOS/Linux. They make
+ * eaiser the porting of code from these platforms.
+ *
+ * by: Rosimildo da Silva: rdasilva@connecttel.com
+ *
+ */
+
+/**
+ * @defgroup i386_io I/O
+ * @ingroup i386_comm
+ * @brief I/O
+ * @{
+ */
+
+#ifndef i386_io_h__
+#define i386_io_h__
+
+#define rtems_inb(port) \
+({ \
+ register int _inb_result; \
+ \
+ __asm__ volatile ("xorl %%eax,%%eax; inb %%dx,%%al" : \
+ "=a" (_inb_result) : "d" (port)); \
+ _inb_result; \
+})
+
+#define rtems_inw(port) \
+({ \
+ register int _inbw_result; \
+ \
+ __asm__ volatile ("xorl %%eax,%%eax; inw %%dx,%%ax" : \
+ "=a" (_inbw_result) : "d" (port)); \
+ _inbw_result; \
+})
+
+#define rtems_outb(port, data) \
+ __asm__ volatile ("outb %%al,%%dx" : : "a" (data), "d" (port))
+
+#define rtems_outw(port, data) \
+ __asm__ volatile ("outw %%ax,%%dx" : : "a" (data), "d" (port))
+
+#define outp(port, val) rtems_outb(port,val)
+#define inp(port) rtems_inb(port)
+
+#define outb(val, port) rtems_outb(port,val)
+#define inb(port) rtems_inb(port)
+
+#define outb_p(val, port) rtems_outb(port,val)
+#define inb_p(port) rtems_inb(port)
+
+#define outportb(port,val) rtems_outb(port,val)
+#define inportb(port) rtems_inb(port)
+
+#define outw(val, port) rtems_outw(port,val)
+#define inw(port) rtems_inw(port)
+
+#define cli() __asm__ __volatile__("cli")
+#define sti() __asm__ __volatile__("sti");
+
+#endif /* i386_io_h__ */
+
+/** @} */
diff --git a/bsps/i386/include/libcpu/byteorder.h b/bsps/i386/include/libcpu/byteorder.h
new file mode 100644
index 0000000000..939e51fe84
--- /dev/null
+++ b/bsps/i386/include/libcpu/byteorder.h
@@ -0,0 +1,31 @@
+/*
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _LIBCPU_BYTEORDER_H
+#define _LIBCPU_BYTEORDER_H
+
+static inline void st_le32(volatile uint32_t *addr, uint32_t value)
+{
+ *(addr)=value ;
+}
+
+static inline uint32_t ld_le32(volatile uint32_t *addr)
+{
+ return(*addr);
+}
+
+static inline void st_le16(volatile uint16_t *addr, uint16_t value)
+{
+ *(addr)=value ;
+}
+
+static inline uint16_t ld_le16(volatile uint16_t *addr)
+{
+ return(*addr);
+}
+
+
+#endif
diff --git a/bsps/i386/include/libcpu/cpuModel.h b/bsps/i386/include/libcpu/cpuModel.h
new file mode 100644
index 0000000000..d17839b7ea
--- /dev/null
+++ b/bsps/i386/include/libcpu/cpuModel.h
@@ -0,0 +1,51 @@
+/*
+ * This file contains declaration for variables and code
+ * that may be used to get the Intel Cpu identification
+ * that has been performed by checkCPUtypeSetCr0 function.
+ */
+
+/*
+ * COPYRIGHT (c) 1998 valette@crf.canon.fr
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef libcpu_cpuModel_h
+#define libcpu_cpuModel_h
+
+/*
+ * Tell us the machine setup..
+ */
+
+extern char hard_math; /* floating point coprocessor present indicator */
+extern char x86; /* type of cpu (3 = 386, 4 =486, ...) */
+extern char x86_model;
+extern char x86_mask;
+extern int x86_capability; /* cpuid:EDX */
+extern int x86_capability_x; /* cpuid:ECX */
+extern int x86_capability_ebx; /* cpuid:EBX */
+extern int x86_capability_cores; /* cpuid.(EAX=4, ECX=0) - physical cores */
+extern char x86_vendor_id[13];
+extern int have_cpuid;
+extern unsigned char Cx86_step; /* cyrix processor identification */
+
+/* Display this information on console in ascii form */
+extern void printCpuInfo(void);
+
+/* determine if the CPU has a TSC */
+#define x86_has_tsc() \
+ (x86_capability & (1 << 4))
+
+static inline unsigned long long
+rdtsc(void)
+{
+ /* Return the value of the on-chip cycle counter. */
+ unsigned long long result;
+ __asm__ volatile(".byte 0x0F, 0x31" : "=A" (result));
+ return result;
+} /* rdtsc */
+
+
+#endif
diff --git a/bsps/i386/include/libcpu/page.h b/bsps/i386/include/libcpu/page.h
new file mode 100644
index 0000000000..5e9cec2227
--- /dev/null
+++ b/bsps/i386/include/libcpu/page.h
@@ -0,0 +1,39 @@
+/*
+ * @file page.h
+ *
+ * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr)
+ * Canon Centre Recherche France.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _LIBCPU_i386_PAGE_H
+#define _LIBCPU_i386_PAGE_H
+
+#ifndef ASM
+
+#include <rtems/score/cpu.h>
+
+/* C declaration for paging management */
+
+extern int _CPU_is_cache_enabled(void);
+extern int _CPU_is_paging_enabled(void);
+extern int init_paging(void);
+extern void _CPU_enable_paging(void);
+extern void _CPU_disable_paging(void);
+extern void _CPU_disable_cache(void);
+extern void _CPU_enable_cache(void);
+extern int _CPU_map_phys_address
+ (void **mappedAddress, void *physAddress,
+ int size, int flag);
+extern int _CPU_unmap_virt_address (void *mappedAddress, int size);
+extern int _CPU_change_memory_mapping_attribute
+ (void **newAddress, void *mappedAddress,
+ unsigned int size, unsigned int flag);
+extern int _CPU_display_memory_attribute(void);
+
+# endif /* ASM */
+
+#endif
diff --git a/bsps/i386/include/uart.h b/bsps/i386/include/uart.h
new file mode 100644
index 0000000000..96e4a312b4
--- /dev/null
+++ b/bsps/i386/include/uart.h
@@ -0,0 +1,191 @@
+/**
+ * @file
+ * @ingroup i386_uart
+ * @brief i386 UART definitions
+ */
+
+/*
+ * This software is Copyright (C) 1998 by T.sqware - all rights limited
+ * It is provided in to the public domain "as is", can be freely modified
+ * as far as this copyight notice is kept unchanged, but does not imply
+ * an endorsement by T.sqware of the product in which it is included.
+ */
+
+/**
+ * @defgroup i386_uart UART
+ * @ingroup i386_comm
+ * @brief i386 UART definitions
+ * @{
+ */
+
+#ifndef _BSPUART_H
+#define _BSPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
+void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
+void BSP_uart_set_baud(int uart, unsigned long baud);
+void BSP_uart_intr_ctrl(int uart, int cmd);
+void BSP_uart_throttle(int uart);
+void BSP_uart_unthrottle(int uart);
+int BSP_uart_polled_status(int uart);
+void BSP_uart_polled_write(int uart, int val);
+int BSP_uart_polled_read(int uart);
+void BSP_uart_termios_set(int uart, void *ttyp);
+int BSP_uart_termios_read_com1(int uart);
+int BSP_uart_termios_read_com2(int uart);
+ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len);
+ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len);
+void BSP_uart_termios_isr_com1(void *);
+void BSP_uart_termios_isr_com2(void *);
+void BSP_uart_dbgisr_com1(void);
+void BSP_uart_dbgisr_com2(void);
+extern int BSP_poll_char_via_serial(void);
+extern void BSP_output_char_via_serial(char val);
+extern int BSPConsolePort;
+extern int BSPBaseBaud;
+
+/** @brief
+ * Command values for BSP_uart_intr_ctrl(),
+ * values are strange in order to catch errors
+ * with assert
+ */
+#define BSP_UART_INTR_CTRL_DISABLE (0)
+#define BSP_UART_INTR_CTRL_GDB (0xaa) ///< RX only
+#define BSP_UART_INTR_CTRL_ENABLE (0xbb) ///< Normal operations
+#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) ///< RX & line status
+
+/** @brief Return values for uart_polled_status() */
+#define BSP_UART_STATUS_ERROR (-1) ///< No character
+#define BSP_UART_STATUS_NOCHAR (0) ///< No character
+#define BSP_UART_STATUS_CHAR (1) ///< Character present
+#define BSP_UART_STATUS_BREAK (2) ///< Break point is detected
+
+/** @brief PC UART definitions */
+#define BSP_UART_COM1 (0)
+#define BSP_UART_COM2 (1)
+
+/** @brief
+ * Base IO for UART
+ */
+
+#define COM1_BASE_IO 0x3F8
+#define COM2_BASE_IO 0x2F8
+
+/** @brief
+ * Offsets from base
+ */
+
+/** @brief DLAB 0 */
+#define RBR (0) ///< Rx Buffer Register (read)
+#define THR (0) ///< Tx Buffer Register (write)
+#define IER (1) ///< Interrupt Enable Register
+
+/** @brief DLAB X */
+#define IIR (2) ///< Interrupt Ident Register (read)
+#define FCR (2) ///< FIFO Control Register (write)
+#define LCR (3) ///< Line Control Register
+#define MCR (4) ///< Modem Control Register
+#define LSR (5) ///< Line Status Register
+#define MSR (6) ///< Modem Status Register
+#define SCR (7) ///< Scratch register
+
+/** @brief DLAB 1 */
+#define DLL (0) ///< Divisor Latch, LSB
+#define DLM (1) ///< Divisor Latch, MSB
+#define AFR (2) ///< Alternate Function register
+
+/** @brief
+ * Interrupt source definition via IIR
+ */
+#define MODEM_STATUS 0
+#define NO_MORE_INTR 1
+#define TRANSMITTER_HODING_REGISTER_EMPTY 2
+#define RECEIVER_DATA_AVAIL 4
+#define RECEIVER_ERROR 6
+#define CHARACTER_TIMEOUT_INDICATION 12
+
+/** @brief
+ * Bits definition of IER
+ */
+#define RECEIVE_ENABLE 0x1
+#define TRANSMIT_ENABLE 0x2
+#define RECEIVER_LINE_ST_ENABLE 0x4
+#define MODEM_ENABLE 0x8
+#define INTERRUPT_DISABLE 0x0
+
+/** @brief
+ * Bits definition of the Line Status Register (LSR)
+ */
+#define DR 0x01 ///< Data Ready
+#define OE 0x02 ///< Overrun Error
+#define PE 0x04 ///< Parity Error
+#define FE 0x08 ///< Framing Error
+#define BI 0x10 ///< Break Interrupt
+#define THRE 0x20 ///< Transmitter Holding Register Empty
+#define TEMT 0x40 ///< Transmitter Empty
+#define ERFIFO 0x80 ///< Error receive Fifo
+
+/** @brief
+ * Bits definition of the MODEM Control Register (MCR)
+ */
+#define DTR 0x01 ///< Data Terminal Ready
+#define RTS 0x02 ///< Request To Send
+#define OUT_1 0x04 ///< Output 1, (reserved on COMPAQ I/O Board)
+#define OUT_2 0x08 ///< Output 2, Enable Asynchronous Port Interrupts
+#define LB 0x10 ///< Enable Internal Loop Back
+
+/** @brief
+ * Bits definition of the Line Control Register (LCR)
+ */
+#define CHR_5_BITS 0
+#define CHR_6_BITS 1
+#define CHR_7_BITS 2
+#define CHR_8_BITS 3
+
+#define WL 0x03 ///< Word length mask
+#define STB 0x04 ///< 1 Stop Bit, otherwise 2 Stop Bits
+#define PEN 0x08 ///< Parity Enabled
+#define EPS 0x10 ///< Even Parity Select, otherwise Odd
+#define SP 0x20 ///< Stick Parity
+#define BCB 0x40 ///< Break Control Bit
+#define DLAB 0x80 ///< Enable Divisor Latch Access
+
+/** @brief
+ * Bits definition of the MODEM Status Register (MSR)
+ */
+#define DCTS 0x01 ///< Delta Clear To Send
+#define DDSR 0x02 ///< Delta Data Set Ready
+#define TERI 0x04 ///< Trailing Edge Ring Indicator
+#define DDCD 0x08 ///< Delta Carrier Detect Indicator
+#define CTS 0x10 ///< Clear To Send (when loop back is active)
+#define DSR 0x20 ///< Data Set Ready (when loop back is active)
+#define RI 0x40 ///< Ring Indicator (when loop back is active)
+#define DCD 0x80 ///< Data Carrier Detect (when loop back is active)
+
+/** @brief
+ * Bits definition of the FIFO Control Register : WD16C552 or NS16550
+ */
+
+#define FIFO_CTRL 0x01 ///< Set to 1 permit access to other bits
+#define FIFO_EN 0x01 ///< Enable the FIFO
+#define XMIT_RESET 0x02 ///< Transmit FIFO Reset
+#define RCV_RESET 0x04 ///< Receive FIFO Reset
+#define FCR3 0x08 ///< do not understand manual!
+
+#define RECEIVE_FIFO_TRIGGER1 0x0 ///< trigger recieve interrupt after 1 byte
+#define RECEIVE_FIFO_TRIGGER4 0x40 ///< trigger recieve interrupt after 4 byte
+#define RECEIVE_FIFO_TRIGGER8 0x80 ///< trigger recieve interrupt after 8 byte
+#define RECEIVE_FIFO_TRIGGER12 0xc0 ///< trigger recieve interrupt after 12 byte
+#define TRIG_LEVEL 0xc0 ///< Mask for the trigger level
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BSPUART_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-02 01:19:38 +0000