diff options
Diffstat (limited to 'bsps/arm/xilinx-zynq/include')
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp.h | 80 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h | 73 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h | 35 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/i2c.h | 50 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/irq.h | 115 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h | 150 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h | 67 | ||||
| -rw-r--r-- | bsps/arm/xilinx-zynq/include/tm27.h | 36 |
8 files changed, 606 insertions, 0 deletions
diff --git a/bsps/arm/xilinx-zynq/include/bsp.h b/bsps/arm/xilinx-zynq/include/bsp.h new file mode 100644 index 0000000000..afc6a66a06 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp.h @@ -0,0 +1,80 @@ +/** + * @file + * @ingroup arm_zynq + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H +#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H + +#include <bspopts.h> + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include <rtems.h> + +#include <bsp/default-initial-extension.h> +#include <bsp/start.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_zynq Xilinx-Zynq Support + * @ingroup bsp_arm + * @brief Xilinz-Zynq Board Support Package + * @{ + */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 + +#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 + +#define BSP_ARM_GIC_DIST_BASE 0xf8f01000 + +#define BSP_ARM_L2C_310_BASE 0xf8f02000 + +#define BSP_ARM_L2C_310_ID 0x410000c8 + +/** + * @brief Zynq specific set up of the MMU. + * + * Provide in the application to override + * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 + * AXI ports. You should add the specific regions that map into your + * PL rather than just open the whole of the GP[01] address space up. + */ +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void); + +uint32_t zynq_clock_cpu_1x(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h new file mode 100644 index 0000000000..c06a47c7f1 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t control; +#define CADENCE_I2C_CONTROL_DIV_A(val) BSP_FLD32(val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_A_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define CADENCE_I2C_CONTROL_DIV_B(val) BSP_FLD32(val, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define CADENCE_I2C_CONTROL_DIV_B_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define CADENCE_I2C_CONTROL_CLR_FIFO BSP_BIT32(6) +#define CADENCE_I2C_CONTROL_SLVMON BSP_BIT32(5) +#define CADENCE_I2C_CONTROL_HOLD BSP_BIT32(4) +#define CADENCE_I2C_CONTROL_ACKEN BSP_BIT32(3) +#define CADENCE_I2C_CONTROL_NEA BSP_BIT32(2) +#define CADENCE_I2C_CONTROL_MS BSP_BIT32(1) +#define CADENCE_I2C_CONTROL_RW BSP_BIT32(0) + uint32_t status; +#define CADENCE_I2C_STATUS_BA BSP_BIT32(8) +#define CADENCE_I2C_STATUS_RXOVF BSP_BIT32(7) +#define CADENCE_I2C_STATUS_TXDV BSP_BIT32(6) +#define CADENCE_I2C_STATUS_RXDV BSP_BIT32(5) +#define CADENCE_I2C_STATUS_RXRW BSP_BIT32(3) + uint32_t address; +#define CADENCE_I2C_ADDRESS(val) BSP_FLD32(val, 0, 9) +#define CADENCE_I2C_ADDRESS_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define CADENCE_I2C_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t data; + uint32_t irqstatus; +#define CADENCE_I2C_IXR_ARB_LOST BSP_BIT32(9) +#define CADENCE_I2C_IXR_RX_UNF BSP_BIT32(7) +#define CADENCE_I2C_IXR_TX_OVR BSP_BIT32(6) +#define CADENCE_I2C_IXR_RX_OVR BSP_BIT32(5) +#define CADENCE_I2C_IXR_SLV_RDY BSP_BIT32(4) +#define CADENCE_I2C_IXR_TO BSP_BIT32(3) +#define CADENCE_I2C_IXR_NACK BSP_BIT32(2) +#define CADENCE_I2C_IXR_DATA BSP_BIT32(1) +#define CADENCE_I2C_IXR_COMP BSP_BIT32(0) + uint32_t transfer_size; +#define CADENCE_I2C_TRANSFER_SIZE(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TRANSFER_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t slave_mon_pause; +#define CADENCE_I2C_SLAVE_MON_PAUSE(val) BSP_FLD32(val, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define CADENCE_I2C_SLAVE_MON_PAUSE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t timeout; +#define CADENCE_I2C_TIMEOUT(val) BSP_FLD32(val, 0, 7) +#define CADENCE_I2C_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define CADENCE_I2C_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t irqmask; + uint32_t irqenable; + uint32_t irqdisable; +} cadence_i2c; + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h new file mode 100644 index 0000000000..9697cf3354 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int i2c_bus_register_cadence( + const char *bus_path, + uintptr_t register_base, + uint32_t input_clock, + rtems_vector_number irq +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/i2c.h b/bsps/arm/xilinx-zynq/include/bsp/i2c.h new file mode 100644 index 0000000000..709ea0178e --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/i2c.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H +#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H + +#include <bsp/cadence-i2c.h> +#include <bsp/irq.h> +#include <bsp.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline int zynq_register_i2c_0(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-0", + 0xe0004000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_0 + ); +} + +static inline int zynq_register_i2c_1(void) +{ + return i2c_bus_register_cadence( + "/dev/i2c-1", + 0xe0005000, + zynq_clock_cpu_1x(), + ZYNQ_IRQ_I2C_1 + ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h b/bsps/arm/xilinx-zynq/include/bsp/irq.h new file mode 100644 index 0000000000..e8288938fe --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h @@ -0,0 +1,115 @@ +/** + * @file + * @ingroup zynq_interrupt + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H +#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H + +#ifndef ASM + +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#include <bsp/arm-a9mpcore-irq.h> +#include <bsp/arm-gic-irq.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_interrupt Interrupt Support + * @ingroup arm_zynq + * @brief Interrupt Support + * @{ + */ + +#define ZYNQ_IRQ_CPU_0 32 +#define ZYNQ_IRQ_CPU_1 33 +#define ZYNQ_IRQ_L2_CACHE 34 +#define ZYNQ_IRQ_OCM 35 +#define ZYNQ_IRQ_PMU_0 37 +#define ZYNQ_IRQ_PMU_1 38 +#define ZYNQ_IRQ_XADC 39 +#define ZYNQ_IRQ_DVI 40 +#define ZYNQ_IRQ_SWDT 41 +#define ZYNQ_IRQ_TTC_0_0 42 +#define ZYNQ_IRQ_TTC_1_0 43 +#define ZYNQ_IRQ_TTC_2_0 44 +#define ZYNQ_IRQ_DMAC_ABORT 45 +#define ZYNQ_IRQ_DMAC_0 46 +#define ZYNQ_IRQ_DMAC_1 47 +#define ZYNQ_IRQ_DMAC_2 48 +#define ZYNQ_IRQ_DMAC_3 49 +#define ZYNQ_IRQ_SMC 50 +#define ZYNQ_IRQ_QUAD_SPI 51 +#define ZYNQ_IRQ_GPIO 52 +#define ZYNQ_IRQ_USB_0 53 +#define ZYNQ_IRQ_ETHERNET_0 54 +#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 +#define ZYNQ_IRQ_SDIO_0 56 +#define ZYNQ_IRQ_I2C_0 57 +#define ZYNQ_IRQ_SPI_0 58 +#define ZYNQ_IRQ_UART_0 59 +#define ZYNQ_IRQ_CAN_0 60 +#define ZYNQ_IRQ_FPGA_0 61 +#define ZYNQ_IRQ_FPGA_1 62 +#define ZYNQ_IRQ_FPGA_2 63 +#define ZYNQ_IRQ_FPGA_3 64 +#define ZYNQ_IRQ_FPGA_4 65 +#define ZYNQ_IRQ_FPGA_5 66 +#define ZYNQ_IRQ_FPGA_6 67 +#define ZYNQ_IRQ_FPGA_7 68 +#define ZYNQ_IRQ_TTC_0_1 69 +#define ZYNQ_IRQ_TTC_1_1 70 +#define ZYNQ_IRQ_TTC_2_1 71 +#define ZYNQ_IRQ_DMAC_4 72 +#define ZYNQ_IRQ_DMAC_5 73 +#define ZYNQ_IRQ_DMAC_6 74 +#define ZYNQ_IRQ_DMAC_7 75 +#define ZYNQ_IRQ_USB_1 76 +#define ZYNQ_IRQ_ETHERNET_1 77 +#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 +#define ZYNQ_IRQ_SDIO_1 79 +#define ZYNQ_IRQ_I2C_1 80 +#define ZYNQ_IRQ_SPI_1 81 +#define ZYNQ_IRQ_UART_1 82 +#define ZYNQ_IRQ_CAN_1 83 +#define ZYNQ_IRQ_FPGA_8 84 +#define ZYNQ_IRQ_FPGA_9 85 +#define ZYNQ_IRQ_FPGA_10 86 +#define ZYNQ_IRQ_FPGA_11 87 +#define ZYNQ_IRQ_FPGA_12 88 +#define ZYNQ_IRQ_FPGA_13 89 +#define ZYNQ_IRQ_FPGA_14 90 +#define ZYNQ_IRQ_FPGA_15 91 +#define ZYNQ_IRQ_PARITY 92 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 92 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h new file mode 100644 index 0000000000..127f272fd9 --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h @@ -0,0 +1,150 @@ +/** + * @file + * @ingroup zynq_uart_regs + * @brief UART register definitions. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup zynq_uart_regs UART Register Definitions + * @ingroup zynq_uart + * @brief UART Register Definitions + * @{ + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H + +#include <bsp/utility.h> + +#define ZYNQ_UART_FIFO_DEPTH 64 + +typedef struct zynq_uart { + uint32_t control; +#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8) +#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7) +#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6) +#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5) +#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4) +#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3) +#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2) +#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1) +#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0) + uint32_t mode; +#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U +#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U +#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U +#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U +#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7) +#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U +#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U +#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U +#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5) +#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define ZYNQ_UART_MODE_PAR_EVEN 0x00U +#define ZYNQ_UART_MODE_PAR_ODD 0x01U +#define ZYNQ_UART_MODE_PAR_SPACE 0x02U +#define ZYNQ_UART_MODE_PAR_MARK 0x03U +#define ZYNQ_UART_MODE_PAR_NONE 0x04U +#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2) +#define ZYNQ_UART_MODE_CHRL_8 0x00U +#define ZYNQ_UART_MODE_CHRL_7 0x02U +#define ZYNQ_UART_MODE_CHRL_6 0x03U +#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0) + uint32_t irq_en; + uint32_t irq_dis; + uint32_t irq_mask; + uint32_t irq_sts; +#define ZYNQ_UART_TOVR BSP_BIT32(12) +#define ZYNQ_UART_TNFUL BSP_BIT32(11) +#define ZYNQ_UART_TTRIG BSP_BIT32(10) +#define ZYNQ_UART_DMSI BSP_BIT32(9) +#define ZYNQ_UART_TIMEOUT BSP_BIT32(8) +#define ZYNQ_UART_PARE BSP_BIT32(7) +#define ZYNQ_UART_FRAME BSP_BIT32(6) +#define ZYNQ_UART_ROVR BSP_BIT32(5) +#define ZYNQ_UART_TFUL BSP_BIT32(4) +#define ZYNQ_UART_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_RFUL BSP_BIT32(2) +#define ZYNQ_UART_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_RTRIG BSP_BIT32(0) + uint32_t baud_rate_gen; +#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t rx_timeout; +#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t rx_fifo_trg_lvl; +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t modem_ctrl; +#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5) +#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1) +#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0) + uint32_t modem_sts; +#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8) +#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7) +#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6) +#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5) +#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4) +#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3) +#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2) +#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1) +#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0) + uint32_t channel_sts; +#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14) +#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13) +#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12) +#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11) +#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10) +#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4) +#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3) +#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2) +#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1) +#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0) + uint32_t tx_rx_fifo; +#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t baud_rate_div; +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t flow_delay; +#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t reserved_3c[2]; + uint32_t tx_fifo_trg_lvl; +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +} zynq_uart; + +/** @} */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h new file mode 100644 index 0000000000..4d3edfabef --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h @@ -0,0 +1,67 @@ +/** + * @file + * @ingroup zynq_uart + * @brief UART support. + */ + +/* + * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H +#define LIBBSP_ARM_XILINX_ZYNQ_UART_H + +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_uart UART Support + * @ingroup arm_zynq + * @brief UART Support + */ + +typedef struct { + rtems_termios_device_context base; + volatile struct zynq_uart *regs; + bool transmitting; + rtems_vector_number irq; +} zynq_uart_context; + +const rtems_termios_device_handler zynq_uart_handler; + +extern zynq_uart_context zynq_uart_instances[2]; + +#define ZYNQ_UART_DEFAULT_BAUD 115200 + +void zynq_uart_initialize(rtems_termios_device_context *base); + +int zynq_uart_read_polled(rtems_termios_device_context *base); + +void zynq_uart_write_polled( + rtems_termios_device_context *base, + char c +); + +/** + * Flush TX FIFO and wait until it is empty. Used in bsp_reset. + */ +void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */ diff --git a/bsps/arm/xilinx-zynq/include/tm27.h b/bsps/arm/xilinx-zynq/include/tm27.h new file mode 100644 index 0000000000..39b8ecafec --- /dev/null +++ b/bsps/arm/xilinx-zynq/include/tm27.h @@ -0,0 +1,36 @@ +/** + * @file + * @ingroup zynq_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup zynq_tm27 TM27 Test Support + * @ingroup arm_zynq + * @brief Interrupt Mechanisms for tm27 test + */ + +#include <bsp/arm-gic-tm27.h> + +#endif /* __tm27_h */ |