diff options
Diffstat (limited to 'bsps/arm/tms570')
89 files changed, 3651 insertions, 1411 deletions
diff --git a/bsps/arm/tms570/README b/bsps/arm/tms570/README index 2a0bd4c8e4..fb196ca8d0 100644 --- a/bsps/arm/tms570/README +++ b/bsps/arm/tms570/README @@ -1,7 +1,13 @@ -Development Board: TMS570LS31x Hercules Development Kit from TI +TI Hercules TMS570 series development boards: + +TMS570LS31: http://www.ti.com/tool/tmds570ls31hdk +TMS570LC43: + +https://www.ti.com/tool/TMDX570LC43HDK + Overview -------- @@ -12,81 +18,68 @@ Drivers: o Ethernet - external lwIP fork repository BSP variants: - tms570ls3137_hdk_intram - place code and data into internal SRAM - tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM - tms570ls3137_hdk_with_loader - reserve 256kB at Flash start for loader - and place RTEMS application from address - 0x00040000 - tms570ls3137_hdk - variant for stand-alone RTEMS application stored - and running directly from flash. This variant - requires initialization of hardware to be integrated - into RTEMS. RTEMS has to be configured with - TMS570_USE_HWINIT_STARTUP=1 - and initialization code has to be included in the sources. - -Tool-chain used for development + + TMS570LS3137: + + tms570ls3137_hdk_intram - place code and data into internal SRAM + tms570ls3137_hdk_sdram - place code and data into external SDRAM + tms570ls3137_hdk - variant for stand-alone RTEMS application stored + and running directly from flash.. + + TMS570LC4357: + + tms570ls4357_hdk_sdram - place code and data into external SDRAM + tms570lc4357_hdk - variant for stand-alone RTEMS application stored + and running directly from flash. + +Toolchain used for development ------------------------------- - arm-rtems4.12-gcc (GCC) 6.1.1 20160526 + Newlib 2.4.0.20160527 + Binutils 2.26.20160125 - - CFLAGS="-O2 -pipe" LDFLAGS=-s \ - ../../../src/gcc-6.1/configure --target=arm-rtems4.12 --prefix=/usr \ - --enable-languages=c,c++ \ - --disable-libstdcxx-pch \ - --with-gnu-ld \ - --with-gnu-as \ - --enable-threads \ - --enable-target-optspace \ - --with-system-zlib \ - --verbose \ - --disable-nls --without-included-gettext \ - --disable-win32-registry \ - --with-newlib \ - --enable-plugin \ - --enable-newlib-io-c99-formats \ - --enable-version-specific-runtime-libs \ - --enable-newlib-iconv \ - --disable-lto \ - --disable-lto \ - --enable-libgomp \ - --enable-newlib-iconv \ - --enable-newlib-iconv-encodings="iso_8859_1,utf_8" \ +Example of RTEMS build configuration (config.ini) used for testing of self-contained applications +running directly from flash: + + [arm/tms570lc4357_hdk] All patches required for Cortex-R and big-endian ARM support are already -integrated in GCC the mainline. +integrated into the GCC and RTEMS mainline. + +MCU-specific flags used during compilation are located in +`externs/rtems/spec/build/bsps/arm/tms570/abi.yml` + +When linking an application to an RTEMs build, ensure the following flags are set +(arm-rtems6-gcc/g++): -RTEMS build configuration used for testing of self contained -applications to run directly from Flash + -mbe32 + -qrtems + -T{RTEMS_BSP_VARIANT_LINKERSCRIPT} - ../../../src/rtems/configure --target=arm-rtems4.12 --prefix=/opt/rtems4.12 \ - --enable-rtems-inlines --disable-multiprocessing --enable-cxx \ - --enable-rdbg --enable-maintainer-mode --enable-tests=samples \ - --disable-networking --enable-posix --enable-itron --disable-ada \ - --disable-expada --disable-multilib --disable-docs \ - --enable-rtemsbsp="tms570ls3137_hdk" \ - --enable-rtems-debug \ - TMS570_USE_HWINIT_STARTUP=1 +RTEMS_BSP_VARIANT_LINKERSCRIPT can be found with the static libraries built for rtems. There +is one for each BSP variant type. For example `linkcmds.tms570lc4357_hdk` Execution --------- -Application build by above process can be directly programmed +Application built by the above process can be directly programmed into Flash and run. -For test and debug purposes, TI's HalCoGen generated application -is used to set up the board and then the RTEMS application -image is loaded using OpenOCD to internal EEC SRAM or external SDRAM. -This prevents wear of Flash which has limited guaranteed -erase cycles count. - -The following features are implemented in the BSP only partially: +The following features are implemented in the `_hdk` BSP variants: + Initial CPU and peripheral initialization + Cores Self-test +For test and debug purposes, TI's HalCoGen generated application +can be used to set up the board and then a RTEMS application +can be loaded using OpenOCD to internal SRAM or external SDRAM. +This prevents wear of Flash which has limited guaranteed +erase cycles count. + Setup application code is available there: https://github.com/hornmich/tms570ls3137-hdk-sdram +A branch that enables loading to Flash via openocd on the TMS570LC4357 +can be found here: + https://github.com/len0rd/openocd + TMDS570LS31HDK setup to use SDRAM to load and debug RTEMS applications ----------------------------------------------------------------------- @@ -101,36 +94,31 @@ For ETHERNET, the lwIP port for TMS570LS3137 has been developed at Industrial Informatics Group of Czech Technical University in Prague and development versions are available on SourceForge. -The RTEMS and TMS570 support is included in uLAN project lwIP -repository for now +RTEMS and TMS570 support is included in uLAN project lwIP +repository https://sourceforge.net/p/ulan/lwip-omk/ -But other place should be found when RTEMS lwIP -integration with read, write, close etc. functions -is implemented in future. +This port has been consolidated with other RTEMS-LWIP ports here: + + https://git.rtems.org/rtems-lwip/tree/rtemslwip/tms570 -Adapt BSP for another TMS570 based hardware -------------------------------------------- +A port to the TMS570LC4357 based off this work is underway. -When TMS570_USE_HWINIT_STARTUP=1 then quite complete -initialization and selft-test code is included in TMS570 -BSP build. The support included in hwinit subdirectory -provides version of bsp_start_hook_0 and bsp_start_hook_1 -which proceeds many self-tests functions, clocks, PLLs -peripherals and other subsystems configuration. +Adapt BSP for other TMS570 based hardware +----------------------------------------- Complete pin multiplexer initialization according to the list of individual pins functions is included. Pins function definition can be found and altered in a file - rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c + `rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c` Complete "database" of all possible pin functions for -TMS570LS3137 chip is provided in a file +a chip is provided in a file - rtems/c/src/lib/libbsp/arm/tms570/include/tms570ls3137zwt-pins.h + `rtems/c/src/lib/libbsp/arm/tms570/include/tms570<MODEL>-pins.h` If another package or chip is considered then tools found in next repository can be used or extended to generate header @@ -145,4 +133,5 @@ Additional information about the BSP and board can be found at https://devel.rtems.org/wiki/TBR/BSP/Tms570 Additional information about the CPU can be found at - http://www.ti.com/product/tms570ls3137 + https://www.ti.com/product/tms570ls3137 + https://www.ti.com/product/TMS570LC4357 diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c index 86b26aafd8..2e71440857 100644 --- a/bsps/arm/tms570/clock/clock.c +++ b/bsps/arm/tms570/clock/clock.c @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief clock functions definitions. + * @brief This source file contains the Clock Driver implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,12 +17,26 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdlib.h> @@ -28,7 +44,7 @@ #include <rtems.h> #include <bsp.h> #include <bsp/irq.h> -#include <bsp/tms570-rti.h> +#include <bsp/tms570.h> #include <rtems/timecounter.h> static struct timecounter tms570_rti_tc; @@ -128,9 +144,9 @@ static void tms570_clock_driver_support_initialize_hardware( void ) * * @retval Void */ -static void tms570_clock_driver_support_at_tick( void ) +static void tms570_clock_driver_support_at_tick(volatile tms570_rti_t *rti) { - TMS570_RTI.INTFLAG = TMS570_RTI_INTFLAG_INT0; + rti->INTFLAG = TMS570_RTI_INTFLAG_INT0; } /** @@ -142,7 +158,7 @@ static void tms570_clock_driver_support_at_tick( void ) * @retval Void */ static void tms570_clock_driver_support_install_isr( - rtems_isr_entry Clock_isr + rtems_interrupt_handler handler ) { rtems_status_code sc = RTEMS_SUCCESSFUL; @@ -151,8 +167,8 @@ static void tms570_clock_driver_support_install_isr( TMS570_IRQ_TIMER_0, "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + handler, + RTEMS_DEVOLATILE(tms570_rti_t *, &TMS570_RTI) ); if ( sc != RTEMS_SUCCESSFUL ) { rtems_fatal_error_occurred(0xdeadbeef); @@ -161,14 +177,12 @@ static void tms570_clock_driver_support_install_isr( #define Clock_driver_support_initialize_hardware \ tms570_clock_driver_support_initialize_hardware -#define Clock_driver_support_at_tick \ - tms570_clock_driver_support_at_tick +#define Clock_driver_support_at_tick(arg) \ + tms570_clock_driver_support_at_tick(arg) #define Clock_driver_support_initialize_hardware \ tms570_clock_driver_support_initialize_hardware -#define Clock_driver_support_install_isr(Clock_isr) \ - tms570_clock_driver_support_install_isr( Clock_isr ) - -void Clock_isr(void *arg); /* to supress warning */ +#define Clock_driver_support_install_isr(handler) \ + tms570_clock_driver_support_install_isr(handler) #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/arm/tms570/config/tms570ls3137_hdk_with_loader-testsuite.tcfg b/bsps/arm/tms570/config/tms570ls3137_hdk_with_loader-testsuite.tcfg deleted file mode 100644 index cd8b657bc5..0000000000 --- a/bsps/arm/tms570/config/tms570ls3137_hdk_with_loader-testsuite.tcfg +++ /dev/null @@ -1,9 +0,0 @@ -# -# tms570ls3137_hdk_with_loader RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/small-memory-testsuite.tcfg - -exclude: linpack diff --git a/bsps/arm/tms570/console/printk-support.c b/bsps/arm/tms570/console/printk-support.c index 3415b7d863..17c3a1f630 100644 --- a/bsps/arm/tms570/console/printk-support.c +++ b/bsps/arm/tms570/console/printk-support.c @@ -1,13 +1,17 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief definitions of serial line for debugging. + * @brief This source file contains the definition of ::BSP_output_char and + * ::BSP_poll_char. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,19 +19,32 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <rtems/bspIo.h> #include <rtems/sysinit.h> #include <stdint.h> #include <string.h> -#include <bsp/tms570-sci.h> #include <bsp/tms570-sci-driver.h> #define TMS570_CONSOLE (&driver_context_table[0]) @@ -39,33 +56,33 @@ * * @retval Void */ -static void tms570_debug_console_putc(char ch) +static void tms570_debug_console_out(char ch) { tms570_sci_context *ctx = TMS570_CONSOLE; volatile tms570_sci_t *regs = ctx->regs; - rtems_interrupt_level level; - rtems_interrupt_disable(level); - while ( ( regs->FLR & TMS570_SCI_FLR_TXRDY ) == 0) { - rtems_interrupt_flash(level); + while ( true ) { + rtems_interrupt_level level; + + while ( ( regs->FLR & TMS570_SCI_FLR_TXRDY ) == 0) { + /* Wait */ + } + + rtems_interrupt_disable( level ); + + if ( ( regs->FLR & TMS570_SCI_FLR_TXRDY ) != 0) { + regs->TD = ch; + rtems_interrupt_enable( level ); + + break; + } + + rtems_interrupt_enable( level ); } - regs->TD = ch; + while ( ( regs->FLR & TMS570_SCI_FLR_TX_EMPTY ) == 0) { - rtems_interrupt_flash(level); + /* Wait */ } - rtems_interrupt_enable(level); -} - -/** - * @brief debug console output - * - * debug functions always use serial dev 0 peripheral - * - * @retval Void - */ -static void tms570_debug_console_out(char c) -{ - tms570_debug_console_putc(c); } static void tms570_debug_console_init(void) @@ -75,7 +92,7 @@ static void tms570_debug_console_init(void) tms570_sci_initialize(ctx); memset(&term, 0, sizeof(term)); - term.c_cflag = B115200; + term.c_ospeed = B115200; tms570_sci_set_attributes(&ctx->base, &term); BSP_output_char = tms570_debug_console_out; } diff --git a/bsps/arm/tms570/console/tms570-sci.c b/bsps/arm/tms570/console/tms570-sci.c index 5eba1f7c92..63f8e7c8ee 100644 --- a/bsps/arm/tms570/console/tms570-sci.c +++ b/bsps/arm/tms570/console/tms570-sci.c @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Serial communication interface (SCI) functions definitions. + * @brief This source file contains the Console Driver implementation using the + * Serial Communication Interface (SCI). */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,26 +18,37 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bspopts.h> #include <termios.h> #include <rtems/termiostypes.h> -#include <bsp/tms570-sci.h> #include <bsp/tms570-sci-driver.h> #include <rtems/console.h> #include <bsp.h> #include <bsp/fatal.h> #include <bsp/irq.h> -#define TMS570_SCI_BUFFER_SIZE 1 - /** * @brief Table including all serial drivers * @@ -156,33 +170,6 @@ rtems_device_driver console_initialize( } /** - * @brief Reads chars from HW - * - * Reads chars from HW peripheral specified in driver context. - * TMS570 does not have HW buffer for serial line so this function can - * return only 0 or 1 char - * - * @param[in] ctx context of the driver - * @param[out] buf read data buffer - * @param[in] N size of buffer - * @retval x Number of read chars from peripherals - */ -static int tms570_sci_read_received_chars( - tms570_sci_context * ctx, - char * buf, - int N) -{ - if ( N < 1 ) { - return 0; - } - if ( ctx->regs->RD != 0 ) { - buf[0] = ctx->regs->RD; - return 1; - } - return 0; -} - -/** * @brief Enables RX interrupt * * Enables RX interrupt source of SCI peripheral @@ -335,23 +322,25 @@ static void tms570_sci_interrupt_handler(void * arg) { rtems_termios_tty *tty = arg; tms570_sci_context *ctx = rtems_termios_get_device_context(tty); - char buf[TMS570_SCI_BUFFER_SIZE]; - size_t n; /* * Check if we have received something. */ if ( (ctx->regs->FLR & TMS570_SCI_FLR_RXRDY ) == TMS570_SCI_FLR_RXRDY ) { - n = tms570_sci_read_received_chars(ctx, buf, TMS570_SCI_BUFFER_SIZE); - if ( n > 0 ) { - /* Hand the data over to the Termios infrastructure */ - rtems_termios_enqueue_raw_characters(tty, buf, n); - } + char buf[1]; + + /* Read the received byte */ + buf[0] = ctx->regs->RD & 0x000000FF; + + /* Hand the data over to the Termios infrastructure */ + rtems_termios_enqueue_raw_characters(tty, buf, 1); } /* * Check if we have something transmitted. */ if ( (ctx->regs->FLR & TMS570_SCI_FLR_TXRDY ) == TMS570_SCI_FLR_TXRDY ) { + size_t n; + n = tms570_sci_transmitted_chars(ctx); if ( n > 0 ) { /* diff --git a/bsps/arm/tms570/cpucounter/cpucounterread.c b/bsps/arm/tms570/cpucounter/cpucounterread.c index 2195199106..009a37bec3 100644 --- a/bsps/arm/tms570/cpucounter/cpucounterread.c +++ b/bsps/arm/tms570/cpucounter/cpucounterread.c @@ -1,29 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * - * @ingroup RTEMSBSPsARMTMS570_clocks - * - * @brief Cortex-R performace counters + * @ingroup RTEMSBSPsARMTMS570 * - * The counters setup functions are these which has been suggested - * on StackOverflow + * @brief This source file contains the CPU Counter implementation. * - * Code is probably for use on Cortex-A without modifications as well. + * The counters setup functions are these which has been suggested on + * StackOverflow. Code is probably for use on Cortex-A without modifications + * as well. * * http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor */ /* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <rtems/counter.h> diff --git a/bsps/arm/tms570/include/bsp.h b/bsps/arm/tms570/include/bsp.h index c5ac0cc59a..287750295f 100644 --- a/bsps/arm/tms570/include/bsp.h +++ b/bsps/arm/tms570/include/bsp.h @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Global BSP definitions. + * @brief This header file provides BSP-specific interfaces. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,11 +17,26 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_BSP_H @@ -44,8 +61,13 @@ #include <rtems.h> #include <bsp/default-initial-extension.h> -#define BSP_OSCILATOR_CLOCK 8000000 +#if TMS570_VARIANT == 4357 +#define BSP_PLL_OUT_CLOCK 150000000 +#else #define BSP_PLL_OUT_CLOCK 160000000 +#endif + +RTEMS_NO_RETURN void bsp_restart(const void *addr); #endif /* ASM */ diff --git a/bsps/arm/tms570/include/bsp/irq.h b/bsps/arm/tms570/include/bsp/irq.h index 872bebd908..d0eb130a92 100644 --- a/bsps/arm/tms570/include/bsp/irq.h +++ b/bsps/arm/tms570/include/bsp/irq.h @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 interrupt definitions. + * @brief This header file provides TMS570 interrupt definitions. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,12 +17,26 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_IRQ_H @@ -106,8 +122,8 @@ #define TMS570_IRQ_EMAC_TX 77 #define TMS570_IRQ_EMAC_THRESH 78 #define TMS570_IRQ_EMAC_RX 79 -#define TMS570_IRQ_HWA_INT_REQ_H 80 -#define TMS570_IRQ_HWA_INT_REQ_H 81 +#define TMS570_IRQ_HWAG1_INT_REQ_H 80 +#define TMS570_IRQ_HWAG2_INT_REQ_H 81 #define TMS570_IRQ_DCC_DONE_INTERRUPT 82 #define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 #define TMS570_IRQ_HWAG1_INT_REQ_L 88 @@ -124,33 +140,56 @@ #ifndef ASM /** - * @brief Set priority of the interrupt vector. - * - * This function is here because of compability. It should set - * priority of the interrupt vector. - * @warning It does not set any priority at HW layer. It is nearly imposible to - * @warning set priority of the interrupt on TMS570 in a nice way. - * @param[in] vector vector of isr - * @param[in] priority new priority assigned to the vector - * @return Void + * @brief Sets the priority of the interrupt vector. + * + * The priority is defined by the VIM interrupt channel. Firstly, the VIM + * Interrupt Control (CHANCTRL) registers are searched to get the current + * channel associated with the interrupt vector. The interrupt vector of the + * channel associated with the priority is assigned to this channel. The + * specified interrupt vector is assigned to the channel associated with the + * priority. So, this function swaps the channels of two interrupt vectors. + * + * @param vector is the number of the interrupt vector to set the priority. + * + * @param priority is the priority to set. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the + * number specified by ``vector``. + * + * @retval ::RTEMS_INVALID_PRIORITY The interrupt priority specified in + * ``priority`` was invalid. */ -void tms570_irq_set_priority( +rtems_status_code tms570_irq_set_priority( rtems_vector_number vector, - unsigned priority + uint32_t priority ); /** - * @brief Gets priority of the interrupt vector. + * @brief Gets the priority of the interrupt vector. * - * This function is here because of compability. It returns priority - * of the isr vector last set by tms570_irq_set_priority function. + * The priority is defined by the VIM interrupt channel. The VIM Interrupt + * Control (CHANCTRL) registers are searched to get the channel associated with + * the interrupt vector. * - * @warning It does not return any real priority of the HW layer. - * @param[in] vector vector of isr - * @retval 0 vector is invalid. - * @retval priority priority of the interrupt + * @param vector is the number of the interrupt vector to set the priority. + * + * @param priority is the priority to set. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_ADDRESS The ``priority`` parameter was NULL. + * + * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the + * number specified by ``vector``. + * + * @retval ::RTEMS_NOT_DEFINED The interrupt has no associated priority. */ -unsigned tms570_irq_get_priority( rtems_vector_number vector ); +rtems_status_code tms570_irq_get_priority( + rtems_vector_number vector, + uint32_t *priority +); #endif /* ASM */ diff --git a/bsps/arm/tms570/include/bsp/system-clocks.h b/bsps/arm/tms570/include/bsp/system-clocks.h index 9c819fef74..1fe30eecc4 100644 --- a/bsps/arm/tms570/include/bsp/system-clocks.h +++ b/bsps/arm/tms570/include/bsp/system-clocks.h @@ -1,31 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief System clocks. + * @brief This header file provides a free-running timer interface. */ /* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H #define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H -#include <bsp/tms570-rti.h> +#include <bsp/tms570.h> #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/tms570/include/bsp/ti_herc/errata_SSWF021_45.h b/bsps/arm/tms570/include/bsp/ti_herc/errata_SSWF021_45.h new file mode 100755 index 0000000000..e1821f8e6e --- /dev/null +++ b/bsps/arm/tms570/include/bsp/ti_herc/errata_SSWF021_45.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides errata SSWF021#45 interfaces. + * + * Pulled in from Halcogen v4.7.1. This is a rare but high-severity errata + * that should always be checked for at system start. + */ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ +#ifndef INCLUDE_ERRATA_SSWF021_45_H_ +#define INCLUDE_ERRATA_SSWF021_45_H_ +#include <stdint.h> + +uint32_t _errata_SSWF021_45_both_plls(uint32_t count); +uint32_t _errata_SSWF021_45_pll1(uint32_t count); +uint32_t _errata_SSWF021_45_pll2(uint32_t count); + + +#endif /* INCLUDE_HL_ERRATA_SSWF021_45_H_ */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h index 1649fbeb4b..fd1965ab8b 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_adc.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides ADC interfaces. + */ + /* The header file is generated by make_header.py from ADC.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h index 941ed54753..c5520058c0 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_ccmsr.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides CCMSR interfaces. + */ + /* The header file is generated by make_header.py from CCMSR.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h index f1352f67b6..8dfffb73b1 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_crc.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides CRC interfaces. + */ + /* The header file is generated by make_header.py from CRC.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h index c278f554ff..5da8355928 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcan.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides DCAN interfaces. + */ + /* The header file is generated by make_header.py from DCAN.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h index 4c90276523..12edca3eb1 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dcc.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides DCC interfaces. + */ + /* The header file is generated by make_header.py from DCC.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ @@ -41,6 +51,12 @@ #include <bsp/utility.h> +enum tms570_dcc1_cnt0_clksrc { + DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/ + DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ +}; + typedef struct{ uint32_t GCTRL; /*DCC Global Control Register*/ uint32_t REV; /*DCC Revision Id Register*/ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h index 717f05b010..4535aa6986 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides DMA interfaces. + */ + /* The header file is generated by make_header.py from DMA.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h index 55d656ef86..ff35475c41 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides DMM interfaces. + */ + /* The header file is generated by make_header.py from DMM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h index decf5bbeff..af0bafd171 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides EFUSE interfaces. + */ + /* The header file is generated by make_header.py from EFUSE.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h index c7c564cf49..e06f946509 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides EMACC interfaces. + */ + /* The header file is generated by make_header.py from EMACC.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h index c6e63210aa..10ae5b5d32 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides EMACM interfaces. + */ + /* The header file is generated by make_header.py from EMACM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h index 0810fd097f..69f13b73a2 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides EMIF interfaces. + */ + /* The header file is generated by make_header.py from EMIF.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h index 3ea4b6b43c..6c57486e8d 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides ESM interfaces. + */ + /* The header file is generated by make_header.py from ESM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h index 6c5a127d0b..8ee20080ba 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides flash interfaces. + */ + /* The header file is generated by make_header.py from FLASH.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h index e077ab65fd..9f72fc8f48 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides FlexRay interfaces. + */ + /* The header file is generated by make_header.py from FLEX_RAY.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h index 3cb7851754..0cc14dcd17 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides GIO interfaces. + */ + /* The header file is generated by make_header.py from GIO.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h index 3df27be461..5241da737b 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides HTU interfaces. + */ + /* The header file is generated by make_header.py from HTU.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h index 63ed3f8d95..4e51455b1e 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides I2C interfaces. + */ + /* The header file is generated by make_header.py from I2C.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h index f6197e811c..414110ff60 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides IOMM interfaces. + */ + /* The header file is generated by make_header.py from IOMM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ @@ -40,40 +50,7 @@ #define LIBBSP_ARM_TMS570_IOMM #include <bsp/utility.h> - -typedef struct{ - uint32_t PINMMR0; /*Pin Multiplexing Control Register 0*/ - uint32_t PINMMR1; /*Pin Multiplexing Control Register 1*/ - uint32_t PINMMR2; /*Pin Multiplexing Control Register 2*/ - uint32_t PINMMR3; /*Pin Multiplexing Control Register 3*/ - uint32_t PINMMR4; /*Pin Multiplexing Control Register 4*/ - uint32_t PINMMR5; /*Pin Multiplexing Control Register 5*/ - uint32_t PINMMR6; /*Pin Multiplexing Control Register 6*/ - uint32_t PINMMR7; /*Pin Multiplexing Control Register 7*/ - uint32_t PINMMR8; /*Pin Multiplexing Control Register 8*/ - uint32_t PINMMR9; /*Pin Multiplexing Control Register 9*/ - uint32_t PINMMR10; /*Pin Multiplexing Control Register 10*/ - uint32_t PINMMR11; /*Pin Multiplexing Control Register 11*/ - uint32_t PINMMR12; /*Pin Multiplexing Control Register 12*/ - uint32_t PINMMR13; /*Pin Multiplexing Control Register 13*/ - uint32_t PINMMR14; /*Pin Multiplexing Control Register 14*/ - uint32_t PINMMR15; /*Pin Multiplexing Control Register 15*/ - uint32_t PINMMR16; /*Pin Multiplexing Control Register 16*/ - uint32_t PINMMR17; /*Pin Multiplexing Control Register 17*/ - uint32_t PINMMR18; /*Pin Multiplexing Control Register 18*/ - uint32_t PINMMR19; /*Pin Multiplexing Control Register 19*/ - uint32_t PINMMR20; /*Pin Multiplexing Control Register 20*/ - uint32_t PINMMR21; /*Pin Multiplexing Control Register 21*/ - uint32_t PINMMR22; /*Pin Multiplexing Control Register 22*/ - uint32_t PINMMR23; /*Pin Multiplexing Control Register 23*/ - uint32_t PINMMR24; /*Pin Multiplexing Control Register 24*/ - uint32_t PINMMR25; /*Pin Multiplexing Control Register 25*/ - uint32_t PINMMR26; /*Pin Multiplexing Control Register 26*/ - uint32_t PINMMR27; /*Pin Multiplexing Control Register 27*/ - uint32_t PINMMR28; /*Pin Multiplexing Control Register 28*/ - uint32_t PINMMR29; /*Pin Multiplexing Control Register 29*/ - uint32_t PINMMR30; /*Pin Multiplexing Control Register 30*/ -} tms570_pinmux_t; +#include <bspopts.h> typedef struct{ uint32_t REVISION_REG; /*Revision Register*/ @@ -92,7 +69,14 @@ typedef struct{ uint32_t FAULT_STATUS_REG; /*Fault Status Register*/ uint32_t FAULT_CLEAR_REG; /*Fault Clear Register*/ uint8_t reserved5 [16]; - tms570_pinmux_t PINMUX; /*Pin Multiplexing Control Registers*/ +#if TMS570_VARIANT == 4357 + uint32_t PINMMR[180]; /* 0x110 - 1A4 : Output Pin Multiplexing Control + Registers (38 registers); 0x250 - 0x29C : Input Pin + Multiplexing Control Registers (20); 0X390 - 3DC : + Special Functionality Control Registers (20) */ +#else + uint32_t PINMMR[30]; /*Pin Multiplexing Control Register 0-30*/ +#endif } tms570_iomm_t; diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h index d2c3a3bfe8..2735072240 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides LIN interfaces. + */ + /* The header file is generated by make_header.py from LIN.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h index 704a0bc8a4..800a069353 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides MDIO interfaces. + */ + /* The header file is generated by make_header.py from MDIO.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h index 06b8bbeb0a..e2feb2e64d 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides N2HET interfaces. + */ + /* The header file is generated by make_header.py from N2HET.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h index 2c5ed29760..1f788512de 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides PBIST interfaces. + */ + /* The header file is generated by make_header.py from PBIST.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h index 4d5613aa9f..21ea62d747 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides PCR interfaces. + */ + /* The header file is generated by make_header.py from PCR.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h index 1cb8b03308..bd783a2689 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides PLL interfaces. + */ + /* The header file is generated by make_header.py from PLL.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h index c834b83999..be2185d5c2 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides PMM interfaces. + */ + /* The header file is generated by make_header.py from PMM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h index 1a4df19f8a..89be0179a6 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides POM interfaces. + */ + /* The header file is generated by make_header.py from POM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h index 029b3b5721..946ce643bc 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides RTI interfaces. + */ + /* The header file is generated by make_header.py from RTI.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h index cd54b29050..2974e5e561 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides RTP interfaces. + */ + /* The header file is generated by make_header.py from RTP.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h index 6b954f7fcf..0a9056d701 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides SCI interfaces. + */ + /* The header file is generated by make_header.py from SCI.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h index 35335c61e0..76edf8a86c 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides SPI interfaces. + */ + /* The header file is generated by make_header.py from SPI.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h index e935f450b8..5ad1f9aaac 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides STC interfaces. + */ + /* The header file is generated by make_header.py from STC.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h index 433e9e8fb6..d5583a1cca 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides SYS interfaces. + */ + /* The header file is generated by make_header.py from SYS.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ @@ -619,6 +629,16 @@ typedef struct{ /* field: WDRST - Watchdog reset flag. */ #define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13) +#if TMS570_VARIANT == 4357 + +/* field: DBGRST - Debug reset flag. */ +#define TMS570_SYS1_SYSESR_DBGRST BSP_BIT32(11) + +/* field: ICSTRST - Interconnect reset flag. */ +#define TMS570_SYS1_SYSESR_ICSTRST BSP_BIT32(7) + +#endif + /* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */ #define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5) diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h index 29ec5a141c..47808d8483 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides SYS2 interfaces. + */ + /* The header file is generated by make_header.py from SYS2.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ @@ -50,9 +60,11 @@ typedef struct{ uint8_t reserved3 [20]; uint32_t CLK2CNTRL; /*Clock 2 Control Register*/ uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/ - uint8_t reserved4 [44]; + uint8_t reserved4 [16]; + uint32_t HCLKCNTL; /* 0x0054 */ + uint8_t reserved5 [24]; uint32_t CLKSLIP; /*Clock Slip Register*/ - uint8_t reserved5 [120]; + uint8_t reserved6 [120]; uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/ uint32_t DIEDL_REG0; /*Die Identification Register*/ uint32_t DIEDH_REG1; /*Die Identification Register*/ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h index 5304504afc..7f14808805 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides TCR interfaces. + */ + /* The header file is generated by make_header.py from TCR.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h index 1a48848e76..710cc2e5a7 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides TCRAM interfaces. + */ + /* The header file is generated by make_header.py from TCRAM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h index d0347a4509..2d3776527d 100644 --- a/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h +++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides VIM interfaces. + */ + /* The header file is generated by make_header.py from VIM.json */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pinmux.h b/bsps/arm/tms570/include/bsp/tms570-pinmux.h index f744b92737..3224636951 100644 --- a/bsps/arm/tms570/include/bsp/tms570-pinmux.h +++ b/bsps/arm/tms570/include/bsp/tms570-pinmux.h @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief I/O Multiplexing Module (IOMM) basic support + * @brief This header file provides interfaces of the I/O Multiplexing Module + * (IOMM) support. */ /* - * Copyright (c) 2015 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2015 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,16 +18,33 @@ * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_PINMUX_H #define LIBBSP_ARM_TMS570_PINMUX_H -#ifndef ASM -#include <bsp/tms570.h> +#include <stddef.h> +#include <stdint.h> #ifdef __cplusplus extern "C" { @@ -40,10 +60,18 @@ extern "C" { * connection is not enabled in parallel to other one. * Mask is ored with pin number in such list. */ -#define TMS570_PIN_CLEAR_RQ_MASK 0x00000800 +#define TMS570_PIN_CLEAR_RQ_MASK 0x00008000 -#define TMS570_PIN_FNC_SHIFT 12 -#define TMS570_PIN_FNC_MASK 0x0000f000 +#define TMS570_PIN_FNC_SHIFT 11 +#define TMS570_PIN_FNC_MASK 0x00007800 + +/** + * @brief This constant indicates that all eight function bits associated with + * the pin shall be cleared. + * + * Use it as a special value for the pin function in TMS570_PIN_AND_FNC(). + */ +#define TMS570_PIN_FNC_CLEAR 0x10U #define TMS570_PIN_NUM_FNC_MASK 0x0000ffff @@ -52,6 +80,15 @@ extern "C" { #define TMS570_PIN_FNC_AUTO (-1) +/** + * @brief Defines the function of the pin. + * + * @param pin is the pin identifier. Use TMS570_BALL_WITH_MMR() to define the + * pin identifier. + * + * param fnc is the pin function. The pin function shall be the function bit + * index or TMS570_PIN_FNC_CLEAR. + */ #define TMS570_PIN_AND_FNC(pin, fnc) \ ((pin) | ((fnc) << TMS570_PIN_FNC_SHIFT)) @@ -61,6 +98,43 @@ extern "C" { #define TMS570_BALL_WITH_MMR(mmrx, pos) \ ((pos) | ((mmrx) << 2)) +/** + * @brief Prepares a pin configuration sequence. + * + * Use tms570_pin_config_apply() to apply pin configurations. Use + * tms570_pin_config_complete() to complete the pin configuration sequence. + */ +void tms570_pin_config_prepare(void); + +/** + * @brief Applies a pin configuration. + * + * This function can only be used if the pin configuration was prepared by + * tms570_pin_config_prepare(). + * + * @param config is the pin configuration defined by TMS570_PIN_AND_FNC() or + * TMS570_PIN_WITH_IN_ALT(). + */ +void tms570_pin_config_apply(uint32_t config); + +/** + * @brief Applies a pin configuration array. + * + * This function can only be used if the pin configuration was prepared by + * tms570_pin_config_prepare(). + * + * @param config is the pin configuration array. Calls + * tms570_pin_config_apply() for each pin configuration in the array. + * + * @param count is the element count of the pin configuration array. + */ +void tms570_pin_config_array_apply(const uint32_t *config, size_t count); + +/** + * @brief Completes a pin configuration sequence. + */ +void tms570_pin_config_complete(void); + /* Generic functions select pin to peripheral connection */ void tms570_bsp_pin_set_function(int pin_num, int pin_fnc); @@ -71,15 +145,6 @@ void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc); void tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_count); -static inline void -tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift, - int pin_num) -{ - pin_num = (pin_num & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT; - *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2); - *pin_shift = (pin_num & 0x3)*8; -} - #define TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) \ (((((pin) & TMS570_PIN_NUM_MASK) >> 2 != (reg)) || ((pin) & TMS570_PIN_CLEAR_RQ_MASK))? 0: \ 1 << ((((pin) & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT) + \ @@ -125,9 +190,6 @@ tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift, #define TMS570_PINMMR_COMA_LIST(pin_list) \ pin_list(TMS570_PINMMR_COMA_LIST_ACTION, 0) - -#endif - /** @} */ #ifdef __cplusplus diff --git a/bsps/arm/tms570/include/bsp/tms570-pins.h b/bsps/arm/tms570/include/bsp/tms570-pins.h index 32839138d0..606b7e243e 100644 --- a/bsps/arm/tms570/include/bsp/tms570-pins.h +++ b/bsps/arm/tms570/include/bsp/tms570-pins.h @@ -1,10 +1,54 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Select pin mapping according to selected chip. - * Defaults to TMS570LS3137ZWT for now. + * @brief This header file selects the pin mapping according to the selected + * chip. */ +/* + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_TMS570_PINS_H +#define LIBBSP_ARM_TMS570_PINS_H + +#include <bspopts.h> + +#if TMS570_VARIANT == 4357 +#include <bsp/tms570lc4357-pins.h> +#else #include <bsp/tms570ls3137zwt-pins.h> +#endif + +#endif /* LIBBSP_ARM_TMS570_PINS_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-pom.h b/bsps/arm/tms570/include/bsp/tms570-pom.h index 7e89ea2b96..aaf95ae8d0 100644 --- a/bsps/arm/tms570/include/bsp/tms570-pom.h +++ b/bsps/arm/tms570/include/bsp/tms570-pom.h @@ -1,20 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file + * * @ingroup RTEMSBSPsARMTMS570 - * @brief Parameter Overlay Module (POM) header file + * + * @brief This header file provides interfaces of the Parameter Overlay Module + * (POM) support. */ /* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_POM_H @@ -48,7 +70,7 @@ extern "C" { #define TMS570_POM_REGADDRMASK ((1<<23)-1) -void tms570_initialize_and_clear(void); +void tms570_pom_initialize_and_clear(void); void tms570_pom_remap(void); /** @} */ diff --git a/bsps/arm/tms570/include/bsp/tms570-rti.h b/bsps/arm/tms570/include/bsp/tms570-rti.h deleted file mode 100644 index fdfdc1578a..0000000000 --- a/bsps/arm/tms570/include/bsp/tms570-rti.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Real Time Interrupt module (RTI) header file. - */ - -/* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> - * - * Google Summer of Code 2014 at - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_RTI_H -#define LIBBSP_ARM_TMS570_RTI_H - -#ifndef ASM - -#include <stdint.h> -#include <bsp/tms570.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570-sci-driver.h b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h index 995e18ffbe..14ee762433 100644 --- a/bsps/arm/tms570/include/bsp/tms570-sci-driver.h +++ b/bsps/arm/tms570/include/bsp/tms570-sci-driver.h @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Declaration of serial's driver inner structure. + * @brief This header file provides interfaces of the SCI support. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,12 +17,26 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef TMS570_SCI_DRIVER @@ -28,7 +44,7 @@ #include <rtems/termiostypes.h> #include <rtems/irq.h> -#include <bsp/tms570-sci.h> +#include <bsp/tms570.h> #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/tms570/include/bsp/tms570-sci.h b/bsps/arm/tms570/include/bsp/tms570-sci.h deleted file mode 100644 index cc92a514cb..0000000000 --- a/bsps/arm/tms570/include/bsp/tms570-sci.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Serial Communication Interface (SCI) header file. - */ - -/* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> - * - * Google Summer of Code 2014 at - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_SCI_H -#define LIBBSP_ARM_TMS570_SCI_H - -#include <libchip/serial.h> - -#include <rtems.h> -#include <stdint.h> -#include <bsp/tms570.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/bsps/arm/tms570/include/bsp/tms570-vim.h b/bsps/arm/tms570/include/bsp/tms570-vim.h deleted file mode 100644 index 9903d31960..0000000000 --- a/bsps/arm/tms570/include/bsp/tms570-vim.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Vectored Interrupt Module (VIM) header file. - */ - -/* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> - * - * Google Summer of Code 2014 at - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_VIM_H -#define LIBBSP_ARM_TMS570_VIM_H - -#ifndef ASM -#include <rtems.h> -#include <stdint.h> -#include <bsp/tms570.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - - -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570.h b/bsps/arm/tms570/include/bsp/tms570.h index f278a93606..b5b8a176c1 100644 --- a/bsps/arm/tms570/include/bsp/tms570.h +++ b/bsps/arm/tms570/include/bsp/tms570.h @@ -1,8 +1,19 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides TMS570 interfaces. + */ + /* This file is generated by make_central_header.py */ /* Current script's version can be found at: */ /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ /* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> * * Czech Technical University in Prague @@ -78,23 +89,31 @@ #include <bsp/ti_herc/reg_sys2.h> #include <bsp/ti_herc/reg_pcr.h> +#include <bspopts.h> + #define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000) #define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200) -#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0XFFFFF600) +#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0xFFFFF600) #define TMS570_CRC (*(volatile tms570_crc_t*)0xFE000000) +#if TMS570_VARIANT == 4357 +#define TMS570_CRC2 (*(volatile tms570_crc_t*)0xFB000000) +#endif #define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00) #define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00) #define TMS570_DCAN3 (*(volatile tms570_dcan_t*)0xFFF7E000) +#if TMS570_VARIANT == 4357 +#define TMS570_DCAN4 (*(volatile tms570_dcan_t*)0xFFF7E200) +#endif #define TMS570_DCC1 (*(volatile tms570_dcc_t*)0xFFFFEC00) #define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xFFFFF400) #define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000) #define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700) -#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C) +#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0xFFF8C01C) #define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800) #define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000) #define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800) -#define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500) -#define TMS570_FLASH (*(volatile tms570_flash_t*)0XFFF87000) +#define TMS570_ESM (*(volatile tms570_esm_t*)0xFFFFF500) +#define TMS570_FLASH (*(volatile tms570_flash_t*)0xFFF87000) #define TMS570_FLEX_RAY (*(volatile tms570_flex_ray_t*)0xFFF7C800) #define TMS570_GIO (*(volatile tms570_gio_t*)0xFFF7BC00) #define TMS570_GIO_PORTA (*(volatile tms570_gio_port_t*)0xFFF7BC34) @@ -108,23 +127,36 @@ #define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400) #define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500) #define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400) -#define TMS570_IOMM (*(volatile tms570_iomm_t*)0XFFFFEA00) -#define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xFFFFEB10) +#if TMS570_VARIANT == 4357 +#define TMS570_I2C2 (*(volatile tms570_i2c_t*)0xFFF7D500) +#endif +#if TMS570_VARIANT == 4357 +#define TMS570_IOMM (*(volatile tms570_iomm_t*)0xFFFF1C00) +#else +#define TMS570_IOMM (*(volatile tms570_iomm_t*)0xFFFFEA00) +#endif +#define TMS570_PINMUX ((volatile uint32_t*)TMS570_IOMM.PINMMR) #define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400) +#if TMS570_VARIANT == 4357 +#define TMS570_LIN2 (*(volatile tms570_lin_t*)0xFFF7E600) +#endif #define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900) #define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800) #define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900) #define TMS570_PBIST (*(volatile tms570_pbist_t*)0xFFFFE400) -#define TMS570_PLL (*(volatile tms570_pll_t*)0XFFFFE100) +#define TMS570_PLL (*(volatile tms570_pll_t*)0xFFFFE100) #define TMS570_PMM (*(volatile tms570_pmm_t*)0xFFFF0000) #define TMS570_RTI (*(volatile tms570_rti_t*)0xFFFFFC00) #define TMS570_RTP (*(volatile tms570_rtp_t*)0xFFFFFA00) #define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E500) +#if TMS570_VARIANT == 4357 +#define TMS570_SCI2 (*(volatile tms570_sci_t*)0xFFF7E700) +#endif #define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800) #define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xFFFFF800) #define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xFFFFF900) -#define TMS570_VIM (*(volatile tms570_vim_t*)0XFFFFFDEC) -#define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000) +#define TMS570_VIM (*(volatile tms570_vim_t*)0xFFFFFDEC) +#define TMS570_POM (*(volatile tms570_pom_t*)0xFFA04000) #define TMS570_SPI1 (*(volatile tms570_spi_t*)0xFFF7F400) #define TMS570_SPI2 (*(volatile tms570_spi_t*)0xFFF7F600) #define TMS570_SPI3 (*(volatile tms570_spi_t*)0xFFF7F800) @@ -133,5 +165,11 @@ #define TMS570_STC (*(volatile tms570_stc_t*)0xFFFFE600) #define TMS570_SYS1 (*(volatile tms570_sys1_t*)0xFFFFFF00) #define TMS570_SYS2 (*(volatile tms570_sys2_t*)0xFFFFE100) -#define TMS570_PCR (*(volatile tms570_pcr_t*)0xFFFFE000) +#if TMS570_VARIANT == 4357 +#define TMS570_PCR1 (*(volatile tms570_pcr_t*)0xFFFF1000) +#define TMS570_PCR2 (*(volatile tms570_pcr_t*)0xFCFF1000) +#define TMS570_PCR3 (*(volatile tms570_pcr_t*)0xFFF78000) +#else +#define TMS570_PCR1 (*(volatile tms570_pcr_t*)0xFFFFE000) +#endif #endif /* LIBBSP_ARM_TMS570 */ diff --git a/bsps/arm/tms570/include/bsp/tms570_hwinit.h b/bsps/arm/tms570/include/bsp/tms570_hwinit.h index 2c84b6e5fa..2af2f3d48a 100644 --- a/bsps/arm/tms570/include/bsp/tms570_hwinit.h +++ b/bsps/arm/tms570/include/bsp/tms570_hwinit.h @@ -1,11 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides interfaces of the hardware initialization + * support. + */ + +/* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef LIBBSP_ARM_TMS570_HWINIT_H #define LIBBSP_ARM_TMS570_HWINIT_H -#define TMS570_TCRAM_START_PTR ( (void *) ( 0x08000000U ) ) -#define TMS570_TCRAM_WINDOW_END_PTR ( (void *) ( 0x08080000U ) ) +#include <bspopts.h> +#include <stdint.h> +#include <bsp/start.h> -#define TMS570_SDRAM_START_PTR ( (void *) ( 0x80000000U ) ) -#define TMS570_SDRAM_WINDOW_END_PTR ( (void *) ( 0xA0000000U ) ) +static inline bool tms570_running_from_tcram( void ) +{ + uintptr_t fncptr = (uintptr_t)bsp_start_hook_0; + return (fncptr - TMS570_MEMORY_SRAM_ORIGIN) < TMS570_MEMORY_SRAM_SIZE; +} + +static inline bool tms570_running_from_sdram( void ) +{ + uintptr_t fncptr = (uintptr_t)bsp_start_hook_0; + return (fncptr - TMS570_MEMORY_SDRAM_ORIGIN) < TMS570_MEMORY_SDRAM_SIZE; +} /* Ti TMS570 core setup implemented in assembly */ void _esmCcmErrorsClear_( void ); @@ -16,16 +69,40 @@ void _coreEnableRamEcc_( void ); void _coreDisableRamEcc_( void ); void _mpuInit_( void ); -void tms570_emif_sdram_init( void ); void tms570_memory_init( uint32_t ram ); -void tms570_system_hw_init( void ); -void tms570_pinmux_init( void ); -void tms570_pll_init( void ); void tms570_trim_lpo_init( void ); void tms570_flash_init( void ); void tms570_periph_init( void ); -void tms570_map_clock_init( void ); void tms570_system_hw_init( void ); void tms570_esm_init( void ); +/* + * The following functions that must be implemented on a per-board basis for + * any BSP variant with hardware initialization. These configure MCU + * peripherals that are specific to a particular board. + */ + +/** + * @brief Initialize the External Memory InterFace (EMIF) peripheral. + */ +void tms570_emif_sdram_init(void); + +/** + * @brief Initialize PLLs source divider/multipliers. + */ +void tms570_pll_init(void); + +/** + * @brief Initialize the tms570 Global Clock Manager (GCM) registers which + * sub-divide the input clock source (generally PLL) into the various + * peripheral clocks (VCLK1-3, etc). + */ +void tms570_map_clock_init(void); + +/** + * @brief Initialize the tms570 PINMUX peripheral. This maps signals to pin + * terminals. + */ +void tms570_pinmux_init(void); + #endif /* LIBBSP_ARM_TMS570_HWINIT_H */ diff --git a/bsps/arm/tms570/include/bsp/tms570_selftest.h b/bsps/arm/tms570/include/bsp/tms570_selftest.h index c7e01a36cd..fdad4de64c 100644 --- a/bsps/arm/tms570/include/bsp/tms570_selftest.h +++ b/bsps/arm/tms570/include/bsp/tms570_selftest.h @@ -1,26 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Definition of TMS570 selftest error codes, addresses and functions. + * @brief This header file provides TMS570 selftest error codes, addresses and + * functions. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * * Algorithms are based on Ti manuals and Ti HalCoGen generated * code available under following copyright. - */ -/* + * * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -199,6 +198,8 @@ void tms570_pbist_fail( void ); void tms570_pbist_stop( void ); +void tms570_pbist_run_and_check( uint32_t raminfoL, uint32_t algomask ); + void tms570_enable_parity( void ); void tms570_disable_parity( void ); diff --git a/bsps/arm/tms570/include/bsp/tms570_selftest_parity.h b/bsps/arm/tms570/include/bsp/tms570_selftest_parity.h index 404a414beb..db95cdb041 100644 --- a/bsps/arm/tms570/include/bsp/tms570_selftest_parity.h +++ b/bsps/arm/tms570/include/bsp/tms570_selftest_parity.h @@ -1,21 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Check of module parity based protection logic to work. + * @brief This header file provides interfaces of the parity selftest support. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_SELFTEST_PARITY_H @@ -81,13 +101,13 @@ extern const tms570_selftest_par_desc_t tms570_selftest_par_can3_desc; extern const tms570_selftest_par_desc_t tms570_selftest_par_vim_desc; -const tms570_selftest_par_desc_t +extern const tms570_selftest_par_desc_t tms570_selftest_par_dma_desc; -const tms570_selftest_par_desc_t +extern const tms570_selftest_par_desc_t tms570_selftest_par_spi1_desc; -const tms570_selftest_par_desc_t +extern const tms570_selftest_par_desc_t tms570_selftest_par_spi3_desc; -const tms570_selftest_par_desc_t +extern const tms570_selftest_par_desc_t tms570_selftest_par_spi5_desc; extern const tms570_selftest_par_desc_t *const diff --git a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h index a7912d1547..a78c9222f2 100644 --- a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h +++ b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h @@ -1,22 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Specification of individual pins mapping to the package + * @brief This header file provides pin mappings for the TMS570LC4357. */ /* - * Copyright (c) 2015-2017 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2015-2017 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H @@ -909,6 +928,11 @@ TMS570_PIN_AND_FNC(TMS570_BALL_B11, 5), \ TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_eQEP2S, 1)) +/// (TM) TODO: is this correct? LS3137ZWT uses TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0) +/// Per the schematic, this pin (called MII_RX_DV / RX_DV) attaches to pad B11 and can select +/// between MII and RMII mode for the PHY. A pin like this is required for the lwip tms570 rtems port +#define TMS570_MMR_SELECT_GMII_SEL TMS570_BALL_B11_MII_RX_DV + #define TMS570_BALL_D8 TMS570_BALL_WITH_MMR(34, 3) #define TMS570_BALL_D8_HET2_01 TMS570_PIN_WITH_IN_ALT( \ TMS570_PIN_AND_FNC(TMS570_BALL_D8, 0), \ @@ -972,10 +996,14 @@ TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 0)) #define TMS570_BALL_N3_MIBSPI2NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N3, 4) +#define TMS570_MMR_SELECT_MII_MODE \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(160, 3), TMS570_PIN_FNC_CLEAR) +#define TMS570_MMR_SELECT_RMII_MODE \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(160, 3), 0) + /* Default pinmux select */ -#define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ - per_pin_action(common_arg, TMS570_BALL_N19_AD1EVT) \ +#define TMS570LC4357_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ per_pin_action(common_arg, TMS570_BALL_D4_EMIF_ADDR_00) \ per_pin_action(common_arg, TMS570_BALL_D5_EMIF_ADDR_01) \ per_pin_action(common_arg, TMS570_BALL_C4_EMIF_ADDR_06) \ @@ -1003,30 +1031,30 @@ per_pin_action(common_arg, TMS570_BALL_R3_EMIF_nRAS) \ per_pin_action(common_arg, TMS570_BALL_P3_EMIF_nWAIT) \ per_pin_action(common_arg, TMS570_BALL_D17_EMIF_nWE) \ - per_pin_action(common_arg, TMS570_BALL_E9_ETMDATA_08) \ - per_pin_action(common_arg, TMS570_BALL_E8_ETMDATA_09) \ - per_pin_action(common_arg, TMS570_BALL_E7_ETMDATA_10) \ - per_pin_action(common_arg, TMS570_BALL_E6_ETMDATA_11) \ - per_pin_action(common_arg, TMS570_BALL_E13_ETMDATA_12) \ - per_pin_action(common_arg, TMS570_BALL_E12_ETMDATA_13) \ - per_pin_action(common_arg, TMS570_BALL_E11_ETMDATA_14) \ - per_pin_action(common_arg, TMS570_BALL_E10_ETMDATA_15) \ - per_pin_action(common_arg, TMS570_BALL_K15_ETMDATA_16) \ - per_pin_action(common_arg, TMS570_BALL_L15_ETMDATA_17) \ - per_pin_action(common_arg, TMS570_BALL_M15_ETMDATA_18) \ - per_pin_action(common_arg, TMS570_BALL_N15_ETMDATA_19) \ - per_pin_action(common_arg, TMS570_BALL_E5_ETMDATA_20) \ - per_pin_action(common_arg, TMS570_BALL_F5_ETMDATA_21) \ - per_pin_action(common_arg, TMS570_BALL_G5_ETMDATA_22) \ - per_pin_action(common_arg, TMS570_BALL_K5_ETMDATA_23) \ - per_pin_action(common_arg, TMS570_BALL_L5_ETMDATA_24) \ - per_pin_action(common_arg, TMS570_BALL_M5_ETMDATA_25) \ - per_pin_action(common_arg, TMS570_BALL_N5_ETMDATA_26) \ - per_pin_action(common_arg, TMS570_BALL_P5_ETMDATA_27) \ - per_pin_action(common_arg, TMS570_BALL_R5_ETMDATA_28) \ - per_pin_action(common_arg, TMS570_BALL_R6_ETMDATA_29) \ - per_pin_action(common_arg, TMS570_BALL_R7_ETMDATA_30) \ - per_pin_action(common_arg, TMS570_BALL_R8_ETMDATA_31) \ + per_pin_action(common_arg, TMS570_BALL_E9_EMIF_ADDR_05) \ + per_pin_action(common_arg, TMS570_BALL_E8_EMIF_ADDR_04) \ + per_pin_action(common_arg, TMS570_BALL_E7_EMIF_ADDR_03) \ + per_pin_action(common_arg, TMS570_BALL_E6_EMIF_ADDR_02) \ + per_pin_action(common_arg, TMS570_BALL_E13_EMIF_BA_0) \ + per_pin_action(common_arg, TMS570_BALL_E12_EMIF_nOE) \ + per_pin_action(common_arg, TMS570_BALL_E11_EMIF_nDQM_1) \ + per_pin_action(common_arg, TMS570_BALL_E10_EMIF_nDQM_0) \ + per_pin_action(common_arg, TMS570_BALL_K15_EMIF_DATA_00) \ + per_pin_action(common_arg, TMS570_BALL_L15_EMIF_DATA_01) \ + per_pin_action(common_arg, TMS570_BALL_M15_EMIF_DATA_02) \ + per_pin_action(common_arg, TMS570_BALL_N15_EMIF_DATA_03) \ + per_pin_action(common_arg, TMS570_BALL_E5_EMIF_DATA_04) \ + per_pin_action(common_arg, TMS570_BALL_F5_EMIF_DATA_05) \ + per_pin_action(common_arg, TMS570_BALL_G5_EMIF_DATA_06) \ + per_pin_action(common_arg, TMS570_BALL_K5_EMIF_DATA_07) \ + per_pin_action(common_arg, TMS570_BALL_L5_EMIF_DATA_08) \ + per_pin_action(common_arg, TMS570_BALL_M5_EMIF_DATA_09) \ + per_pin_action(common_arg, TMS570_BALL_N5_EMIF_DATA_10) \ + per_pin_action(common_arg, TMS570_BALL_P5_EMIF_DATA_11) \ + per_pin_action(common_arg, TMS570_BALL_R5_EMIF_DATA_12) \ + per_pin_action(common_arg, TMS570_BALL_R6_EMIF_DATA_13) \ + per_pin_action(common_arg, TMS570_BALL_R7_EMIF_DATA_14) \ + per_pin_action(common_arg, TMS570_BALL_R8_EMIF_DATA_15) \ per_pin_action(common_arg, TMS570_BALL_R9_ETMTRACECLKIN) \ per_pin_action(common_arg, TMS570_BALL_R10_ETMTRACECLKOUT) \ per_pin_action(common_arg, TMS570_BALL_R11_ETMTRACECTL) \ @@ -1108,7 +1136,27 @@ per_pin_action(common_arg, TMS570_BALL_U7_MII_TX_CLK) \ per_pin_action(common_arg, TMS570_BALL_E2_HET2_03) \ per_pin_action(common_arg, TMS570_BALL_N3_HET2_07) \ + per_pin_action(common_arg, TMS570_BALL_K3_EMIF_CLK) \ + per_pin_action(common_arg, TMS570_BALL_N19_MII_RX_ER) \ + per_pin_action(common_arg, TMS570_BALL_F3_MII_COL) \ + per_pin_action(common_arg, TMS570_BALL_E18_MII_TXD_3) \ + per_pin_action(common_arg, TMS570_BALL_R2_MII_TXD_2) \ + per_pin_action(common_arg, TMS570_BALL_J19_MII_TXD_1) \ + per_pin_action(common_arg, TMS570_BALL_J18_MII_TXD_0) \ + per_pin_action(common_arg, TMS570_BALL_H19_MII_TXEN) \ + per_pin_action(common_arg, TMS570_BALL_D19_MII_TX_CLK) \ + per_pin_action(common_arg, TMS570_BALL_B4_MII_CRS) \ + per_pin_action(common_arg, TMS570_BALL_K19_MII_RXCLK) \ + per_pin_action(common_arg, TMS570_BALL_H18_MII_RXD_3) \ + per_pin_action(common_arg, TMS570_BALL_G19_MII_RXD_2) \ + per_pin_action(common_arg, TMS570_BALL_A14_MII_RXD_1) \ + per_pin_action(common_arg, TMS570_BALL_P1_MII_RXD_0) \ + per_pin_action(common_arg, TMS570_BALL_B11_MII_RX_DV) \ + per_pin_action(common_arg, TMS570_BALL_G3_MDIO) \ + per_pin_action(common_arg, TMS570_BALL_V5_MDCLK) /* End of default PINMMR list */ +// Note EMIF Clock enable (EMIF_CKE) on Ball L3 has no alternate functions and is enabled by default + #endif /*LIBBSP_ARM_TMS570_TMS570LC4357_PINS_H*/ diff --git a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h index 089f0d4248..2f1895569b 100644 --- a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h +++ b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h @@ -1,22 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Specification of individual pins mapping to the package + * @brief This header file provides pin mappings for the TMS570LS3137ZWT. */ /* - * Copyright (c) 2015 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2015 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_TMS570_TMS570LS3137ZWT_PINS_H @@ -555,7 +574,10 @@ #define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(29, 2) #define TMS570_BALL_F2_GIOB_2 TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0) -#define TMS570_MMR_SELECT_GMII_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0) +#define TMS570_MMR_SELECT_MII_MODE \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0) +#define TMS570_MMR_SELECT_RMII_MODE \ + TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), TMS570_PIN_FNC_CLEAR) #define TMS570_MMR_SELECT_ADC_TRG1 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 0) #define TMS570_MMR_SELECT_ADC_TRG2 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 0), 1) diff --git a/bsps/arm/tms570/include/tm27.h b/bsps/arm/tms570/include/tm27.h index 0dfa7bf628..a8ca08a0dd 100644 --- a/bsps/arm/tms570/include/tm27.h +++ b/bsps/arm/tms570/include/tm27.h @@ -1 +1,128 @@ -#include <rtems/tm27-default.h> +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This header file provides a TM27 support implementation. + */ + +/* + * Copyright (c) 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <rtems.h> + +#include <bsp/irq.h> +#include <bsp/tms570.h> +#include <rtems/score/armv4.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define TM27_INTERRUPT_VECTOR_DEFAULT TMS570_IRQ_TIMER_3 + +#define TM27_INTERRUPT_VECTOR_ALTERNATIVE TMS570_IRQ_TIMER_1 + +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) +{ + static rtems_interrupt_entry entry_2; + static rtems_interrupt_entry entry_3; + + TMS570_RTI.CNT[1].CPUCx = 1; + TMS570_RTI.CNT[1].UCx = 0; + TMS570_RTI.CNT[1].FRCx = 0; + TMS570_RTI.CMP[1].COMPx = 1; + TMS570_RTI.CMP[1].UDCPx = 1; + TMS570_RTI.CMP[2].COMPx = 1; + TMS570_RTI.CMP[2].UDCPx = 1; + TMS570_RTI.CMP[3].COMPx = 1; + TMS570_RTI.CMP[3].UDCPx = 1; + TMS570_RTI.COMPCTRL |= TMS570_RTI_COMPCTRL_COMPSEL1 | + TMS570_RTI_COMPCTRL_COMPSEL2 | + TMS570_RTI_COMPCTRL_COMPSEL3; + TMS570_RTI.GCTRL |= TMS570_RTI_GCTRL_CNT1EN; + + rtems_interrupt_entry_initialize( + &entry_2, + handler, + NULL, + "tm27" + ); + (void) rtems_interrupt_entry_install( + TMS570_IRQ_TIMER_2, + RTEMS_INTERRUPT_SHARED, + &entry_2 + ); + + rtems_interrupt_entry_initialize( + &entry_3, + handler, + NULL, + "tm27" + ); + (void) rtems_interrupt_entry_install( + TMS570_IRQ_TIMER_3, + RTEMS_INTERRUPT_SHARED, + &entry_3 + ); +} + +static inline void Cause_tm27_intr(void) +{ + TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT3; +} + +static inline void Clear_tm27_intr(void) +{ + TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEARINT2 | + TMS570_RTI_CLEARINTENA_CLEARINT3; +} + +static inline void Lower_tm27_intr(void) +{ + TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT2; + (void) _ARMV4_Status_irq_enable(); +} + +static inline rtems_status_code _TM27_Raise_alternative(void) +{ + TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT1; + return RTEMS_SUCCESSFUL; +} + +static inline rtems_status_code _TM27_Clear_alternative(void) +{ + TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEARINT1; + return RTEMS_SUCCESSFUL; +} + +#endif /* __tm27_h */ diff --git a/bsps/arm/tms570/irq/irq.c b/bsps/arm/tms570/irq/irq.c index 437c1ab27c..9a80e0e3d2 100644 --- a/bsps/arm/tms570/irq/irq.c +++ b/bsps/arm/tms570/irq/irq.c @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 interrupt support functions definitions. + * @brief This source file contains the interrupt controller support + * implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,61 +18,142 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> #include <bsp/irq-generic.h> -#include <bsp/tms570-vim.h> +#include <bsp/tms570.h> #include <bsp/irq.h> #include <rtems/score/armv4.h> -unsigned int priorityTable[BSP_INTERRUPT_VECTOR_COUNT]; +#define VIM_CHANCTRL_COUNT 24 +#define VIM_CHANMAP_MASK UINT32_C(0x7f) +#define VIM_CHANMAP_SHIFT(i) (24 - (8 * (i))) +#define VIM_REQ_REG(vector) ((vector) >> 5) +#define VIM_REQ_BIT(vector) (UINT32_C(1) << ((vector) & 0x1f)) -/** - * @brief Set priority of the interrupt vector. - * - * This function is here because of compability. It should set - * priority of the interrupt vector. - * @warning It does not set any priority at HW layer. It is nearly imposible to - * @warning set priority of the interrupt on TMS570 in a nice way. - * @param[in] vector vector of isr - * @param[in] priority new priority assigned to the vector - * @return Void - */ -void tms570_irq_set_priority( +static void vim_set_channel_request(uint32_t channel, uint32_t request) +{ + uint32_t chanctrl; + int shift; + + chanctrl = TMS570_VIM.CHANCTRL[channel / 4]; + shift = VIM_CHANMAP_SHIFT(channel % 4); + chanctrl &= ~(VIM_CHANMAP_MASK << shift); + chanctrl |= request << shift; + TMS570_VIM.CHANCTRL[channel / 4] = chanctrl; +} + +rtems_status_code tms570_irq_set_priority( rtems_vector_number vector, - unsigned priority + uint32_t priority ) { - if ( bsp_interrupt_is_valid_vector(vector) ) { - priorityTable[vector] = priority; + rtems_interrupt_level level; + uint32_t current_channel; + uint32_t chanctrl; + size_t i; + size_t j; + + if (!bsp_interrupt_is_valid_vector(vector)) { + return RTEMS_INVALID_ID; + } + + if (priority < 2) { + return RTEMS_INVALID_PRIORITY; + } + + if (priority >= BSP_INTERRUPT_VECTOR_COUNT) { + return RTEMS_INVALID_PRIORITY; + } + + rtems_interrupt_disable(level); + current_channel = TMS570_VIM.CHANCTRL[priority / 4]; + current_channel >>= VIM_CHANMAP_SHIFT(priority % 4); + current_channel &= VIM_CHANMAP_MASK; + + for (i = 0; i < VIM_CHANCTRL_COUNT; ++i) { + chanctrl = TMS570_VIM.CHANCTRL[i]; + + for (j = 0; j < 4; ++j) { + uint32_t channel_vector; + + channel_vector = (chanctrl >> VIM_CHANMAP_SHIFT(j)) & VIM_CHANMAP_MASK; + + if (channel_vector == vector) { + vim_set_channel_request(i * 4 + j, current_channel); + goto set_my_request; + } + } } + +set_my_request: + + vim_set_channel_request(priority, vector); + rtems_interrupt_enable(level); + return RTEMS_SUCCESSFUL; } -/** - * @brief Gets priority of the interrupt vector. - * - * This function is here because of compability. It returns priority - * of the isr vector last set by tms570_irq_set_priority function. - * - * @warning It does not return any real priority of the HW layer. - * @param[in] vector vector of isr - * @retval 0 vector is invalid. - * @retval priority priority of the interrupt - */ -unsigned tms570_irq_get_priority( - rtems_vector_number vector +rtems_status_code tms570_irq_get_priority( + rtems_vector_number vector, + unsigned *priority ) { - if ( bsp_interrupt_is_valid_vector(vector) ) { - return priorityTable[vector]; - } - return 0; + rtems_interrupt_level level; + size_t i; + size_t j; + + if (priority == NULL) { + return RTEMS_INVALID_ADDRESS; + } + + if (!bsp_interrupt_is_valid_vector(vector)) { + return RTEMS_INVALID_ID; + } + + rtems_interrupt_disable(level); + + for (i = 0; i < VIM_CHANCTRL_COUNT; ++i) { + uint32_t chanctrl; + + chanctrl = TMS570_VIM.CHANCTRL[i]; + + for (j = 0; j < 4; ++j) { + uint32_t channel_vector; + + channel_vector = (chanctrl >> VIM_CHANMAP_SHIFT(j)) & VIM_CHANMAP_MASK; + + if (channel_vector == vector) { + rtems_interrupt_enable(level); + *priority = i * 4 + j; + return RTEMS_SUCCESSFUL; + } + } + } + + rtems_interrupt_enable(level); + *priority = UINT32_MAX; + return RTEMS_NOT_DEFINED; } /** @@ -82,9 +166,23 @@ unsigned tms570_irq_get_priority( */ void bsp_interrupt_dispatch(void) { - rtems_vector_number vector = TMS570_VIM.IRQINDEX-1; + while (true) { + uint32_t irqindex; + + irqindex = TMS570_VIM.IRQINDEX; + + if (irqindex == 0) { + return; + } + + bsp_interrupt_handler_dispatch(irqindex - 1); + } +} - bsp_interrupt_handler_dispatch(vector); +static bool can_disable(rtems_vector_number vector) +{ + /* INT_REQ0 and INT_REQ1 are always enabled as FIQ/NMI */ + return vector >= 2; } /** @@ -101,6 +199,20 @@ rtems_status_code bsp_interrupt_get_attributes( rtems_interrupt_attributes *attributes ) { + bool can_disable_vector; + + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); + bsp_interrupt_assert(attributes != NULL); + + can_disable_vector = can_disable(vector); + attributes->is_maskable = can_disable_vector; + attributes->can_enable = true; + attributes->maybe_enable = true; + attributes->can_disable = can_disable_vector; + attributes->maybe_disable = can_disable_vector; + attributes->can_get_affinity = true; + attributes->can_set_affinity = true; + return RTEMS_SUCCESSFUL; } @@ -109,10 +221,14 @@ rtems_status_code bsp_interrupt_is_pending( bool *pending ) { + uint32_t intreq; + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(pending != NULL); - *pending = false; - return RTEMS_UNSATISFIED; + + intreq = TMS570_VIM.INTREQ[VIM_REQ_REG(vector)]; + *pending = (intreq & VIM_REQ_BIT(vector)) != 0; + return RTEMS_SUCCESSFUL; } rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) @@ -132,10 +248,14 @@ rtems_status_code bsp_interrupt_vector_is_enabled( bool *enabled ) { + uint32_t reqen; + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(enabled != NULL); - *enabled = false; - return RTEMS_UNSATISFIED; + + reqen = TMS570_VIM.REQENASET[VIM_REQ_REG(vector)]; + *enabled = (reqen & VIM_REQ_BIT(vector)) != 0; + return RTEMS_SUCCESSFUL; } rtems_status_code bsp_interrupt_vector_enable( @@ -143,7 +263,7 @@ rtems_status_code bsp_interrupt_vector_enable( ) { bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - TMS570_VIM.REQENASET[vector >> 5] = 1 << (vector & 0x1f); + TMS570_VIM.REQENASET[VIM_REQ_REG(vector)] = VIM_REQ_BIT(vector); return RTEMS_SUCCESSFUL; } @@ -160,8 +280,12 @@ rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ) { + if (!can_disable(vector)) { + return RTEMS_UNSATISFIED; + } + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - TMS570_VIM.REQENACLR[vector >> 5] = 1 << (vector & 0x1f); + TMS570_VIM.REQENACLR[VIM_REQ_REG(vector)] = VIM_REQ_BIT(vector); return RTEMS_SUCCESSFUL; } @@ -186,7 +310,7 @@ void bsp_interrupt_facility_initialize(void) TMS570_VIM.REQENACLR[i] = 0xffffffff; } /* Map default events on interrupt vectors */ - for ( i = 0; i < 24; i += 1, value += 0x04040404) { + for ( i = 0; i < VIM_CHANCTRL_COUNT; i += 1, value += 0x04040404) { TMS570_VIM.CHANCTRL[i] = value; } /* Set all vectors as IRQ (not FIR) */ diff --git a/bsps/arm/tms570/start/bsp_specs b/bsps/arm/tms570/start/bsp_specs deleted file mode 100644 index e69de29bb2..0000000000 --- a/bsps/arm/tms570/start/bsp_specs +++ /dev/null diff --git a/bsps/arm/tms570/start/bspreset.c b/bsps/arm/tms570/start/bspreset.c index daca621c86..67cf96c67c 100644 --- a/bsps/arm/tms570/start/bspreset.c +++ b/bsps/arm/tms570/start/bspreset.c @@ -1,25 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Reset code. + * @brief This source file contains the bsp_reset() implementation. */ /* - * Copyright (c) 2015 Taller Technologies. + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic * - * @author Martin Galvan <martin.galvan@tallertechnologies.com> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/bootcard.h> #include <bsp/tms570.h> -#include <bsp/start.h> +#include <bsp/tms570-pom.h> static void handle_esm_errors(uint32_t esm_irq_channel) { @@ -35,7 +57,14 @@ static void handle_esm_errors(uint32_t esm_irq_channel) void bsp_reset(void) { - uint32_t esm_irq_channel = TMS570_ESM.IOFFHR - 1; + rtems_interrupt_level level; + uint32_t esm_irq_channel; + + rtems_interrupt_disable(level); + (void) level; + + tms570_pom_initialize_and_clear(); + esm_irq_channel = TMS570_ESM.IOFFHR - 1; if (esm_irq_channel) { handle_esm_errors(esm_irq_channel); diff --git a/bsps/arm/tms570/start/bsprestart.c b/bsps/arm/tms570/start/bsprestart.c new file mode 100644 index 0000000000..c989d8fc77 --- /dev/null +++ b/bsps/arm/tms570/start/bsprestart.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (c) 2017 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> + +void bsp_restart( const void *addr ) +{ + rtems_interrupt_level level; + void(*start)(void) = (void(*)(void))(addr); + + rtems_interrupt_disable(level); + (void)level; + rtems_cache_disable_instruction(); + rtems_cache_disable_data(); + + start(); + RTEMS_UNREACHABLE(); +} diff --git a/bsps/arm/tms570/start/bspstart.c b/bsps/arm/tms570/start/bspstart.c index 25ea4e3a17..60ce5345a9 100644 --- a/bsps/arm/tms570/start/bspstart.c +++ b/bsps/arm/tms570/start/bspstart.c @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Startup code. + * @brief This source file contains the bsp_start() implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,27 +17,39 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/tms570-pom.h> #include <bsp/irq-generic.h> -#include <bsp/start.h> #include <bsp/bootcard.h> #include <bsp/linker-symbols.h> -#include <rtems/endian.h> void bsp_start( void ) { void *need_remap_ptr; unsigned int need_remap_int; - tms570_initialize_and_clear(); + tms570_pom_initialize_and_clear(); /* * If RTEMS image does not start at address 0x00000000 diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c b/bsps/arm/tms570/start/bspstarthooks-hwinit.c index 660c87f08d..6407cc4a45 100644 --- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c +++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c @@ -1,3 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the bsp_start_hook_0() implementation. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #include <stdint.h> #include <bsp.h> #include <bsp/start.h> @@ -6,29 +47,38 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_selftest_parity.h> #include <bsp/tms570_hwinit.h> +#include <bsp/ti_herc/errata_SSWF021_45.h> -void bsp_start_hook_0_done( void ); +#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */ -static inline -int tms570_running_from_tcram( void ) +/* Use assembly code to avoid using the stack */ +__attribute__((__naked__)) void bsp_start_hook_0( void ) { - void *fncptr = (void*)bsp_start_hook_0; - return ( fncptr >= (void*)TMS570_TCRAM_START_PTR ) && - ( fncptr < (void*)TMS570_TCRAM_WINDOW_END_PTR ); -} + __asm__ volatile ( + /* Check if we run in SRAM */ + "ldr r0, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_ORIGIN ) "\n" + "ldr r1, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_SIZE ) "\n" + "sub r0, lr, r0\n" + "cmp r1, r0\n" + "blt 1f\n" -static inline -int tms570_running_from_sdram( void ) -{ - void *fncptr = (void*)bsp_start_hook_0; - return ( ( (void*)fncptr >= (void*)TMS570_SDRAM_START_PTR ) && - ( (void*)fncptr < (void*)TMS570_SDRAM_WINDOW_END_PTR ) ); -} + /* + * Initialize the SRAM if we are not running in SRAM. While we are called, + * non-volatile register r7 is not used by start.S. + */ + "movs r0, #0x1\n" + "mov r7, lr\n" + "bl tms570_memory_init\n" + "mov lr, r7\n" -#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */ + /* Jump to the high level start hook */ + "1: b tms570_start_hook_0\n" + ); +} -BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) +static RTEMS_USED void tms570_start_hook_0( void ) { +#if TMS570_VARIANT == 3137 /* * Work Around for Errata DEVICE#140: ( Only on Rev A silicon) * @@ -40,6 +90,15 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) if ( TMS570_SYS1.DEVID == 0x802AAD05U ) { _esmCcmErrorsClear_(); } +#endif + +#if TMS570_VARIANT == 4357 + uint32_t pll_result; + + do { + pll_result = _errata_SSWF021_45_both_plls(10); + } while (pll_result != 0 && pll_result != 4); +#endif /* Enable CPU Event Export */ /* This allows the CPU to signal any single-bit or double-bit errors detected @@ -47,58 +106,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) */ _coreEnableEventBusExport_(); +#if TMS570_VARIANT == 3137 /* Workaround for Errata CORTEXR4 66 */ _errata_CORTEXR4_66_(); /* Workaround for Errata CORTEXR4 57 */ _errata_CORTEXR4_57_(); - - /* check for power-on reset condition */ - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_PORST ) != 0U ) { - /* clear all reset status flags */ - TMS570_SYS1.SYSESR = 0xFFFFU; - - /* continue with normal start-up sequence */ - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_OSCRST ) != 0U ) { - /* Reset caused due to oscillator failure. - Add user code here to handle oscillator failure */ - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_WDRST ) != 0U ) { - /* Reset caused due - * 1) windowed watchdog violation - Add user code here to handle watchdog violation. - * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS - */ - /* Check the WatchDog Status register */ - if ( TMS570_RTI.WDSTATUS != 0U ) { - /* Add user code here to handle watchdog violation. */ - /* Clear the Watchdog reset flag in Exception Status register */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; - } else { - /* Clear the ICEPICK reset flag in Exception Status register */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; - } - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_CPURST ) != 0U ) { - /* Reset caused due to CPU reset. - CPU reset can be caused by CPU self-test completion, or - by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ - - /* clear all reset status flags */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_CPURST; - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_SWRST ) != 0U ) { - /* Reset caused due to software reset. - Add user code to handle software reset. */ - } else { - /* Reset caused by nRST being driven low externally. - Add user code to handle external reset. */ - } +#endif /* * Check if there were ESM group3 errors during power-up. @@ -113,8 +127,20 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ +#if TMS570_VARIANT == 4357 + /* + * During code-loading/debug-resets SR[2][4] may get set (indicates double + * ECC error in internal RAM) ignore for now as its resolved with ESM + * init/reset below. + */ + if ((TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_DBGRST) == 0) { + for (;; ) { + } /* Wait */ + } +#else for (;; ) { } /* Wait */ +#endif } /* Initialize System - Clock, Flash settings with Efuse self check */ @@ -133,47 +159,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) tms570_pbist_self_check(); /* Run PBIST on STC ROM */ - tms570_pbist_run( (uint32_t) STC_ROM_PBIST_RAM_GROUP, + tms570_pbist_run_and_check( (uint32_t) STC_ROM_PBIST_RAM_GROUP, ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); - /* Wait for PBIST for STC ROM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if PBIST on STC ROM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* PBIST and STC ROM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - /* Run PBIST on PBIST ROM */ - tms570_pbist_run( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP, + tms570_pbist_run_and_check( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP, ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); - /* Wait for PBIST for PBIST ROM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if PBIST ROM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* PBIST and STC ROM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - if ( !tms570_running_from_tcram() ) { /* * The next sequence tests TCRAM, main TMS570 system operation RAM area. @@ -201,35 +193,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the * device datasheet. */ - tms570_pbist_run( 0x08300020U, /* ESRAM Single Port PBIST */ + tms570_pbist_run_and_check( 0x08300020U, /* ESRAM Single Port PBIST */ (uint32_t) PBIST_March13N_SP ); - /* Wait for PBIST for CPU RAM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if CPU RAM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* CPU RAM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - - /* - * Initialize CPU RAM. - * This function uses the system module's hardware for auto-initialization of memories and their - * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. - * Hence the value 0x1 passed to the function. - * This function will initialize the entire CPU RAM and the corresponding ECC locations. - */ - tms570_memory_init( 0x1U ); - /* * Enable ECC checking for TCRAM accesses. * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. @@ -263,6 +229,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) if ( !tms570_running_from_tcram() ) { +#if TMS570_VARIANT == 3137 /* Test the CPU ECC mechanism for RAM accesses. * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error @@ -271,6 +238,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) * following the one that caused the abort. */ tms570_check_tcram_ecc(); +#endif /* Wait for PBIST for CPU RAM to be completed */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ @@ -318,17 +286,18 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers. Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. */ - tms570_memory_init( (uint32_t) ( (uint32_t) 1U << 1U ) | /* DMA RAM */ - (uint32_t) ( (uint32_t) 1U << 2U ) | /* VIM RAM */ - (uint32_t) ( (uint32_t) 1U << 5U ) | /* CAN1 RAM */ - (uint32_t) ( (uint32_t) 1U << 6U ) | /* CAN2 RAM */ - (uint32_t) ( (uint32_t) 1U << 10U ) | /* CAN3 RAM */ - (uint32_t) ( (uint32_t) 1U << 8U ) | /* ADC1 RAM */ - (uint32_t) ( (uint32_t) 1U << 14U ) | /* ADC2 RAM */ - (uint32_t) ( (uint32_t) 1U << 3U ) | /* HET1 RAM */ - (uint32_t) ( (uint32_t) 1U << 4U ) | /* HTU1 RAM */ - (uint32_t) ( (uint32_t) 1U << 15U ) | /* HET2 RAM */ - (uint32_t) ( (uint32_t) 1U << 16U ) /* HTU2 RAM */ + tms570_memory_init( + ( UINT32_C(1) << 1 ) | /* DMA RAM */ + ( UINT32_C(1) << 2 ) | /* VIM RAM */ + ( UINT32_C(1) << 5 ) | /* CAN1 RAM */ + ( UINT32_C(1) << 6 ) | /* CAN2 RAM */ + ( UINT32_C(1) << 10 ) | /* CAN3 RAM */ + ( UINT32_C(1) << 8 ) | /* ADC1 RAM */ + ( UINT32_C(1) << 14 ) | /* ADC2 RAM */ + ( UINT32_C(1) << 3 ) | /* HET1 RAM */ + ( UINT32_C(1) << 4 ) | /* HTU1 RAM */ + ( UINT32_C(1) << 15 ) | /* HET2 RAM */ + ( UINT32_C(1) << 16 ) /* HTU2 RAM */ ); /* Disable parity */ @@ -366,6 +335,11 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /* Configure system response to error conditions signaled to the ESM group1 */ tms570_esm_init(); + tms570_emif_sdram_init(); + + /* Configures and enables the ARM-core Memory Protection Unit (MPU) */ + _mpuInit_(); + #if 1 /* * Do not depend on link register to be restored to @@ -376,26 +350,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) #endif } -BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) -{ - /* At this point we can use objects outside the .start section */ -#if 0 - /* Do not run attempt to initialize MPU when code is running from SDRAM */ - if ( !tms570_running_from_sdram() ) { - /* - * MPU background areas setting has to be overlaid - * if execution of code is required from external memory/SDRAM. - * This region is non executable by default. - */ - _mpuInit_(); - } -#endif - tms570_emif_sdram_init(); - - bsp_start_copy_sections(); - bsp_start_clear_bss(); -} - /* * Chip specific list of peripherals which should be tested * for functional RAM parity reporting diff --git a/bsps/arm/tms570/start/bspstarthooks.c b/bsps/arm/tms570/start/bspstarthooks.c index 55a50ca65b..8dc7fdfdf8 100644 --- a/bsps/arm/tms570/start/bspstarthooks.c +++ b/bsps/arm/tms570/start/bspstarthooks.c @@ -1,14 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief First configurations and initializations to the correct - * functionality of the board. + * @brief This source file contains the bsp_start_hook_1(0 implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -16,26 +17,57 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/start.h> - -BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) -{ - ; -} +#include <libcpu/arm-cp15.h> BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) { - bsp_start_copy_sections(); + uint32_t ctrl; + size_t size; + + ctrl = arm_cp15_get_control(); + + if ( ( ctrl & ARM_CP15_CTRL_I ) == 0 ) { + rtems_cache_invalidate_entire_instruction(); + ctrl |= ARM_CP15_CTRL_I; + arm_cp15_set_control(ctrl); + } + + if ( ( ctrl & ARM_CP15_CTRL_C ) == 0 ) { + rtems_cache_invalidate_entire_data(); + ctrl |= ARM_CP15_CTRL_C; + arm_cp15_set_control(ctrl); + } + + bsp_start_copy_sections_compact(); bsp_start_clear_bss(); - /* At this point we can use objects outside the .start section */ + size =(size_t) bsp_section_fast_text_size; + RTEMS_OBFUSCATE_VARIABLE( size ); + + if ( size != 0 ) { + rtems_cache_flush_multiple_data_lines( bsp_section_fast_text_begin, size ); + } } diff --git a/bsps/arm/tms570/start/errata_SSWF021_45.c b/bsps/arm/tms570/start/errata_SSWF021_45.c new file mode 100755 index 0000000000..1591e64798 --- /dev/null +++ b/bsps/arm/tms570/start/errata_SSWF021_45.c @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains errata SSWF021#45 workaround + * implementation. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include <bsp/ti_herc/errata_SSWF021_45.h> +#include <bsp/tms570.h> + +#define SYS_CLKSRC_PLL1 0x00000002U +#define SYS_CLKSRC_PLL2 0x00000040U +#define SYS_CLKCNTRL_PENA 0x00000100U +#define ESM_SR1_PLL1SLIP 0x400U +#define ESM_SR4_PLL2SLIP 0x400U +#define PLL1 0x08 +#define PLL2 0x80 +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +static uint32_t check_frequency(uint32_t cnt1_clksrc); +static uint32_t disable_plls(uint32_t plls); + +/** @fn uint32_t _errata_SSWF021_45_both_plls(uint32_t count) + * @brief This handles the errata for PLL1 and PLL2. This function is called + * in device startup + * + * @param[in] count : Number of retries until both PLLs are locked + * successfully Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_both_plls(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + TMS570_SYS1.PLLCTL1 = 0x20001A00U; + TMS570_SYS1.PLLCTL2 = 0x3FC0723DU; + TMS570_SYS2.PLLCTL3 = 0x20001A00U; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while ((((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && + ((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) == 0U)) || + (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && + ((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) == 0U))) { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if (((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 1U; + } else { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + /* If PLL2 valid, check the frequency */ + if (((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 2U; + } else { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t _errata_SSWF021_45_pll1(uint32_t count) + * @brief This handles the errata for PLL1. This function is called in device + * startup + * + * @param[in] count : Number of retries until both PLL1 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_pll1(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + TMS570_SYS1.PLLCTL1 = 0x20001A00U; + TMS570_SYS1.PLLCTL2 = 0x3FC0723DU; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && + ((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) == 0U)) { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if (((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 1U; + } else { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t _errata_SSWF021_45_pll2(uint32_t count) + * @brief This handles the errata for PLL2. This function is called in device + * startup + * + * @param[in] count : Number of retries until PLL2 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_pll2(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + TMS570_SYS2.PLLCTL3 = 0x20001A00U; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && + ((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) == 0U)) { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if (((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 2U; + } else { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t check_frequency(uint32_t cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32_t check_frequency(uint32_t cnt1_clksrc) { + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + TMS570_DCC1.GCTRL = + (uint32_t)0x5U | /** Disable DCC1 */ + (uint32_t)((uint32_t)0x5U << 4U) | /** No Error Interrupt */ + (uint32_t)((uint32_t)0xAU << 8U) | /** Single Shot mode */ + (uint32_t)((uint32_t)0x5U << 12U); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + TMS570_DCC1.STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + TMS570_DCC1.CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + TMS570_DCC1.VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + TMS570_DCC1.CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + TMS570_DCC1.CNT1CLKSRC = + (uint32_t)((uint32_t)10U << 12U) | /** DCC Enable / Disable Key */ + (uint32_t)cnt1_clksrc; /** DCC1 Clock Source 1 */ + + TMS570_DCC1.CNT0CLKSRC = + (uint32_t)DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + TMS570_DCC1.GCTRL = + (uint32_t)0xAU | /** Enable DCC1 */ + (uint32_t)((uint32_t)0x5U << 4U) | /** No Error Interrupt */ + (uint32_t)((uint32_t)0xAU << 8U) | /** Single Shot mode */ + (uint32_t)((uint32_t)0x5U << 12U); /** No Done Interrupt */ + while (TMS570_DCC1.STAT == 0U) { + /* Wait */ + } + return (TMS570_DCC1.STAT & 0x01U); +} + +/** @fn uint32_t disable_plls(uint32_t plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and + * then been disabled) + * 4 = The workaround function was not able to disable at least one + * of the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +static uint32_t disable_plls(uint32_t plls) { + uint32_t timeout, failCode; + + TMS570_SYS1.CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + while (((TMS570_SYS1.CSVSTAT & (plls)) != 0U) && (timeout != 0U)) { + /* Clear ESM and GLBSTAT PLL slip flags */ + TMS570_SYS1.GLBSTAT = 0x00000300U; + + if ((plls & SYS_CLKSRC_PLL1) == SYS_CLKSRC_PLL1) { + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + } + if ((plls & SYS_CLKSRC_PLL2) == SYS_CLKSRC_PLL2) { + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + } + timeout--; + /* Wait */ + } + if (timeout == 0U) { + failCode = 4U; + } else { + failCode = 0U; + } + return failCode; +} diff --git a/bsps/arm/tms570/start/fail_notification.c b/bsps/arm/tms570/start/fail_notification.c index 00276e23d7..54d4e6a37b 100644 --- a/bsps/arm/tms570/start/fail_notification.c +++ b/bsps/arm/tms570/start/fail_notification.c @@ -1,3 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the default + * bsp_selftest_fail_notification() and + * tms570_memory_port0_fail_notification() implementations. + */ + +/* + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #include <stdint.h> #include <stdbool.h> #include <bsp/tms570.h> diff --git a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c new file mode 100644 index 0000000000..7c01b8306f --- /dev/null +++ b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. + */ + +/* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include <bsp/tms570.h> +#include <bsp/tms570_hwinit.h> +#include <bsp/tms570-pinmux.h> + +typedef enum Tms570ClockDisableSources { + TMS570_CLKDIS_SRC_OSC = 0x01, ///< External high-speed oscillator as clock source + TMS570_CLKDIS_SRC_PLL1 = 0x02, + TMS570_CLKDIS_SRC_RESERVED = 0x04, ///< reserved. not tied to actual clock source + TMS570_CLKDIS_SRC_EXT_CLK1 = 0x08, + TMS570_CLKDIS_SRC_LOW_FREQ_LPO = 0x10, + TMS570_CLKDIS_SRC_HIGH_FREQ_LPO = 0x20, + TMS570_CLKDIS_SRC_PLL2 = 0x40, + TMS570_CLKDIS_SRC_EXT_CLK2 = 0x80, +} Tms570ClockDisableSources; + +// Source selection for G, H, and V clocks SYS1.GHVSRC reg +typedef enum Tms570GhvClockSources { + TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ + TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ + TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ + TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ + TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ + TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ +} Tms570GhvClockSources; + +/* + * The next construct allows to compute values for individual + * PINMMR registers based on the multiple processing + * complete pin functions list at compile time. + * Each line computes 32-bit value which selects function + * of consecutive four pins. Each pin function is defined + * by single byte. + */ +static const uint32_t tms570_pinmmr_init_data[] = { + TMS570_PINMMR_REG_VAL( 0, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 1, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 2, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 3, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 4, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 5, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 6, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 7, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 8, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 9, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 10, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 11, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 12, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 13, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 14, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 15, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 16, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 17, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 18, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 19, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 20, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 21, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 22, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 23, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 24, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 25, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 26, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 27, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 28, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 29, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 30, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 31, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 32, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 33, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 34, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 35, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 36, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 37, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), +}; + +void tms570_pinmux_init( void ) +{ + tms570_bsp_pinmmr_config(tms570_pinmmr_init_data, 0, RTEMS_ARRAY_SIZE(tms570_pinmmr_init_data)); + + tms570_pin_config_prepare(); + TMS570_PINMUX[174] = (TMS570_PINMUX[174] & ~(UINT32_C(0x3) << 8)) | (UINT32_C(0x2) << 8); // emif output-enable bit8= 0, bit9= 1 + tms570_pin_config_complete(); +} + +void tms570_emif_sdram_init( void ) +{ + uint32_t dummy; + + /* Do not run attempt to initialize SDRAM when code is running from it */ + if ( tms570_running_from_sdram() ) + return; + + // Following the initialization procedure as described in EMIF-errata #5 for the tms570lc43 + // at EMIF clock rates >= 40Mhz + // Note step one of this procedure is running this EMIF initialization sequence before PLL + // and clocks are mapped/enabled + // For additional details on startup procedure see tms570lc43 TRM s21.2.5.5.B + + // Set SDRAM timings. These are dependent on the EMIF CLK rate, which = VCLK3 + // Set these based on the final EMIF clock rate once PLL & VCLK is enabled + TMS570_EMIF.SDTIMR = (uint32_t)1U << 27U| + (uint32_t)0U << 24U| + (uint32_t)0U << 20U| + (uint32_t)0U << 19U| + (uint32_t)1U << 16U| + (uint32_t)1U << 12U| + (uint32_t)1U << 8U| + (uint32_t)0U << 4U; + + /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ + // Also set this based on the final EMIF clk + TMS570_EMIF.SDSRETR = 2; + // Program the RR Field of SDRCR to provide 200us of initialization time + // Per Errata#5, for EMIF startup, set this based on the non-VLCK3 clk rate. + // The Errata is this register must be calculated as `SDRCR = 200us * EMIF_CLK` + // (typically this would be `SDRCR = (200us * EMIF_CLK) / 8` ) + // Since the PLL's arent enabled yet, EMIF_CLK would be EXT_OSCIN / 2 + TMS570_EMIF.SDRCR = 1600; + + TMS570_EMIF.SDCR = ((uint32_t)0U << 31U)| + ((uint32_t)1U << 14U)| + ((uint32_t)2U << 9U)| + ((uint32_t)1U << 8U)| + ((uint32_t)2U << 4U)| + ((uint32_t)0); // pagesize = 256 + + // Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes + dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN; + (void) dummy; + + // Program the RR field to the default Refresh Interval of the SDRAM + // Program this to the correct interval for the VCLK3/EMIF_CLK rate + // Do this in the typical way per TRM: SDRCR = ((200us * EMIF_CLK) / 8) + 1 + TMS570_EMIF.SDRCR = 1251; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second initialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *((volatile unsigned char *)(&TMS570_EMIF.SDCR) + 0x0U) = 0x80; +} + +/** + * @brief Setup all system PLLs (HCG:setupPLL) + * + */ +void tms570_pll_init( void ) +{ + //based on HalCoGen setupPLL method + uint32_t pll12_dis = TMS570_CLKDIS_SRC_PLL1 | TMS570_CLKDIS_SRC_PLL2; + + /* Disable PLL1 and PLL2 */ + TMS570_SYS1.CSDISSET = pll12_dis; + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { + /* Wait */ + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x301U; + + // Configure PLL control registers + + /** - Setup pll control register 1: + * - Disable reset on oscillator slip (ROS) + * - Enable bypass on pll slip + * TODO: desired: switches to OSC when PLL slip detected + * - setup Pll output clock divider to max before Lock + * - Disable reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + * + * - PLL1: 16MHz OSC in -> 300MHz PLL1 out + */ + TMS570_SYS1.PLLCTL1 = (TMS570_SYS1_PLLCTL1_ROS * 0) + | (uint32_t)0x40000000U + | TMS570_SYS1_PLLCTL1_PLLDIV(0x1F) + | (TMS570_SYS1_PLLCTL1_ROF * 0) + | TMS570_SYS1_PLLCTL1_REFCLKDIV(4U - 1U) + | TMS570_SYS1_PLLCTL1_PLLMUL((75U - 1U) << 8); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + TMS570_SYS1.PLLCTL2 = ((uint32_t)255U << 22U) + | ((uint32_t)7U << 12U) + | ((uint32_t)(1U - 1U) << 9U) + | 61U; + + // Initialize Pll2 + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2(1U - 1U) + | TMS570_SYS2_PLLCTL3_PLLDIV2(0x1FU) + | TMS570_SYS2_PLLCTL3_REFCLKDIV2(8U - 1U) + | TMS570_SYS2_PLLCTL3_PLLMUL2(( 150U - 1U) << 8 ); + + // Enable PLL(s) to start up or Lock + // Enable all clock sources except the following + TMS570_SYS1.CSDIS = (TMS570_CLKDIS_SRC_EXT_CLK2 | TMS570_CLKDIS_SRC_EXT_CLK1 | TMS570_CLKDIS_SRC_RESERVED); +} + +void tms570_map_clock_init(void) +{ + // based on HalCoGen mapClocks method + uint32_t sys_csvstat, sys_csdis; + + TMS570_SYS2.HCLKCNTL = 1U; + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 ON */ + ( 1U << 5U ) | /* AVCLK 2 OFF */ + ( 0U << 8U ) | /* VCLK3 ON */ + ( 0U << 9U ) | /* VCLK4 ON */ + ( 0U << 10U ) | /* AVCLK 3 ON */ + ( 0U << 11U ); /* AVCLK 4 ON */ + + /* Work Around for Errata SYS#46: + * Despite this being a LS3137 errata, hardware testing on the LC4357 indicates this wait is still necessary + */ + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + + while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != + ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + } + + TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE(TMS570_SYS_CLK_SRC_PLL1) + | TMS570_SYS1_GHVSRC_HVLPM(TMS570_SYS_CLK_SRC_PLL1) + | TMS570_SYS1_GHVSRC_GHVSRC(TMS570_SYS_CLK_SRC_PLL1); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + TMS570_SYS1.RCLKSRC = ((uint32_t)1U << 24U) /* RTI2 divider (Not applicable for lock-step device) */ + | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 16U) /* RTI2 clock source (Not applicable for lock-step device) Field not in TRM? */ + | ((uint32_t)1U << 8U) /* RTI1 divider */ + | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 0U); /* RTI1 clock source */ + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + TMS570_SYS1.VCLKASRC = TMS570_SYS1_VCLKASRC_VCLKA2S(TMS570_SYS_CLK_SRC_VCLK) + | TMS570_SYS1_VCLKASRC_VCLKA1S(TMS570_SYS_CLK_SRC_VCLK); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + + // VCLK2 = PLL1 / HCLK_DIV / 2 = 75MHz + TMS570_SYS1.CLKCNTL = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R(0xF)) + | TMS570_SYS1_CLKCNTL_VCLK2R(0x1); + // VLCK1 = PLL1 / HCLK_DIV / 2 = 75MHz + TMS570_SYS1.CLKCNTL = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR(0xF)) + | TMS570_SYS1_CLKCNTL_VCLKR(0x1); + + // VCLK3 = PLL1 / HCLK_DIV / 3 = 50MHz + TMS570_SYS2.CLK2CNTRL = (TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R(0xF)) + | TMS570_SYS2_CLK2CNTRL_VCLK3R(0x2); + + TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R(1U - 1U) + | (TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0) + | TMS570_SYS2_VCLKACON1_VCLKA4S(TMS570_SYS_CLK_SRC_VCLK) + | TMS570_SYS2_VCLKACON1_VCLKA3R(1U - 1U) + | (TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0) + | TMS570_SYS2_VCLKACON1_VCLKA3S(TMS570_SYS_CLK_SRC_VCLK); + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ + TMS570_SYS1.PLLCTL1 = (TMS570_SYS1.PLLCTL1 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U); + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> " Clear and write to the volatile register " */ + TMS570_SYS2.PLLCTL3 = (TMS570_SYS2.PLLCTL3 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U); + + /* Enable/Disable Frequency modulation */ + TMS570_SYS1.PLLCTL2 |= 0x00000000U; +} diff --git a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c new file mode 100644 index 0000000000..1f2bbd96f2 --- /dev/null +++ b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. + */ + +/* + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include <bsp/tms570.h> +#include <bsp/tms570_hwinit.h> +#include <bsp/tms570-pinmux.h> + +enum tms570_system_clock_source { + TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ + TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ + TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ + TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ + TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ + TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ +}; + +/* + * Definition of fuctions for all pins of TMS570LS3137. + * This setup correctponds to TMS570LS31x HDK Kit + */ + +#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \ + per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \ + per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \ + per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \ + per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \ + per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \ + per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \ + per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \ + per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \ + per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \ + per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \ + per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \ + per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \ + per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \ + per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \ + per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \ + per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \ + per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \ + per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \ + per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \ + per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \ + per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \ + per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \ + per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \ + per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \ + per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \ + per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \ + per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \ + per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \ + per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \ + per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \ + per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \ + per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \ + per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \ + per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \ + per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \ + per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \ + per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \ + per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \ + per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \ + per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \ + per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \ + per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \ + per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \ + per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \ + per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \ + per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \ + per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \ + per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \ + per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \ + per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \ + per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \ + per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \ + per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \ + per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \ + per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \ + per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \ + per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \ + per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \ + per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \ + per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \ + per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \ + per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \ + per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \ + per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \ + per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \ + per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \ + per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \ + per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \ + per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \ + per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \ + per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \ + per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \ + per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \ + per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \ + per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \ + per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \ + per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \ + per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \ + per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \ + per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \ + per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \ + per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \ + per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \ + per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \ + per_pin_action( common_arg, \ + TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, \ + TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, \ + TMS570_MMR_SELECT_MII_MODE | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 ) + +/* + * The next construct allows to compute values for individual + * PINMMR registers based on the multiple processing + * complete pin functions list at compile time. + * Each line computes 32-bit value which selects function + * of consecutive four pins. Each pin function is defined + * by single byte. + */ +static const uint32_t tms570_pinmmr_init_data[] = { + TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ), +}; + +/** + * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit) + */ +void tms570_pinmux_init( void ) +{ + tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0, + RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) ); +} + +void tms570_emif_sdram_init(void) +{ + uint32_t dummy; + uint32_t sdtimr = 0; + uint32_t sdcr = 0; + + /* Do not run attempt to initialize SDRAM when code is running from it */ + if ( tms570_running_from_sdram() ) + return; + + sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 ); + + TMS570_EMIF.SDTIMR = sdtimr; + + /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ + TMS570_EMIF.SDSRETR = 5; + /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ + TMS570_EMIF.SDRCR = 2000; + + /* SR - Self-Refresh mode bit. */ + sdcr |= TMS570_EMIF_SDCR_SR * 0; + /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */ + sdcr |= TMS570_EMIF_SDCR_PD * 0; + /* PDWR - Perform refreshes during power down. */ + sdcr |= TMS570_EMIF_SDCR_PDWR * 0; + /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */ + sdcr |= TMS570_EMIF_SDCR_NM * 1; + /* CL - CAS Latency. */ + sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 ); + /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ + sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1; + /* IBANK - Internal SDRAM Bank size. */ + sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */ + /* Page Size. This field defines the internal page size of connected SDRAM devices. */ + sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */ + + TMS570_EMIF.SDCR = sdcr; + + dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN; + (void) dummy; + TMS570_EMIF.SDRCR = 31; + + /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ + TMS570_EMIF.SDRCR = 312; +} + +/** + * @brief Setup all system PLLs (HCG:setupPLL) + * + */ +void tms570_pll_init( void ) +{ + uint32_t pll12_dis = 0x42; + + /* Disable PLL1 and PLL2 */ + TMS570_SYS1.CSDISSET = pll12_dis; + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { + /* Wait */ + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP | + TMS570_SYS1_GLBSTAT_RFSLIP | + TMS570_SYS1_GLBSTAT_OSCFAIL; + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /* Setup pll control register 1 */ + TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 | + TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) | + TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */ + TMS570_SYS1_PLLCTL1_ROF * 0 | + TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) | + TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 ); + + /* Setup pll control register 2 */ + TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 | + TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) | + TMS570_SYS1_PLLCTL2_MULMOD( 7 ) | + TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) | + TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 ); + + /** @b Initialize @b Pll2: */ + + /* Setup pll2 control register */ + TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) | + TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */ + TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) | + TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 ); + + /** - Enable PLL(s) to start up or Lock */ + TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */ + 0x00000000 | /* CLKSR1 on */ + 0x00000008 | /* CLKSR3 off */ + 0x00000000 | /* CLKSR4 on */ + 0x00000000 | /* CLKSR5 on */ + 0x00000000 | /* CLKSR6 on */ + 0x00000080; /* CLKSR7 off */ +} + +/** + * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks) + * + */ +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : HL_SR469 */ +void tms570_map_clock_init( void ) +{ + uint32_t sys_csvstat, sys_csdis; + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */ + ( 0U << 5U ) | /* AVCLK 2 OFF */ + ( 0U << 8U ) | /* VCLK3 OFF */ + ( 0U << 9U ) | /* VCLK4 OFF */ + ( 1U << 10U ) | /* AVCLK 3 OFF */ + ( 0U << 11U ); /* AVCLK 4 OFF */ + + /* Work Around for Errata SYS#46: + * + * Errata Description: + * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid + * Workaround: + * Always check the CSDIS register to make sure the clock source is turned on and check + * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + + while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != + ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + } /* Wait */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ + TMS570_SYS1.PLLCTL1 = + ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) | + TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 ); + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + TMS570_SYS2.PLLCTL3 = + ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) | + TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 ); + + /* Enable/Disable Frequency modulation */ + TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA; + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ + TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) | + TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) | + TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + TMS570_SYS1.CLKCNTL = + ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) | + TMS570_SYS1_CLKCNTL_VCLK2R( 1 ); + + TMS570_SYS1.CLKCNTL = + ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) | + TMS570_SYS1_CLKCNTL_VCLKR( 1 ); + + TMS570_SYS2.CLK2CNTRL = + ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) | + TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 ); + + TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) | + ( 1U << 8U ); /* FIXME: unknown in manual*/ + + /** - Setup RTICLK1 and RTICLK2 clocks */ + TMS570_SYS1.RCLKSRC = ( 1U << 24U ) | + ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */ + TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) | + TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK ); + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + TMS570_SYS1.VCLKASRC = + TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) | + TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK ); + + TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) | + TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 | + TMS570_SYS2_VCLKACON1_VCLKA4S( + TMS570_SYS_CLK_SRC_VCLK ) | + TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) | + TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 | + TMS570_SYS2_VCLKACON1_VCLKA3S( + TMS570_SYS_CLK_SRC_VCLK ); +} diff --git a/bsps/arm/tms570/start/init_emif_sdram.c b/bsps/arm/tms570/start/init_emif_sdram.c deleted file mode 100644 index 2ce7946203..0000000000 --- a/bsps/arm/tms570/start/init_emif_sdram.c +++ /dev/null @@ -1,64 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Initialization of external memory/SDRAM interface. - */ - -#include <stdint.h> -#include <bsp/tms570.h> -#include <bsp/tms570_hwinit.h> - -void tms570_emif_sdram_init( void ) -{ - uint32_t dummy; - uint32_t sdtimr = 0; - uint32_t sdcr = 0; - - /* Do not run attempt to initialize SDRAM when code is running from it */ - if ( ( (void*)tms570_emif_sdram_init >= (void*)TMS570_SDRAM_START_PTR ) && - ( (void*)tms570_emif_sdram_init <= (void*)TMS570_SDRAM_WINDOW_END_PTR ) ) - return; - - sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 ); - - TMS570_EMIF.SDTIMR = sdtimr; - - /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ - TMS570_EMIF.SDSRETR = 5; - /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ - TMS570_EMIF.SDRCR = 2000; - - /* SR - Self-Refresh mode bit. */ - sdcr |= TMS570_EMIF_SDCR_SR * 0; - /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */ - sdcr |= TMS570_EMIF_SDCR_PD * 0; - /* PDWR - Perform refreshes during power down. */ - sdcr |= TMS570_EMIF_SDCR_PDWR * 0; - /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */ - sdcr |= TMS570_EMIF_SDCR_NM * 1; - /* CL - CAS Latency. */ - sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 ); - /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ - sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1; - /* IBANK - Internal SDRAM Bank size. */ - sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */ - /* Page Size. This field defines the internal page size of connected SDRAM devices. */ - sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */ - - TMS570_EMIF.SDCR = sdcr; - - dummy = *(volatile uint32_t*)TMS570_SDRAM_START_PTR; - (void) dummy; - TMS570_EMIF.SDRCR = 31; - - /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ - TMS570_EMIF.SDRCR = 312; -} diff --git a/bsps/arm/tms570/start/init_esm.c b/bsps/arm/tms570/start/init_esm.c index fdc7f94b90..35fd1c8eab 100644 --- a/bsps/arm/tms570/start/init_esm.c +++ b/bsps/arm/tms570/start/init_esm.c @@ -1,9 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Error signaling module initialization + * @brief This source file contains the error signaling module initialization. + */ + +/* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> @@ -36,8 +69,12 @@ void tms570_esm_init( void ) /** - Reset error pin */ if (TMS570_ESM.EPSR == 0U) { - TMS570_ESM.EKR = 0x00000005U; - } else { + /* + * Per TMS570LC4x Errata DEVICE#60, the error pin cannot be cleared with a + * normal EKR write upon system reset. Put in diagnostic followed by + * normal mode instead. This sequence works also on other chip variants. + */ + TMS570_ESM.EKR = 0x0000000AU; TMS570_ESM.EKR = 0x00000000U; } diff --git a/bsps/arm/tms570/start/init_pinmux.c b/bsps/arm/tms570/start/init_pinmux.c deleted file mode 100644 index e86a115541..0000000000 --- a/bsps/arm/tms570/start/init_pinmux.c +++ /dev/null @@ -1,259 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Initialize pin multiplexers. - */ -/* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <stdint.h> -#include <bsp/tms570.h> -#include <bsp/tms570-pinmux.h> -#include <rtems.h> -#include <bsp/tms570_hwinit.h> - -/* - * To check that content is right generated use - * - * objdump --section=.rodata -s init_pinmux.o - */ -#if 0 - -/* - * Test of use of the default pins configuration with one line added. - * This can be used to concatenate partial lists but care has to - * be taken to not attempt to override already defined pin. - * This would not work and result in two PINMMR bits set - * for given pine. - */ - -#ifndef TMS570_PINMMR_INIT_LIST - #define TMS570_PINMMR_INIT_LIST(per_pin_action, common_arg) \ - TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ - per_pin_action(common_arg, TMS570_BALL_E3_HET2_18) -#endif - -#else - -/* - * Definition of fuctions for all pins of TMS570LS3137. - * This setup correctponds to TMS570LS31x HDK Kit - */ - -#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \ - per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \ - per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \ - per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \ - per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \ - per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \ - per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \ - per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \ - per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \ - per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \ - per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \ - per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \ - per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \ - per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \ - per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \ - per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \ - per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \ - per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \ - per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \ - per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \ - per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \ - per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \ - per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \ - per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \ - per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \ - per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \ - per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \ - per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \ - per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \ - per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \ - per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \ - per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \ - per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \ - per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \ - per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \ - per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \ - per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \ - per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \ - per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \ - per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \ - per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \ - per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \ - per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \ - per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \ - per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \ - per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \ - per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \ - per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \ - per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \ - per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \ - per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \ - per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \ - per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \ - per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \ - per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \ - per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \ - per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \ - per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \ - per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \ - per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \ - per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \ - per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \ - per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \ - per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \ - per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \ - per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \ - per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \ - per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \ - per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \ - per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \ - per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \ - per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \ - per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \ - per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \ - per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \ - per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \ - per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \ - per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \ - per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \ - per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \ - per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \ - per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \ - per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \ - per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \ - per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \ - per_pin_action( common_arg, \ - TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, \ - TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, \ - TMS570_MMR_SELECT_GMII_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 ) \ - - -#endif - -/* - * The next construct allows to compute values for individual - * PINMMR registers based on the multiple processing - * complete pin functions list at compile time. - * Each line computes 32-bit value which selects function - * of consecutive four pins. Each pin function is defined - * by single byte. - */ -const uint32_t tms570_pinmmr_init_data[] = { - TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ), -}; - -/** - * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit) - */ -void tms570_pinmux_init( void ) -{ - tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0, - RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) ); -} - -#if 0 - -/* - * Alternative option how to set function of individual pins - * or use list for one by one setting. This is much slower - * and consumes more memory to hold complete list. - * - * On the other hand this solution can be used for configuration - * or reconfiguration of some shorter groups of pins at runtime. - * - */ - -const uint32_t tms570_pinmmr_init_list[] = { - TMS570_PINMMR_COMA_LIST( TMS570_PINMMR_INIT_LIST ) -}; - -void tms570_pinmux_init_by_list( void ) -{ - int pincnt = RTEMS_ARRAY_SIZE( tms570_pinmmr_init_list ); - const uint32_t *pinfnc = tms570_pinmmr_init_list; - - while ( pincnt-- ) - tms570_bsp_pin_config_one( *(pinfnc++) ); -} -#endif diff --git a/bsps/arm/tms570/start/init_system.c b/bsps/arm/tms570/start/init_system.c index 690ee9ba1c..4d2c2ef29f 100644 --- a/bsps/arm/tms570/start/init_system.c +++ b/bsps/arm/tms570/start/init_system.c @@ -1,9 +1,15 @@ -/** @file +/* SPDX-License-Identifier: BSD-3-Clause */ - based on Ti HalCoGen generated file +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. */ /* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -45,62 +51,6 @@ #include <bsp/tms570_hwinit.h> /** - * @brief Setup all system PLLs (HCG:setupPLL) - * - */ -void tms570_pll_init( void ) -{ - uint32_t pll12_dis = 0x42; - - /* Disable PLL1 and PLL2 */ - TMS570_SYS1.CSDISSET = pll12_dis; - - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { - /* Wait */ - } - - /* Clear Global Status Register */ - TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP | - TMS570_SYS1_GLBSTAT_RFSLIP | - TMS570_SYS1_GLBSTAT_OSCFAIL; - /** - Configure PLL control registers */ - /** @b Initialize @b Pll1: */ - - /* Setup pll control register 1 */ - TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 | - TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) | - TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */ - TMS570_SYS1_PLLCTL1_ROF * 0 | - TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) | - TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 ); - - /* Setup pll control register 2 */ - TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 | - TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) | - TMS570_SYS1_PLLCTL2_MULMOD( 7 ) | - TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) | - TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 ); - - /** @b Initialize @b Pll2: */ - - /* Setup pll2 control register */ - TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) | - TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */ - TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) | - TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 ); - - /** - Enable PLL(s) to start up or Lock */ - TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */ - 0x00000000 | /* CLKSR1 on */ - 0x00000008 | /* CLKSR3 off */ - 0x00000000 | /* CLKSR4 on */ - 0x00000000 | /* CLKSR5 on */ - 0x00000000 | /* CLKSR6 on */ - 0x00000080; /* CLKSR7 off */ -} - -/** * @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO) * */ @@ -125,17 +75,6 @@ enum tms570_flash_power_modes { TMS570_FLASH_SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ }; -enum tms570_system_clock_source { - TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ - TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ - TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ - TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ - TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ - TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ - TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ - TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ -}; - /** * @brief Setup Flash memory parameters and timing (HCG:setupFlash) * @@ -182,113 +121,28 @@ void tms570_periph_init( void ) /** - Release peripherals from reset and enable clocks to all peripherals */ /** - Power-up all peripherals */ - TMS570_PCR.PSPWRDWNCLR0 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR1 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR2 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR3 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR3 = 0xFFFFFFFFU; + +#if TMS570_VARIANT == 4357 + TMS570_PCR2.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR3 = 0xFFFFFFFFU; + + TMS570_PCR3.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR3 = 0xFFFFFFFFU; +#endif /** - Enable Peripherals */ TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA; } /** - * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks) - * - */ -/* SourceId : SYSTEM_SourceId_005 */ -/* DesignId : SYSTEM_DesignId_005 */ -/* Requirements : HL_SR469 */ -void tms570_map_clock_init( void ) -{ - uint32_t sys_csvstat, sys_csdis; - - /** @b Initialize @b Clock @b Tree: */ - /** - Disable / Enable clock domain */ - TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */ - ( 0U << 5U ) | /* AVCLK 2 OFF */ - ( 0U << 8U ) | /* VCLK3 OFF */ - ( 0U << 9U ) | /* VCLK4 OFF */ - ( 1U << 10U ) | /* AVCLK 3 OFF */ - ( 0U << 11U ); /* AVCLK 4 OFF */ - - /* Work Around for Errata SYS#46: - * - * Errata Description: - * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid - * Workaround: - * Always check the CSDIS register to make sure the clock source is turned on and check - * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. - */ - /** - Wait for until clocks are locked */ - sys_csvstat = TMS570_SYS1.CSVSTAT; - sys_csdis = TMS570_SYS1.CSDIS; - - while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != - ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { - sys_csvstat = TMS570_SYS1.CSVSTAT; - sys_csdis = TMS570_SYS1.CSDIS; - } /* Wait */ - - /* Now the PLLs are locked and the PLL outputs can be sped up */ - /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ - TMS570_SYS1.PLLCTL1 = - ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) | - TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 ); - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ - TMS570_SYS2.PLLCTL3 = - ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) | - TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 ); - - /* Enable/Disable Frequency modulation */ - TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA; - - /** - Map device clock domains to desired sources and configure top-level dividers */ - /** - All clock domains are working off the default clock sources until now */ - /** - The below assignments can be easily modified using the HALCoGen GUI */ - - /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ - TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) | - TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) | - TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 ); - - /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ - TMS570_SYS1.CLKCNTL = - ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) | - TMS570_SYS1_CLKCNTL_VCLK2R( 1 ); - - TMS570_SYS1.CLKCNTL = - ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) | - TMS570_SYS1_CLKCNTL_VCLKR( 1 ); - - TMS570_SYS2.CLK2CNTRL = - ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) | - TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 ); - - TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) | - ( 1U << 8U ); /* FIXME: unknown in manual*/ - - /** - Setup RTICLK1 and RTICLK2 clocks */ - TMS570_SYS1.RCLKSRC = ( 1U << 24U ) | - ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */ - TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) | - TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK ); - - /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ - TMS570_SYS1.VCLKASRC = - TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) | - TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK ); - - TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) | - TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 | - TMS570_SYS2_VCLKACON1_VCLKA4S( - TMS570_SYS_CLK_SRC_VCLK ) | - TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) | - TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 | - TMS570_SYS2_VCLKACON1_VCLKA3S( - TMS570_SYS_CLK_SRC_VCLK ); -} - -/** * @brief TMS570 system hardware initialization (HCG:systemInit) * */ diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_with_loader b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk index aa0000379d..70f60662a6 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_with_loader +++ b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk @@ -1,11 +1,4 @@ - -MEMORY { - ROM_BOOT(RX) : ORIGIN = 0x00000000, LENGTH = 256k - ROM_INT (RX) : ORIGIN = 0x00040000, LENGTH = 3M-256k - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", ROM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -25,6 +18,7 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; +bsp_int_vec_overlay_start = ORIGIN(ROM_INT) + 64; INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram new file mode 100644 index 0000000000..b6a76ff407 --- /dev/null +++ b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram @@ -0,0 +1,30 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", RAM_EXT); +REGION_ALIAS ("REGION_VECTOR", RAM_EXT); +REGION_ALIAS ("REGION_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_RODATA", RAM_EXT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_DATA", RAM_EXT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_BSS", RAM_EXT); +REGION_ALIAS ("REGION_WORK", RAM_EXT); +REGION_ALIAS ("REGION_STACK", RAM_EXT); +REGION_ALIAS ("REGION_NOCACHE", RAM_EXT); +REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_EXT); + +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} + +INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk index ca68617231..70f60662a6 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", ROM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -24,6 +18,7 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; +bsp_int_vec_overlay_start = ORIGIN(ROM_INT) + 64; INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram index ca216204dc..6060eec80c 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", RAM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -24,6 +18,13 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram index 1bf4a1cae1..b6a76ff407 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", RAM_EXT); REGION_ALIAS ("REGION_VECTOR", RAM_EXT); @@ -16,7 +10,7 @@ REGION_ALIAS ("REGION_DATA", RAM_EXT); REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); -REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); REGION_ALIAS ("REGION_BSS", RAM_EXT); REGION_ALIAS ("REGION_WORK", RAM_EXT); @@ -24,6 +18,13 @@ REGION_ALIAS ("REGION_STACK", RAM_EXT); REGION_ALIAS ("REGION_NOCACHE", RAM_EXT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_EXT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/pinmux.c b/bsps/arm/tms570/start/pinmux.c index 6aec5f7c32..16eb41a129 100644 --- a/bsps/arm/tms570/start/pinmux.c +++ b/bsps/arm/tms570/start/pinmux.c @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief I/O Multiplexing Module (IOMM) basic support + * @brief This source file contains the I/O Multiplexing Module (IOMM) support + * implementation. */ /* - * Copyright (c) 2015 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2015 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,17 +18,45 @@ * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp/tms570.h> #include <bsp/tms570-pinmux.h> #include <bsp/irq.h> -uint32_t tms570_bsp_pinmmr_kick_key0 = 0x83E70B13U; -uint32_t tms570_bsp_pinmmr_kick_key1 = 0x95A4F1E0U; +RTEMS_STATIC_ASSERT( + TMS570_PIN_CLEAR_RQ_MASK == TMS570_PIN_FNC_CLEAR << TMS570_PIN_FNC_SHIFT, + TMS570_PIN_CONFIG +); + +static inline void +tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, uint32_t *pin_shift, + uint32_t config) +{ + uint32_t pin_num = (config & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT; + *pinmmrx = TMS570_PINMUX + (pin_num >> 2); + *pin_shift = (pin_num & 0x3)*8; +} /** * @brief select desired function of pin/ball @@ -110,33 +141,11 @@ void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc) { rtems_interrupt_level intlev; - uint32_t pin_in_alt; rtems_interrupt_disable(intlev); - - TMS570_IOMM.KICK_REG0 = tms570_bsp_pinmmr_kick_key0; - TMS570_IOMM.KICK_REG1 = tms570_bsp_pinmmr_kick_key1; - - pin_in_alt = pin_num_and_fnc & TMS570_PIN_IN_ALT_MASK; - if ( pin_in_alt ) { - pin_in_alt >>= TMS570_PIN_IN_ALT_SHIFT; - if ( pin_in_alt & TMS570_PIN_CLEAR_RQ_MASK ) { - tms570_bsp_pin_clear_function(pin_in_alt, TMS570_PIN_FNC_AUTO); - } else { - tms570_bsp_pin_set_function(pin_in_alt, TMS570_PIN_FNC_AUTO); - } - } - - pin_num_and_fnc &= TMS570_PIN_NUM_FNC_MASK; - if ( pin_num_and_fnc & TMS570_PIN_CLEAR_RQ_MASK ) { - tms570_bsp_pin_clear_function(pin_num_and_fnc, TMS570_PIN_FNC_AUTO); - } else { - tms570_bsp_pin_set_function(pin_num_and_fnc, TMS570_PIN_FNC_AUTO); - } - - TMS570_IOMM.KICK_REG0 = 0; - TMS570_IOMM.KICK_REG1 = 0; - + tms570_pin_config_prepare(); + tms570_pin_config_apply(pin_num_and_fnc); + tms570_pin_config_complete(); rtems_interrupt_enable(intlev); } @@ -167,29 +176,75 @@ tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_c if ( reg_count <= 0) return; - TMS570_IOMM.KICK_REG0 = tms570_bsp_pinmmr_kick_key0; - TMS570_IOMM.KICK_REG1 = tms570_bsp_pinmmr_kick_key1; + tms570_pin_config_prepare(); - pinmmrx = (&TMS570_IOMM.PINMUX.PINMMR0) + reg_start; + pinmmrx = TMS570_PINMUX + reg_start; pval = pinmmr_values; cnt = reg_count; do { - *pinmmrx = *pinmmrx & *pval; + *pinmmrx = *pval; pinmmrx++; pval++; } while( --cnt ); - pinmmrx = (&TMS570_IOMM.PINMUX.PINMMR0) + reg_start; - pval = pinmmr_values; - cnt = reg_count; + tms570_pin_config_complete(); +} - do { - *pinmmrx = *pval; - pinmmrx++; - pval++; - } while( --cnt ); +void tms570_pin_config_prepare(void) +{ + TMS570_IOMM.KICK_REG0 = 0x83E70B13U; + TMS570_IOMM.KICK_REG1 = 0x95A4F1E0U; +} + +static void +tms570_pin_set_function(uint32_t config) +{ + volatile uint32_t *pinmmrx; + uint32_t pin_shift; + uint32_t pin_fnc; + uint32_t bit; + uint32_t val; + + tms570_bsp_pin_to_pinmmrx(&pinmmrx, &pin_shift, config); + pin_fnc = (config & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT; + bit = 1U << (pin_fnc + pin_shift); + val = *pinmmrx; + val &= ~(0xffU << pin_shift); + + if ((config & TMS570_PIN_CLEAR_RQ_MASK) == 0) { + val |= bit; + } + + *pinmmrx = val; +} + +void tms570_pin_config_apply(uint32_t config) +{ + uint32_t pin_in_alt; + uint32_t pin_num_and_fnc; + pin_in_alt = config & TMS570_PIN_IN_ALT_MASK; + if (pin_in_alt != 0) { + pin_in_alt >>= TMS570_PIN_IN_ALT_SHIFT; + tms570_pin_set_function(pin_in_alt); + } + + pin_num_and_fnc = config & TMS570_PIN_NUM_FNC_MASK; + tms570_pin_set_function(pin_num_and_fnc); +} + +void tms570_pin_config_array_apply(const uint32_t *config, size_t count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + tms570_pin_config_apply(config[i]); + } +} + +void tms570_pin_config_complete(void) +{ TMS570_IOMM.KICK_REG0 = 0; TMS570_IOMM.KICK_REG1 = 0; } diff --git a/bsps/arm/tms570/start/tms570-pom.c b/bsps/arm/tms570/start/tms570-pom.c index 8f31d01b77..f1a6d2d4af 100644 --- a/bsps/arm/tms570/start/tms570-pom.c +++ b/bsps/arm/tms570/start/tms570-pom.c @@ -1,22 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 Parameter Overlay Module functions definitions. + * @brief This source file contains the Parameter Overlay Module (POM) support + * implementation. */ - /* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> +/* + * Copyright (C) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> @@ -66,7 +86,7 @@ uint32_t pom_global_overlay_target_address_start = * * @retval Void */ -void tms570_initialize_and_clear(void) +void tms570_pom_initialize_and_clear(void) { int i; @@ -87,7 +107,12 @@ void tms570_initialize_and_clear(void) */ void tms570_pom_remap(void) { - uint32_t vec_overlay_start = pom_global_overlay_target_address_start; + void *vec_overlay_start = (void *) pom_global_overlay_target_address_start; + void *addr_tab = (char *) bsp_start_vector_table_begin + 64; + + if (vec_overlay_start == addr_tab) { + return; + } /* * Copy RTEMS the first level exception processing code @@ -99,7 +124,10 @@ void tms570_pom_remap(void) * table found in * c/src/lib/libbsp/arm/shared/start/start.S */ - memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64); + rtems_cache_invalidate_multiple_data_lines(addr_tab, 64); + memcpy(vec_overlay_start, addr_tab, 64); + rtems_cache_flush_multiple_data_lines(vec_overlay_start, 64); + rtems_cache_invalidate_multiple_instruction_lines(vec_overlay_start, 64); #if 0 { diff --git a/bsps/arm/tms570/start/tms570_selftest.c b/bsps/arm/tms570/start/tms570_selftest.c index 6f3e553acd..99b8718a4a 100644 --- a/bsps/arm/tms570/start/tms570_selftest.c +++ b/bsps/arm/tms570/start/tms570_selftest.c @@ -1,11 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 selftest support functions implementation. + * @brief This source file contains the selftest support implementation. */ + /* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -46,6 +51,32 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_hwinit.h> +/* + * According to the TMS570LS3137 (HCLK max 180MHz, VCLK max 100MHz) and + * TMS570LC4357 (GCLK1 max 300MHz, VCLK max 110MHz, HCLK max 150MHz) + * datasheets, the PBIST ROM clock frequency is limited to 90MHz. + * + * For LS3137 PBIST ROM clock frequency = HCLK / (1 << MSTGCR[9:8]) + * + * For LC4357 PBIST ROM clock frequency = GCLK1 / (1 << MSTGCR[9:8]) + */ +#if TMS570_VARIANT == 4357 +#define MSTGCR_ENABLE_MEMORY_SELF_TEST 0x0000020a +#define MSTGCR_DISABLE_MEMORY_SELF_TEST 0x00000205 +#define PBIST_RESET_DELAY (64 * 4) +#else +#define MSTGCR_ENABLE_MEMORY_SELF_TEST 0x0000010a +#define MSTGCR_DISABLE_MEMORY_SELF_TEST 0x00000105 +#define PBIST_RESET_DELAY (32 * 2) +#endif + +static void tms570_pbist_reset_delay( void ) +{ + for ( int i = 0; i < PBIST_RESET_DELAY; ++i ) { + __asm__ volatile ( "" ); + } +} + /** * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest). / @@ -229,7 +260,6 @@ uint32_t tms570_efc_check( void ) /* Requirements : HL_SR399 */ void tms570_pbist_self_check( void ) { - volatile uint32_t i = 0U; uint32_t PBIST_wait_done_loop = 0U; /* Run a diagnostic check on the memory self-test controller */ @@ -238,15 +268,14 @@ void tms570_pbist_self_check( void ) /* Disable PBIST clocks and ROM clock */ TMS570_PBIST.PACT = 0x0U; - /* PBIST ROM clock frequency = HCLK frequency /2 */ /* Disable memory self controller */ - TMS570_SYS1.MSTGCR = 0x00000105U; + TMS570_SYS1.MSTGCR = MSTGCR_DISABLE_MEMORY_SELF_TEST; /* Disable Memory Initialization controller */ TMS570_SYS1.MINITGCR = 0x5U; /* Enable memory self controller */ - TMS570_SYS1.MSTGCR = 0x0000010AU; + TMS570_SYS1.MSTGCR = MSTGCR_ENABLE_MEMORY_SELF_TEST; /* Clear PBIST Done */ TMS570_SYS1.MSTCGSTAT = 0x1U; @@ -254,14 +283,10 @@ void tms570_pbist_self_check( void ) /* Enable PBIST controller */ TMS570_SYS1.MSIENA = 0x1U; - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ - } + tms570_pbist_reset_delay(); /* Enable PBIST clocks and ROM clock */ - TMS570_PBIST.PACT = 0x3U; + TMS570_PBIST.PACT = 0x1U; /* CPU control of PBIST */ TMS570_PBIST.DLR = 0x10U; @@ -328,11 +353,8 @@ void tms570_pbist_run( uint32_t algomask ) { - volatile uint32_t i = 0U; - - /* PBIST ROM clock frequency = HCLK frequency /2 */ /* Disable memory self controller */ - TMS570_SYS1.MSTGCR = 0x00000105U; + TMS570_SYS1.MSTGCR = MSTGCR_DISABLE_MEMORY_SELF_TEST; /* Disable Memory Initialization controller */ TMS570_SYS1.MINITGCR = 0x5U; @@ -341,16 +363,12 @@ void tms570_pbist_run( TMS570_SYS1.MSIENA = 0x1U; /* Enable memory self controller */ - TMS570_SYS1.MSTGCR = 0x0000010AU; + TMS570_SYS1.MSTGCR = MSTGCR_ENABLE_MEMORY_SELF_TEST; - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ - } + tms570_pbist_reset_delay(); /* Enable PBIST clocks and ROM clock */ - TMS570_PBIST.PACT = 0x3U; + TMS570_PBIST.PACT = 0x1U; /* Select all algorithms to be tested */ TMS570_PBIST.ALGO = algomask; @@ -424,6 +442,33 @@ bool tms570_pbist_is_test_passed( void ) } /** + * Helper method that will run a pbist test and blocks until it finishes + * Reduces code duplication in start system start hooks + */ +void tms570_pbist_run_and_check(uint32_t raminfoL, uint32_t algomask) +{ + /* Run PBIST on region */ + tms570_pbist_run(raminfoL, algomask); + + /* Wait for PBIST for region to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while (!tms570_pbist_is_test_completed()) { + } /* Wait */ + + /* Check if PBIST on region passed the self-test */ + if (!tms570_pbist_is_test_passed()) { + /* PBIST and region failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + tms570_pbist_fail(); + } + + /* Disable PBIST clocks and disable memory self-test mode */ + tms570_pbist_stop(); +} + +/** * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus) * @param[in] port - Select the port to get the status. * @return 1 if PBIST Port test completed successfully, otherwise 0. @@ -490,21 +535,27 @@ void tms570_pbist_fail( void ) /* SourceId : SELFTEST_SourceId_002 */ /* DesignId : SELFTEST_DesignId_004 */ /* Requirements : HL_SR396 */ -void tms570_memory_init( uint32_t ram ) +__attribute__((__naked__)) void tms570_memory_init( uint32_t ram ) { - /* Enable Memory Hardware Initialization */ - TMS570_SYS1.MINITGCR = 0xAU; - - /* Enable Memory Hardware Initialization for selected RAM's */ - TMS570_SYS1.MSIENA = ram; - - /* Wait until Memory Hardware Initialization complete */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) { - } /* Wait */ - - /* Disable Memory Hardware Initialization */ - TMS570_SYS1.MINITGCR = 0x5U; + __asm__ volatile ( + /* Load memory controller base address */ + "ldr r1, =#0xffffff00\n" + /* Enable Memory Hardware Initialization (MINITGCR) */ + "movs r2, #0xa\n" + "str r2, [r1, #0x5c]\n" + /* Enable Memory Hardware Initialization for selected RAM's (MSIENA) */ + "str r0, [r1, #0x60]\n" + /* Wait until Memory Hardware Initialization completes (MSTCGSTAT) */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + "1: ldr r2, [r1, #0x68]\n" + "tst r2, #0x100\n" + "beq 1b\n" + /* Disable Memory Hardware Initialization (MINITGCR) */ + "movs r2, #0x5\n" + "str r2, [r1, #0x5c]\n" + /* Return */ + "bx lr\n" + ); } volatile uint32_t *const diff --git a/bsps/arm/tms570/start/tms570_selftest_par_can.c b/bsps/arm/tms570/start/tms570_selftest_par_can.c index 7f622c38a8..65c7348763 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_can.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_can.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Test CAN module parity based protection logic to work. + * @brief This source file contains the CAN module parity based protection + * support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c b/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c index 0acac1f0e6..67ed1a978b 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Test MibSPI module parity based protection logic to work. + * @brief This source file contains the MibSPI module parity based protection + * support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_par_std.c b/bsps/arm/tms570/start/tms570_selftest_par_std.c index 60bc35d422..da82f47a94 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_std.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_std.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Generic parity based protection logic check applicable to HETx, HTUx, ADC, DMA and VIM. + * @brief This source file contains the HETx, HTUx, ADC, DMA and VIM module + * parity based protection support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_parity.c b/bsps/arm/tms570/start/tms570_selftest_parity.c index 8152180eee..0ceec446d3 100644 --- a/bsps/arm/tms570/start/tms570_selftest_parity.c +++ b/bsps/arm/tms570/start/tms570_selftest_parity.c @@ -1,21 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Check of module parity based protection logic to work. + * @brief This source file contains parts of the parity based protection + * support. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_sys_core.S b/bsps/arm/tms570/start/tms570_sys_core.S index de44cf0d10..83dee26ec8 100644 --- a/bsps/arm/tms570/start/tms570_sys_core.S +++ b/bsps/arm/tms570/start/tms570_sys_core.S @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the parts of the system initialization. + */ + /*-------------------------------------------------------------------------- tms570_sys_core.S @@ -572,4 +582,206 @@ _errata_CORTEXR4_66_: mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register pop {r0} bx lr + /*-------------------------------------------------------------------------------*/ +@ Initialize Mpu: pulled from LC4357 R5f Halcogen generation + + .weak _mpuInit_ + .type _mpuInit_, %function + +_mpuInit_: + @ Disable mpu + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + @ Disable background region + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + @ Setup region 1 + mov r0, #0 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r1Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1000 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 2 + mov r0, #1 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r2Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0002 + orr r0, r0, #0x0600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 3 - Internal RAM + mov r0, #2 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r3Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x000B + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 4 + mov r0, #3 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r4Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 5 + mov r0, #4 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r5Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0000 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1B << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 6 - EMIF CS0 == External SDRAM + mov r0, #5 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r6Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0002 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 7 + mov r0, #6 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r7Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 8 + mov r0, #7 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r8Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 9 + mov r0, #8 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r9Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 10 + mov r0, #9 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r10Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x000C + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 11 + mov r0, #10 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r11Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x0600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 12 + mov r0, #11 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r12Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 13 + mov r0, #12 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r13Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 14 + mov r0, #13 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r14Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 15 + mov r0, #14 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r15Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 16 + mov r0, #15 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r16Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + + @ Enable mpu + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + bx lr + +r1Base: .word 0x00000000 +r2Base: .word 0x00000000 +r3Base: .word 0x08000000 +r4Base: .word 0xF8000000 +r5Base: .word 0x60000000 +r6Base: .word 0x80000000 +r7Base: .word 0xF0000000 +r8Base: .word 0x00000000 +r9Base: .word 0x00000000 +r10Base: .word 0x00000000 +r11Base: .word 0x00000000 +r12Base: .word 0x00000000 +r13Base: .word 0x00000000 +r14Base: .word 0x00000000 +r15Base: .word 0x00000000 +r16Base: .word 0xFFF80000 diff --git a/bsps/arm/tms570/start/tms570_tcram_tests.c b/bsps/arm/tms570/start/tms570_tcram_tests.c index e920717cd8..edfd441874 100644 --- a/bsps/arm/tms570/start/tms570_tcram_tests.c +++ b/bsps/arm/tms570/start/tms570_tcram_tests.c @@ -1,26 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TCRAM selftest function. + * @brief This source file contains TCRAM selftest functions. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * * Algorithms are based on Ti manuals and Ti HalCoGen generated * code available under following copyright. - */ -/* + * * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -59,6 +57,8 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_hwinit.h> +#if TMS570_VARIANT == 3137 + #define tcramA1bitError (*(volatile uint32_t *)(0x08400000U)) #define tcramA2bitError (*(volatile uint32_t *)(0x08400010U)) @@ -183,3 +183,5 @@ void tms570_check_tcram_ecc( void ) tcramA2bit = tcramA2_bk; tcramB2bit = tcramB2_bk; } + +#endif /* TMS570_VARIANT */ |