diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h | 214 |
1 files changed, 128 insertions, 86 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h index 35c00f2535..dcdd688031 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -65,7 +64,10 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] = */ /* Private macros ------------------------------------------------------------*/ - +/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros + * @ingroup RTEMSBSPsARMSTM32H7 + * @{ + */ /** * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. @@ -75,6 +77,9 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] = */ #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) @@ -139,7 +144,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + This parameter can be a value of @ref DMAMUX1_Request_selection This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ @@ -500,7 +505,7 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); } @@ -522,7 +527,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); } @@ -544,7 +549,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); } @@ -581,7 +586,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, @@ -609,7 +614,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); } @@ -634,7 +639,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); } @@ -661,7 +666,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); } @@ -687,7 +692,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); } @@ -712,7 +717,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); } @@ -736,7 +741,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); } @@ -761,7 +766,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); } @@ -785,7 +790,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); } @@ -811,7 +816,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); } @@ -836,7 +841,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); } @@ -862,7 +867,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); } @@ -887,7 +892,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); } @@ -912,7 +917,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); } @@ -936,7 +941,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); } @@ -963,7 +968,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); } @@ -989,7 +994,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); } @@ -1011,7 +1016,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 */ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); } @@ -1033,7 +1038,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); } @@ -1058,7 +1063,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_ */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); } @@ -1082,7 +1087,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); } @@ -1176,7 +1181,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMAMUX1_REQ_USART6_TX * @arg @ref LL_DMAMUX1_REQ_I2C3_RX * @arg @ref LL_DMAMUX1_REQ_I2C3_TX - * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) * @arg @ref LL_DMAMUX1_REQ_CRYP_IN * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT * @arg @ref LL_DMAMUX1_REQ_HASH_IN @@ -1190,8 +1195,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMAMUX1_REQ_SPI5_TX * @arg @ref LL_DMAMUX1_REQ_SAI1_A * @arg @ref LL_DMAMUX1_REQ_SAI1_B - * @arg @ref LL_DMAMUX1_REQ_SAI2_A - * @arg @ref LL_DMAMUX1_REQ_SAI2_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT @@ -1218,9 +1223,28 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) - * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) - * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * * @note (*) Availability depends on devices. * @retval None */ @@ -1319,7 +1343,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMAMUX1_REQ_USART6_TX * @arg @ref LL_DMAMUX1_REQ_I2C3_RX * @arg @ref LL_DMAMUX1_REQ_I2C3_TX - * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) * @arg @ref LL_DMAMUX1_REQ_CRYP_IN * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT * @arg @ref LL_DMAMUX1_REQ_HASH_IN @@ -1333,8 +1357,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMAMUX1_REQ_SPI5_TX * @arg @ref LL_DMAMUX1_REQ_SAI1_A * @arg @ref LL_DMAMUX1_REQ_SAI1_B - * @arg @ref LL_DMAMUX1_REQ_SAI2_A - * @arg @ref LL_DMAMUX1_REQ_SAI2_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT @@ -1361,9 +1385,28 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) - * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) - * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * * @note (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) @@ -1393,7 +1436,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St */ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); } @@ -1419,7 +1462,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); } @@ -1446,7 +1489,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); } @@ -1472,7 +1515,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); } @@ -1497,7 +1540,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); } @@ -1521,7 +1564,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); } @@ -1543,7 +1586,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); } @@ -1565,7 +1608,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S */ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); } @@ -1593,7 +1636,7 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); } @@ -1615,7 +1658,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); } @@ -1637,7 +1680,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); } @@ -1664,7 +1707,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); } @@ -1690,7 +1733,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); } @@ -1721,7 +1764,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); } @@ -1751,7 +1794,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 */ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) @@ -1787,7 +1830,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); } @@ -1812,7 +1855,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); } @@ -1835,7 +1878,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); } @@ -1858,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); } @@ -1883,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); } @@ -1908,7 +1951,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); } @@ -1931,7 +1974,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); } @@ -1954,7 +1997,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); } @@ -1977,7 +2020,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str */ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); } @@ -1999,7 +2042,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream */ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); } @@ -2919,7 +2962,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); } @@ -2941,7 +2984,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); } @@ -2963,7 +3006,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); } @@ -2985,7 +3028,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); } @@ -3007,7 +3050,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); } @@ -3029,7 +3072,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); } @@ -3051,7 +3094,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); } @@ -3073,7 +3116,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); } @@ -3095,7 +3138,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); } @@ -3117,13 +3160,13 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); } /** - * @brief Check if Half transfer interrup is enabled. + * @brief Check if Half transfer interrupt is enabled. * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -3139,7 +3182,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); } @@ -3161,13 +3204,13 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); } /** - * @brief Check if Transfer complete interrup is enabled. + * @brief Check if Transfer complete interrupt is enabled. * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -3183,7 +3226,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); } @@ -3205,13 +3248,13 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); } /** - * @brief Check if FIFO error interrup is enabled. + * @brief Check if FIFO error interrupt is enabled. * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -3227,7 +3270,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); } @@ -3271,4 +3314,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif /* __STM32H7xx_LL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |