diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h')
-rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h | 125 |
1 files changed, 80 insertions, 45 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h index 32a76b1767..8f7223f3cd 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -239,11 +238,11 @@ typedef struct * Scale 2 mode. * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output * Scale 3 mode. - * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, - * configuring Voltage Scale 0 is only possible when Vcore is supplied - * from LDO (Low DropOut). The SYSCFG Clock must be enabled through - * __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale - * 0 using __HAL_PWR_VOLTAGESCALING_CONFIG(). + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0 using + * __HAL_PWR_VOLTAGESCALING_CONFIG(). * Transition to Voltage Scale 0 is only possible when the system is * already in Voltage Scale 1. * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 @@ -256,16 +255,18 @@ typedef struct * low power mode. * @retval None. */ -#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ +#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ do { \ __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ /* Delay after setting the voltage scaling */ \ tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ UNUSED(tmpreg); \ } while(0) -#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */ +#else /* 3 power domains devices */ +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ do { \ __IO uint32_t tmpreg = 0x00; \ @@ -294,7 +295,18 @@ do { \ } \ UNUSED(tmpreg); \ } while(0) -#endif /* PWR_SRDCR_VOS */ +#else /* STM32H72xxx and STM32H73xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#endif /* defined(SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ /** @brief Check PWR flags are set or not. * @param __FLAG__ : Specifies the flag to check. @@ -367,10 +379,10 @@ do { \ * family except STM32H7Axxx and STM32H7Bxxx lines. * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and * STM32H7Bxxx lines. - * The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742, - * STM32H750, STM32H7Axx and STM32H7Bxx lines. - * The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ, - * STM32H7BxxQ lines. + * The PWR_FLAG_SCUEN flag is used for devices that support only LDO + * regulator. + * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO + * and SMPS regulators. * @retval The (__FLAG__) state (TRUE or FALSE). */ #if defined (DUAL_CORE) /* Dual core lines */ @@ -397,7 +409,25 @@ do { \ ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) #else /* Single core lines */ -#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */ +#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ +#if defined (SMPS) /* STM32H725 and STM32H735 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ #define __HAL_PWR_GET_FLAG(__FLAG__) \ (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ @@ -414,9 +444,10 @@ do { \ ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* defined (SMPS) */ #else /* STM32H7Axxx and STM32H7Bxxx lines */ -#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */ -#define __HAL_PWR_GET_FLAG(__FLAG__) \ +#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ @@ -431,8 +462,8 @@ do { \ ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) -#else /* STM32H7Axx and STM32H7Bxx LDO lines */ -#define __HAL_PWR_GET_FLAG(__FLAG__) \ +#else /* STM32H7Axx and STM32H7Bxx lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ @@ -460,6 +491,8 @@ do { \ * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. * @retval The (__FLAG__) state (TRUE or FALSE). */ #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) @@ -486,8 +519,9 @@ do { \ * @note This parameter is not used for the STM32H7 family and is kept as * parameter just to maintain compatibility with other families. * @note This macro clear all CPU flags. - * For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF. - * For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx. + * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU + * flags are STOPF, SBF, SBF_D1 and SBF_D2. + * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. * @retval None. */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) @@ -502,6 +536,8 @@ do { \ * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. * @retval None. */ #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) @@ -651,44 +687,44 @@ do { \ * @{ */ -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); +void HAL_PWR_DeInit (void); +void HAL_PWR_EnableBkUpAccess (void); +void HAL_PWR_DisableBkUpAccess (void); /** * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions * @{ */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD (void); +void HAL_PWR_DisablePVD (void); /* WakeUp pins configuration */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); /* Low Power modes entry */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode (void); /* Power PVD IRQ Handler */ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); +void HAL_PWR_PVD_IRQHandler (void); +void HAL_PWR_PVDCallback (void); /* Cortex System Control functions *******************************************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); +void HAL_PWR_EnableSleepOnExit (void); +void HAL_PWR_DisableSleepOnExit (void); +void HAL_PWR_EnableSEVOnPend (void); +void HAL_PWR_DisableSEVOnPend (void); /** * @} */ @@ -786,4 +822,3 @@ void HAL_PWR_DisableSEVOnPend(void); #endif /* STM32H7xx_HAL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |