diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h | 359 |
1 files changed, 179 insertions, 180 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h index d9f493b2f7..7467897d8a 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,52 +48,49 @@ */ typedef struct { - uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt - indicating that data are available in reception or free place - is available in transmission. - This parameter can be a value between 1 and 32 */ - uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to - quad mode on two different devices to increase the throughput. - This parameter can be a value of @ref OSPI_DualQuad */ - uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. - This parameter can be a value of @ref OSPI_MemoryType */ - uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, - it corresponds to the number of address bits required to access - the external device. - This parameter can be a value between 1 and 32 */ - uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select - must remain high between commands. - This parameter can be a value between 1 and 8 */ - uint32_t FreeRunningClock; /* It enables or not the free running clock. - This parameter can be a value of @ref OSPI_FreeRunningClock */ - uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. - This parameter can be a value of @ref OSPI_ClockMode */ - uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. - This parameter can be a value of @ref OSPI_WrapSize */ - uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating - the external clock based on the AHB clock. - This parameter can be a value between 1 and 256 */ - uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order - to take in account external signal delays. - This parameter can be a value of @ref OSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. - This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ - uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and - defines the boundary of bytes to release the chip select. - This parameter can be a value between 0 and 31 */ - uint32_t ClkChipSelectHighTime; /* It defines the number of clocks provided on the CLK/nCLK pins when - the chip select is set to high at the end of a transaction. - This parameter can be a value between 0 and 7 */ - uint32_t DelayBlockBypass; /* It enables the delay block bypass, so the sampling is not affected - by the delay block. - This parameter can be a value of @ref OSPI_DelayBlockBypass */ - uint32_t MaxTran; /* It enables the communication regulation feature. The chip select is - released every MaxTran+1 bytes when the other OctoSPI request the access - to the bus. - This parameter can be a value between 0 and 255 */ - uint32_t Refresh; /* It enables the refresh rate feature. The chip select is released every - Refresh+1 clock cycles. - This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + This parameter can be a value between 1 and 32 */ + uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to + quad mode on two different devices to increase the throughput. + This parameter can be a value of @ref OSPI_DualQuad */ + uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. + This parameter can be a value of @ref OSPI_MemoryType */ + uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value between 1 and 32 */ + uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 8 */ + uint32_t FreeRunningClock; /*!< It enables or not the free running clock. + This parameter can be a value of @ref OSPI_FreeRunningClock */ + uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref OSPI_ClockMode */ + uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref OSPI_WrapSize */ + uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 1 and 256 */ + uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref OSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value between 0 and 31 */ + uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected + by the delay block. + This parameter can be a value of @ref OSPI_DelayBlockBypass */ + uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is + released every MaxTran+1 bytes when the other OctoSPI request the access + to the bus. + This parameter can be a value between 0 and 255 */ + uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every + Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ }OSPI_InitTypeDef; /** @@ -104,17 +100,17 @@ typedef struct typedef struct __OSPI_HandleTypeDef #else typedef struct -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ { - OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ - OSPI_InitTypeDef Init; /* OSPI initialization parameters */ - uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ - __IO uint32_t XferSize; /* Number of data to transfer */ - __IO uint32_t XferCount; /* Counter of data transferred */ - MDMA_HandleTypeDef *hmdma; /* Handle of the MDMA channel used for the transfer */ - __IO uint32_t State; /* Internal state of the OSPI HAL driver */ - __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ - uint32_t Timeout; /* Timeout used for the OSPI external device access */ + OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ + OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ + uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ + __IO uint32_t XferSize; /*!< Number of data to transfer */ + __IO uint32_t XferCount; /*!< Counter of data transferred */ + MDMA_HandleTypeDef *hmdma; /*!< Handle of the MDMA channel used for the transfer */ + __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ + __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ + uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); @@ -129,7 +125,7 @@ typedef struct void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ }OSPI_HandleTypeDef; /** @@ -137,50 +133,50 @@ typedef struct */ typedef struct { - uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or - to the registers for the write operation (these registers are only - used for memory-mapped mode). - This parameter can be a value of @ref OSPI_OperationType */ - uint32_t FlashId; /* It indicates which external device is selected for this command (it - applies only if Dualquad is disabled in the initialization structure). - This parameter can be a value of @ref OSPI_FlashId */ - uint32_t Instruction; /* It contains the instruction to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t InstructionMode; /* It indicates the mode of the instruction. - This parameter can be a value of @ref OSPI_InstructionMode */ - uint32_t InstructionSize; /* It indicates the size of the instruction. - This parameter can be a value of @ref OSPI_InstructionSize */ - uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. - This parameter can be a value of @ref OSPI_InstructionDtrMode */ - uint32_t Address; /* It contains the address to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressMode; /* It indicates the mode of the address. - This parameter can be a value of @ref OSPI_AddressMode */ - uint32_t AddressSize; /* It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. - This parameter can be a value of @ref OSPI_AddressDtrMode */ - uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesMode */ - uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesSize */ - uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. - This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ - uint32_t DataMode; /* It indicates the mode of the data. - This parameter can be a value of @ref OSPI_DataMode */ - uint32_t NbData; /* It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF */ - uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. - This parameter can be a value of @ref OSPI_DataDtrMode */ - uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. - This parameter can be a value between 0 and 31 */ - uint32_t DQSMode; /* It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ - uint32_t SIOOMode; /* It enables or not the SIOO mode. - This parameter can be a value of @ref OSPI_SIOOMode */ + uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref OSPI_OperationType */ + uint32_t FlashId; /*!< It indicates which external device is selected for this command (it + applies only if Dualquad is disabled in the initialization structure). + This parameter can be a value of @ref OSPI_FlashID */ + uint32_t Instruction; /*!< It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t InstructionMode; /*!< It indicates the mode of the instruction. + This parameter can be a value of @ref OSPI_InstructionMode */ + uint32_t InstructionSize; /*!< It indicates the size of the instruction. + This parameter can be a value of @ref OSPI_InstructionSize */ + uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref OSPI_InstructionDtrMode */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /*!< It indicates the mode of the address. + This parameter can be a value of @ref OSPI_AddressMode */ + uint32_t AddressSize; /*!< It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref OSPI_AddressDtrMode */ + uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesMode */ + uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesSize */ + uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ + uint32_t DataMode; /*!< It indicates the mode of the data. + This parameter can be a value of @ref OSPI_DataMode */ + uint32_t NbData; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF */ + uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref OSPI_DataDtrMode */ + uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t SIOOMode; /*!< It enables or not the SIOO mode. + This parameter can be a value of @ref OSPI_SIOOMode */ }OSPI_RegularCmdTypeDef; /** @@ -188,14 +184,14 @@ typedef struct */ typedef struct { - uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. - This parameter can be a value between 0 and 255 */ - uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. - This parameter can be a value between 0 and 255 */ - uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. - This parameter can be a value of @ref OSPI_WriteZeroLatency */ - uint32_t LatencyMode; /* It configures the latency mode. - This parameter can be a value of @ref OSPI_LatencyMode */ + uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255 */ + uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. + This parameter can be a value between 0 and 255 */ + uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. + This parameter can be a value of @ref OSPI_WriteZeroLatency */ + uint32_t LatencyMode; /*!< It configures the latency mode. + This parameter can be a value of @ref OSPI_LatencyMode */ }OSPI_HyperbusCfgTypeDef; /** @@ -203,18 +199,18 @@ typedef struct */ typedef struct { - uint32_t AddressSpace; /* It indicates the address space accessed by the command. - This parameter can be a value of @ref OSPI_AddressSpace */ - uint32_t Address; /* It contains the address to be sent tot he device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressSize; /* It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t NbData; /* It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF - In case of autopolling mode, this parameter can be any value between 1 and 4 */ - uint32_t DQSMode; /* It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. + This parameter can be a value of @ref OSPI_AddressSpace */ + uint32_t Address; /*!< It contains the address to be sent tot he device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressSize; /*!< It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t NbData; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be any value between 1 and 4 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ }OSPI_HyperbusCmdTypeDef; /** @@ -222,16 +218,16 @@ typedef struct */ typedef struct { - uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t MatchMode; /* Specifies the method used for determining a match. - This parameter can be a value of @ref OSPI_MatchMode */ - uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. - This parameter can be a value of @ref OSPI_AutomaticStop */ - uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. - This parameter can be any value between 0 and 0xFFFF */ + uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t MatchMode; /*!< Specifies the method used for determining a match. + This parameter can be a value of @ref OSPI_MatchMode */ + uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref OSPI_AutomaticStop */ + uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF */ }OSPI_AutoPollingTypeDef; /** @@ -239,10 +235,10 @@ typedef struct */ typedef struct { - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. - This parameter can be a value of @ref OSPI_TimeOutActivation */ - uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. - This parameter can be any value between 0 and 0xFFFF */ + uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref OSPI_TimeOutActivation */ + uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ }OSPI_MemoryMappedTypeDef; /** @@ -250,19 +246,19 @@ typedef struct */ typedef struct { - uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. - This parameter can be a value between 1 and 8 */ - uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. - This parameter can be a value between 1 and 8 */ - uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. - This parameter can be a value between 1 and 8 */ - uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected - if some signals are multiplexed in the OSPI IO Manager with the other OSPI. - This parameter can be a value between 1 and 256 */ + uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. + This parameter can be a value between 1 and 8 */ + uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. + This parameter can be a value between 0 and 8, 0 means that signal not used */ + uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. + This parameter can be a value between 1 and 8 */ + uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected + if some signals are multiplexed in the OSPI IO Manager with the other OSPI. + This parameter can be a value between 1 and 256 */ }OSPIM_CfgTypeDef; #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) @@ -290,7 +286,7 @@ typedef enum * @brief HAL OSPI Callback pointer definition */ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** * @} */ @@ -334,7 +330,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ /** * @} */ @@ -695,6 +691,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ +#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ @@ -735,7 +732,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); } while(0) #else #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** @brief Enable the OSPI peripheral. * @param __HANDLE__ specifies the OSPI Handle. @@ -787,7 +784,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ + == (__INTERRUPT__)) /** * @brief Check whether the selected OSPI flag is set or not. @@ -802,7 +800,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag * @retval None */ -#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ + != 0U) ? SET : RESET) /** @brief Clears the specified OSPI's flag status. * @param __HANDLE__ specifies the OSPI Handle. @@ -846,22 +845,22 @@ void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); /* OSPI command configuration functions */ -HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); -HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); /* OSPI indirect mode functions */ -HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); /* OSPI status flag polling mode functions */ -HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); +HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); /* OSPI memory-mapped mode functions */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); @@ -886,9 +885,10 @@ void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /* OSPI callback registering/unregistering */ -HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); -#endif +HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, + pOSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** * @} */ @@ -913,7 +913,7 @@ uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); /** @addtogroup OSPI_Exported_Functions_Group4 * @{ */ -HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); /** * @} @@ -1062,8 +1062,6 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) -#define IS_OSPI_CKCSHT(CLK_NB) ((CLK_NB) <= 7U) - #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) @@ -1071,7 +1069,10 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) -#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ +#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) + +#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ + ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ @@ -1110,5 +1111,3 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #endif #endif /* STM32H7xx_HAL_OSPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |