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Diffstat (limited to 'bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c')
-rw-r--r--bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c197
1 files changed, 110 insertions, 87 deletions
diff --git a/bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c b/bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c
index c7cea3e7d4..89af591d86 100644
--- a/bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c
+++ b/bsps/arm/stm32h7/hal/stm32h7xx_ll_rcc.c
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
@@ -22,9 +20,9 @@
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
+#include "stm32_assert.h"
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32H7xx_LL_Driver
@@ -39,7 +37,14 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Variables
+ * @{
+ */
const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCC_LL_Private_Macros
@@ -56,16 +61,20 @@ const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
|| ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
-#if defined(LL_RCC_SAI4A_CLKSOURCE)
+#if defined(SAI3)
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
+#elif defined(SAI4)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
#else
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
-#endif /* LL_RCC_SAI4A_CLKSOURCE */
+#endif /* SAI3 */
#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
@@ -80,12 +89,12 @@ const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
* @ingroup RTEMSBSPsARMSTM32H7
* @{
*/
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
/**
* @}
@@ -116,30 +125,37 @@ uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
*/
void LL_RCC_DeInit(void)
{
+ /* Increasing the CPU frequency */
+ if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
/* Set HSION bit */
SET_BIT(RCC->CR, RCC_CR_HSION);
/* Wait for HSI READY bit */
- while(LL_RCC_HSI_IsReady() == 0U)
+ while (LL_RCC_HSI_IsReady() == 0U)
{}
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
- |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
+ | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
/* Wait for PLL1 READY bit to be reset */
- while(LL_RCC_PLL1_IsReady() != 0U)
+ while (LL_RCC_PLL1_IsReady() != 0U)
{}
/* Wait for PLL2 READY bit to be reset */
- while(LL_RCC_PLL2_IsReady() != 0U)
+ while (LL_RCC_PLL2_IsReady() != 0U)
{}
/* Wait for PLL3 READY bit to be reset */
- while(LL_RCC_PLL3_IsReady() != 0U)
+ while (LL_RCC_PLL3_IsReady() != 0U)
{}
#if defined(RCC_D1CFGR_HPRE)
@@ -164,7 +180,7 @@ void LL_RCC_DeInit(void)
#endif /* RCC_D1CFGR_HPRE */
/* Reset PLLCKSELR register to default value */
- RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+ RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
/* Reset PLLCFGR register to default value */
LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
@@ -195,11 +211,19 @@ void LL_RCC_DeInit(void)
/* Clear all interrupts */
SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
- | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
- | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
+ | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
+ | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
/* Clear reset source flags */
SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
}
/**
@@ -280,7 +304,7 @@ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
case LL_RCC_PLLSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -354,7 +378,7 @@ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
case LL_RCC_PLLSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -428,7 +452,7 @@ void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
case LL_RCC_PLLSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -498,9 +522,9 @@ uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N,
{
float_t freq;
- freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
+ freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
- freq = freq/(float_t)PQR;
+ freq = freq / (float_t)PQR;
return (uint32_t)freq;
}
@@ -524,11 +548,11 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
switch (LL_RCC_GetUSARTClockSource(USARTxSource))
{
case LL_RCC_USART16_CLKSOURCE_PCLK2:
- usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_USART234578_CLKSOURCE_PCLK1:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_USART16_CLKSOURCE_PLL2Q:
@@ -553,7 +577,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
case LL_RCC_USART234578_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -596,7 +620,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
{
case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
- lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
@@ -618,7 +642,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
case LL_RCC_LPUART1_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -663,11 +687,11 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
switch (LL_RCC_GetI2CClockSource(I2CxSource))
{
case LL_RCC_I2C123_CLKSOURCE_PCLK1:
- i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_I2C4_CLKSOURCE_PCLK4:
- i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_I2C123_CLKSOURCE_PLL3R:
@@ -683,7 +707,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
case LL_RCC_I2C4_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -723,12 +747,12 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
{
case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
- lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
- lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
@@ -811,14 +835,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
- case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
-#endif /* (SAI4_Block_A) || (SAI4_Block_B) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL1_IsReady() != 0U)
{
LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
@@ -830,14 +854,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL2P:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
- case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL2_IsReady() != 0U)
{
LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
@@ -849,14 +873,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL3P:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
- case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL3_IsReady() != 0U)
{
LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
@@ -868,14 +892,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
+ case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
- case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
sai_frequency = EXTERNAL_CLOCK_VALUE;
break;
@@ -883,14 +907,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_CLKP:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_CLKP:
+ case LL_RCC_SAI4B_CLKSOURCE_CLKP:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_CLKP:
case LL_RCC_SAI2B_CLKSOURCE_CLKP:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_CLKP:
- case LL_RCC_SAI4B_CLKSOURCE_CLKP:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
break;
@@ -1139,7 +1163,7 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
break;
case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
- dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
default:
@@ -1171,7 +1195,7 @@ uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
break;
case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
- dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
default:
@@ -1261,7 +1285,7 @@ uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
case LL_RCC_SPDIF_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -1328,11 +1352,11 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
break;
case LL_RCC_SPI45_CLKSOURCE_PCLK2:
- spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_SPI6_CLKSOURCE_PCLK4:
- spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
@@ -1357,7 +1381,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
case LL_RCC_SPI6_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -1399,13 +1423,13 @@ uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
switch (LL_RCC_GetSWPClockSource(SWPxSource))
{
case LL_RCC_SWP_CLKSOURCE_PCLK1:
- swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+ swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
break;
case LL_RCC_SWP_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -1477,7 +1501,7 @@ uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
switch (LL_RCC_GetFMCClockSource(FMCxSource))
{
case LL_RCC_FMC_CLKSOURCE_HCLK:
- fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+ fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
break;
case LL_RCC_FMC_CLKSOURCE_PLL1Q:
@@ -1524,7 +1548,7 @@ uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
{
case LL_RCC_QSPI_CLKSOURCE_HCLK:
- qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+ qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
break;
case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
@@ -1559,7 +1583,7 @@ uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
#if defined(OCTOSPI1) || defined(OCTOSPI2)
/**
* @brief Return OSPI clock frequency
- * @param QSPIxSource This parameter can be one of the following values:
+ * @param OSPIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_OSPI_CLKSOURCE
* @retval OSPI clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
@@ -1573,7 +1597,7 @@ uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
{
case LL_RCC_OSPI_CLKSOURCE_HCLK:
- ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+ ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
break;
case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
@@ -1621,7 +1645,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
case LL_RCC_CLKP_CLKSOURCE_HSI:
if (LL_RCC_HSI_IsReady() != 0U)
{
- clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
}
break;
@@ -1663,7 +1687,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
-uint32_t RCC_GetSystemClockFreq(void)
+static uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency = 0U;
LL_PLL_ClocksTypeDef PLL_Clocks;
@@ -1673,7 +1697,7 @@ uint32_t RCC_GetSystemClockFreq(void)
{
/* No check on Ready: Won't be selected by hardware if not */
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
- frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+ frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
@@ -1702,7 +1726,7 @@ uint32_t RCC_GetSystemClockFreq(void)
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
@@ -1713,7 +1737,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
@@ -1724,7 +1748,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
@@ -1735,7 +1759,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK3 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK3 clock frequency */
return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
@@ -1746,7 +1770,7 @@ uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK4 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK4 clock frequency */
return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
@@ -1768,4 +1792,3 @@ uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-09 18:58:18 +0000