diff options
Diffstat (limited to 'bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c')
| -rw-r--r-- | bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c | 199 |
1 files changed, 175 insertions, 24 deletions
diff --git a/bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c b/bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c index b458ee26c2..60d1535d6a 100644 --- a/bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c +++ b/bsps/arm/stm32h7/hal/stm32h7xx_hal_flash_ex.c @@ -22,7 +22,7 @@ (+) Global readout protection (RDP) (+) Write protection (+) Secure access only protection - (+) Bank / register swapping + (+) Bank / register swapping (when Dual-Bank) (+) Cyclic Redundancy Check (CRC) ##### How to use this driver ##### @@ -45,6 +45,8 @@ (++) PCROP protection configuration and control per bank (++) Secure area configuration and control per bank (++) Core Boot address configuration + (++) TCM / AXI shared RAM configuration + (++) CPU Frequency Boost configuration (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(), HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions @@ -60,14 +62,12 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -125,12 +125,22 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, #if defined (DUAL_CORE) static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); -#endif /* DUAL_CORE */ +#endif /*DUAL_CORE*/ #if defined (FLASH_OTPBL_LOCKBL) static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); static uint32_t FLASH_OB_OTP_GetLock(void); #endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); +static uint32_t FLASH_OB_SharedRAM_GetConfig(void); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); +static uint32_t FLASH_OB_CPUFreq_GetBoost(void); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ /** * @} */ @@ -191,6 +201,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } } +#if defined (DUAL_BANK) /* Wait for last operation to be completed on Bank2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { @@ -199,6 +210,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t status = HAL_ERROR; } } +#endif /* DUAL_BANK */ if(status == HAL_OK) { @@ -207,7 +219,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Mass erase to be done */ FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed on Bank 1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) @@ -217,6 +229,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* if the erase operation is completed, disable the Bank1 BER Bit */ FLASH->CR1 &= (~FLASH_CR_BER); } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) @@ -226,6 +240,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* if the erase operation is completed, disable the Bank2 BER Bit */ FLASH->CR2 &= (~FLASH_CR_BER); } +#endif /* DUAL_BANK */ } else { @@ -245,6 +260,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* If the erase operation is completed, disable the SER Bit */ FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); } +#if defined (DUAL_BANK) if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Wait for last operation to be completed */ @@ -253,6 +269,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* If the erase operation is completed, disable the SER Bit */ FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); } +#endif /* DUAL_BANK */ if(status != HAL_OK) { @@ -291,7 +308,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed on Bank 1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) @@ -300,6 +317,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) } } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) @@ -307,6 +326,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) status = HAL_ERROR; } } +#endif /* DUAL_BANK */ if (status != HAL_OK) { @@ -326,6 +346,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); #endif /* FLASH_CR_OPERRIE */ } +#if defined (DUAL_BANK) if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Enable End of Operation and Error interrupts for Bank 2 */ @@ -337,6 +358,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); #endif /* FLASH_CR_OPERRIE */ } +#endif /* DUAL_BANK */ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { @@ -345,10 +367,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; } +#if defined (DUAL_BANK) else if(pEraseInit->Banks == FLASH_BANK_2) { pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; } +#endif /* DUAL_BANK */ else { pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; @@ -359,6 +383,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) else { /* Erase by sector to be done */ +#if defined (DUAL_BANK) if(pEraseInit->Banks == FLASH_BANK_1) { pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; @@ -367,6 +392,9 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; } +#else + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; +#endif /* DUAL_BANK */ pFlash.NbSectorsToErase = pEraseInit->NbSectors; pFlash.Sector = pEraseInit->Sector; @@ -382,7 +410,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -405,10 +433,12 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { status = HAL_ERROR; } +#if defined (DUAL_BANK) else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) { status = HAL_ERROR; } +#endif /* DUAL_BANK */ else { status = HAL_OK; @@ -495,6 +525,22 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); } #endif /* FLASH_OTPBL_LOCKBL */ + +#if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + /* TCM / AXI Shared RAM configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + { + FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + } +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + /* CPU Frequency Boost configuration */ + if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + { + FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + } +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ } /* Process Unlocked */ @@ -505,7 +551,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that * contains the configuration information for the programming. * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. @@ -525,7 +571,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get BOR Level*/ pOBInit->BORLevel = FLASH_OB_GetBOR(); +#if defined (DUAL_BANK) if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) +#else + if (pOBInit->Banks == FLASH_BANK_1) +#endif /* DUAL_BANK */ { pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); @@ -556,6 +606,20 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /* Get OTP Block Lock */ pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); #endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + + /* Get TCM / AXI Shared RAM */ + pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + + /* Get CPU Frequency Boost */ + pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ } /** @@ -591,6 +655,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) return HAL_OK; } +#if defined (DUAL_BANK) /** * @brief Unlock the FLASH Bank2 control registers access * @retval HAL Status @@ -623,6 +688,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) SET_BIT(FLASH->CR2, FLASH_CR_LOCK); return HAL_OK; } +#endif /* DUAL_BANK */ /* * @brief Perform a CRC computation on the specified FLASH memory area @@ -697,6 +763,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Clear CRC flags */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); } +#if defined (DUAL_BANK) else { /* Enable CRC feature */ @@ -745,6 +812,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Clear CRC flags */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); } +#endif /* DUAL_BANK */ } return status; @@ -791,6 +859,7 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) #endif /* FLASH_CR_PSIZE */ assert_param(IS_FLASH_BANK(Banks)); +#if defined (DUAL_BANK) /* Flash Mass Erase */ if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) { @@ -808,6 +877,7 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) FLASH->OPTCR |= FLASH_OPTCR_MER; } else +#endif /* DUAL_BANK */ { /* Proceed to erase Flash Bank */ if((Banks & FLASH_BANK_1) == FLASH_BANK_1) @@ -821,6 +891,8 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) /* Erase Bank1 */ FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); } + +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { #if defined (FLASH_CR_PSIZE) @@ -832,6 +904,7 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) /* Erase Bank2 */ FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); } +#endif /* DUAL_BANK */ } } @@ -878,6 +951,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) #endif /* FLASH_CR_PSIZE */ } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { #if defined (FLASH_CR_PSIZE) @@ -892,13 +966,14 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); #endif /* FLASH_CR_PSIZE */ } +#endif /* DUAL_BANK */ } /** * @brief Enable the write protection of the desired bank1 or bank 2 sectors * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All + * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL * * @param Banks the specific bank to apply WRP sectors * This parameter can be one of the following values: @@ -920,18 +995,20 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Enable Write Protection for bank 2 */ FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); } +#endif /* DUAL_BANK */ } /** * @brief Disable the write protection of the desired bank1 or bank 2 sectors * @param WRPSector specifies the sector(s) to disable write protection. * This parameter can be one of the following values: - * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL * * @param Banks the specific bank to apply WRP sectors * This parameter can be one of the following values: @@ -953,11 +1030,13 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Disable Write Protection for bank 2 */ FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); } +#endif /* DUAL_BANK */ } /** @@ -968,7 +1047,7 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) * @param WRPSector gives the write protected sector(s) on the given bank . * This parameter can be one of the following values: - * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL * * @param Bank the specific bank to apply WRP sectors * This parameter can be exclusively one of the following values: @@ -982,15 +1061,17 @@ static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Ba { uint32_t regvalue = 0U; - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->WPSN_CUR1; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->WPSN_CUR2; } +#endif /* DUAL_BANK */ (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; @@ -1203,7 +1284,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); optr_reg_mask |= FLASH_OPTSR_BCM7; } +#endif /* DUAL_CORE */ +#if defined (FLASH_OPTSR_NRST_STOP_D2) if((UserType & OB_USER_NRST_STOP_D2) != 0U) { /* NRST_STOP option byte should be modified */ @@ -1223,7 +1306,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; } -#endif /* DUAL_CORE */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) if((UserType & OB_USER_SWAP_BANK) != 0U) { /* SWAP_BANK_OPT option byte should be modified */ @@ -1233,6 +1318,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; } +#endif /* DUAL_BANK */ if((UserType & OB_USER_IOHSLV) != 0U) { @@ -1329,6 +1415,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, PCROPConfig; } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); @@ -1339,6 +1426,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ PCROPConfig; } +#endif /* DUAL_BANK */ } /** @@ -1364,17 +1452,19 @@ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, u uint32_t regvalue = 0; uint32_t bankBase = 0; - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->PRAR_CUR1; bankBase = FLASH_BANK1_BASE; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->PRAR_CUR2; bankBase = FLASH_BANK2_BASE; } +#endif /* DUAL_BANK */ (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); @@ -1565,6 +1655,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure (SecureAreaConfig & FLASH_SCAR_DMES); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Check the parameters */ @@ -1576,6 +1667,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ (SecureAreaConfig & FLASH_SCAR_DMES); } +#endif /* DUAL_BANK */ } /** @@ -1593,17 +1685,19 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA uint32_t bankBase = 0; /* Check Bank parameter value */ - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->SCAR_CUR1; bankBase = FLASH_BANK1_BASE; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->SCAR_CUR2; bankBase = FLASH_BANK2_BASE; } +#endif /* DUAL_BANK */ /* Get the secure area settings */ (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); @@ -1631,6 +1725,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) /* Select CRC Sector and activate ADD_SECT bit */ FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; } +#if defined (DUAL_BANK) else { /* Clear CRC sector */ @@ -1639,6 +1734,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) /* Select CRC Sector and activate ADD_SECT bit */ FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; } +#endif /* DUAL_BANK */ } /** @@ -1659,6 +1755,7 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, FLASH->CRCSADD1 = CRCStartAddr; FLASH->CRCEADD1 = CRCEndAddr; } +#if defined (DUAL_BANK) else { assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); @@ -1668,6 +1765,7 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, FLASH->CRCSADD2 = CRCStartAddr; FLASH->CRCEADD2 = CRCEndAddr; } +#endif /* DUAL_BANK */ } /** * @} @@ -1700,6 +1798,60 @@ static uint32_t FLASH_OB_OTP_GetLock(void) } #endif /* FLASH_OTPBL_LOCKBL */ +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** + * @brief Configure the TCM / AXI Shared RAM. + * @param SharedRamConfig specifies the Shared RAM configuration. + * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + * @retval None + */ +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig)); + + /* Configure the TCM / AXI Shared RAM in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig); +} + +/** + * @brief Get the TCM / AXI Shared RAM configuration. + * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. + * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + */ +static uint32_t FLASH_OB_SharedRAM_GetConfig(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED); +} +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** + * @brief Configure the CPU Frequency Boost. + * @param FreqBoost specifies the CPU Frequency Boost state. + * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + * @retval None + */ +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost)); + + /* Configure the CPU Frequency Boost in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost); +} + +/** + * @brief Get the CPU Frequency Boost state. + * @retval FreqBoost returns the CPU Frequency Boost state. + * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + */ +static uint32_t FLASH_OB_CPUFreq_GetBoost(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST); +} +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + #endif /* HAL_FLASH_MODULE_ENABLED */ /** @@ -1710,4 +1862,3 @@ static uint32_t FLASH_OB_OTP_GetLock(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |