diff options
Diffstat (limited to '')
25 files changed, 246 insertions, 79 deletions
diff --git a/bsps/arm/shared/cache/cache-cp15.c b/bsps/arm/shared/cache/cache-cp15.c index 4ad9965529..d78ec4feb4 100644 --- a/bsps/arm/shared/cache/cache-cp15.c +++ b/bsps/arm/shared/cache/cache-cp15.c @@ -9,7 +9,7 @@ */ /* - * Copyright (C) 2009, 2018 embedded brains GmbH + * Copyright (C) 2009, 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -200,6 +200,7 @@ static inline void _CPU_cache_disable_instruction(void) rtems_interrupt_local_enable(level); } +#if __ARM_ARCH >= 6 static inline size_t arm_cp15_get_cache_size( uint32_t level, uint32_t which @@ -238,5 +239,30 @@ static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level) { return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION); } +#else +static inline size_t _CPU_cache_get_data_cache_size(uint32_t level) +{ + uint32_t cache_type; + + if (level > 0) { + return 0; + } + + cache_type = arm_cp15_get_cache_type(); + return 1U << (((cache_type >> (12 + 6)) & 0xf) + 9); +} + +static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level) +{ + uint32_t cache_type; + + if (level > 0) { + return 0; + } + + cache_type = arm_cp15_get_cache_type(); + return 1U << (((cache_type >> (0 + 6)) & 0xf) + 9); +} +#endif #include "../../shared/cache/cacheimpl.h" diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h index 0e1297a84d..7f1eb87812 100644 --- a/bsps/arm/shared/cache/cache-cp15.h +++ b/bsps/arm/shared/cache/cache-cp15.h @@ -1,15 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** + * @file + * * @ingroup RTEMSBSPsARMShared * - * @brief Level 1 Cache definitions and functions. - * - * This file implements handling for the ARM Level 1 cache controller + * @brief This header file provides interfaces of the ARM CP15 cache controller + * suppport. */ /* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c index 7bfa1a564c..6826043afd 100644 --- a/bsps/arm/shared/cache/cache-l2c-310.c +++ b/bsps/arm/shared/cache/cache-l2c-310.c @@ -1,9 +1,10 @@ /** - * @ingroup L2C-310_cache + * @file * - * @brief Cache definitions and functions. + * @ingroup L2C310CacheSupport * - * This file implements handling for the ARM L2C-310 cache controller + * @brief This source file contains the implementation of the ARM L2C-310 cache + * controller support. */ /* @@ -96,13 +97,15 @@ #define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) /** - * @defgroup L2C-310_cache Cache Support + * @defgroup L2C310CacheSupport L2C-310 Cache Support + * * @ingroup RTEMSBSPsARMShared - * @brief Cache Functions and Defitions + * + * @brief This group contains the L2C-310 cache support. + * * @{ */ - /** * @brief L2CC Register Offsets */ diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S index a5b4b7a3d1..24baa8c4dc 100644 --- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S +++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2018 embedded brains GmbH + * Copyright (C) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/cache/cache-v7m.c b/bsps/arm/shared/cache/cache-v7m.c index ee68e7f9db..edaf1141ae 100644 --- a/bsps/arm/shared/cache/cache-v7m.c +++ b/bsps/arm/shared/cache/cache-v7m.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * Copyright (c) 2016 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/clock/clock-a9mpcore.c b/bsps/arm/shared/clock/clock-a9mpcore.c index d4c374d4e2..c393933c81 100644 --- a/bsps/arm/shared/clock/clock-a9mpcore.c +++ b/bsps/arm/shared/clock/clock-a9mpcore.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup A9MPCoreSupport + * + * @brief This source file contains the Clock Driver for Cortex-A9 MPCore + * compatible devices. + */ + /* - * Copyright (c) 2013, 2016 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -38,32 +47,33 @@ static struct timecounter a9mpcore_tc; -/* This is defined in dev/clock/clockimpl.h */ -void Clock_isr(rtems_irq_hdl_param arg); - __attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void) { /* default to the BSP option. */ return BSP_ARM_A9MPCORE_PERIPHCLK; } -static void a9mpcore_clock_at_tick(void) +static void a9mpcore_clock_at_tick(volatile a9mpcore_gt *gt) { - volatile a9mpcore_gt *gt = A9MPCORE_GT; - gt->irqst = A9MPCORE_GT_IRQST_EFLG; } -static void a9mpcore_clock_handler_install(void) +static rtems_interrupt_entry a9mpcore_clock_interrupt_entry; + +static void a9mpcore_clock_handler_install(rtems_interrupt_handler handler) { rtems_status_code sc; - sc = rtems_interrupt_handler_install( + rtems_interrupt_entry_initialize( + &a9mpcore_clock_interrupt_entry, + handler, + RTEMS_DEVOLATILE(a9mpcore_gt *, A9MPCORE_GT), + "Clock" + ); + sc = rtems_interrupt_entry_install( A9MPCORE_IRQ_GT, - "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + &a9mpcore_clock_interrupt_entry ); if (sc != RTEMS_SUCCESSFUL) { bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL); @@ -179,14 +189,14 @@ CPU_Counter_ticks _CPU_Counter_read(void) return gt->cntrlower; } -#define Clock_driver_support_at_tick() \ - a9mpcore_clock_at_tick() +#define Clock_driver_support_at_tick(arg) \ + a9mpcore_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() \ a9mpcore_clock_initialize() #define Clock_driver_support_install_isr(isr) \ - a9mpcore_clock_handler_install() + a9mpcore_clock_handler_install(isr) /* Include shared source clock driver code */ #include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/arm/shared/clock/clock-armv7m.c b/bsps/arm/shared/clock/clock-armv7m.c index 255de1ca42..ce1d3b38bd 100644 --- a/bsps/arm/shared/clock/clock-armv7m.c +++ b/bsps/arm/shared/clock/clock-armv7m.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * Copyright (C) 2011, 2018 Sebastian Huber * * Redistribution and use in source and binary forms, with or without @@ -90,7 +90,7 @@ static void _ARMV7M_Clock_initialize_early(void) interval = (uint32_t) ((freq * us_per_tick) / 1000000); - systick->rvr = interval; + systick->rvr = interval - 1; systick->cvr = 0; systick->csr = ARMV7M_SYSTICK_CSR_ENABLE | ARMV7M_SYSTICK_CSR_CLKSOURCE; } diff --git a/bsps/arm/shared/clock/clock-nxp-lpc.c b/bsps/arm/shared/clock/clock-nxp-lpc.c index 1490699ec5..77d6d423a2 100644 --- a/bsps/arm/shared/clock/clock-nxp-lpc.c +++ b/bsps/arm/shared/clock/clock-nxp-lpc.c @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2009-2015 embedded brains GmbH. All rights reserved. + * Copyright (C) 2009, 2015 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,9 +41,6 @@ #ifdef ARM_MULTILIB_ARCH_V4 -/* This is defined in ../../../shared/dev/clock/clockimpl.h */ -void Clock_isr(rtems_irq_hdl_param arg); - static volatile lpc_timer *const lpc_clock = (volatile lpc_timer *) LPC_CLOCK_TIMER_BASE; @@ -57,12 +54,12 @@ static uint32_t lpc_clock_tc_get_timecount(struct timecounter *tc) return lpc_timecounter->tc; } -static void lpc_clock_at_tick(void) +static void lpc_clock_at_tick(volatile lpc_timer *regs) { - lpc_clock->ir = LPC_TIMER_IR_MR0; + regs->ir = LPC_TIMER_IR_MR0; } -static void lpc_clock_handler_install(void) +static void lpc_clock_handler_install(rtems_interrupt_handler handler) { rtems_status_code sc = RTEMS_SUCCESSFUL; @@ -70,8 +67,8 @@ static void lpc_clock_handler_install(void) LPC_CLOCK_INTERRUPT, "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + handler, + RTEMS_DEVOLATILE(lpc_timer *, lpc_clock) ); if (sc != RTEMS_SUCCESSFUL) { rtems_fatal_error_occurred(0xdeadbeef); @@ -118,10 +115,10 @@ static void lpc_clock_initialize(void) rtems_timecounter_install(&lpc_clock_tc); } -#define Clock_driver_support_at_tick() lpc_clock_at_tick() +#define Clock_driver_support_at_tick(arg) lpc_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() lpc_clock_initialize() #define Clock_driver_support_install_isr(isr) \ - lpc_clock_handler_install() + lpc_clock_handler_install(isr) /* Include shared source clock driver code */ #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c index f15ed02612..39f60e945e 100644 --- a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c +++ b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief This source file contains the implementation of + * arm_cp15_set_exception_handler(). + */ + /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c index db00fd6c26..25ee8103e4 100644 --- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief This source file contains the implementation of + * arm_cp15_set_translation_table_entries(). + */ + /* - * Copyright (c) 2010-2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2010, 2019 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/cpucounter/cpucounter-armv7m.c b/bsps/arm/shared/cpucounter/cpucounter-armv7m.c index 3bdf90c29f..f43ad42248 100644 --- a/bsps/arm/shared/cpucounter/cpucounter-armv7m.c +++ b/bsps/arm/shared/cpucounter/cpucounter-armv7m.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2016, 2018 embedded brains GmbH. All rights reserved. + * Copyright (C) 2016, 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/doxygen.h b/bsps/arm/shared/doxygen.h index 6617afa816..469928d712 100644 --- a/bsps/arm/shared/doxygen.h +++ b/bsps/arm/shared/doxygen.h @@ -1,4 +1,12 @@ /** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file defines BSP-specific groups. + */ + +/** * @defgroup RTEMSBSPsARM ARM * * @ingroup RTEMSBSPs diff --git a/bsps/arm/shared/fb/arm-pl111.c b/bsps/arm/shared/fb/arm-pl111.c index 00779971b0..f88fed5d9a 100644 --- a/bsps/arm/shared/fb/arm-pl111.c +++ b/bsps/arm/shared/fb/arm-pl111.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/irq/irq-armv7m.c b/bsps/arm/shared/irq/irq-armv7m.c index 2602340e65..9e0c1f3a87 100644 --- a/bsps/arm/shared/irq/irq-armv7m.c +++ b/bsps/arm/shared/irq/irq-armv7m.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * Copyright (C) 2011, 2012 Sebastian Huber * * Redistribution and use in source and binary forms, with or without diff --git a/bsps/arm/shared/pins/imx-gpio.c b/bsps/arm/shared/pins/imx-gpio.c index 552e1d5cc2..1e39822b93 100644 --- a/bsps/arm/shared/pins/imx-gpio.c +++ b/bsps/arm/shared/pins/imx-gpio.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2019-2020 embedded brains GmbH. + * Copyright (C) 2019, 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,14 +33,17 @@ #include <rtems.h> #include <rtems/sysinit.h> -#define IMX_GPIO_ALIAS_NAME "gpioX" +/* + * Most of the time it's gpio1 or gpio13. + */ +#define IMX_GPIO_ALIAS_NAME "gpioXY" /* - * i.MX6ULL has 5, i.MX7D has 7 + * i.MX6ULL has 5, i.MX7D has 7, i.MXRT1160 has 13 (base) + 2 (core-specific). * * Be careful when changing this. The attach() does a simple ASCII conversion. */ -#define IMX_MAX_GPIO_MODULES 7 +#define IMX_MAX_GPIO_MODULES 15 struct imx_gpio_regs { uint32_t dr; @@ -88,7 +91,14 @@ static void imx_gpio_attach(void) int len; memcpy(imx_gpio[i].name, IMX_GPIO_ALIAS_NAME, sizeof(IMX_GPIO_ALIAS_NAME)); - imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-2] = (char)('0' + i); + if (i < 10) { + imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-3] = (char)('0' + i); + imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-2] = '\0'; + } else { + imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-3] = (char)('0' + i / 10); + imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-2] = (char)('0' + i % 10); + imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-1] = '\0'; + } path = fdt_get_alias(fdt, imx_gpio[i].name); if (path == NULL) { @@ -181,12 +191,11 @@ static void imx_gpio_set_interrupt_mode(struct imx_gpio_pin *pin, uint32_t mode) } } -rtems_status_code imx_gpio_init_from_fdt_property ( +rtems_status_code imx_gpio_init_from_fdt_property_pointer ( struct imx_gpio_pin *pin, - int node_offset, - const char *property, + const uint32_t *prop_pointer, enum imx_gpio_mode mode, - size_t index + const uint32_t **next_prop_pointer ) { int len; @@ -195,7 +204,6 @@ rtems_status_code imx_gpio_init_from_fdt_property ( const void *fdt; uint32_t gpio_regs; const unsigned pin_length_dwords = 3; - const unsigned pin_length_bytes = (pin_length_dwords * sizeof(uint32_t)); uint32_t gpio_phandle; uint32_t pin_nr; int cfgnode; @@ -203,16 +211,12 @@ rtems_status_code imx_gpio_init_from_fdt_property ( memset(pin, 0, sizeof(*pin)); fdt = bsp_fdt_get(); - val = fdt_getprop(fdt, node_offset, property, &len); - if (val == NULL || (len % pin_length_bytes != 0) || - (index >= len / pin_length_bytes)) { - sc = RTEMS_UNSATISFIED; - } if (sc == RTEMS_SUCCESSFUL) { - pin_nr = fdt32_to_cpu(val[1 + index * pin_length_dwords]); - gpio_phandle = fdt32_to_cpu(val[0 + index * pin_length_dwords]); + pin_nr = fdt32_to_cpu(prop_pointer[1]); + gpio_phandle = fdt32_to_cpu(prop_pointer[0]); cfgnode = fdt_node_offset_by_phandle(fdt, gpio_phandle); + /* FIXME: Check compatible strings here. */ val = fdt_getprop(fdt, cfgnode, "reg", &len); if (len > 0) { gpio_regs = fdt32_to_cpu(val[0]); @@ -229,6 +233,43 @@ rtems_status_code imx_gpio_init_from_fdt_property ( if (sc == RTEMS_SUCCESSFUL) { imx_gpio_init(pin); } + if (sc == RTEMS_SUCCESSFUL && next_prop_pointer != NULL) { + *next_prop_pointer = prop_pointer + pin_length_dwords; + } + + return sc; +} + +rtems_status_code imx_gpio_init_from_fdt_property ( + struct imx_gpio_pin *pin, + int node_offset, + const char *property, + enum imx_gpio_mode mode, + size_t index +) +{ + int len; + const uint32_t *val; + rtems_status_code sc = RTEMS_SUCCESSFUL; + const void *fdt; + const unsigned pin_length_dwords = 3; + const unsigned pin_length_bytes = pin_length_dwords * 4; + + memset(pin, 0, sizeof(*pin)); + + fdt = bsp_fdt_get(); + val = fdt_getprop(fdt, node_offset, property, &len); + if (val == NULL || (len % pin_length_bytes != 0) || + (index >= len / pin_length_bytes)) { + sc = RTEMS_UNSATISFIED; + } + if (sc == RTEMS_SUCCESSFUL) { + sc = imx_gpio_init_from_fdt_property_pointer( + pin, + val + index * pin_length_dwords, + mode, + NULL); + } return sc; } diff --git a/bsps/arm/shared/pins/imx_iomux.c b/bsps/arm/shared/pins/imx_iomux.c index 1ff4186360..e6c604481a 100644 --- a/bsps/arm/shared/pins/imx_iomux.c +++ b/bsps/arm/shared/pins/imx_iomux.c @@ -307,7 +307,17 @@ int imx_iomux_configure_pins(const void *fdt, uint32_t cfgxref) WR4(sc, cfg->mux_reg, cfg->mux_val | sion); iomux_configure_input(sc, cfg->input_reg, cfg->input_val); if ((cfg->padconf_val & PADCONF_NONE) == 0) +#ifndef __rtems__ WR4(sc, cfg->padconf_reg, cfg->padconf_val); +#else /* __rtems__ */ + /* + * Need to mask the flags. On (for example) i.MXRT1166 + * they are used for domain write protection. On other + * i.MX* these are Reserved. + */ + WR4(sc, cfg->padconf_reg, cfg->padconf_val + & ~(PADCONF_SION | PADCONF_NONE)); +#endif /* __rtems__ */ #ifndef __rtems__ if (bootverbose) { char name[32]; diff --git a/bsps/arm/shared/serial/arm-pl050.c b/bsps/arm/shared/serial/arm-pl050.c index 0a4e9493b4..c84de7ff16 100644 --- a/bsps/arm/shared/serial/arm-pl050.c +++ b/bsps/arm/shared/serial/arm-pl050.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c b/bsps/arm/shared/start/arm-a9mpcore-smp.c index c30e099a84..c99f68f9cf 100644 --- a/bsps/arm/shared/start/arm-a9mpcore-smp.c +++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,20 +41,24 @@ uint32_t _CPU_SMP_Initialize(void) return arm_gic_irq_processor_count(); } +static rtems_interrupt_entry arm_a9mpcore_ipi_entry = + RTEMS_INTERRUPT_ENTRY_INITIALIZER( + bsp_inter_processor_interrupt, + NULL, + "IPI" + ); + void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) { if (cpu_count > 0) { rtems_status_code sc; - sc = rtems_interrupt_handler_install( + sc = rtems_interrupt_entry_install( ARM_GIC_IRQ_SGI_0, - "IPI", RTEMS_INTERRUPT_UNIQUE, - bsp_inter_processor_interrupt, - NULL + &arm_a9mpcore_ipi_entry ); - _Assert(sc == RTEMS_SUCCESSFUL); - (void) sc; + _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL); #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) /* Enable unified L2 cache */ diff --git a/bsps/arm/shared/start/bsp-start-memcpy.S b/bsps/arm/shared/start/bsp-start-memcpy.S index b20324c4d4..0cfd47b820 100644 --- a/bsps/arm/shared/start/bsp-start-memcpy.S +++ b/bsps/arm/shared/start/bsp-start-memcpy.S @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/start/bspreset-armv7m.c b/bsps/arm/shared/start/bspreset-armv7m.c index c5e348b6fa..816334bd70 100644 --- a/bsps/arm/shared/start/bspreset-armv7m.c +++ b/bsps/arm/shared/start/bspreset-armv7m.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2015 embedded brains GmbH. All rights reserved. + * Copyright (c) 2015 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/shared/start/bspstarthook0-empty.c b/bsps/arm/shared/start/bspstarthook0-empty.c new file mode 100644 index 0000000000..65e2efcf03 --- /dev/null +++ b/bsps/arm/shared/start/bspstarthook0-empty.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief This source file contains a bsp_start_hook_0() implentation which + * does nothing. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/start.h> + +void BSP_START_TEXT_SECTION bsp_start_hook_0( void ) +{ + /* Do nothing */ +} diff --git a/bsps/arm/shared/start/linkcmds.armv4 b/bsps/arm/shared/start/linkcmds.armv4 index d78a08eb48..e666c953f3 100644 --- a/bsps/arm/shared/start/linkcmds.armv4 +++ b/bsps/arm/shared/start/linkcmds.armv4 @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2010, 2014 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsps/arm/shared/start/linkcmds.armv7m b/bsps/arm/shared/start/linkcmds.armv7m index ccc73734e7..2bface96ee 100644 --- a/bsps/arm/shared/start/linkcmds.armv7m +++ b/bsps/arm/shared/start/linkcmds.armv7m @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsps/arm/shared/start/linkcmds.base b/bsps/arm/shared/start/linkcmds.base index c9cf360ee7..aeca87005b 100644 --- a/bsps/arm/shared/start/linkcmds.base +++ b/bsps/arm/shared/start/linkcmds.base @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2016 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -152,7 +152,7 @@ SECTIONS { } > REGION_RODATA AT > REGION_RODATA_LOAD .data.rel.ro : ALIGN_WITH_INPUT { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) - *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) + *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } > REGION_RODATA AT > REGION_RODATA_LOAD .jcr : ALIGN_WITH_INPUT { KEEP (*(.jcr)) diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S index b90801c2aa..dfd0d3891d 100644 --- a/bsps/arm/shared/start/start.S +++ b/bsps/arm/shared/start/start.S @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2008, 2020 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2020 embedded brains GmbH & Co. KG * * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * @@ -29,7 +29,9 @@ /* Global symbols */ .globl _start + .type _start, %function .globl bsp_start_hook_0_done + .type bsp_start_hook_0_done, %function .globl bsp_start_vector_table_begin .globl bsp_start_vector_table_end .globl bsp_start_vector_table_size @@ -75,6 +77,10 @@ bsp_start_vector_table_begin: ldr pc, .Lhandler_addr_irq ldr pc, .Lhandler_addr_fiq +#ifdef BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT +.balign BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT +#endif + .Lhandler_addr_reset: #ifdef BSP_START_RESET_VECTOR @@ -194,7 +200,7 @@ _start: /* * Check that this is a configured processor. If not, then there is - * not much what can be done since we do not have a stack available for + * not much that can be done since we do not have a stack available for * this processor. Just loop forever in this case. */ ldr r1, =_SMP_Processor_configured_maximum @@ -285,6 +291,7 @@ _start: sub r3, r3, r1 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION + /* These are banked FIQ mode registers */ mov r8, #0 mov r9, #0 mov r10, #0 |