5 files changed, 43 insertions, 13 deletions
diff --git a/bsps/arm/shared/cache/cache-cp15.c b/bsps/arm/shared/cache/cache-cp15.c
index 4ad9965529..d78ec4feb4 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -9,7 +9,7 @@
  */
 
 /*
- * Copyright (C) 2009, 2018 embedded brains GmbH
+ * Copyright (C) 2009, 2018 embedded brains GmbH & Co. KG
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -200,6 +200,7 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_local_enable(level);
 }
 
+#if __ARM_ARCH >= 6
 static inline size_t arm_cp15_get_cache_size(
   uint32_t level,
   uint32_t which
@@ -238,5 +239,30 @@ static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
 {
   return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION);
 }
+#else
+static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
+{
+  uint32_t cache_type;
+
+  if (level > 0) {
+    return 0;
+  }
+
+  cache_type = arm_cp15_get_cache_type();
+  return 1U << (((cache_type >> (12 + 6)) & 0xf) + 9);
+}
+
+static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
+{
+  uint32_t cache_type;
+
+  if (level > 0) {
+    return 0;
+  }
+
+  cache_type = arm_cp15_get_cache_type();
+  return 1U << (((cache_type >> (0 + 6)) & 0xf) + 9);
+}
+#endif
 
 #include "../../shared/cache/cacheimpl.h"
diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h
index 0e1297a84d..7f1eb87812 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -1,15 +1,16 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /**
+ * @file
+ *
  * @ingroup RTEMSBSPsARMShared
  *
- * @brief Level 1 Cache definitions and functions.
- * 
- * This file implements handling for the ARM Level 1 cache controller
+ * @brief This header file provides interfaces of the ARM CP15 cache controller
+ *   suppport.
  */
 
 /*
- * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c
index 7bfa1a564c..6826043afd 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -1,9 +1,10 @@
 /**
- * @ingroup L2C-310_cache
+ * @file
  *
- * @brief Cache definitions and functions.
+ * @ingroup L2C310CacheSupport
  *
- * This file implements handling for the ARM L2C-310 cache controller
+ * @brief This source file contains the implementation of the ARM L2C-310 cache
+ *   controller support.
  */
 
 /*
@@ -96,13 +97,15 @@
 #define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
 
 /**
- * @defgroup L2C-310_cache Cache Support
+ * @defgroup L2C310CacheSupport L2C-310 Cache Support
+ *
  * @ingroup RTEMSBSPsARMShared
- * @brief Cache Functions and Defitions
+ *
+ * @brief This group contains the L2C-310 cache support.
+ *
  * @{
  */
 
-
 /**
  * @brief L2CC Register Offsets
  */
diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
index a5b4b7a3d1..24baa8c4dc 100644
--- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S
+++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
@@ -1,7 +1,7 @@
 /*
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (C) 2018 embedded brains GmbH
+ * Copyright (C) 2018 embedded brains GmbH & Co. KG
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/bsps/arm/shared/cache/cache-v7m.c b/bsps/arm/shared/cache/cache-v7m.c
index ee68e7f9db..edaf1141ae 100644
--- a/bsps/arm/shared/cache/cache-v7m.c
+++ b/bsps/arm/shared/cache/cache-v7m.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 
 /*
- * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions