diff options
Diffstat (limited to 'bsps/arm/include/bsp')
26 files changed, 3252 insertions, 0 deletions
diff --git a/bsps/arm/include/bsp/arm-a8core-start.h b/bsps/arm/include/bsp/arm-a8core-start.h new file mode 100644 index 0000000000..416f282028 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a8core-start.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A8CORE_START Support + */ + +/* + * Copyright (c) 2014 Chris Johns <chrisj@rtems.org>. All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A8CORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A8CORE_START_H + +#include <libcpu/arm-cp15.h> + +#include <bsp.h> +#include <bsp/start.h> +#include <bsp/arm-errata.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline arm_a8core_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline arm_a8core_start_hook_1(void) +{ + arm_a8core_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A8CORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-clock.h b/bsps/arm/include/bsp/arm-a9mpcore-clock.h new file mode 100644 index 0000000000..9a8c653801 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-clock.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013 Chris Johns <chrisj@rtems.org>. All rights reserved. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H + +#include <rtems/counter.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Return the peripheral clock. For systems such as the zynq this + * is controlled by the PL logic generation and can vary. Provide this + * function in your application to override the BSP default. + */ +uint32_t a9mpcore_clock_periphclk(void); + +/** + * @brief Do early clock initialization so that the CPU counter conversion + * works. + */ +static inline void a9mpcore_clock_initialize_early(void) +{ + rtems_counter_initialize_converter(a9mpcore_clock_periphclk()); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_CLOCK_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-irq.h b/bsps/arm/include/bsp/arm-a9mpcore-irq.h new file mode 100644 index 0000000000..f0d3c1b983 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-irq.h @@ -0,0 +1,40 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_IRQ Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define A9MPCORE_IRQ_GT 27 +#define A9MPCORE_IRQ_NFIQ 28 +#define A9MPCORE_IRQ_PT 29 +#define A9MPCORE_IRQ_PW 30 +#define A9MPCORE_IRQ_NIRQ 31 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-regs.h b/bsps/arm/include/bsp/arm-a9mpcore-regs.h new file mode 100644 index 0000000000..d1538357d8 --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-regs.h @@ -0,0 +1,133 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM_A9MPCORE_REGS Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t ctrl; +#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0) +#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1) +#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2) +#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3) +#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4) +#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5) +#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6) + uint32_t cfg; +#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) + uint32_t pwrst; + uint32_t invss; +#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) +#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved_09[8]; + uint32_t diagn_ctrl; +#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) + uint32_t reserved_10[3]; + uint32_t fltstart; + uint32_t fltend; + uint32_t reserved_48[2]; + uint32_t sac; + uint32_t snsac; +} a9mpcore_scu; + +typedef struct { +} a9mpcore_gic; + +typedef struct { + uint32_t cntrlower; + uint32_t cntrupper; +#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3) +#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1) +#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t ctrl; +#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0) + uint32_t irqst; + uint32_t cmpvallower; + uint32_t cmpvalupper; + uint32_t autoinc; +} a9mpcore_gt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; +#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2) +#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1) +#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0) + uint32_t irqst; +#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0) +} a9mpcore_pt; + +typedef struct { + uint32_t load; + uint32_t cntr; + uint32_t ctrl; + uint32_t irqst; + uint32_t rstst; + uint32_t dis; +} a9mpcore_pw; + +typedef struct { +} a9mpcore_idist; + +typedef struct { + a9mpcore_scu scu; + uint32_t reserved_58[42]; + a9mpcore_gic gic; + uint32_t reserved_100[64]; + a9mpcore_gt gt; + uint32_t reserved_21c[249]; + a9mpcore_pt pt; + uint32_t reserved_610[4]; + a9mpcore_pw pw; + uint32_t reserved_638[626]; + a9mpcore_idist idist; +} a9mpcore; + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h b/bsps/arm/include/bsp/arm-a9mpcore-start.h new file mode 100644 index 0000000000..7d6185b39e --- /dev/null +++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h @@ -0,0 +1,172 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief A9MPCORE_START Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H +#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H + +#include <rtems/score/smpimpl.h> + +#include <libcpu/arm-cp15.h> + +#include <bsp.h> +#include <bsp/start.h> +#include <bsp/arm-a9mpcore-regs.h> +#include <bsp/arm-errata.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_set_vector_base(void) +{ + /* + * Do not use bsp_vector_table_begin == 0, since this will get optimized away. + */ + if (bsp_vector_table_end != bsp_vector_table_size) { + uint32_t ctrl; + + /* + * For now we assume that every Cortex-A9 MPCore has the Security Extensions. + * Later it might be necessary to evaluate the ID_PFR1 register. + */ + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_V; + arm_cp15_set_control(ctrl); + } +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate( + volatile a9mpcore_scu *scu, + uint32_t cpu_id, + uint32_t ways +) +{ + scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu) +{ + if (arm_errata_is_applicable_processor_errata_764369()) { + scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE; + } +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu) +{ + scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN; + arm_a9mpcore_start_errata_764369_handler(scu); +} + +#ifdef RTEMS_SMP +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_on_secondary_processor(void) +{ + uint32_t ctrl; + + arm_a9mpcore_start_set_vector_base(); + + arm_gic_irq_initialize_secondary_cpu(); + + ctrl = arm_cp15_start_setup_mmu_and_cache( + 0, + ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z + ); + + arm_cp15_set_domain_access_control( + ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) + ); + + /* FIXME: Sharing the translation table between processors is brittle */ + arm_cp15_set_translation_table_base( + (uint32_t *) bsp_translation_table_base + ); + + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + arm_cp15_set_control(ctrl); + + _SMP_Start_multitasking_on_secondary_processor(); +} + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_enable_smp_in_auxiliary_control(void) +{ + /* + * Enable cache coherency support and cache/MMU maintenance broadcasts for + * this processor. + */ + uint32_t actlr = arm_cp15_get_auxiliary_control(); + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; + arm_cp15_set_auxiliary_control(actlr); +} +#endif + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) +{ + volatile a9mpcore_scu *scu = + (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE; + uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); + + arm_cp15_branch_predictor_invalidate_all(); + + if (cpu_id == 0) { + arm_a9mpcore_start_scu_enable(scu); + } + +#ifdef RTEMS_SMP + arm_a9mpcore_start_enable_smp_in_auxiliary_control(); +#endif + + arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf); + +#ifdef RTEMS_SMP + if (cpu_id != 0) { + arm_a9mpcore_start_on_secondary_processor(); + } +#endif +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void) +{ + volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE; + + gt->ctrl = 0; + gt->cntrlower = 0; + gt->cntrupper = 0; + gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN; +} + +BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void) +{ + arm_a9mpcore_start_global_timer(); + arm_a9mpcore_start_set_vector_base(); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */ diff --git a/bsps/arm/include/bsp/arm-cp15-start.h b/bsps/arm/include/bsp/arm-cp15-start.h new file mode 100644 index 0000000000..a749f7dc98 --- /dev/null +++ b/bsps/arm/include/bsp/arm-cp15-start.h @@ -0,0 +1,187 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief Arm CP15 start. + */ + + +/* + * Copyright (c) 2013 Hesham AL-Matary. + * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H +#define LIBBSP_ARM_SHARED_ARM_CP15_START_H + +#include <libcpu/arm-cp15.h> +#include <bsp/start.h> +#include <bsp/linker-symbols.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t begin; + uint32_t end; + uint32_t flags; +} arm_cp15_start_section_config; + +#define ARMV7_CP15_START_DEFAULT_SECTIONS \ + { \ + .begin = (uint32_t) bsp_section_fast_text_begin, \ + .end = (uint32_t) bsp_section_fast_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_fast_data_begin, \ + .end = (uint32_t) bsp_section_fast_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_start_begin, \ + .end = (uint32_t) bsp_section_start_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_vector_begin, \ + .end = (uint32_t) bsp_section_vector_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_text_begin, \ + .end = (uint32_t) bsp_section_text_end, \ + .flags = ARMV7_MMU_CODE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_rodata_begin, \ + .end = (uint32_t) bsp_section_rodata_end, \ + .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_data_begin, \ + .end = (uint32_t) bsp_section_data_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_bss_begin, \ + .end = (uint32_t) bsp_section_bss_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_work_begin, \ + .end = (uint32_t) bsp_section_work_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_stack_begin, \ + .end = (uint32_t) bsp_section_stack_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + }, { \ + .begin = (uint32_t) bsp_section_nocache_begin, \ + .end = (uint32_t) bsp_section_nocache_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_section_nocachenoload_begin, \ + .end = (uint32_t) bsp_section_nocachenoload_end, \ + .flags = ARMV7_MMU_DEVICE \ + }, { \ + .begin = (uint32_t) bsp_translation_table_base, \ + .end = (uint32_t) bsp_translation_table_end, \ + .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ + } + +BSP_START_DATA_SECTION extern const arm_cp15_start_section_config + arm_cp15_start_mmu_config_table[]; + +BSP_START_DATA_SECTION extern const size_t + arm_cp15_start_mmu_config_table_size; + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_set_translation_table_entries( + uint32_t *ttb, + const arm_cp15_start_section_config *config +) +{ + uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); + uint32_t iend = + ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); + uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U; + + if (config->begin != config->end) { + while (i != iend) { + ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; + i = (i + 1U) & index_mask; + } + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table( + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT); + size_t i; + + arm_cp15_set_domain_access_control(dac); + arm_cp15_set_translation_table_base(ttb); + + /* Initialize translation table with invalid entries */ + for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { + ttb [i] = 0; + } + + for (i = 0; i < config_count; ++i) { + arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]); + } +} + +BSP_START_TEXT_SECTION static inline void +arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( + uint32_t ctrl, + uint32_t *ttb, + uint32_t client_domain, + const arm_cp15_start_section_config *config_table, + size_t config_count +) +{ + arm_cp15_start_setup_translation_table( + ttb, + client_domain, + config_table, + config_count + ); + + /* Enable MMU and cache */ + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + + arm_cp15_set_control(ctrl); +} + +BSP_START_TEXT_SECTION static inline uint32_t +arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set) +{ + uint32_t ctrl = arm_cp15_get_control(); + + ctrl &= ~ctrl_clear; + ctrl |= ctrl_set; + + arm_cp15_set_control(ctrl); + + arm_cp15_tlb_invalidate(); + + return ctrl; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */ diff --git a/bsps/arm/include/bsp/arm-errata.h b/bsps/arm/include/bsp/arm-errata.h new file mode 100644 index 0000000000..5108c98f15 --- /dev/null +++ b/bsps/arm/include/bsp/arm-errata.h @@ -0,0 +1,121 @@ +/** + * @file arm-errata.h + * + * @ingroup arm_shared + * + * @brief Create #defines which state which erratas shall get applied + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_ERRATA_H_ +#define ARM_ERRATA_H_ + +#include <bsp/arm-release-id.h> +#include <libcpu/arm-cp15.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline arm_release_id arm_errata_get_processor_release(void) +{ + const uint32_t MIDR = arm_cp15_get_id_code(); + const uint8_t REVISION = (MIDR & 0xF00000U) >> 20; + const uint8_t PATCH_LEVEL = (MIDR & 0xFU); + + return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( + REVISION, + PATCH_LEVEL + ); +} + +static inline bool arm_errata_is_applicable_processor_errata_764369(void) +{ +#if defined(RTEMS_SMP) + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R4_P1: + case ARM_RELEASE_ID_R4_P4: + case ARM_RELEASE_ID_R3_P0: + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + case ARM_RELEASE_ID_R2_P0: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +#else + return false; +#endif +} + +static inline bool arm_errata_is_applicable_processor_errata_775420(void) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + is_applicable = true; + break; + default: + is_applicable = false; + break; + } + + return is_applicable; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_ERRATA_H_ */ diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h new file mode 100644 index 0000000000..09d3fe5ac2 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-irq.h @@ -0,0 +1,112 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC IRQ + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H + +#include <bsp.h> +#include <bsp/arm-gic.h> +#include <rtems/score/processormask.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ARM_GIC_IRQ_SGI_0 0 +#define ARM_GIC_IRQ_SGI_1 1 +#define ARM_GIC_IRQ_SGI_2 2 +#define ARM_GIC_IRQ_SGI_3 3 +#define ARM_GIC_IRQ_SGI_5 5 +#define ARM_GIC_IRQ_SGI_6 6 +#define ARM_GIC_IRQ_SGI_7 7 +#define ARM_GIC_IRQ_SGI_8 8 +#define ARM_GIC_IRQ_SGI_9 9 +#define ARM_GIC_IRQ_SGI_10 10 +#define ARM_GIC_IRQ_SGI_11 11 +#define ARM_GIC_IRQ_SGI_12 12 +#define ARM_GIC_IRQ_SGI_13 13 +#define ARM_GIC_IRQ_SGI_14 14 +#define ARM_GIC_IRQ_SGI_15 15 + +#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +); + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +typedef enum { + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF +} arm_gic_irq_software_irq_target_filter; + +static inline rtems_status_code arm_gic_irq_generate_software_irq( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (vector <= ARM_GIC_IRQ_SGI_15) { + volatile gic_dist *dist = ARM_GIC_DIST; + + dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) + | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) + | GIC_DIST_ICDSGIR_SGIINTID(vector); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +static inline uint32_t arm_gic_irq_processor_count(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; +} + +void arm_gic_irq_initialize_secondary_cpu(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-gic-regs.h new file mode 100644 index 0000000000..2375b5cf74 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-regs.h @@ -0,0 +1,138 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H +#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t iccicr; +#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) + uint32_t iccpmr; +#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t iccbpr; +#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t icciar; +#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t icceoir; +#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccrpr; +#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t icchpir; +#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccabpr; +#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t reserved_20[55]; + uint32_t icciidr; +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +} gic_cpuif; + +typedef struct { + uint32_t icddcr; +#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) + uint32_t icdictr; +#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) +#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) +#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t icdiidr; +#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + uint32_t reserved_0c[29]; + uint32_t icdisr[32]; + uint32_t icdiser[32]; + uint32_t icdicer[32]; + uint32_t icdispr[32]; + uint32_t icdicpr[32]; + uint32_t icdabr[32]; + uint32_t reserved_380[32]; + uint8_t icdipr[256]; + uint32_t reserved_500[192]; + uint8_t icdiptr[256]; + uint32_t reserved_900[192]; + uint32_t icdicfr[64]; + uint32_t reserved_d00[128]; + uint32_t icdsgir; +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define GIC_DIST_ICDSGIR_SATT BSP_BIT32(15) +#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +} gic_dist; + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-gic-tm27.h b/bsps/arm/include/bsp/arm-gic-tm27.h new file mode 100644 index 0000000000..95f3077716 --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic-tm27.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC TM27 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H +#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H + +#include <assert.h> + +#include <bsp.h> +#include <bsp/irq.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 + +#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 + +#define ARM_GIC_TM27_PRIO_LOW 0x80 + +#define ARM_GIC_TM27_PRIO_HIGH 0x00 + +static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_LOW, + "tm27 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_TM27_PRIO_LOW + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_HIGH, + "tm27 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_TM27_PRIO_HIGH + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Cause_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Clear_tm27_intr(void) +{ + /* Nothing to do */ +} + +static inline void Lower_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/arm/include/bsp/arm-gic.h b/bsps/arm/include/bsp/arm-gic.h new file mode 100644 index 0000000000..ab5840919a --- /dev/null +++ b/bsps/arm/include/bsp/arm-gic.h @@ -0,0 +1,207 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H +#define LIBBSP_ARM_SHARED_ARM_GIC_H + +#include <bsp/arm-gic-regs.h> + +#include <stdbool.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_gic ARM GIC + * + * @ingroup arm_shared + * + * @brief ARM_GIC Support Package + */ + +#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) +#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) + +#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) +#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) + +static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdiser[i] & bit) != 0; +} + +static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdiser[i] = bit; +} + +static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicer[i] = bit; +} + +static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdispr[i] & bit) != 0; +} + +static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdispr[i] = bit; +} + +static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicpr[i] = bit; +} + +static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdabr[i] & bit) != 0; +} + +static inline void gic_id_set_priority( + volatile gic_dist *dist, + uint32_t id, + uint8_t priority +) +{ + dist->icdipr[id] = priority; +} + +static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdipr[id]; +} + +static inline void gic_id_set_targets( + volatile gic_dist *dist, + uint32_t id, + uint8_t targets +) +{ + dist->icdiptr[id] = targets; +} + +static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdiptr[id]; +} + +typedef enum { + GIC_LEVEL_SENSITIVE, + GIC_EDGE_TRIGGERED +} gic_trigger_mode; + +static inline gic_trigger_mode gic_id_get_trigger_mode( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? + GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; +} + +static inline void gic_id_set_trigger_mode( + volatile gic_dist *dist, + uint32_t id, + gic_trigger_mode mode +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = mode << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +typedef enum { + GIC_N_TO_N, + GIC_1_TO_N +} gic_handling_model; + +static inline gic_handling_model gic_id_get_handling_model( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; +} + +static inline void gic_id_set_handling_model( + volatile gic_dist *dist, + uint32_t id, + gic_handling_model model +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = model << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h b/bsps/arm/include/bsp/arm-pl011-regs.h new file mode 100644 index 0000000000..2b930f4b4c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011-regs.h @@ -0,0 +1,130 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t uartdr; +#define PL011_UARTDR_OE BSP_BIT32(11) +#define PL011_UARTDR_BE BSP_BIT32(10) +#define PL011_UARTDR_PE BSP_BIT32(9) +#define PL011_UARTDR_FE BSP_BIT32(8) +#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartrsr_uartecr; +#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3) +#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2) +#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1) +#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0) + uint32_t reserved_08[4]; + uint32_t uartfr; +#define PL011_UARTFR_RI BSP_BIT32(8) +#define PL011_UARTFR_TXFE BSP_BIT32(7) +#define PL011_UARTFR_RXFF BSP_BIT32(6) +#define PL011_UARTFR_TXFF BSP_BIT32(5) +#define PL011_UARTFR_RXFE BSP_BIT32(4) +#define PL011_UARTFR_BUSY BSP_BIT32(3) +#define PL011_UARTFR_DCD BSP_BIT32(2) +#define PL011_UARTFR_DSR BSP_BIT32(1) +#define PL011_UARTFR_CTS BSP_BIT32(0) + uint32_t reserved_1c; + uint32_t uartilpr; +#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7) +#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t uartibrd; +#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t uartfbrd; +#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t uartlcr_h; +#define PL011_UARTLCR_H_SPS BSP_BIT32(7) +#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6) +#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define PL011_UARTLCR_H_WLEN_5 0x00U +#define PL011_UARTLCR_H_WLEN_6 0x01U +#define PL011_UARTLCR_H_WLEN_7 0x02U +#define PL011_UARTLCR_H_WLEN_8 0x03U +#define PL011_UARTLCR_H_FEN BSP_BIT32(4) +#define PL011_UARTLCR_H_STP2 BSP_BIT32(3) +#define PL011_UARTLCR_H_EPS BSP_BIT32(2) +#define PL011_UARTLCR_H_PEN BSP_BIT32(1) +#define PL011_UARTLCR_H_BRK BSP_BIT32(0) + uint32_t uartcr; +#define PL011_UARTCR_CTSEN BSP_BIT32(15) +#define PL011_UARTCR_RTSEN BSP_BIT32(14) +#define PL011_UARTCR_OUT2 BSP_BIT32(13) +#define PL011_UARTCR_OUT1 BSP_BIT32(12) +#define PL011_UARTCR_RTS BSP_BIT32(11) +#define PL011_UARTCR_DTR BSP_BIT32(10) +#define PL011_UARTCR_RXE BSP_BIT32(9) +#define PL011_UARTCR_TXE BSP_BIT32(8) +#define PL011_UARTCR_LBE BSP_BIT32(7) +#define PL011_UARTCR_SIRLP BSP_BIT32(3) +#define PL011_UARTCR_SIREN BSP_BIT32(2) +#define PL011_UARTCR_UARTEN BSP_BIT32(1) + uint32_t uartifls; +#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5) +#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) +#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t uartimsc; + uint32_t uartris; + uint32_t uartmis; + uint32_t uarticr; +#define PL011_UARTI_OEI BSP_BIT32(10) +#define PL011_UARTI_BEI BSP_BIT32(9) +#define PL011_UARTI_PEI BSP_BIT32(8) +#define PL011_UARTI_FEI BSP_BIT32(7) +#define PL011_UARTI_RTI BSP_BIT32(6) +#define PL011_UARTI_TXI BSP_BIT32(5) +#define PL011_UARTI_RXI BSP_BIT32(4) +#define PL011_UARTI_DSRMI BSP_BIT32(3) +#define PL011_UARTI_DCDMI BSP_BIT32(2) +#define PL011_UARTI_CTSMI BSP_BIT32(1) +#define PL011_UARTI_RIMI BSP_BIT32(0) + uint32_t uartdmacr; +#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2) +#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1) +#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0) + uint32_t reserved_4c[997]; + uint32_t uartperiphid0; + uint32_t uartperiphid1; + uint32_t uartperiphid2; + uint32_t uartperiphid3; + uint32_t uartpcellid0; + uint32_t uartpcellid1; + uint32_t uartpcellid2; + uint32_t uartpcellid3; +} pl011; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/arm/include/bsp/arm-pl011.h new file mode 100644 index 0000000000..08189c477c --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl011.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL011 Support Package + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL011_H +#define LIBBSP_ARM_SHARED_ARM_PL011_H + +#include <rtems/termiostypes.h> + +#include <bsp/arm-pl011-regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl011 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl011_context; + +bool arm_pl011_probe(rtems_termios_device_context *base); + +void arm_pl011_write_polled(rtems_termios_device_context *base, char c); + +extern const rtems_termios_device_handler arm_pl011_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL011_H */ diff --git a/bsps/arm/include/bsp/arm-pl050-regs.h b/bsps/arm/include/bsp/arm-pl050-regs.h new file mode 100644 index 0000000000..f90aeb6cf9 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050-regs.h @@ -0,0 +1,57 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Register Definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL050_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t kmicr; +#define PL050_KMICR_KMITYPE BSP_BIT32(5) +#define PL050_KMICR_KMIRXINTREN BSP_BIT32(4) +#define PL050_KMICR_KMITXINTREN BSP_BIT32(3) +#define PL050_KMICR_KMIEN BSP_BIT32(2) +#define PL050_KMICR_FKMID BSP_BIT32(1) +#define PL050_KMICR_FKMIC BSP_BIT32(0) + uint32_t kmistat; +#define PL050_KMISTAT_TXEMPTY BSP_BIT32(6) +#define PL050_KMISTAT_TXBUSY BSP_BIT32(5) +#define PL050_KMISTAT_RXFULL BSP_BIT32(4) +#define PL050_KMISTAT_RXBUSY BSP_BIT32(3) +#define PL050_KMISTAT_RXPARITY BSP_BIT32(2) +#define PL050_KMISTAT_KMIC BSP_BIT32(1) +#define PL050_KMISTAT_KMID BSP_BIT32(0) + uint32_t kmidata; +#define PL050_KMIDATA_KMIDATA(val) BSP_FLD32(val, 0, 7) +#define PL050_KMIDATA_KMIDATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL050_KMIDATA_KMIDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t kmiclkdiv; +#define PL050_KMICLKDIV_KMICLKDIV(val) BSP_FLD32(val, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define PL050_KMICLKDIV_KMICLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t kmiir; +#define PL050_KMIIR_KMITXINTR BSP_BIT32(1) +#define PL050_KMIIR_KMIRXINTR BSP_BIT32(0) +} pl050; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-pl050.h b/bsps/arm/include/bsp/arm-pl050.h new file mode 100644 index 0000000000..af4e246124 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl050.h @@ -0,0 +1,47 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL050 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL050_H +#define LIBBSP_ARM_SHARED_ARM_PL050_H + +#include <rtems/termiostypes.h> + +#include <bsp/arm-pl050-regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + volatile pl050 *regs; + rtems_vector_number irq; + uint32_t initial_baud; +} arm_pl050_context; + +extern const rtems_termios_device_handler arm_pl050_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_PL050_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-fb.h b/bsps/arm/include/bsp/arm-pl111-fb.h new file mode 100644 index 0000000000..0c8c6231e1 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-fb.h @@ -0,0 +1,44 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 FB Support + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_FB_H +#define LIBBSP_ARM_SHARED_ARM_PL111_FB_H + +#include <bsp/arm-pl111-regs.h> + +typedef struct pl111_fb_config { + volatile pl111 *regs; + uint32_t timing0; + uint32_t timing1; + uint32_t timing2; + uint32_t timing3; + uint32_t control; + uint32_t power_delay_in_us; + void (*set_up)(const struct pl111_fb_config *cfg); + void (*pins_set_up)(const struct pl111_fb_config *cfg); + void (*pins_tear_down)(const struct pl111_fb_config *cfg); + void (*tear_down)(const struct pl111_fb_config *cfg); +} pl111_fb_config; + +const pl111_fb_config *arm_pl111_fb_get_config(void); + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_FB_H */ diff --git a/bsps/arm/include/bsp/arm-pl111-regs.h b/bsps/arm/include/bsp/arm-pl111-regs.h new file mode 100644 index 0000000000..ed27ba41a0 --- /dev/null +++ b/bsps/arm/include/bsp/arm-pl111-regs.h @@ -0,0 +1,184 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARM PL111 Register definitions + */ + +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H +#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t timing0; +#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7) +#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7) +#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15) +#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing1; +#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9) +#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15) +#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23) +#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31) +#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) + uint32_t timing2; +#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) +#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5) +#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10) +#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define PL111_LCD_TIMING2_IVS BSP_BIT32(11) +#define PL111_LCD_TIMING2_IHS BSP_BIT32(12) +#define PL111_LCD_TIMING2_IPC BSP_BIT32(13) +#define PL111_LCD_TIMING2_IOE BSP_BIT32(14) +#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25) +#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_LCD_TIMING2_BCD BSP_BIT32(26) +#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) +#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31) + uint32_t timing3; +#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6) +#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define PL111_LCD_TIMING3_LEE BSP_BIT32(16) + uint32_t upbase; + uint32_t lpbase; + uint32_t control; +#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0) +#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3) +#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U +#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U +#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U +#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U +#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U +#define PL111_LCD_CONTROL_LCD_BPP_16 0x06U +#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U +#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4) +#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5) +#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6) +#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7) +#define PL111_LCD_CONTROL_BGR BSP_BIT32(8) +#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9) +#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10) +#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11) +#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16) + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; +#define PL111_LCD_I_FUF BSP_BIT32(1) +#define PL111_LCD_I_LNBU BSP_BIT32(2) +#define PL111_LCD_I_VCOMP BSP_BIT32(3) +#define PL111_LCD_I_MBERROR BSP_BIT32(4) + uint32_t upcurr; + uint32_t lpcurr; + uint32_t reserved_34[115]; + uint16_t pal[256]; +#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4) +#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4) +#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9) +#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9) +#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14) +#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14) +#define PL111_LCD_PAL_I BSP_BIT16(15) +} pl111_lcd; + +typedef struct { + uint8_t image[1024]; + uint32_t ctrl; +#define PL111_CRSR_CTRL_ON BSP_BIT32(0) +#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5) +#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5) + uint32_t config; +#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0) +#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1) + uint32_t palette0; + uint32_t palette1; +#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7) +#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) + uint32_t xy; +#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9) +#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) +#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11) +#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25) +#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25) +#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27) +#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27) +#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27) + uint32_t clip; +#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5) +#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) +#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13) +#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) + uint32_t imsc; + uint32_t icr; + uint32_t ris; + uint32_t mis; +#define PL111_CRSR_I_CRSR BSP_BIT32(0) +} pl111_crsr; + +typedef struct { + pl111_lcd lcd; + uint32_t reserved_400[256]; + pl111_crsr crsr; +} pl111; + +#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-release-id.h b/bsps/arm/include/bsp/arm-release-id.h new file mode 100644 index 0000000000..e06be006da --- /dev/null +++ b/bsps/arm/include/bsp/arm-release-id.h @@ -0,0 +1,152 @@ +/** + * @file arm-release-id.h + * + * @ingroup arm_shared + * + * @brief Create #defines for release IDs + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_RELEASE_ID_H_ +#define ARM_RELEASE_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* #define the IDs which identify a release. This must be done + * prior to #including bsp.h */ +#define ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( release_no, patch_level ) \ + ( ( ( ( release_no ) & 0xFFFF ) << 16 ) + ( ( patch_level ) & 0xFFFF ) ) + +typedef enum { + ARM_RELEASE_ID_R0_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 0 ), + ARM_RELEASE_ID_R0_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 1 ), + ARM_RELEASE_ID_R0_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 2 ), + ARM_RELEASE_ID_R0_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 3 ), + ARM_RELEASE_ID_R0_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 4 ), + ARM_RELEASE_ID_R0_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 5 ), + ARM_RELEASE_ID_R0_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 6 ), + ARM_RELEASE_ID_R0_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 7 ), + ARM_RELEASE_ID_R0_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 8 ), + ARM_RELEASE_ID_R0_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 9 ), + ARM_RELEASE_ID_R0_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 0, 10 ), + ARM_RELEASE_ID_R1_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 0 ), + ARM_RELEASE_ID_R1_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 1 ), + ARM_RELEASE_ID_R1_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 2 ), + ARM_RELEASE_ID_R1_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 3 ), + ARM_RELEASE_ID_R1_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 4 ), + ARM_RELEASE_ID_R1_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 5 ), + ARM_RELEASE_ID_R1_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 6 ), + ARM_RELEASE_ID_R1_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 7 ), + ARM_RELEASE_ID_R1_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 8 ), + ARM_RELEASE_ID_R1_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 9 ), + ARM_RELEASE_ID_R1_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 1, 10 ), + ARM_RELEASE_ID_R2_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 0 ), + ARM_RELEASE_ID_R2_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 1 ), + ARM_RELEASE_ID_R2_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 2 ), + ARM_RELEASE_ID_R2_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 3 ), + ARM_RELEASE_ID_R2_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 4 ), + ARM_RELEASE_ID_R2_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 5 ), + ARM_RELEASE_ID_R2_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 6 ), + ARM_RELEASE_ID_R2_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 7 ), + ARM_RELEASE_ID_R2_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 8 ), + ARM_RELEASE_ID_R2_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 9 ), + ARM_RELEASE_ID_R2_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 2, 10 ), + ARM_RELEASE_ID_R3_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 0 ), + ARM_RELEASE_ID_R3_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 1 ), + ARM_RELEASE_ID_R3_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 2 ), + ARM_RELEASE_ID_R3_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 3 ), + ARM_RELEASE_ID_R3_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 4 ), + ARM_RELEASE_ID_R3_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 5 ), + ARM_RELEASE_ID_R3_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 6 ), + ARM_RELEASE_ID_R3_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 7 ), + ARM_RELEASE_ID_R3_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 8 ), + ARM_RELEASE_ID_R3_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 9 ), + ARM_RELEASE_ID_R3_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 3, 10 ), + ARM_RELEASE_ID_R4_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 0 ), + ARM_RELEASE_ID_R4_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 1 ), + ARM_RELEASE_ID_R4_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 2 ), + ARM_RELEASE_ID_R4_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 3 ), + ARM_RELEASE_ID_R4_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 4 ), + ARM_RELEASE_ID_R4_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 5 ), + ARM_RELEASE_ID_R4_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 6 ), + ARM_RELEASE_ID_R4_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 7 ), + ARM_RELEASE_ID_R4_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 8 ), + ARM_RELEASE_ID_R4_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 9 ), + ARM_RELEASE_ID_R4_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 4, 10 ), + ARM_RELEASE_ID_R5_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 0 ), + ARM_RELEASE_ID_R5_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 1 ), + ARM_RELEASE_ID_R5_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 2 ), + ARM_RELEASE_ID_R5_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 3 ), + ARM_RELEASE_ID_R5_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 4 ), + ARM_RELEASE_ID_R5_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 5 ), + ARM_RELEASE_ID_R5_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 6 ), + ARM_RELEASE_ID_R5_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 7 ), + ARM_RELEASE_ID_R5_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 8 ), + ARM_RELEASE_ID_R5_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 9 ), + ARM_RELEASE_ID_R5_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 5, 10 ), + ARM_RELEASE_ID_R6_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 0 ), + ARM_RELEASE_ID_R6_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 1 ), + ARM_RELEASE_ID_R6_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 2 ), + ARM_RELEASE_ID_R6_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 3 ), + ARM_RELEASE_ID_R6_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 4 ), + ARM_RELEASE_ID_R6_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 5 ), + ARM_RELEASE_ID_R6_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 6 ), + ARM_RELEASE_ID_R6_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 7 ), + ARM_RELEASE_ID_R6_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 8 ), + ARM_RELEASE_ID_R6_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 9 ), + ARM_RELEASE_ID_R6_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 6, 10 ), + ARM_RELEASE_ID_R7_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 0 ), + ARM_RELEASE_ID_R7_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 1 ), + ARM_RELEASE_ID_R7_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 2 ), + ARM_RELEASE_ID_R7_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 3 ), + ARM_RELEASE_ID_R7_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 4 ), + ARM_RELEASE_ID_R7_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 5 ), + ARM_RELEASE_ID_R7_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 6 ), + ARM_RELEASE_ID_R7_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 7 ), + ARM_RELEASE_ID_R7_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 8 ), + ARM_RELEASE_ID_R7_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 9 ), + ARM_RELEASE_ID_R7_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 7, 10 ), + ARM_RELEASE_ID_R8_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 0 ), + ARM_RELEASE_ID_R8_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 1 ), + ARM_RELEASE_ID_R8_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 2 ), + ARM_RELEASE_ID_R8_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 3 ), + ARM_RELEASE_ID_R8_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 4 ), + ARM_RELEASE_ID_R8_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 5 ), + ARM_RELEASE_ID_R8_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 6 ), + ARM_RELEASE_ID_R8_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 7 ), + ARM_RELEASE_ID_R8_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 8 ), + ARM_RELEASE_ID_R8_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 9 ), + ARM_RELEASE_ID_R8_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 8, 10 ), + ARM_RELEASE_ID_R9_P0 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 0 ), + ARM_RELEASE_ID_R9_P1 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 1 ), + ARM_RELEASE_ID_R9_P2 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 2 ), + ARM_RELEASE_ID_R9_P3 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 3 ), + ARM_RELEASE_ID_R9_P4 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 4 ), + ARM_RELEASE_ID_R9_P5 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 5 ), + ARM_RELEASE_ID_R9_P6 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 6 ), + ARM_RELEASE_ID_R9_P7 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 7 ), + ARM_RELEASE_ID_R9_P8 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 8 ), + ARM_RELEASE_ID_R9_P9 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 9 ), + ARM_RELEASE_ID_R9_P10 = ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( 9, 10 ) +} arm_release_id; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_RELEASE_ID_H_ */
\ No newline at end of file diff --git a/bsps/arm/include/bsp/armv7m-irq.h b/bsps/arm/include/bsp/armv7m-irq.h new file mode 100644 index 0000000000..f91ab362e7 --- /dev/null +++ b/bsps/arm/include/bsp/armv7m-irq.h @@ -0,0 +1,36 @@ +/** + * @file + * + * @ingroup arm_shared + * + * @brief ARMV7M Support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARMV7M_IRQ_H +#define LIBBSP_ARM_SHARED_ARMV7M_IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +void _ARMV7M_NVIC_Interrupt_dispatch(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARMV7M_IRQ_H */ diff --git a/bsps/arm/include/bsp/linker-symbols.h b/bsps/arm/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..1a996f51f2 --- /dev/null +++ b/bsps/arm/include/bsp/linker-symbols.h @@ -0,0 +1,167 @@ +/** + * @file + * + * @ingroup arm_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_linker Linker Support + * + * @ingroup arm_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_stack_irq_begin) +LINKER_SYMBOL(bsp_stack_irq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_fiq_begin) +LINKER_SYMBOL(bsp_stack_fiq_end) +LINKER_SYMBOL(bsp_stack_irq_size) + +LINKER_SYMBOL(bsp_stack_abt_begin) +LINKER_SYMBOL(bsp_stack_abt_end) +LINKER_SYMBOL(bsp_stack_abt_size) + +LINKER_SYMBOL(bsp_stack_und_begin) +LINKER_SYMBOL(bsp_stack_und_end) +LINKER_SYMBOL(bsp_stack_und_size) + +LINKER_SYMBOL(bsp_stack_hyp_begin) +LINKER_SYMBOL(bsp_stack_hyp_end) +LINKER_SYMBOL(bsp_stack_hyp_size) + +LINKER_SYMBOL(bsp_stack_svc_begin) +LINKER_SYMBOL(bsp_stack_svc_end) +LINKER_SYMBOL(bsp_stack_svc_size) + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +LINKER_SYMBOL(bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/arm/include/bsp/lpc-dma.h b/bsps/arm/include/bsp/lpc-dma.h new file mode 100644 index 0000000000..45d567b36c --- /dev/null +++ b/bsps/arm/include/bsp/lpc-dma.h @@ -0,0 +1,221 @@ +/** + * @file + * + * @ingroup lpc_dma + * + * @brief DMA support API. + */ + +/* + * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H +#define LIBBSP_ARM_SHARED_LPC_DMA_H + +#include <bspopts.h> +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_dma DMA Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief DMA support. + * + * @{ + */ + +/** + * @brief DMA descriptor item. + */ +typedef struct { + uint32_t src; + uint32_t dest; + uint32_t lli; + uint32_t ctrl; +} lpc_dma_descriptor; + +/** + * @brief DMA channel block. + */ +typedef struct { + lpc_dma_descriptor desc; + uint32_t cfg; + uint32_t reserved [3]; +} lpc_dma_channel; + +/** + * @brief DMA control block. + */ +typedef struct { + uint32_t int_stat; + uint32_t int_tc_stat; + uint32_t int_tc_clear; + uint32_t int_err_stat; + uint32_t int_err_clear; + uint32_t raw_tc_stat; + uint32_t raw_err_stat; + uint32_t enabled_channels; + uint32_t soft_burst_req; + uint32_t soft_single_req; + uint32_t soft_last_burst_req; + uint32_t soft_last_single_req; + uint32_t cfg; + uint32_t sync; + uint32_t reserved [50]; + lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT]; +} lpc_dma; + +/** + * @name DMA Configuration Register + * + * @{ + */ + +#define DMA_CFG_E BSP_BIT32(0) +#define DMA_CFG_M_0 BSP_BIT32(1) +#define DMA_CFG_M_1 BSP_BIT32(2) + +/** @} */ + +/** + * @name DMA Channel Control Register + * + * @{ + */ + +#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11) +#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff) + +#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14) +#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0) +#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1) +#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2) +#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3) +#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4) +#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5) +#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6) +#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7) + +#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17) +#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0) +#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1) +#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2) +#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3) +#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4) +#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5) +#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6) +#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7) + +#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20) +#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0) +#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1) +#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2) + +#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23) +#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0) +#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1) +#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2) + +#define DMA_CH_CTRL_S BSP_BIT32(24) +#define DMA_CH_CTRL_D BSP_BIT32(25) +#define DMA_CH_CTRL_SI BSP_BIT32(26) +#define DMA_CH_CTRL_DI BSP_BIT32(27) +#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30) +#define DMA_CH_CTRL_I BSP_BIT32(31) + +/** @} */ + +/** + * @name DMA Channel Configuration Register + * + * @{ + */ + +#define DMA_CH_CFG_E BSP_BIT32(0) +#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5) +#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10) + +#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13) +#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3) +#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4) +#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5) +#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6) +#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7) + +#define DMA_CH_CFG_IE BSP_BIT32(14) +#define DMA_CH_CFG_ITC BSP_BIT32(15) +#define DMA_CH_CFG_L BSP_BIT32(16) +#define DMA_CH_CFG_A BSP_BIT32(17) +#define DMA_CH_CFG_H BSP_BIT32(18) + +/** @} */ + +/** + * @name LPC24XX DMA Peripherals + * + * @{ + */ + +#define LPC24XX_DMA_PER_SSP_0_TX 0 +#define LPC24XX_DMA_PER_SSP_0_RX 1 +#define LPC24XX_DMA_PER_SSP_1_TX 2 +#define LPC24XX_DMA_PER_SSP_1_RX 3 +#define LPC24XX_DMA_PER_SD_MMC 4 +#define LPC24XX_DMA_PER_I2S_CH_0 5 +#define LPC24XX_DMA_PER_I2S_CH_1 6 + +/** @} */ + +/** + * @name LPC32XX DMA Peripherals + * + * @{ + */ + +#define LPC32XX_DMA_PER_I2S_0_CH_0 0 +#define LPC32XX_DMA_PER_I2S_0_CH_1 13 +#define LPC32XX_DMA_PER_I2S_1_CH_0 2 +#define LPC32XX_DMA_PER_I2S_1_CH_1 10 +#define LPC32XX_DMA_PER_NAND_0 1 +#define LPC32XX_DMA_PER_NAND_1 12 +#define LPC32XX_DMA_PER_SD_MMC 4 +#define LPC32XX_DMA_PER_SSP_0_RX 14 +#define LPC32XX_DMA_PER_SSP_0_TX 15 +#define LPC32XX_DMA_PER_SSP_1_RX 3 +#define LPC32XX_DMA_PER_SSP_1_TX 11 +#define LPC32XX_DMA_PER_UART_1_RX 6 +#define LPC32XX_DMA_PER_UART_1_TX 5 +#define LPC32XX_DMA_PER_UART_2_RX 8 +#define LPC32XX_DMA_PER_UART_2_TX 7 +#define LPC32XX_DMA_PER_UART_7_RX 10 +#define LPC32XX_DMA_PER_UART_7_TX 9 + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */ diff --git a/bsps/arm/include/bsp/lpc-emc.h b/bsps/arm/include/bsp/lpc-emc.h new file mode 100644 index 0000000000..31cb4241c8 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-emc.h @@ -0,0 +1,170 @@ +/** + * @file + * + * @ingroup lpc_emc + * + * @brief EMC support API. + */ + +/* + * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H +#define LIBBSP_ARM_SHARED_LPC_EMC_H + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup lpc_emc EMC Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief EMC Support + * + * @{ + */ + +/** + * @name EMC Control Register (EMCControl) + * + * @{ + */ + +#define EMC_CTRL_E BSP_BIT32(0) +#define EMC_CTRL_M BSP_BIT32(0) +#define EMC_CTRL_L BSP_BIT32(2) + +/** @} */ + +/** + * @name EMC Dynamic Memory Control Register (EMCDynamicControl) + * + * @{ + */ + +#define EMC_DYN_CTRL_CE BSP_BIT32(0) +#define EMC_DYN_CTRL_CS BSP_BIT32(1) +#define EMC_DYN_CTRL_SR BSP_BIT32(2) +#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3) +#define EMC_DYN_CTRL_IMCC BSP_BIT32(4) +#define EMC_DYN_CTRL_MCC BSP_BIT32(5) +#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8) +#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8) +#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8) +#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8) +#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8) +#define EMC_DYN_CTRL_DP BSP_BIT32(13) + +/** @} */ + +/** + * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) + * + * @{ + */ + +#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1) +#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4) +#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9) +#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12) + +/** @} */ + +/** + * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN) + * + * @{ + */ + +#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4) +#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2) +#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14) +#define EMC_DYN_CFG_B BSP_BIT32(19) +#define EMC_DYN_CFG_P BSP_BIT32(20) + +/** @} */ + +/** + * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN) + * + * @{ + */ + +#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3) +#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10) + +/** @} */ + +#define EMC_DYN_CHIP_COUNT 4 + +#define EMC_STATIC_CHIP_COUNT 4 + +typedef struct { + uint32_t config; + uint32_t rascas; + uint32_t reserved_0 [6]; +} lpc_emc_dynamic; + +typedef struct { + uint32_t config; + uint32_t waitwen; + uint32_t waitoen; + uint32_t waitrd; + uint32_t waitpage; + uint32_t waitwr; + uint32_t waitturn; + uint32_t reserved_0 [1]; +} lpc_emc_static; + +typedef struct { + uint32_t control; + uint32_t status; + uint32_t config; + uint32_t reserved_0 [5]; + uint32_t dynamiccontrol; + uint32_t dynamicrefresh; + uint32_t dynamicreadconfig; + uint32_t reserved_1; + uint32_t dynamictrp; + uint32_t dynamictras; + uint32_t dynamictsrex; + uint32_t dynamictapr; + uint32_t dynamictdal; + uint32_t dynamictwr; + uint32_t dynamictrc; + uint32_t dynamictrfc; + uint32_t dynamictxsr; + uint32_t dynamictrrd; + uint32_t dynamictmrd; + uint32_t dynamictcdlr; + uint32_t reserved_3 [8]; + uint32_t staticextendedwait; + uint32_t reserved_4 [31]; + lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT]; + uint32_t reserved_5 [32]; + lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT]; +} lpc_emc; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */ diff --git a/bsps/arm/include/bsp/lpc-i2s.h b/bsps/arm/include/bsp/lpc-i2s.h new file mode 100644 index 0000000000..65e951b7d7 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-i2s.h @@ -0,0 +1,132 @@ +/** + * @file + * + * @ingroup lpc_i2s + * + * @brief I2S API. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H +#define LIBBSP_ARM_SHARED_LPC_I2S_H + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_i2s I2S Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief I2S support. + * + * @{ + */ + +/** + * @brief I2S control block. + */ +typedef struct { + uint32_t dao; + uint32_t dai; + uint32_t txfifo; + uint32_t rxfifo; + uint32_t state; + uint32_t dma [2]; + uint32_t irq; + uint32_t txrate; + uint32_t rxrate; +} lpc_i2s; + +/** + * @name I2S Digital Audio Input and Output + * + * @{ + */ + +#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1) +#define I2S_DAIO_MONO BSP_BIT32(2) +#define I2S_DAIO_STOP BSP_BIT32(3) +#define I2S_DAIO_RESET BSP_BIT32(4) +#define I2S_DAIO_WS_SEL BSP_BIT32(5) +#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14) +#define I2S_DAIO_MUTE BSP_BIT32(15) + +/** @} */ + +/** + * @name I2S Status Feedback + * + * @{ + */ + +#define I2S_STATE_IRQ BSP_BIT32(0) +#define I2S_STATE_DMAREQ_0 BSP_BIT32(1) +#define I2S_STATE_DMAREQ_1 BSP_BIT32(2) +#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19) + +/** @} */ + +/** + * @name I2S DMA Configuration + * + * @{ + */ + +#define I2S_DMA_RX_ENABLE BSP_BIT32(0) +#define I2S_DMA_TX_ENABLE BSP_BIT32(1) +#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Interrupt Request Control + * + * @{ + */ + +#define I2S_IRQ_RX BSP_BIT32(0) +#define I2S_IRQ_TX BSP_BIT32(1) +#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11) +#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19) + +/** @} */ + +/** + * @name I2S Transmit and Receive Clock Rate + * + * @{ + */ + +#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9) +#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7) +#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */ diff --git a/bsps/arm/include/bsp/lpc-lcd.h b/bsps/arm/include/bsp/lpc-lcd.h new file mode 100644 index 0000000000..a3ca4fe11a --- /dev/null +++ b/bsps/arm/include/bsp/lpc-lcd.h @@ -0,0 +1,213 @@ +/** + * @file + * + * @ingroup lpc_lcd + * + * @brief LCD support API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H +#define LIBBSP_ARM_SHARED_LPC_LCD_H + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_lcd LCD Support + * + * @ingroup lpc + * @ingroup arm_lpc32xx + * + * @brief LCD support. + * + * @{ + */ + +typedef struct { + uint8_t img [1024]; + uint32_t ctrl; + uint32_t cfg; + uint32_t pal0; + uint32_t pal1; + uint32_t xy; + uint32_t clip; + uint32_t intmsk; + uint32_t intclr; + uint32_t intraw; + uint32_t intstat; +} lpc_cursor; + +typedef struct { + uint32_t timh; + uint32_t timv; + uint32_t pol; + uint32_t le; + uint32_t upbase; + uint32_t lpbase; + uint32_t ctrl; + uint32_t intmsk; + uint32_t intraw; + uint32_t intstat; + uint32_t intclr; + uint32_t upcurr; + uint32_t lpcurr; + uint8_t reserved_0 [0x200 - 0x034]; + uint16_t pal [256]; + uint8_t reserved_1 [0x800 - 0x400]; + lpc_cursor crsr; +} lpc_lcd; + +/** + * @name LCD Configuration Register + * + * @{ + */ + +#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4) +#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5) +#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7) +#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8) + +/** @} */ + +/** + * @name LCD Horizontal Timing Register + * + * @{ + */ + +#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7) +#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) +#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15) +#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Vertical Timing Register + * + * @{ + */ + +#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9) +#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15) +#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23) +#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31) +#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) + +/** @} */ + +/** + * @name LCD Clock and Signal Polarity Register + * + * @{ + */ + +#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4) +#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define LCD_POL_CLKSEL BSP_BIT32(5) +#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10) +#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define LCD_POL_IVS BSP_BIT32(11) +#define LCD_POL_IHS BSP_BIT32(12) +#define LCD_POL_IPC BSP_BIT32(13) +#define LCD_POL_IOE BSP_BIT32(14) +#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25) +#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) +#define LCD_POL_BCD BSP_BIT32(26) +#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31) +#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) + +/** @} */ + +/** + * @name LCD Line End Control Register + * + * @{ + */ + +#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6) +#define LCD_LE_LEE BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Control Register + * + * @{ + */ + +#define LCD_CTRL_LCDEN BSP_BIT32(0) +#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3) +#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3) +#define LCD_CTRL_LCDBW BSP_BIT32(4) +#define LCD_CTRL_LCDTFT BSP_BIT32(5) +#define LCD_CTRL_LCDMONO8 BSP_BIT32(6) +#define LCD_CTRL_LCDDUAL BSP_BIT32(7) +#define LCD_CTRL_BGR BSP_BIT32(8) +#define LCD_CTRL_BEBO BSP_BIT32(9) +#define LCD_CTRL_BEPO BSP_BIT32(10) +#define LCD_CTRL_LCDPWR BSP_BIT32(11) +#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13) +#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define LCD_CTRL_WATERMARK BSP_BIT32(16) + +/** @} */ + +/** + * @name LCD Interrupt Registers + * + * @{ + */ + +#define LCD_INT_FUF BSP_BIT32(1) +#define LCD_INT_LNBU BSP_BIT32(2) +#define LCD_INT_VCOMP BSP_BIT32(3) +#define LCD_INT_BER BSP_BIT32(4) + +/** @} */ + +/** + * @name LCD Color Palette Register + * + * @{ + */ + +#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4) +#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9) +#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14) +#define LCD_PAL_I BSP_BIT16(15) + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */ diff --git a/bsps/arm/include/bsp/lpc-timer.h b/bsps/arm/include/bsp/lpc-timer.h new file mode 100644 index 0000000000..4c7ad4f1d1 --- /dev/null +++ b/bsps/arm/include/bsp/lpc-timer.h @@ -0,0 +1,159 @@ +/** + * @file + * + * @ingroup lpc_timer + * + * @brief Timer API. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H +#define LIBBSP_ARM_SHARED_LPC_TIMER_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lpc_timer Timer Support + * + * @ingroup arm_lpc24xx + * @ingroup arm_lpc32xx + * + * @brief Timer support. + * + * @{ + */ + +/** + * @name Interrupt Register Defines + * + * @{ + */ + +#define LPC_TIMER_IR_MR0 0x1U +#define LPC_TIMER_IR_MR1 0x2U +#define LPC_TIMER_IR_MR2 0x4U +#define LPC_TIMER_IR_MR3 0x8U +#define LPC_TIMER_IR_CR0 0x10U +#define LPC_TIMER_IR_CR1 0x20U +#define LPC_TIMER_IR_CR2 0x40U +#define LPC_TIMER_IR_CR3 0x80U +#define LPC_TIMER_IR_ALL 0xffU + +/** @} */ + +/** + * @name Timer Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_TCR_EN 0x1U +#define LPC_TIMER_TCR_RST 0x2U + +/** @} */ + +/** + * @name Match Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_MCR_MR0_INTR 0x1U +#define LPC_TIMER_MCR_MR0_RST 0x2U +#define LPC_TIMER_MCR_MR0_STOP 0x4U +#define LPC_TIMER_MCR_MR1_INTR 0x8U +#define LPC_TIMER_MCR_MR1_RST 0x10U +#define LPC_TIMER_MCR_MR1_STOP 0x20U +#define LPC_TIMER_MCR_MR2_INTR 0x40U +#define LPC_TIMER_MCR_MR2_RST 0x80U +#define LPC_TIMER_MCR_MR2_STOP 0x100U +#define LPC_TIMER_MCR_MR3_INTR 0x200U +#define LPC_TIMER_MCR_MR3_RST 0x400U +#define LPC_TIMER_MCR_MR3_STOP 0x800U + +/** @} */ + +/** + * @name Capture Control Register Defines + * + * @{ + */ + +#define LPC_TIMER_CCR_CAP0_RE 0x1U +#define LPC_TIMER_CCR_CAP0_FE 0x2U +#define LPC_TIMER_CCR_CAP0_INTR 0x4U +#define LPC_TIMER_CCR_CAP1_RE 0x8U +#define LPC_TIMER_CCR_CAP1_FE 0x10U +#define LPC_TIMER_CCR_CAP1_INTR 0x20U +#define LPC_TIMER_CCR_CAP2_RE 0x40U +#define LPC_TIMER_CCR_CAP2_FE 0x80U +#define LPC_TIMER_CCR_CAP2_INTR 0x100U +#define LPC_TIMER_CCR_CAP3_RE 0x200U +#define LPC_TIMER_CCR_CAP3_FE 0x400U +#define LPC_TIMER_CCR_CAP3_INTR 0x800U + +/** @} */ + +/** + * @name External Match Register Defines + * + * @{ + */ + +#define LPC_TIMER_EMR_EM0_RE 0x1U +#define LPC_TIMER_EMR_EM1_FE 0x2U +#define LPC_TIMER_EMR_EM2_INTR 0x4U +#define LPC_TIMER_EMR_EM3_RE 0x8U +#define LPC_TIMER_EMR_EMC0_FE 0x10U +#define LPC_TIMER_EMR_EMC1_INTR 0x20U +#define LPC_TIMER_EMR_EMC2_RE 0x40U +#define LPC_TIMER_EMR_EMC3_FE 0x80U + +/** @} */ + +/** + * @brief Timer control block. + */ +typedef struct { + uint32_t ir; + uint32_t tcr; + uint32_t tc; + uint32_t pr; + uint32_t pc; + uint32_t mcr; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t ccr; + uint32_t cr0; + uint32_t cr1; + uint32_t cr2; + uint32_t cr3; + uint32_t emr; + uint32_t ctcr; +} lpc_timer; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */ diff --git a/bsps/arm/include/bsp/start.h b/bsps/arm/include/bsp/start.h new file mode 100644 index 0000000000..bf8eed4433 --- /dev/null +++ b/bsps/arm/include/bsp/start.h @@ -0,0 +1,183 @@ +/** + * @file + * + * @ingroup arm_start + * + * @brief ARM system low level start. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_START_H +#define LIBBSP_ARM_SHARED_START_H + +#include <string.h> + +#include <bsp/linker-symbols.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_start System Start + * + * @ingroup arm_shared + * + * @brief ARM system low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/* +* Many ARM boot loaders pass arguments to loaded OS kernel +*/ +#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS +#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int saved_dtb_adr +#else +#define BSP_START_HOOKS_LOADER_ARGS void +#endif + +/** +* @brief System start entry. +*/ +void _start(void); + +/** +* @brief Start entry hook 0. +* +* This hook will be called from the start entry code after all modes and +* stack pointers are initialized but before the copying of the exception +* vectors. +*/ +void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS); + +/** +* @brief Start entry hook 1. +* +* This hook will be called from the start entry code after copying of the +* exception vectors but before the call to boot_card(). +*/ +void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS); + +/** + * @brief Similar to standard memcpy(). + * + * The memory areas must be word aligned. Copy code will be executed from the + * stack. If @a dest equals @a src nothing will be copied. + */ +void bsp_start_memcpy(int *dest, const int *src, size_t n); + +/** + * @brief ARM entry point to bsp_start_memcpy(). + */ +void bsp_start_memcpy_arm(int *dest, const int *src, size_t n); + +/** + * @brief Copies all standard sections from the load to the runtime area. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void) +{ + /* Copy .text section */ + bsp_start_memcpy( + (int *) bsp_section_text_begin, + (const int *) bsp_section_text_load_begin, + (size_t) bsp_section_text_size + ); + + /* Copy .rodata section */ + bsp_start_memcpy( + (int *) bsp_section_rodata_begin, + (const int *) bsp_section_rodata_load_begin, + (size_t) bsp_section_rodata_size + ); + + /* Copy .data section */ + bsp_start_memcpy( + (int *) bsp_section_data_begin, + (const int *) bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy( + (int *) bsp_section_fast_text_begin, + (const int *) bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy( + (int *) bsp_section_fast_data_begin, + (const int *) bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void +bsp_start_memcpy_libc(void *dest, const void *src, size_t n) +{ + if (dest != src) { + memcpy(dest, src, n); + } +} + +/** + * @brief Copies the .data, .fast_text and .fast_data sections from the load to + * the runtime area using the C library memcpy(). + * + * Works only in case the .start, .text and .rodata sections reside in one + * memory region. + */ +BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections_compact(void) +{ + /* Copy .data section */ + bsp_start_memcpy_libc( + bsp_section_data_begin, + bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast_text section */ + bsp_start_memcpy_libc( + bsp_section_fast_text_begin, + bsp_section_fast_text_load_begin, + (size_t) bsp_section_fast_text_size + ); + + /* Copy .fast_data section */ + bsp_start_memcpy_libc( + bsp_section_fast_data_begin, + bsp_section_fast_data_load_begin, + (size_t) bsp_section_fast_data_size + ); +} + +BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void) +{ + memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_START_H */ |