diff options
Diffstat (limited to 'bsps/arm/include/bsp/arm-a9mpcore-start.h')
| -rw-r--r-- | bsps/arm/include/bsp/arm-a9mpcore-start.h | 28 |
1 files changed, 4 insertions, 24 deletions
diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h b/bsps/arm/include/bsp/arm-a9mpcore-start.h index 5f870acec7..f377745c56 100644 --- a/bsps/arm/include/bsp/arm-a9mpcore-start.h +++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h @@ -30,6 +30,7 @@ #include <bsp.h> #include <bsp/start.h> #include <bsp/arm-a9mpcore-regs.h> +#include <bsp/arm-cp15-start.h> #include <bsp/arm-errata.h> #include <dev/irq/arm-gic-irq.h> @@ -37,27 +38,6 @@ extern "C" { #endif /* __cplusplus */ -BSP_START_TEXT_SECTION static inline void -arm_a9mpcore_start_set_vector_base(void) -{ - /* - * Do not use bsp_vector_table_begin == 0, since this will get optimized away. - */ - if (bsp_vector_table_end != bsp_vector_table_size) { - uint32_t ctrl; - - /* - * For now we assume that every Cortex-A9 MPCore has the Security Extensions. - * Later it might be necessary to evaluate the ID_PFR1 register. - */ - arm_cp15_set_vector_base_address(bsp_vector_table_begin); - - ctrl = arm_cp15_get_control(); - ctrl &= ~ARM_CP15_CTRL_V; - arm_cp15_set_control(ctrl); - } -} - BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate( volatile a9mpcore_scu *scu, uint32_t cpu_id, @@ -88,10 +68,11 @@ arm_a9mpcore_start_on_secondary_processor(void) { uint32_t ctrl; - arm_a9mpcore_start_set_vector_base(); - arm_gic_irq_initialize_secondary_cpu(); + /* Change the VBAR from the start to the normal vector table */ + arm_cp15_set_vector_base_address(bsp_vector_table_begin); + ctrl = arm_cp15_start_setup_mmu_and_cache( 0, ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z @@ -194,7 +175,6 @@ BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void) BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void) { arm_a9mpcore_start_global_timer(); - arm_a9mpcore_start_set_vector_base(); } #ifdef __cplusplus |