diff options
Diffstat (limited to 'bsps/arm/imxrt/mcux-sdk')
3 files changed, 34 insertions, 1 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h index 64ce9ee126..1936e4c5de 100644 --- a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/MIMXRT1166_cm7.h @@ -60038,6 +60038,31 @@ typedef struct { /*! @name CFGR0 - Configuration 0 */ /*! @{ */ +#ifdef __rtems__ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..LPSPI_HREQ pin is active low + * 0b1..LPSPI_HREQ pin is active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#endif /* __rtems__ */ #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c index 1e40dc4038..4928b1aad7 100644 --- a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c @@ -1735,7 +1735,11 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); USBPHY1->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#ifndef __rtems__ USBPHY1->PWD_SET = 0x0; +#else /* __rtems__ */ + USBPHY1->PWD = 0x0; +#endif /* __rtems__ */ while (0UL == (USBPHY1->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) { @@ -1841,7 +1845,11 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); USBPHY2->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#ifndef __rtems__ USBPHY2->PWD_SET = 0x0; +#else /* __rtems__ */ + USBPHY2->PWD = 0x0; +#endif /* __rtems__ */ while (0UL == (USBPHY2->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) { diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/qtmr_1/fsl_qtmr.c b/bsps/arm/imxrt/mcux-sdk/drivers/qtmr_1/fsl_qtmr.c index 4c8bd71be5..33271d6e9a 100644 --- a/bsps/arm/imxrt/mcux-sdk/drivers/qtmr_1/fsl_qtmr.c +++ b/bsps/arm/imxrt/mcux-sdk/drivers/qtmr_1/fsl_qtmr.c @@ -99,7 +99,7 @@ uint32_t QTMR_get_src_clk(TMR_Type *base) #elif IMXRT_IS_MIMXRT11xx (void) base; - return CLOCK_GetRootClockMux(kCLOCK_Root_Bus); + return CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); #else #error Getting Timer clock frequency is not implemented for this chip #endif |