diff options
Diffstat (limited to 'bsps/arm/imxrt/mcux-sdk/drivers/mecc')
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.c | 340 | ||||
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.h | 396 |
2 files changed, 736 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.c b/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.c new file mode 100644 index 0000000000..04ee5b7de5 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.c @@ -0,0 +1,340 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mecc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mecc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base MECC base address + * + * @return The MECC instance + */ +static uint32_t MECC_GetInstance(MECC_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MECC bases for each instance. */ +static MECC_Type *const s_meccBases[] = MECC_BASE_PTRS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MECC_GetInstance(MECC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_meccBases); instance++) + { + if (s_meccBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_meccBases)); + + return instance; +} + +/*! + * brief MECC module initialization function. + * + * param base MECC base address. + */ +void MECC_Init(MECC_Type *base, mecc_config_t *config) +{ + uint32_t instance = MECC_GetInstance(base); + volatile uint64_t *ocramStartAddr = NULL; + + /* enable all the interrupt status */ + base->ERR_STAT_EN = kMECC_AllInterruptsStatusEnable; + /* clear all the interrupt status */ + base->ERR_STATUS = kMECC_AllInterruptsFlag; + /* disable all the interrpt */ + base->ERR_SIG_EN = 0U; + + /* enable ECC function */ + base->PIPE_ECC_EN = MECC_PIPE_ECC_EN_ECC_EN(config->enableMecc); + + __DSB(); + + if (instance == (uint32_t)kMECC_Instance0) + { + /* Need to be initialized for ECC function operation, note that do not use memset() to initialize, + because it will use STR instruction and STR is byte access and MECC is 64 bits access operation. */ + ocramStartAddr = (uint64_t *)config->Ocram1StartAddress; + while (ocramStartAddr < (uint64_t *)config->Ocram1EndAddress) + { + *ocramStartAddr = 0x00; + ocramStartAddr++; + } + } + else if (instance == (uint32_t)kMECC_Instance1) + { + /* Need to be initialized for ECC function operation, note that do not use memset() to initialize, + because it will use STR instruction and STR is byte access and MECC is 64 bits access operation. */ + ocramStartAddr = (uint64_t *)config->Ocram2StartAddress; + while (ocramStartAddr < (uint64_t *)config->Ocram2EndAddress) + { + *ocramStartAddr = 0x00; + ocramStartAddr++; + } + } + else + { + ; /* Intentional empty for MISRA rule 15.7 */ + } +} + +/*! + * brief Deinitializes the MECC. + * + */ +void MECC_Deinit(MECC_Type *base) +{ + /* Disable ECC function */ + base->PIPE_ECC_EN &= ~MECC_PIPE_ECC_EN_ECC_EN(1); +} + +void MECC_GetDefaultConfig(mecc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Default MECC function. */ + config->enableMecc = false; + /* Ocram 1 start address */ + config->Ocram1StartAddress = 0x20240000; + /* Ocram 1 end address */ + config->Ocram1EndAddress = 0x202BFFFF; + /* Ocram 2 address */ + config->Ocram1StartAddress = 0x202C0000; + /* Ocram 2 address */ + config->Ocram1EndAddress = 0x2033FFFF; +} + +/* Initialize OCRAM */ + +/* Mainly use for debug, it can be deprecated when release */ +status_t MECC_ErrorInjection( + MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber) +{ + status_t status = kStatus_Success; + + switch (banknumber) + { + case kMECC_OcramBank0: + /* Low 32 bits of Ocram bank0 error injection */ + base->ERR_DATA_INJ_LOW0 = lowerrordata; + /* High 32 bits of Ocram bank0 error injection */ + base->ERR_DATA_INJ_HIGH0 = higherrordata; + /* Ecc code of Ocram bank0 error injection */ + base->ERR_ECC_INJ0 = eccdata; + break; + + case kMECC_OcramBank1: + /* Low 32 bits of Ocram bank1 error injection */ + base->ERR_DATA_INJ_LOW1 = lowerrordata; + /* High 32 bits of Ocram bank1 error injection */ + base->ERR_DATA_INJ_HIGH1 = higherrordata; + /* Ecc code of Ocram bank1 error injection */ + base->ERR_ECC_INJ1 = eccdata; + break; + + case kMECC_OcramBank2: + /* Low 32 bits of Ocram bank2 error injection */ + base->ERR_DATA_INJ_LOW2 = lowerrordata; + /* High 32 bits of Ocram bank2 error injection */ + base->ERR_DATA_INJ_HIGH2 = higherrordata; + /* Ecc code of Ocram bank2 error injection */ + base->ERR_ECC_INJ2 = eccdata; + break; + + case kMECC_OcramBank3: + /* Low 32 bits of Ocram bank3 error injection */ + base->ERR_DATA_INJ_LOW3 = lowerrordata; + /* High 32 bits of Ocram bank3 error injection */ + base->ERR_DATA_INJ_HIGH3 = higherrordata; + /* Ecc code of Ocram bank3 error injection */ + base->ERR_ECC_INJ3 = eccdata; + break; + + default: + status = kStatus_MECC_BankMiss; + break; + } + + return status; +} + +status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber) +{ + assert(info != NULL); + status_t status = kStatus_Success; + uint8_t tempPosLow = 0U; + uint8_t tempPosHigh = 0U; + uint32_t counter = 0U; + + switch (banknumber) + { + case kMECC_OcramBank0: + info->singleErrorEccCode = + (uint8_t)((base->SINGLE_ERR_ADDR_ECC0 & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT); + info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC0 & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT; + info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW0; + info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH0; + tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW0; + tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH0; + break; + + case kMECC_OcramBank1: + info->singleErrorEccCode = + (uint8_t)((base->SINGLE_ERR_ADDR_ECC1 & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT); + info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC1 & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT; + info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW1; + info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH1; + tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW1; + tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH1; + break; + + case kMECC_OcramBank2: + info->singleErrorEccCode = + (uint8_t)((base->SINGLE_ERR_ADDR_ECC2 & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT); + info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC2 & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT; + info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW2; + info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH2; + tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW2; + tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH2; + break; + + case kMECC_OcramBank3: + info->singleErrorEccCode = + (uint8_t)((base->SINGLE_ERR_ADDR_ECC3 & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT); + info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC3 & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK) >> + MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT; + info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW3; + info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH3; + tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW3; + tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH3; + break; + + default: + status = kStatus_MECC_BankMiss; + break; + } + + while (tempPosLow > 0U) + { + tempPosLow = tempPosLow >> 1; + counter++; + } + + if (counter == 0U) + { + info->singleErrorPosLow = 0; + } + else + { + info->singleErrorPosLow = counter - 1U; + } + + counter = 0U; + while (tempPosHigh > 0U) + { + tempPosHigh = tempPosHigh >> 1; + counter++; + } + + if (counter == 0U) + { + info->singleErrorPosHigh = 0; + } + else + { + info->singleErrorPosHigh = counter - 1U; + } + + return status; +} + +status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber) +{ + assert(info != NULL); + status_t status = kStatus_Success; + + switch (banknumber) + { + case kMECC_OcramBank0: + info->multiErrorEccCode = + (uint8_t)((base->MULTI_ERR_ADDR_ECC0 & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK) >> + MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT); + info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC0 & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK) >> + MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT; + info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW0; + info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH0; + break; + + case kMECC_OcramBank1: + info->multiErrorEccCode = + (uint8_t)((base->MULTI_ERR_ADDR_ECC1 & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK) >> + MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT); + info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC1 & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK) >> + MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT; + info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW1; + info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH1; + break; + + case kMECC_OcramBank2: + info->multiErrorEccCode = + (uint8_t)((base->MULTI_ERR_ADDR_ECC2 & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK) >> + MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT); + info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC2 & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK) >> + MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT; + info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW2; + info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH2; + break; + + case kMECC_OcramBank3: + info->multiErrorEccCode = + (uint8_t)((base->MULTI_ERR_ADDR_ECC3 & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK) >> + MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT); + info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC3 & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK) >> + MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT; + info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW3; + info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH3; + break; + + default: + status = kStatus_MECC_BankMiss; + break; + } + + return status; +} diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.h b/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.h new file mode 100644 index 0000000000..472bac08d4 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/mecc/fsl_mecc.h @@ -0,0 +1,396 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MECC_H_ +#define _FSL_MECC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mecc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.2. */ +#define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) +/*@}*/ +/*! @brief Error codes for the MECC driver. */ +enum +{ + kStatus_MECC_BankMiss = MAKE_STATUS(kStatusGroup_MECC, 0), /*!< Ocram bank miss */ +}; + +/*! + * @brief MECC interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the MECC interrupt configurations. + */ +enum +{ + kMECC_SingleError0InterruptEnable = + MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt enable.*/ + kMECC_SingleError1InterruptEnable = + MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt enable*/ + kMECC_SingleError2InterruptEnable = + MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt enable*/ + kMECC_SingleError3InterruptEnable = + MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt enable*/ + + kMECC_MultiError0InterruptEnable = + MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt enable*/ + kMECC_MultiError1InterruptEnable = + MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt enable*/ + kMECC_MultiError2InterruptEnable = + MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt enable*/ + kMECC_MultiError3InterruptEnable = + MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt enable*/ + + kMECC_StrobeError0InterruptEnable = + MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt enable*/ + kMECC_StrobeError1InterruptEnable = + MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt enable*/ + kMECC_StrobeError2InterruptEnable = + MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt enable*/ + kMECC_StrobeError3InterruptEnable = + MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt enable*/ + + kMECC_AccessError0InterruptEnable = + MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt enable*/ + kMECC_AccessError1InterruptEnable = + MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt enable*/ + kMECC_AccessError2InterruptEnable = + MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt enable*/ + kMECC_AccessError3InterruptEnable = + MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt enable*/ + + kMECC_AllInterruptsEnable = 0xFFFF, /*!< all interrupts enable */ +}; + +/*! + * @brief MECC interrupt status configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the MECC interrupt status configurations. + */ +enum +{ + kMECC_SingleError0InterruptStatusEnable = + MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt status enable.*/ + kMECC_SingleError1InterruptStatusEnable = + MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt status enable*/ + kMECC_SingleError2InterruptStatusEnable = + MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt status enable*/ + kMECC_SingleError3InterruptStatusEnable = + MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt status enable*/ + + kMECC_MultiError0InterruptStatusEnable = + MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt status enable*/ + kMECC_MultiError1InterruptStatusEnable = + MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt status enable*/ + kMECC_MultiError2InterruptStatusEnable = + MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt status enable*/ + kMECC_MultiError3InterruptStatusEnable = + MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt status enable*/ + + kMECC_StrobeError0InterruptStatusEnable = + MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt status enable*/ + kMECC_StrobeError1InterruptStatusEnable = + MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt status enable*/ + kMECC_StrobeError2InterruptStatusEnable = + MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt status enable*/ + kMECC_StrobeError3InterruptStatusEnable = + MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt status enable*/ + + kMECC_AccessError0InterruptStatusEnable = + MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt status enable*/ + kMECC_AccessError1InterruptStatusEnable = + MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt status enable*/ + kMECC_AccessError2InterruptStatusEnable = + MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt status enable*/ + kMECC_AccessError3InterruptStatusEnable = + MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt status enable*/ + + kMECC_AllInterruptsStatusEnable = 0xFFFF, /*!< all interrupts enable */ +}; + +/*! + * @brief MECC status flags. + * + * This provides constants for the MECC status flags for use in the MECC functions. + */ +enum +{ + kMECC_SingleError0InterruptFlag = + MECC_ERR_STATUS_SINGLE_ERR0_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt flag*/ + kMECC_SingleError1InterruptFlag = + MECC_ERR_STATUS_SINGLE_ERR1_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt flag*/ + kMECC_SingleError2InterruptFlag = + MECC_ERR_STATUS_SINGLE_ERR2_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt flag*/ + kMECC_SingleError3InterruptFlag = + MECC_ERR_STATUS_SINGLE_ERR3_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt flag*/ + + kMECC_MultiError0InterruptFlag = + MECC_ERR_STATUS_MULTI_ERR0_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt flag*/ + kMECC_MultiError1InterruptFlag = + MECC_ERR_STATUS_MULTI_ERR1_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt flag*/ + kMECC_MultiError2InterruptFlag = + MECC_ERR_STATUS_MULTI_ERR2_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt flag*/ + kMECC_MultiError3InterruptFlag = + MECC_ERR_STATUS_MULTI_ERR3_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt flag*/ + + kMECC_StrobeError0InterruptFlag = + MECC_ERR_STATUS_STRB_ERR0_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt flag*/ + kMECC_StrobeError1InterruptFlag = + MECC_ERR_STATUS_STRB_ERR1_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt flag*/ + kMECC_StrobeError2InterruptFlag = + MECC_ERR_STATUS_STRB_ERR2_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt flag*/ + kMECC_StrobeError3InterruptFlag = + MECC_ERR_STATUS_STRB_ERR3_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt flag*/ + + kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK, /*!< Ocram Access Error On Bank0 interrupt flag*/ + kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK, /*!< Ocram Access Error On Bank1 interrupt flag*/ + kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK, /*!< Ocram Access Error On Bank2 interrupt flag*/ + kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK, /*!< Ocram Access Error On Bank3 interrupt flag*/ + + kMECC_AllInterruptsFlag = 0xFFFF, /*!< all interrupts interrupt flag */ +}; + +/*! @brief MECC ocram bank number */ +enum +{ + kMECC_OcramBank0 = 0U, /*!< ocram bank number 0: ocram_base_address+0x20*i */ + kMECC_OcramBank1 = 1U, /*!< ocram bank number 1: ocram_base_address+0x20*i+0x8 */ + kMECC_OcramBank2 = 2U, /*!< ocram bank number 2: ocram_base_address+0x20*i+0x10 */ + kMECC_OcramBank3 = 3U, /*!< ocram bank number 3: ocram_base_address+0x20*i+0x18 */ +}; + +/*! @brief MECC instance */ +enum +{ + kMECC_Instance0 = 0U, /*!< Peripheral MECC1 base */ + kMECC_Instance1 = 1U, /*!< Peripheral MECC2 base */ +}; + +/*! @brief MECC user configuration.*/ +typedef struct _mecc_config +{ + bool enableMecc; /*!< Enable the MECC function. */ + uint32_t Ocram1StartAddress; /*!< Ocram 1 start address. */ + uint32_t Ocram1EndAddress; /*!< Ocram 1 end address. */ + uint32_t Ocram2StartAddress; /*!< Ocram 2 start address. */ + uint32_t Ocram2EndAddress; /*!< Ocram 2 end address. */ +} mecc_config_t; + +/*! @brief MECC ocram single error information, including single error address, ECC code, error data and error bit + * position */ +typedef struct _mecc_single_error_info +{ + uint32_t singleErrorAddress; /*!< Single error address on Ocram bank n */ + uint32_t singleErrorDataLow; /*!< Single error low 32 bits uncorrected read data on Ocram bank n */ + uint32_t singleErrorDataHigh; /*!< Single error high 32 bits uncorrected read data on Ocram bank n */ + uint32_t singleErrorPosLow; /*!< Single error bit postion of low 32 bits read data on Ocram bank n */ + uint32_t singleErrorPosHigh; /*!< Single error bit postion of high 32 bits read data on Ocram bank n */ + uint8_t singleErrorEccCode; /*!< Single error ECC code on Ocram bank n */ +} mecc_single_error_info_t; + +/*! @brief MECC ocram multiple error information, including multiple error address, ECC code, error data */ +typedef struct _mecc_multi_error_info +{ + uint32_t multiErrorAddress; /*!< Multiple error address on Ocram bank n */ + uint32_t multiErrorDataLow; /*!< Multiple error low 32 bits read data on Ocram bank n */ + uint32_t multiErrorDataHigh; /*!< Multiple error high 32 bits read data on Ocram bank n */ + uint8_t multiErrorEccCode; /*!< Multiple error ECC code on Ocram bank n */ +} mecc_multi_error_info_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief MECC module initialization function. + * + * @param base MECC base address. + * @param config pointer to the MECC configuration structure. + */ +void MECC_Init(MECC_Type *base, mecc_config_t *config); + +/*! + * @brief Deinitializes the MECC. + * + * @param base MECC base address. + */ +void MECC_Deinit(MECC_Type *base); + +/*! + * @brief Sets the MECC configuration structure to default values. + * + * @param config pointer to the MECC configuration structure. + */ +void MECC_GetDefaultConfig(mecc_config_t *config); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Gets MECC status flags. + * + * @param base MECC peripheral base address. + * @return MECC status flags. + */ +static inline uint32_t MECC_GetStatusFlags(MECC_Type *base) +{ + return base->ERR_STATUS & (uint32_t)kMECC_AllInterruptsFlag; +} + +/*! + * @brief MECC module clear interrupt status. + * + * @param base MECC base address. + * @param mask status to clear. + */ +static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask) +{ + base->ERR_STATUS = mask; +} + +/*! + * @brief MECC module enable interrupt status. + * + * @param base MECC base address. + * @param mask status to enable. + */ +static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask) +{ + base->ERR_STAT_EN |= mask; +} + +/*! + * @brief MECC module disable interrupt status. + * + * @param base MECC base address. + * @param mask status to disable. + */ +static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask) +{ + base->ERR_STAT_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief MECC module enable interrupt. + * + * @param base MECC base address. + * @param mask The interrupts to enable. + */ +static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask) +{ + base->ERR_SIG_EN |= mask; +} + +/*! + * @brief MECC module disable interrupt. + * + * @param base MECC base address. + * @param mask The interrupts to disable. + */ +static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask) +{ + base->ERR_SIG_EN &= ~mask; +} +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief MECC module error injection. + * + * @param base MECC base address. + * @param lowerrordata low 32 bits data. + * @param higherrordata high 32 bits data. + * @param eccdata ecc code. + * @param banknumber ocram bank number. + * @retval kStatus_Success. + * + * Bank0: ocram_base_address+0x20*i + * Bank1: ocram_base_address+0x20*i+0x8 + * Bank2: ocram_base_address+0x20*i+0x10 + * Bank3: ocram_base_address+0x20*i+0x18 + * i = 0,1,2,3,4..... + */ +status_t MECC_ErrorInjection( + MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber); + +/*! + * @brief MECC module get single error information. + * + * @param base MECC base address. + * @param info single error information. + * @param banknumber ocram bank number. + * @retval kStatus_Success. + * @retval kStatus_MECC_BankMiss. + * + * Bank0: ocram_base_address+0x20*i + * Bank1: ocram_base_address+0x20*i+0x8 + * Bank2: ocram_base_address+0x20*i+0x10 + * Bank3: ocram_base_address+0x20*i+0x18 + * i = 0,1,2,3,4..... + */ +status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber); + +/*! + * @brief MECC module get multiple error information. + * + * @param base MECC base address. + * @param info multiple error information. + * @param banknumber ocram bank number. + * @retval kStatus_Success. + * @retval kStatus_MECC_BankMiss. + * + * Bank0: ocram_base_address+0x20*i + * Bank1: ocram_base_address+0x20*i+0x8 + * Bank2: ocram_base_address+0x20*i+0x10 + * Bank3: ocram_base_address+0x20*i+0x18 + * i = 0,1,2,3,4..... + */ +status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif |