diff options
Diffstat (limited to 'bsps/arm/imxrt/mcux-sdk/drivers/flexram')
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.c | 423 | ||||
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.h | 508 |
2 files changed, 931 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.c b/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.c new file mode 100644 index 0000000000..65e7318301 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.c @@ -0,0 +1,423 @@ +/* + * Copyright 2017-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexram.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexram" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base FLEXRAM base address + * + * @return The FLEXRAM instance + */ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FLEXRAM bases for each instance. */ +static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FLEXRAM clocks for each instance. */ +static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO +/*! Look-up table to calculate single-bit error bit position for ITCM. */ +static const uint8_t ItcmLookUpTable[64] = { + 0xC1, 0x43, 0x9E, 0x83, 0x15, 0x4C, 0x4A, 0x8C, 0x31, 0x1C, 0xA2, 0xE0, 0x51, 0x2C, 0xC2, 0xD0, + 0x19, 0x1A, 0x26, 0xEA, 0x29, 0x94, 0x16, 0x64, 0x37, 0xA4, 0x0D, 0xC4, 0x75, 0x38, 0x4F, 0x58, + 0x46, 0x91, 0x86, 0x61, 0x49, 0x98, 0x89, 0x68, 0x32, 0x34, 0x07, 0xC8, 0x92, 0xA8, 0xA7, 0x54, + 0xA1, 0xD9, 0x25, 0xF8, 0x0E, 0x0B, 0x8A, 0x2A, 0x52, 0x45, 0x13, 0x85, 0x62, 0x70, 0x23, 0xB0}; +/*! Look-up table to calculate single-bit error bit position for DTCM. */ +static const uint8_t DtcmLookUpTable[32] = {0x61, 0x51, 0x19, 0x45, 0x43, 0x31, 0x29, 0x13, 0x62, 0x52, 0x4A, + 0x46, 0x32, 0x2A, 0x23, 0x1A, 0x2C, 0x64, 0x26, 0x25, 0x34, 0x16, + 0x15, 0x54, 0x0B, 0x58, 0x1C, 0x4C, 0x38, 0x0E, 0x0D, 0x49}; +#endif /* FLEXRAM_ECC_ERROR_DETAILED_INFO */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++) + { + if (s_flexramBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexramBases)); + + return instance; +} + +/*! + * brief FLEXRAM module initialization function. + * + * param base FLEXRAM base address. + */ +void FLEXRAM_Init(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* enable all the interrupt status */ + base->INT_STAT_EN |= (uint32_t)kFLEXRAM_InterruptStatusAll; + /* clear all the interrupt status */ + base->INT_STATUS |= (uint32_t)kFLEXRAM_InterruptStatusAll; + /* disable all the interrpt */ + base->INT_SIG_EN = 0U; +} + +/*! + * brief Deinitializes the FLEXRAM. + * + */ +void FLEXRAM_Deinit(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC) +void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable) +{ + if (true == OcramECCEnable) + { + base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK; + } + else + { + base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK; + } + + if (true == TcmECCEnable) + { + base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK; + } + else + { + base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK; + } +} + +void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error) +{ + assert(error != NULL); + + switch (memory) + { + case kFLEXRAM_OCRAM: + base->OCRAM_ECC_ERROR_INJEC = + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_ITCM: + base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_D0TCM: + base->D0TCM_ECC_ERROR_INJEC = + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion); + break; + case kFLEXRAM_D1TCM: + base->D1TCM_ECC_ERROR_INJEC = + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) | + FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion); + break; + default: + assert(NULL); + break; + } + + __DSB(); +} + +void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info) +{ + assert(NULL != info); + +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + info->OcramSingleErrorECCCipher = + (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) >> + FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT); + info->OcramSingleErrorECCSyndrome = + (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) >> + FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT); +#else + info->OcramSingleErrorInfo = base->OCRAM_ECC_SINGLE_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->OcramSingleErrorAddr = base->OCRAM_ECC_SINGLE_ERROR_ADDR; + info->OcramSingleErrorDataLSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_LSB; + info->OcramSingleErrorDataMSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_MSB; +} + +void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info) +{ + assert(NULL != info); + +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + info->OcramMultiErrorECCCipher = + (uint8_t)((base->OCRAM_ECC_MULTI_ERROR_INFO & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) >> + FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT); +#else + info->OcramMultiErrorInfo = base->OCRAM_ECC_MULTI_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + info->OcramMultiErrorAddr = base->OCRAM_ECC_MULTI_ERROR_ADDR; + info->OcramMultiErrorDataLSB = base->OCRAM_ECC_MULTI_ERROR_DATA_LSB; + info->OcramMultiErrorDataMSB = base->OCRAM_ECC_MULTI_ERROR_DATA_MSB; +} + +void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info) +{ + assert(NULL != info); + +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */ + uint8_t singleErrorECCSyndrome = 0x00U; + + info->ItcmSingleErrorTCMWriteRead = + (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) >> + FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT); + info->ItcmSingleErrorTCMAccessSize = + (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT); + info->ItcmSingleErrorTCMMaster = + (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >> + FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT); + info->ItcmSingleErrorTCMPrivilege = + (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >> + FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT); + singleErrorECCSyndrome = + (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >> + FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT); + + for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++) + { + if (singleErrorECCSyndrome == ItcmLookUpTable[i]) + { + info->ItcmSingleErrorBitPostion = i; + break; + } + } +#else + info->ItcmSingleErrorInfo = base->ITCM_ECC_SINGLE_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->ItcmSingleErrorAddr = base->ITCM_ECC_SINGLE_ERROR_ADDR; + info->ItcmSingleErrorDataLSB = base->ITCM_ECC_SINGLE_ERROR_DATA_LSB; + info->ItcmSingleErrorDataMSB = base->ITCM_ECC_SINGLE_ERROR_DATA_MSB; +} + +void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info) +{ + assert(NULL != info); + +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + info->ItcmMultiErrorTCMWriteRead = + (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >> + FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_SHIFT); + info->ItcmMultiErrorTCMAccessSize = + (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT); + info->ItcmMultiErrorTCMMaster = + (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >> + FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT); + info->ItcmMultiErrorTCMPrivilege = + (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >> + FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT); + info->ItcmMultiErrorECCSyndrome = + (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >> + FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT); +#else + info->ItcmMultiErrorInfo = base->ITCM_ECC_MULTI_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->ItcmMultiErrorAddr = base->ITCM_ECC_MULTI_ERROR_ADDR; + info->ItcmMultiErrorDataLSB = base->ITCM_ECC_MULTI_ERROR_DATA_LSB; + info->ItcmMultiErrorDataMSB = base->ITCM_ECC_MULTI_ERROR_DATA_MSB; +} + +void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank) +{ + assert(NULL != info); + assert((0x00U == bank) || (0x01U == bank)); + + if (0x00U == bank) + { +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */ + uint8_t singleErrorECCSyndrome = 0x00U; + + info->DtcmSingleErrorTCMWriteRead = + (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >> + FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT); + info->DtcmSingleErrorTCMAccessSize = + (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT); + info->DtcmSingleErrorTCMMaster = + (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >> + FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT); + info->DtcmSingleErrorTCMPrivilege = + (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >> + FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT); + singleErrorECCSyndrome = + (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >> + FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT); + + for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++) + { + if (singleErrorECCSyndrome == ItcmLookUpTable[i]) + { + info->DtcmSingleErrorBitPostion = i; + break; + } + } +#else + info->DtcmSingleErrorInfo = base->D0TCM_ECC_SINGLE_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->DtcmSingleErrorAddr = base->D0TCM_ECC_SINGLE_ERROR_ADDR; + info->DtcmSingleErrorData = base->D0TCM_ECC_SINGLE_ERROR_DATA; + } + else + { +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */ + uint8_t singleErrorECCSyndrome = 0x00U; + + info->DtcmSingleErrorTCMWriteRead = + (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) >> + FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT); + info->DtcmSingleErrorTCMAccessSize = + (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT); + info->DtcmSingleErrorTCMMaster = + (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) >> + FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT); + info->DtcmSingleErrorTCMPrivilege = + (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) >> + FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT); + singleErrorECCSyndrome = + (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) >> + FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT); + + for (uint8_t i = 0x00U; i < sizeof(DtcmLookUpTable) / sizeof(DtcmLookUpTable[0]); i++) + { + if (singleErrorECCSyndrome == DtcmLookUpTable[i]) + { + info->DtcmSingleErrorBitPostion = i; + break; + } + } +#else + info->DtcmSingleErrorInfo = base->D1TCM_ECC_SINGLE_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->DtcmSingleErrorAddr = base->D1TCM_ECC_SINGLE_ERROR_ADDR; + info->DtcmSingleErrorData = base->D1TCM_ECC_SINGLE_ERROR_DATA; + } +} + +void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank) +{ + assert(NULL != info); + assert((0x00U == bank) || (0x01U == bank)); + + if (0x00U == bank) + { +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + info->DtcmMultiErrorTCMWriteRead = + (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >> + FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT); + info->DtcmMultiErrorTCMAccessSize = + (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT); + info->DtcmMultiErrorTCMMaster = + (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >> + FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT); + info->DtcmMultiErrorTCMPrivilege = + (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >> + FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT); + info->DtcmMultiErrorECCSyndrome = + (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >> + FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT); +#else + info->DtcmMultiErrorInfo = base->D0TCM_ECC_MULTI_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->DtcmMultiErrorAddr = base->D0TCM_ECC_MULTI_ERROR_ADDR; + info->DtcmMultiErrorData = base->D0TCM_ECC_MULTI_ERROR_DATA; + } + else + { +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + info->DtcmMultiErrorTCMWriteRead = + (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >> + FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT); + info->DtcmMultiErrorTCMAccessSize = + (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >> + FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT); + info->DtcmMultiErrorTCMMaster = + (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >> + FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT); + info->DtcmMultiErrorTCMPrivilege = + (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >> + FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT); + info->DtcmMultiErrorECCSyndrome = + (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >> + FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT); +#else + info->DtcmMultiErrorInfo = base->D1TCM_ECC_MULTI_ERROR_INFO; +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + + info->DtcmMultiErrorAddr = base->D1TCM_ECC_MULTI_ERROR_ADDR; + info->DtcmMultiErrorData = base->D1TCM_ECC_MULTI_ERROR_DATA; + } +} +#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */ diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.h b/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.h new file mode 100644 index 0000000000..3c9a9c2db3 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/flexram/fsl_flexram.h @@ -0,0 +1,508 @@ +/* + * Copyright 2017-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXRAM_H_ +#define _FSL_FLEXRAM_H_ + +#include "fsl_common.h" +#include "fsl_flexram_allocate.h" + +/*! + * @addtogroup flexram + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U)) +/*@}*/ + +/*! @brief Get ECC error detailed information. */ +#ifndef FLEXRAM_ECC_ERROR_DETAILED_INFO +#define FLEXRAM_ECC_ERROR_DETAILED_INFO \ + 0U /* Define to zero means get raw ECC error information, which needs parse it by user. */ +#endif + +/*! @brief Flexram write/read selection. */ +enum +{ + kFLEXRAM_Read = 0U, /*!< read */ + kFLEXRAM_Write = 1U, /*!< write */ +}; + +/*! @brief Interrupt status flag mask */ +enum +{ + kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< OCRAM accesses unallocated address */ + kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< DTCM accesses unallocated address */ + kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< ITCM accesses unallocated address */ + +#if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR + kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< OCRAM magic address match */ + kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< DTCM magic address match */ + kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< ITCM magic address match */ + +#if defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC + kFLEXRAM_OCRAMECCMultiError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK, + kFLEXRAM_OCRAMECCSingleError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK, + kFLEXRAM_ITCMECCMultiError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK, + kFLEXRAM_ITCMECCSingleError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK, + kFLEXRAM_D0TCMECCMultiError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK, + kFLEXRAM_D0TCMECCSingleError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK, + kFLEXRAM_D1TCMECCMultiError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK, + kFLEXRAM_D1TCMECCSingleError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK, + + kFLEXRAM_InterruptStatusAll = + FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | + FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK | + FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK | + FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK | + FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK | + FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK | + FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK, +#else + kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | + FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK | + FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, +#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */ + +/*!< all the interrupt status mask */ +#else + kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | + FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */ +#endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */ + +}; + +/*! @brief FLEXRAM TCM access mode. + * Fast access mode expected to be finished in 1-cycle; + * Wait access mode expected to be finished in 2-cycle. + * Wait access mode is a feature of the flexram and it should be used when + * the CPU clock is too fast to finish TCM access in 1-cycle. + * Normally, fast mode is the default mode, the efficiency of the TCM access will better. + */ +typedef enum _flexram_tcm_access_mode +{ + kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */ + kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */ +} flexram_tcm_access_mode_t; + +/*! @brief FLEXRAM TCM support size */ +enum +{ + kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size be 32KB */ + kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size be 64KB */ + kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size be 128KB */ + kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size be 256KB */ + kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size be 512KB */ +}; + +#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC) +/*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */ +typedef enum _flexram_memory_type +{ + kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */ + kFLEXRAM_ITCM = 1U, /*!< Memory type ITCM */ + kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */ + kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */ +} flexram_memory_type_t; + +/*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */ +typedef struct _flexram_ecc_error_type +{ + uint8_t SingleBitPos; /*!< Bit position of the bit to inject ECC Error. */ + uint8_t SecondBitPos; /*!< Bit position of the second bit to inject multi-bit ECC Error */ + bool Fource1BitDataInversion; /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */ + bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write + access */ + bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory + write access */ + bool FourceContiNCDataInversion; /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on + memory write access */ +} flexram_ecc_error_type_t; + +/*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */ +typedef struct _flexram_ocram_ecc_single_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t OcramSingleErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM single-bit ECC error. */ + uint8_t OcramSingleErrorECCSyndrome; /*!< OCRAM corresponding ECC syndrome of OCRAM single-bit ECC error, + which can be used to locate the Error bit using a look-up table. */ +#else + uint32_t OcramSingleErrorInfo; /*!< Ocram single error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t OcramSingleErrorAddr; /*!< Ocram single error address */ + uint32_t OcramSingleErrorDataLSB; /*!< Ocram single error data LSB */ + uint32_t OcramSingleErrorDataMSB; /*!< Ocram single error data MSB */ +} flexram_ocram_ecc_single_error_info_t; + +/*! @brief FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data + */ +typedef struct _flexram_ocram_ecc_multi_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t OcramMultiErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM multi-bit ECC error. */ +#else + uint32_t OcramMultiErrorInfo; /*!< Ocram single error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t OcramMultiErrorAddr; /*!< Ocram multiple error address */ + uint32_t OcramMultiErrorDataLSB; /*!< Ocram multiple error data LSB */ + uint32_t OcramMultiErrorDataMSB; /*!< Ocram multiple error data MSB */ +} flexram_ocram_ecc_multi_error_info_t; + +/*! @brief FLEXRAM itcm ecc single error information, including single error information, error address, error data */ +typedef struct _flexram_itcm_ecc_single_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t ItcmSingleErrorTCMWriteRead; /*!< itcm single-bit ECC error corresponding tcm_wr value, which is to tell + whether it is a write access(0x01) or a read access(0x00). */ + uint8_t ItcmSingleErrorTCMAccessSize; /*!< itcm single-bit ECC error corresponding tcm access size, + which should be 3 (64bit). */ + uint8_t ItcmSingleErrorTCMMaster; /*!< itcm single-bit ECC error corresponding tcm_master, + which is to tell the requester of the current access. */ + uint8_t ItcmSingleErrorTCMPrivilege; /*!< itcm single-bit ECC error corresponding tcm_priv, + which is to tell the privilege level of access. */ + uint8_t ItcmSingleErrorBitPostion; /*!< itcm single-bit ECC error corresponding bit postion. */ +#else + uint32_t ItcmSingleErrorInfo; /*!< itcm single error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t ItcmSingleErrorAddr; /*!< itcm single error address */ + uint32_t ItcmSingleErrorDataLSB; /*!< itcm single error data LSB */ + uint32_t ItcmSingleErrorDataMSB; /*!< itcm single error data MSB */ +} flexram_itcm_ecc_single_error_info_t; + +/*! @brief FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data + */ +typedef struct _flexram_itcm_ecc_multi_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t ItcmMultiErrorTCMWriteRead; /*!< itcm multiple-bit ECC error corresponding tcm_wr value, which is to tell + whether it is a write access(0x01) or a read access(0x00). */ + uint8_t ItcmMultiErrorTCMAccessSize; /*!< itcm multiple-bit ECC error corresponding tcm access size, + which should be 3 (64bit). */ + uint8_t ItcmMultiErrorTCMMaster; /*!< itcm multiple-bit ECC error corresponding tcm_master, + which is to tell the requester of the current access. */ + uint8_t ItcmMultiErrorTCMPrivilege; /*!< itcm multiple-bit ECC error corresponding tcm_priv, + which is to tell the privilege level of access. */ + uint8_t ItcmMultiErrorECCSyndrome; /*!< itcm multiple-bit ECC error corresponding syndrome, + which can not be used to locate the Error bit using a look-up table. */ +#else + uint32_t ItcmMultiErrorInfo; /*!< itcm multiple error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t ItcmMultiErrorAddr; /*!< itcm multiple error address */ + uint32_t ItcmMultiErrorDataLSB; /*!< itcm multiple error data LSB */ + uint32_t ItcmMultiErrorDataMSB; /*!< itcm multiple error data MSB */ +} flexram_itcm_ecc_multi_error_info_t; + +/*! @brief FLEXRAM dtcm ecc single error information, including single error information, error address, error data */ +typedef struct _flexram_dtcm_ecc_single_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t DtcmSingleErrorTCMWriteRead; /*!< dtcm single-bit ECC error corresponding tcm_wr value, which is to tell + whether it is a write access(0x01) or a read access(0x00). */ + uint8_t DtcmSingleErrorTCMAccessSize; /*!< dtcm single-bit ECC error corresponding tcm access size, + which should be 2 (32bit). */ + uint8_t DtcmSingleErrorTCMMaster; /*!< dtcm single-bit ECC error corresponding tcm_master, + which is to tell the requester of the current access. */ + uint8_t DtcmSingleErrorTCMPrivilege; /*!< dtcm single-bit ECC error corresponding tcm_priv, + which is to tell the privilege level of access. */ + uint8_t DtcmSingleErrorBitPostion; /*!< dtcm single-bit ECC error corresponding bit postion. */ +#else + uint32_t DtcmSingleErrorInfo; /*!< dtcm single error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t DtcmSingleErrorAddr; /*!< dtcm single error address */ + uint32_t DtcmSingleErrorData; /*!< dtcm single error data */ +} flexram_dtcm_ecc_single_error_info_t; + +/*! @brief FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data + */ +typedef struct _flexram_dtcm_ecc_multi_error_info +{ +#if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO + uint8_t DtcmMultiErrorTCMWriteRead; /*!< dtcm multiple-bit ECC error corresponding tcm_wr value, which is to tell + whether it is a write access(0x01) or a read access(0x00). */ + uint8_t DtcmMultiErrorTCMAccessSize; /*!< dtcm multiple-bit ECC error corresponding tcm access size, + which should be 3 (64bit). */ + uint8_t DtcmMultiErrorTCMMaster; /*!< dtcm multiple-bit ECC error corresponding tcm_master, + which is to tell the requester of the current access. */ + uint8_t DtcmMultiErrorTCMPrivilege; /*!< dtcm multiple-bit ECC error corresponding tcm_priv, + which is to tell the privilege level of access. */ + uint8_t DtcmMultiErrorECCSyndrome; /*!< dtcm multiple-bit ECC error corresponding syndrome, + which can not be used to locate the Error bit using a look-up table. */ +#else + uint32_t DtcmMultiErrorInfo; /*!< dtcm multiple error information, user should parse it by themself. */ +#endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/ + uint32_t DtcmMultiErrorAddr; /*!< dtcm multiple error address */ + uint32_t DtcmMultiErrorData; /*!< dtcm multiple error data */ +} flexram_dtcm_ecc_multi_error_info_t; + +#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */ + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief FLEXRAM module initialization function. + * + * @param base FLEXRAM base address. + */ +void FLEXRAM_Init(FLEXRAM_Type *base); + +/*! + * @brief De-initializes the FLEXRAM. + * + */ +void FLEXRAM_Deinit(FLEXRAM_Type *base); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief FLEXRAM module gets interrupt status. + * + * @param base FLEXRAM base address. + */ +static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base) +{ + return base->INT_STATUS & (uint32_t)kFLEXRAM_InterruptStatusAll; +} + +/*! + * @brief FLEXRAM module clears interrupt status. + * + * @param base FLEXRAM base address. + * @param status Status to be cleared. + */ +static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STATUS |= status; +} + +/*! + * @brief FLEXRAM module enables interrupt status. + * + * @param base FLEXRAM base address. + * @param status Status to be enabled. + */ +static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN |= status; +} + +/*! + * @brief FLEXRAM module disable interrupt status. + * + * @param base FLEXRAM base address. + * @param status Status to be disabled. + */ +static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN &= ~status; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief FLEXRAM module enables interrupt. + * + * @param base FLEXRAM base address. + * @param status Status interrupt to be enabled. + */ +static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN |= status; +} + +/*! + * @brief FLEXRAM module disables interrupt. + * + * @param base FLEXRAM base address. + * @param status Status interrupt to be disabled. + */ +static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN &= ~status; +} +/* @} */ + +/*! + * @brief FLEXRAM module sets TCM read access mode + * + * @param base FLEXRAM base address. + * @param mode Access mode. + */ +static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK; + base->TCM_CTRL |= (uint32_t)mode; +} + +/*! + * @brief FLEXRAM module set TCM write access mode + * + * @param base FLEXRAM base address. + * @param mode Access mode. + */ +static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK; + base->TCM_CTRL |= (uint32_t)mode; +} + +/*! + * @brief FLEXRAM module force ram clock on + * + * @param base FLEXRAM base address. + * @param enable Enable or disable clock force on. + */ +static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable) +{ + if (enable) + { + base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } + else + { + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR +/*! + * @brief FLEXRAM OCRAM magic addr configuration. + * When read/write access hit magic address, it will generate interrupt. + * @param base FLEXRAM base address. + * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1]. + * @param rwSel Read/write selection. 0 for read access while 1 for write access. + */ +static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->OCRAM_MAGIC_ADDR = FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | + FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR((uint32_t)magicAddr >> 3); +} + +/*! + * @brief FLEXRAM DTCM magic addr configuration. + * When read/write access hits magic address, it will generate interrupt. + * @param base FLEXRAM base address. + * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1]. + * @param rwSel Read/write selection. 0 for read access while 1 write access. + */ +static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->DTCM_MAGIC_ADDR = FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | + FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR((uint32_t)magicAddr >> 3); +} + +/*! + * @brief FLEXRAM ITCM magic addr configuration. + * When read/write access hits magic address, it will generate interrupt. + * @param base FLEXRAM base address. + * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1]. + * @param rwSel Read/write selection. 0 for read access while 1 for write access. + */ +static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) +{ + base->ITCM_MAGIC_ADDR = FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | + FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR((uint32_t)magicAddr >> 3); +} +#endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */ + +#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC) +/*! + * @brief FLEXRAM get ocram ecc single error information. + * @param base FLEXRAM base address. + * @param OcramECCEnable ocram ecc enablement. + * @param TcmECCEnable tcm(itcm/d0tcm/d1tcm) ecc enablement. + */ +void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable); + +/*! + * @brief FLEXRAM ECC error injection. + * @param base FLEXRAM base address. + * @param memory memory type, such as OCRAM/ITCM/DTCM. + * @param error ECC error type. + */ +void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error); + +/*! + * @brief FLEXRAM get ocram ecc single error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + */ +void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info); + +/*! + * @brief FLEXRAM get ocram ecc multiple error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + */ +void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info); + +/*! + * @brief FLEXRAM get itcm ecc single error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + */ +void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info); + +/*! + * @brief FLEXRAM get itcm ecc multiple error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + */ +void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info); + +/*! + * @brief FLEXRAM get d0tcm ecc single error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM. + */ +void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank); + +/*! + * @brief FLEXRAM get d0tcm ecc multiple error information. + * @param base FLEXRAM base address. + * @param info ecc error information. + * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM. + */ +void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank); + +#endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif |