diff options
Diffstat (limited to 'bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers')
8 files changed, 6022 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.c new file mode 100644 index 0000000000..dbb00d5e49 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.c @@ -0,0 +1,1535 @@ +/* + * Copyright 2017 - 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if (defined(__ICCARM__)) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif (defined(__GNUC__)) + +#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +volatile uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +volatile uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/*! + * @brief Get the frequency of PLL USB1 software clock. + * + * @return The frequency of PLL USB1 software clock. + */ +static uint32_t CLOCK_GetPllUsb1SWFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +static uint32_t CLOCK_GetPllUsb1SWFreq(void) +{ + uint32_t freq; + + switch ((CCM->CCSR & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) >> CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT) + { + case 0: + { + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + } + case 1: + { + freq = 24000000UL; + break; + } + default: + freq = 0UL; + break; + } + + return freq; +} + +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0UL) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + { + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + } + else + { + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; + } +} + +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if ((CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) != 0U) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if ((CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) != 0U) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the PER clock frequency. + * + * return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if ((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) != 0U) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetIpgFreq(); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + + case kCLOCK_SemcClk: + freq = CLOCK_GetSemcFreq(); + break; + + case kCLOCK_IpgClk: + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb1SwClk: + freq = CLOCK_GetPllUsb1SWFreq(); + break; + case kCLOCK_Usb1Sw120MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 4UL; + break; + case kCLOCK_Usb1Sw60MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 8UL; + break; + case kCLOCK_Usb1Sw80MClk: + freq = CLOCK_GetPllUsb1SWFreq() / 6UL; + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Gets the frequency of selected clock root. + * + * param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t. + * return The frequency of selected clock root. + */ +uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot) +{ + static const clock_name_t clockRootSourceArray[][6] = CLOCK_ROOT_SOUCE; + static const clock_mux_t clockRootMuxTupleArray[] = CLOCK_ROOT_MUX_TUPLE; + static const clock_div_t clockRootDivTupleArray[][2] = CLOCK_ROOT_DIV_TUPLE; + uint32_t freq = 0UL; + clock_mux_t clockRootMuxTuple = clockRootMuxTupleArray[(uint8_t)clockRoot]; + clock_div_t clockRootPreDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][0]; + clock_div_t clockRootPostDivTuple = clockRootDivTupleArray[(uint8_t)clockRoot][1]; + uint32_t clockRootMuxValue = (CCM_TUPLE_REG(CCM, clockRootMuxTuple) & CCM_TUPLE_MASK(clockRootMuxTuple)) >> + CCM_TUPLE_SHIFT(clockRootMuxTuple); + clock_name_t clockSourceName; + + clockSourceName = clockRootSourceArray[(uint8_t)clockRoot][clockRootMuxValue]; + + assert(clockSourceName != kCLOCK_NoneName); + + freq = CLOCK_GetFreq(clockSourceName); + + if (clockRootPreDivTuple != kCLOCK_NonePreDiv) + { + freq /= ((CCM_TUPLE_REG(CCM, clockRootPreDivTuple) & CCM_TUPLE_MASK(clockRootPreDivTuple)) >> + CCM_TUPLE_SHIFT(clockRootPreDivTuple)) + + 1UL; + } + + freq /= ((CCM_TUPLE_REG(CCM, clockRootPostDivTuple) & CCM_TUPLE_MASK(clockRootPostDivTuple)) >> + CCM_TUPLE_SHIFT(clockRootPostDivTuple)) + + 1UL; + + return freq; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + uint32_t i; + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + uint32_t i = 0; + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + static const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) != 0U) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +/*! + * brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +/*! + * brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = (uint32_t)CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + } + + if (config->enableClkOutput25M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0UL) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + clock_64b_t freqTmp; + + static const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); + break; + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0UL) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2U): + freq = freq >> 0U; + break; + + default: + assert(false); + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0): + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(0): + freq >>= 0U; + break; + + default: + assert(false); + break; + } + break; + + case kCLOCK_PllVideo: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))); + freqTmp /= ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2U): + freq = freq >> 0U; + break; + + default: + assert(false); + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3U): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1U): + freq >>= 1U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(0U): + case CCM_ANALOG_MISC2_VIDEO_DIV(2U): + freq >>= 0U; + break; + + default: + assert(false); + break; + } + break; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (freq * (((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) + << (8UL * pfdIndex))); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | ((uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex)); +} + +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= (uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8U * (uint8_t)pfd); +} + +/*! + * brief Check if Sys PFD is enabled + * + * param pfd PFD control name + * return PFD bypass status. + * - true: power on. + * - false: power off. + */ +bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd) +{ + return ((CCM_ANALOG->PFD_528 & (uint32_t)CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8UL * (uint8_t)pfd)) == 0U); +} + +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~(((uint32_t)((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) + << (8UL * pfdIndex))); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | ((uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8UL * pfdIndex)); +} + +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= (uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * (uint8_t)pfd); +} + +/*! + * brief Check if Usb1 PFD is enabled + * + * param pfd PFD control name. + * return PFD bypass status. + * - true: power on. + * - false: power off. + */ +bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd) +{ + return ((CCM_ANALOG->PFD_480 & (uint32_t)CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8UL * (uint8_t)pfd)) == 0U); +} + +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + static const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Set the clock source and the divider of the clock output1. + * + * param selection The clock source to be output, please refer to clock_output1_selection_t. + * param divider The divider of the output clock signal, please refer to clock_output_divider_t. + */ +void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider) +{ + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + if (selection == kCLOCK_DisableClockOutput1) + { + tmp32 &= ~CCM_CCOSR_CLKO1_EN_MASK; + } + else + { + tmp32 |= CCM_CCOSR_CLKO1_EN_MASK; + tmp32 &= ~(CCM_CCOSR_CLKO1_SEL_MASK | CCM_CCOSR_CLKO1_DIV_MASK); + tmp32 |= CCM_CCOSR_CLKO1_SEL(selection) | CCM_CCOSR_CLKO1_DIV(divider); + } + CCM->CCOSR = tmp32; +} + +/*! + * brief Set the clock source and the divider of the clock output2. + * + * param selection The clock source to be output, please refer to clock_output2_selection_t. + * param divider The divider of the output clock signal, please refer to clock_output_divider_t. + */ +void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider) +{ + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + if (selection == kCLOCK_DisableClockOutput2) + { + tmp32 &= CCM_CCOSR_CLKO2_EN_MASK; + } + else + { + tmp32 |= CCM_CCOSR_CLKO2_EN_MASK; + tmp32 &= ~(CCM_CCOSR_CLKO2_SEL_MASK | CCM_CCOSR_CLKO2_DIV_MASK); + tmp32 |= CCM_CCOSR_CLKO2_SEL(selection) | CCM_CCOSR_CLKO2_DIV(divider); + } + + CCM->CCOSR = tmp32; +} + +/*! + * brief Get the frequency of clock output1 clock signal. + * + * return The frequency of clock output1 clock signal. + */ +uint32_t CLOCK_GetClockOutCLKO1Freq(void) +{ + uint32_t freq = 0U; + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + + if ((tmp32 & CCM_CCOSR_CLKO1_EN_MASK) != 0UL) + { + switch ((tmp32 & CCM_CCOSR_CLKO1_SEL_MASK) >> CCM_CCOSR_CLKO1_SEL_SHIFT) + { + case (uint32_t)kCLOCK_OutputPllUsb1: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 2U; + break; + case (uint32_t)kCLOCK_OutputPllSys: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys) / 2U; + break; + case (uint32_t)kCLOCK_OutputPllVideo: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2U; + break; + case (uint32_t)kCLOCK_OutputSemcClk: + freq = CLOCK_GetSemcFreq(); + break; + case (uint32_t)kCLOCK_OutputLcdifPixClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_LcdifClkRoot); + break; + case (uint32_t)kCLOCK_OutputAhbClk: + freq = CLOCK_GetAhbFreq(); + break; + case (uint32_t)kCLOCK_OutputIpgClk: + freq = CLOCK_GetIpgFreq(); + break; + case (uint32_t)kCLOCK_OutputPerClk: + freq = CLOCK_GetPerClkFreq(); + break; + case (uint32_t)kCLOCK_OutputCkilSyncClk: + freq = CLOCK_GetRtcFreq(); + break; + case (uint32_t)kCLOCK_OutputPll4MainClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + default: + /* This branch should never be hit. */ + break; + } + + freq /= (((tmp32 & CCM_CCOSR_CLKO1_DIV_MASK) >> CCM_CCOSR_CLKO1_DIV_SHIFT) + 1U); + } + else + { + freq = 0UL; + } + + return freq; +} + +/*! + * brief Get the frequency of clock output2 clock signal. + * + * return The frequency of clock output2 clock signal. + */ +uint32_t CLOCK_GetClockOutClkO2Freq(void) +{ + uint32_t freq = 0U; + uint32_t tmp32; + + tmp32 = CCM->CCOSR; + + if ((tmp32 & CCM_CCOSR_CLKO2_EN_MASK) != 0UL) + { + switch ((tmp32 & CCM_CCOSR_CLKO2_SEL_MASK) >> CCM_CCOSR_CLKO2_SEL_SHIFT) + { + case (uint32_t)kCLOCK_OutputUsdhc1Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc1ClkRoot); + break; + case (uint32_t)kCLOCK_OutputLpi2cClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Lpi2cClkRoot); + break; + case (uint32_t)kCLOCK_OutputCsiClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_CsiClkRoot); + break; + case (uint32_t)kCLOCK_OutputOscClk: + freq = CLOCK_GetOscFreq(); + break; + case (uint32_t)kCLOCK_OutputUsdhc2Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Usdhc2ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai1Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai1ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai2Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai2ClkRoot); + break; + case (uint32_t)kCLOCK_OutputSai3Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_Sai3ClkRoot); + break; + case (uint32_t)kCLOCK_OutputCanClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_CanClkRoot); + break; + case (uint32_t)kCLOCK_OutputFlexspiClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot); + break; + case (uint32_t)kCLOCK_OutputUartClk: + freq = CLOCK_GetClockRootFreq(kCLOCK_UartClkRoot); + break; + case (uint32_t)kCLOCK_OutputSpdif0Clk: + freq = CLOCK_GetClockRootFreq(kCLOCK_SpdifClkRoot); + break; + default: + /* This branch should never be hit. */ + break; + } + + freq /= (((tmp32 & CCM_CCOSR_CLKO2_DIV_MASK) >> CCM_CCOSR_CLKO2_DIV_SHIFT) + 1U); + } + else + { + freq = 0UL; + } + + return freq; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h new file mode 100644 index 0000000000..f74c0e00a4 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h @@ -0,0 +1,2038 @@ +/* + * Copyright 2017 - 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.5.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL) +#endif + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CSCDR3_OFFSET 0x3C +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define PLL_ARM_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_VIDEO_OFFSET 0xA0 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) \ + ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off)))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/* Definition for ERRATA 50235 check */ +#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235) +#define CAN_CLOCK_CHECK_NO_AFFECTS \ + ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \ + (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK))) +#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */ + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); + * CLOCK_SetXtalFreq(240000000); + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \ + {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +#define CLOCK_SOURCE_NONE (0xFFU) + +#define CLOCK_ROOT_SOUCE \ + { \ + {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \ + {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \ + {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \ + kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \ + {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \ + kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \ + {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \ + kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \ + {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \ + kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \ + {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \ + {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \ + {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \ + {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \ + kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \ + {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \ + kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \ + {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \ + kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \ + } + +#define CLOCK_ROOT_MUX_TUPLE \ + { \ + kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \ + kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \ + kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \ + } + +#define CLOCK_ROOT_NONE_PRE_DIV 0UL + +#define CLOCK_ROOT_DIV_TUPLE \ + { \ + {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \ + {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, \ + {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \ + {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \ + {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \ + {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \ + {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \ + {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + kCLOCK_Usb1SwClk = 0x17U, /*!< USB1PLLSWCLK */ + kCLOCK_Usb1Sw120MClk = 0x18U, /*!< USB1PLLSw120MCLK */ + kCLOCK_Usb1Sw60MClk = 0x19U, /*!< USB1PLLSw60MCLK */ + kCLOCK_Usb1Sw80MClk = 0x1AU, /*!< USB1PLLSw80MCLK */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + + kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */ + kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_TRACE_CLK_SEL_SHIFT, + CCM_CBCMR_TRACE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, + CCM_CBCMR_LPSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI3_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_SEL_SHIFT, + CCM_CSCMR2_CAN_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_SEL_SHIFT, + CCM_CSCDR1_UART_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, + CCM_CDCDR_SPDIF0_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, + CCM_CSCDR2_LPI2C_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET, + CCM_CSCDR3_CSI_CLK_SEL_SHIFT, + CCM_CSCDR3_CSI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET, + CCM_CACRR_ARM_PODF_SHIFT, + CCM_CACRR_ARM_PODF_MASK, + CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_AHB_PODF_SHIFT, + CCM_CBCDR_AHB_PODF_MASK, + CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE( + CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_PODF_SHIFT, + CCM_CSCMR1_FLEXSPI_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_PODF_SHIFT, + CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_PODF_SHIFT, + CCM_CSCMR2_CAN_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_TRACE_PODF_SHIFT, + CCM_CSCDR1_TRACE_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC2_PODF_SHIFT, + CCM_CSCDR1_USDHC2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC1_PODF_SHIFT, + CCM_CSCDR1_USDHC1_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_PODF_SHIFT, + CCM_CSCDR1_UART_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI3_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, + CCM_CS2CDR_SAI2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRED_SHIFT, + CCM_CSCDR2_LCDIF_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE( + CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ + + kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */ +} clock_div_t; + +/*! + * @brief Clock divider value. + */ +typedef enum _clock_div_value +{ + kCLOCK_ArmDivBy1 = 0, /*!< ARM clock divider set to divided by 1. */ + kCLOCK_ArmDivBy2 = 1, /*!< ARM clock divider set to divided by 2. */ + kCLOCK_ArmDivBy3 = 2, /*!< ARM clock divider set to divided by 3. */ + kCLOCK_ArmDivBy4 = 3, /*!< ARM clock divider set to divided by 4. */ + kCLOCK_ArmDivBy5 = 4, /*!< ARM clock divider set to divided by 5. */ + kCLOCK_ArmDivBy6 = 5, /*!< ARM clock divider set to divided by 6. */ + kCLOCK_ArmDivBy7 = 6, /*!< ARM clock divider set to divided by 7. */ + kCLOCK_ArmDivBy8 = 7, /*!< ARM clock divider set to divided by 8. */ + + kCLOCK_PeriphClk2DivBy1 = 0, /*!< PeriphClk2 divider set to divided by 1. */ + kCLOCK_PeriphClk2DivBy2 = 1, /*!< PeriphClk2 divider set to divided by 2. */ + kCLOCK_PeriphClk2DivBy3 = 2, /*!< PeriphClk2 divider set to divided by 3. */ + kCLOCK_PeriphClk2DivBy4 = 3, /*!< PeriphClk2 divider set to divided by 4. */ + kCLOCK_PeriphClk2DivBy5 = 4, /*!< PeriphClk2 divider set to divided by 5. */ + kCLOCK_PeriphClk2DivBy6 = 5, /*!< PeriphClk2 divider set to divided by 6. */ + kCLOCK_PeriphClk2DivBy7 = 6, /*!< PeriphClk2 divider set to divided by 7. */ + kCLOCK_PeriphClk2DivBy8 = 7, /*!< PeriphClk2 divider set to divided by 8. */ + + kCLOCK_SemcDivBy1 = 0, /*!< SEMC divider set to divided by 1. */ + kCLOCK_SemcDivBy2 = 1, /*!< SEMC divider set to divided by 2. */ + kCLOCK_SemcDivBy3 = 2, /*!< SEMC divider set to divided by 3. */ + kCLOCK_SemcDivBy4 = 3, /*!< SEMC divider set to divided by 4. */ + kCLOCK_SemcDivBy5 = 4, /*!< SEMC divider set to divided by 5. */ + kCLOCK_SemcDivBy6 = 5, /*!< SEMC divider set to divided by 6. */ + kCLOCK_SemcDivBy7 = 6, /*!< SEMC divider set to divided by 7. */ + kCLOCK_SemcDivBy8 = 7, /*!< SEMC divider set to divided by 8. */ + + kCLOCK_AhbDivBy1 = 0, /*!< AHB divider set to divided by 1. */ + kCLOCK_AhbDivBy2 = 1, /*!< AHB divider set to divided by 2. */ + kCLOCK_AhbDivBy3 = 2, /*!< AHB divider set to divided by 3. */ + kCLOCK_AhbDivBy4 = 3, /*!< AHB divider set to divided by 4. */ + kCLOCK_AhbDivBy5 = 4, /*!< AHB divider set to divided by 5. */ + kCLOCK_AhbDivBy6 = 5, /*!< AHB divider set to divided by 6. */ + kCLOCK_AhbDivBy7 = 6, /*!< AHB divider set to divided by 7. */ + kCLOCK_AhbDivBy8 = 7, /*!< AHB divider set to divided by 8. */ + + kCLOCK_IpgDivBy1 = 0, /*!< Ipg divider set to divided by 1. */ + kCLOCK_IpgDivBy2 = 1, /*!< Ipg divider set to divided by 2. */ + kCLOCK_IpgDivBy3 = 2, /*!< Ipg divider set to divided by 3. */ + kCLOCK_IpgDivBy4 = 3, /*!< Ipg divider set to divided by 4. */ + + kCLOCK_LpspiDivBy1 = 0, /*!< LPSPI divider set to divided by 1. */ + kCLOCK_LpspiDivBy2 = 1, /*!< LPSPI divider set to divided by 2. */ + kCLOCK_LpspiDivBy3 = 2, /*!< LPSPI divider set to divided by 3. */ + kCLOCK_LpspiDivBy4 = 3, /*!< LPSPI divider set to divided by 4. */ + kCLOCK_LpspiDivBy5 = 4, /*!< LPSPI divider set to divided by 5. */ + kCLOCK_LpspiDivBy6 = 5, /*!< LPSPI divider set to divided by 6. */ + kCLOCK_LpspiDivBy7 = 6, /*!< LPSPI divider set to divided by 7. */ + kCLOCK_LpspiDivBy8 = 7, /*!< LPSPI divider set to divided by 8. */ + + kCLOCK_LcdifDivBy1 = 0, /*!< LPDIF divider set to divided by 1. */ + kCLOCK_LcdifDivBy2 = 1, /*!< LPDIF divider set to divided by 2. */ + kCLOCK_LcdifDivBy3 = 2, /*!< LPDIF divider set to divided by 3. */ + kCLOCK_LcdifDivBy4 = 3, /*!< LPDIF divider set to divided by 4. */ + kCLOCK_LcdifDivBy5 = 4, /*!< LPDIF divider set to divided by 5. */ + kCLOCK_LcdifDivBy6 = 5, /*!< LPDIF divider set to divided by 6. */ + kCLOCK_LcdifDivBy7 = 6, /*!< LPDIF divider set to divided by 7. */ + kCLOCK_LcdifDivBy8 = 7, /*!< LPDIF divider set to divided by 8. */ + + kCLOCK_FlexspiDivBy1 = 0, /*!< FLEXSPI divider set to divided by 1. */ + kCLOCK_FlexspiDivBy2 = 1, /*!< FLEXSPI divider set to divided by 2. */ + kCLOCK_FlexspiDivBy3 = 2, /*!< FLEXSPI divider set to divided by 3. */ + kCLOCK_FlexspiDivBy4 = 3, /*!< FLEXSPI divider set to divided by 4. */ + kCLOCK_FlexspiDivBy5 = 4, /*!< FLEXSPI divider set to divided by 5. */ + kCLOCK_FlexspiDivBy6 = 5, /*!< FLEXSPI divider set to divided by 6. */ + kCLOCK_FlexspiDivBy7 = 6, /*!< FLEXSPI divider set to divided by 7. */ + kCLOCK_FlexspiDivBy8 = 7, /*!< FLEXSPI divider set to divided by 8. */ + + kCLOCK_TraceDivBy1 = 0, /*!< TRACE divider set to divided by 1. */ + kCLOCK_TraceDivBy2 = 1, /*!< TRACE divider set to divided by 2. */ + kCLOCK_TraceDivBy3 = 2, /*!< TRACE divider set to divided by 3. */ + kCLOCK_TraceDivBy4 = 3, /*!< TRACE divider set to divided by 4. */ + + kCLOCK_Usdhc2DivBy1 = 0, /*!< USDHC2 divider set to divided by 1. */ + kCLOCK_Usdhc2DivBy2 = 1, /*!< USDHC2 divider set to divided by 2. */ + kCLOCK_Usdhc2DivBy3 = 2, /*!< USDHC2 divider set to divided by 3. */ + kCLOCK_Usdhc2DivBy4 = 3, /*!< USDHC2 divider set to divided by 4. */ + kCLOCK_Usdhc2DivBy5 = 4, /*!< USDHC2 divider set to divided by 5. */ + kCLOCK_Usdhc2DivBy6 = 5, /*!< USDHC2 divider set to divided by 6. */ + kCLOCK_Usdhc2DivBy7 = 6, /*!< USDHC2 divider set to divided by 7. */ + kCLOCK_Usdhc2DivBy8 = 7, /*!< USDHC2 divider set to divided by 8. */ + + kCLOCK_Usdhc1DivBy1 = 0, /*!< USDHC1 divider set to divided by 1. */ + kCLOCK_Usdhc1DivBy2 = 1, /*!< USDHC1 divider set to divided by 2. */ + kCLOCK_Usdhc1DivBy3 = 2, /*!< USDHC1 divider set to divided by 3. */ + kCLOCK_Usdhc1DivBy4 = 3, /*!< USDHC1 divider set to divided by 4. */ + kCLOCK_Usdhc1DivBy5 = 4, /*!< USDHC1 divider set to divided by 5. */ + kCLOCK_Usdhc1DivBy6 = 5, /*!< USDHC1 divider set to divided by 6. */ + kCLOCK_Usdhc1DivBy7 = 6, /*!< USDHC1 divider set to divided by 7. */ + kCLOCK_Usdhc1DivBy8 = 7, /*!< USDHC1 divider set to divided by 8. */ + + kCLOCK_Flexio2DivBy1 = 0, /*!< Flexio2 divider set to divided by 1. */ + kCLOCK_Flexio2DivBy2 = 1, /*!< Flexio2 divider set to divided by 2. */ + kCLOCK_Flexio2DivBy3 = 2, /*!< Flexio2 divider set to divided by 3. */ + kCLOCK_Flexio2DivBy4 = 3, /*!< Flexio2 divider set to divided by 4. */ + kCLOCK_Flexio2DivBy5 = 4, /*!< Flexio2 divider set to divided by 5. */ + kCLOCK_Flexio2DivBy6 = 5, /*!< Flexio2 divider set to divided by 6. */ + kCLOCK_Flexio2DivBy7 = 6, /*!< Flexio2 divider set to divided by 7. */ + kCLOCK_Flexio2DivBy8 = 7, /*!< Flexio2 divider set to divided by 8. */ + + kCLOCK_Sai3PreDivBy1 = 0, /*!< SAI3ClkPred divider set to divided by 1. */ + kCLOCK_Sai3PreDivBy2 = 1, /*!< SAI3ClkPred divider set to divided by 2. */ + kCLOCK_Sai3PreDivBy3 = 2, /*!< SAI3ClkPred divider set to divided by 3. */ + kCLOCK_Sai3PreDivBy4 = 3, /*!< SAI3ClkPred divider set to divided by 4. */ + kCLOCK_Sai3PreDivBy5 = 4, /*!< SAI3ClkPred divider set to divided by 5. */ + kCLOCK_Sai3PreDivBy6 = 5, /*!< SAI3ClkPred divider set to divided by 6. */ + kCLOCK_Sai3PreDivBy7 = 6, /*!< SAI3ClkPred divider set to divided by 7. */ + kCLOCK_Sai3PreDivBy8 = 7, /*!< SAI3ClkPred divider set to divided by 8. */ + + kCLOCK_Flexio2PreDivBy1 = 0, /*!< Flexio2 pre divider set to divided by 1. */ + kCLOCK_Flexio2PreDivBy2 = 1, /*!< Flexio2 pre divider set to divided by 2. */ + kCLOCK_Flexio2PreDivBy3 = 2, /*!< Flexio2 pre divider set to divided by 3. */ + kCLOCK_Flexio2PreDivBy4 = 3, /*!< Flexio2 pre divider set to divided by 4. */ + kCLOCK_Flexio2PreDivBy5 = 4, /*!< Flexio2 pre divider set to divided by 5. */ + kCLOCK_Flexio2PreDivBy6 = 5, /*!< Flexio2 pre divider set to divided by 6. */ + kCLOCK_Flexio2PreDivBy7 = 6, /*!< Flexio2 pre divider set to divided by 7. */ + kCLOCK_Flexio2PreDivBy8 = 7, /*!< Flexio2 pre divider set to divided by 8. */ + + kCLOCK_Sai1PreDivBy1 = 0, /*!< SAI1 pred divider set to divided by 1. */ + kCLOCK_Sai1PreDivBy2 = 1, /*!< SAI1 pred divider set to divided by 2. */ + kCLOCK_Sai1PreDivBy3 = 2, /*!< SAI1 pred divider set to divided by 3. */ + kCLOCK_Sai1PreDivBy4 = 3, /*!< SAI1 pred divider set to divided by 4. */ + kCLOCK_Sai1PreDivBy5 = 4, /*!< SAI1 pred divider set to divided by 5. */ + kCLOCK_Sai1PreDivBy6 = 5, /*!< SAI1 pred divider set to divided by 6. */ + kCLOCK_Sai1PreDivBy7 = 6, /*!< SAI1 pred divider set to divided by 7. */ + kCLOCK_Sai1PreDivBy8 = 7, /*!< SAI1 pred divider set to divided by 8. */ + + kCLOCK_Sai2PreDivBy1 = 0, /*!< SAI2ClkPred divider set to divided by 1. */ + kCLOCK_Sai2PreDivBy2 = 1, /*!< SAI2ClkPred divider set to divided by 2. */ + kCLOCK_Sai2PreDivBy3 = 2, /*!< SAI2ClkPred divider set to divided by 3. */ + kCLOCK_Sai2PreDivBy4 = 3, /*!< SAI2ClkPred divider set to divided by 4. */ + kCLOCK_Sai2PreDivBy5 = 4, /*!< SAI2ClkPred divider set to divided by 5. */ + kCLOCK_Sai2PreDivBy6 = 5, /*!< SAI2ClkPred divider set to divided by 6. */ + kCLOCK_Sai2PreDivBy7 = 6, /*!< SAI2ClkPred divider set to divided by 7. */ + kCLOCK_Sai2PreDivBy8 = 7, /*!< SAI2ClkPred divider set to divided by 8. */ + + kCLOCK_Spdif0PreDivBy1 = 0, /*!< SPDIF0 pred divider set to divided by 1. */ + kCLOCK_Spdif0PreDivBy2 = 1, /*!< SPDIF0 pred divider set to divided by 2. */ + kCLOCK_Spdif0PreDivBy3 = 2, /*!< SPDIF0 pred divider set to divided by 3. */ + kCLOCK_Spdif0PreDivBy4 = 3, /*!< SPDIF0 pred divider set to divided by 4. */ + kCLOCK_Spdif0PreDivBy5 = 4, /*!< SPDIF0 pred divider set to divided by 5. */ + kCLOCK_Spdif0PreDivBy6 = 5, /*!< SPDIF0 pred divider set to divided by 6. */ + kCLOCK_Spdif0PreDivBy7 = 6, /*!< SPDIF0 pred divider set to divided by 7. */ + kCLOCK_Spdif0PreDivBy8 = 7, /*!< SPDIF0 pred divider set to divided by 8. */ + + kCLOCK_Spdif0DivBy1 = 0, /*!< SPDIF divider set to divided by 1. */ + kCLOCK_Spdif0DivBy2 = 1, /*!< SPDIF divider set to divided by 2. */ + kCLOCK_Spdif0DivBy3 = 2, /*!< SPDIF divider set to divided by 3. */ + kCLOCK_Spdif0DivBy4 = 3, /*!< SPDIF divider set to divided by 4. */ + kCLOCK_Spdif0DivBy5 = 4, /*!< SPDIF divider set to divided by 5. */ + kCLOCK_Spdif0DivBy6 = 5, /*!< SPDIF divider set to divided by 6. */ + kCLOCK_Spdif0DivBy7 = 6, /*!< SPDIF divider set to divided by 7. */ + kCLOCK_Spdif0DivBy8 = 7, /*!< SPDIF divider set to divided by 8. */ + + kCLOCK_Flexio1PreDivBy1 = 0, /*!< Flexio1 pre divider set to divided by 1. */ + kCLOCK_Flexio1PreDivBy2 = 1, /*!< Flexio1 pre divider set to divided by 2. */ + kCLOCK_Flexio1PreDivBy3 = 2, /*!< Flexio1 pre divider set to divided by 3. */ + kCLOCK_Flexio1PreDivBy4 = 3, /*!< Flexio1 pre divider set to divided by 4. */ + kCLOCK_Flexio1PreDivBy5 = 4, /*!< Flexio1 pre divider set to divided by 5. */ + kCLOCK_Flexio1PreDivBy6 = 5, /*!< Flexio1 pre divider set to divided by 6. */ + kCLOCK_Flexio1PreDivBy7 = 6, /*!< Flexio1 pre divider set to divided by 7. */ + kCLOCK_Flexio1PreDivBy8 = 7, /*!< Flexio1 pre divider set to divided by 8. */ + + kCLOCK_Flexio1DivBy1 = 0, /*!< Flexio1 divider set to divided by 1. */ + kCLOCK_Flexio1DivBy2 = 1, /*!< Flexio1 divider set to divided by 2. */ + kCLOCK_Flexio1DivBy3 = 2, /*!< Flexio1 divider set to divided by 3. */ + kCLOCK_Flexio1DivBy4 = 3, /*!< Flexio1 divider set to divided by 4. */ + kCLOCK_Flexio1DivBy5 = 4, /*!< Flexio1 divider set to divided by 5. */ + kCLOCK_Flexio1DivBy6 = 5, /*!< Flexio1 divider set to divided by 6. */ + kCLOCK_Flexio1DivBy7 = 6, /*!< Flexio1 divider set to divided by 7. */ + kCLOCK_Flexio1DivBy8 = 7, /*!< Flexio1 divider set to divided by 8. */ + + kCLOCK_LcdifPreDivBy1 = 0, /*!< Lcdif pre divider set to divided by 1. */ + kCLOCK_LcdifPreDivBy2 = 1, /*!< Lcdif pre divider set to divided by 2. */ + kCLOCK_LcdifPreDivBy3 = 2, /*!< Lcdif pre divider set to divided by 3. */ + kCLOCK_LcdifPreDivBy4 = 3, /*!< Lcdif pre divider set to divided by 4. */ + kCLOCK_LcdifPreDivBy5 = 4, /*!< Lcdif pre divider set to divided by 5. */ + kCLOCK_LcdifPreDivBy6 = 5, /*!< Lcdif pre divider set to divided by 6. */ + kCLOCK_LcdifPreDivBy7 = 6, /*!< Lcdif pre divider set to divided by 7. */ + kCLOCK_LcdifPreDivBy8 = 7, /*!< Lcdif pre divider set to divided by 8. */ + + kCLOCK_CsiDivBy1 = 0, /*!< Csi pre divider set to divided by 1. */ + kCLOCK_CsiDivBy2 = 1, /*!< Csi pre divider set to divided by 2. */ + kCLOCK_CsiDivBy3 = 2, /*!< Csi pre divider set to divided by 3. */ + kCLOCK_CsiDivBy4 = 3, /*!< Csi pre divider set to divided by 4. */ + kCLOCK_CsiDivBy5 = 4, /*!< Csi pre divider set to divided by 5. */ + kCLOCK_CsiDivBy6 = 5, /*!< Csi pre divider set to divided by 6. */ + kCLOCK_CsiDivBy7 = 6, /*!< Csi pre divider set to divided by 7. */ + kCLOCK_CsiDivBy8 = 7, /*!< Csi pre divider set to divided by 8. */ + + /* Only kCLOCK_Lpi2cDiv, kCLOCK_CanDiv, kCLOCK_UartDiv, kCLOCK_Sai1Div, + * kCLOCK_Sai2Div, kCLOCK_Sai3Div, kCLOCK_PerclkDiv can use these. + */ + kCLOCK_MiscDivBy1 = 0, /*!< Misc divider like LPI2C set to divided by1. */ + kCLOCK_MiscDivBy2 = 1, /*!< Misc divider like LPI2C set to divided by2. */ + kCLOCK_MiscDivBy3 = 2, /*!< Misc divider like LPI2C set to divided by3. */ + kCLOCK_MiscDivBy4 = 3, /*!< Misc divider like LPI2C set to divided by4. */ + kCLOCK_MiscDivBy5 = 4, /*!< Misc divider like LPI2C set to divided by5. */ + kCLOCK_MiscDivBy6 = 5, /*!< Misc divider like LPI2C set to divided by6. */ + kCLOCK_MiscDivBy7 = 6, /*!< Misc divider like LPI2C set to divided by7. */ + kCLOCK_MiscDivBy8 = 7, /*!< Misc divider like LPI2C set to divided by8. */ + kCLOCK_MiscDivBy9 = 8, /*!< Misc divider like LPI2C set to divided by9. */ + kCLOCK_MiscDivBy10 = 9, /*!< Misc divider like LPI2C set to divided by10. */ + kCLOCK_MiscDivBy11 = 10, /*!< Misc divider like LPI2C set to divided by11. */ + kCLOCK_MiscDivBy12 = 11, /*!< Misc divider like LPI2C set to divided by12. */ + kCLOCK_MiscDivBy13 = 12, /*!< Misc divider like LPI2C set to divided by13. */ + kCLOCK_MiscDivBy14 = 13, /*!< Misc divider like LPI2C set to divided by14. */ + kCLOCK_MiscDivBy15 = 14, /*!< Misc divider like LPI2C set to divided by15. */ + kCLOCK_MiscDivBy16 = 15, /*!< Misc divider like LPI2C set to divided by16. */ + kCLOCK_MiscDivBy17 = 16, /*!< Misc divider like LPI2C set to divided by17. */ + kCLOCK_MiscDivBy18 = 17, /*!< Misc divider like LPI2C set to divided by18. */ + kCLOCK_MiscDivBy19 = 18, /*!< Misc divider like LPI2C set to divided by19. */ + kCLOCK_MiscDivBy20 = 19, /*!< Misc divider like LPI2C set to divided by20. */ + kCLOCK_MiscDivBy21 = 20, /*!< Misc divider like LPI2C set to divided by21. */ + kCLOCK_MiscDivBy22 = 21, /*!< Misc divider like LPI2C set to divided by22. */ + kCLOCK_MiscDivBy23 = 22, /*!< Misc divider like LPI2C set to divided by23. */ + kCLOCK_MiscDivBy24 = 23, /*!< Misc divider like LPI2C set to divided by24. */ + kCLOCK_MiscDivBy25 = 24, /*!< Misc divider like LPI2C set to divided by25. */ + kCLOCK_MiscDivBy26 = 25, /*!< Misc divider like LPI2C set to divided by26. */ + kCLOCK_MiscDivBy27 = 26, /*!< Misc divider like LPI2C set to divided by27. */ + kCLOCK_MiscDivBy28 = 27, /*!< Misc divider like LPI2C set to divided by28. */ + kCLOCK_MiscDivBy29 = 28, /*!< Misc divider like LPI2C set to divided by29. */ + kCLOCK_MiscDivBy30 = 29, /*!< Misc divider like LPI2C set to divided by30. */ + kCLOCK_MiscDivBy31 = 30, /*!< Misc divider like LPI2C set to divided by31. */ + kCLOCK_MiscDivBy32 = 31, /*!< Misc divider like LPI2C set to divided by32. */ + kCLOCK_MiscDivBy33 = 32, /*!< Misc divider like LPI2C set to divided by33. */ + kCLOCK_MiscDivBy34 = 33, /*!< Misc divider like LPI2C set to divided by34. */ + kCLOCK_MiscDivBy35 = 34, /*!< Misc divider like LPI2C set to divided by35. */ + kCLOCK_MiscDivBy36 = 35, /*!< Misc divider like LPI2C set to divided by36. */ + kCLOCK_MiscDivBy37 = 36, /*!< Misc divider like LPI2C set to divided by37. */ + kCLOCK_MiscDivBy38 = 37, /*!< Misc divider like LPI2C set to divided by38. */ + kCLOCK_MiscDivBy39 = 38, /*!< Misc divider like LPI2C set to divided by39. */ + kCLOCK_MiscDivBy40 = 39, /*!< Misc divider like LPI2C set to divided by40. */ + kCLOCK_MiscDivBy41 = 40, /*!< Misc divider like LPI2C set to divided by41. */ + kCLOCK_MiscDivBy42 = 41, /*!< Misc divider like LPI2C set to divided by42. */ + kCLOCK_MiscDivBy43 = 42, /*!< Misc divider like LPI2C set to divided by43. */ + kCLOCK_MiscDivBy44 = 43, /*!< Misc divider like LPI2C set to divided by44. */ + kCLOCK_MiscDivBy45 = 44, /*!< Misc divider like LPI2C set to divided by45. */ + kCLOCK_MiscDivBy46 = 45, /*!< Misc divider like LPI2C set to divided by46. */ + kCLOCK_MiscDivBy47 = 46, /*!< Misc divider like LPI2C set to divided by47. */ + kCLOCK_MiscDivBy48 = 47, /*!< Misc divider like LPI2C set to divided by48. */ + kCLOCK_MiscDivBy49 = 48, /*!< Misc divider like LPI2C set to divided by49. */ + kCLOCK_MiscDivBy50 = 49, /*!< Misc divider like LPI2C set to divided by50. */ + kCLOCK_MiscDivBy51 = 50, /*!< Misc divider like LPI2C set to divided by51. */ + kCLOCK_MiscDivBy52 = 51, /*!< Misc divider like LPI2C set to divided by52. */ + kCLOCK_MiscDivBy53 = 52, /*!< Misc divider like LPI2C set to divided by53. */ + kCLOCK_MiscDivBy54 = 53, /*!< Misc divider like LPI2C set to divided by54. */ + kCLOCK_MiscDivBy55 = 54, /*!< Misc divider like LPI2C set to divided by55. */ + kCLOCK_MiscDivBy56 = 55, /*!< Misc divider like LPI2C set to divided by56. */ + kCLOCK_MiscDivBy57 = 56, /*!< Misc divider like LPI2C set to divided by57. */ + kCLOCK_MiscDivBy58 = 57, /*!< Misc divider like LPI2C set to divided by58. */ + kCLOCK_MiscDivBy59 = 58, /*!< Misc divider like LPI2C set to divided by59. */ + kCLOCK_MiscDivBy60 = 59, /*!< Misc divider like LPI2C set to divided by60. */ + kCLOCK_MiscDivBy61 = 60, /*!< Misc divider like LPI2C set to divided by61. */ + kCLOCK_MiscDivBy62 = 61, /*!< Misc divider like LPI2C set to divided by62. */ + kCLOCK_MiscDivBy63 = 62, /*!< Misc divider like LPI2C set to divided by63. */ + kCLOCK_MiscDivBy64 = 63, /*!< Misc divider like LPI2C set to divided by64. */ +} clock_div_value_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/*! + * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on. + */ +typedef enum _clock_output1_selection +{ + kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */ + kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */ + kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */ + kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */ + kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */ + kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */ + kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */ + kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */ + kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */ + kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */ + kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */ +} clock_output1_selection_t; + +/*! + * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on. + * + */ +typedef enum _clock_output2_selection +{ + kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */ + kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */ + kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */ + kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */ + kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */ + kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */ + kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */ + kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */ + kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */ + kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */ + kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */ + kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */ + kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */ +} clock_output2_selection_t; + +/*! + * @brief The enumerator of clock output's divider. + */ +typedef enum _clock_output_divider +{ + kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */ + kCLOCK_DivideBy2, /*!< Output clock divided by 2. */ + kCLOCK_DivideBy3, /*!< Output clock divided by 3. */ + kCLOCK_DivideBy4, /*!< Output clock divided by 4. */ + kCLOCK_DivideBy5, /*!< Output clock divided by 5. */ + kCLOCK_DivideBy6, /*!< Output clock divided by 6. */ + kCLOCK_DivideBy7, /*!< Output clock divided by 7. */ + kCLOCK_DivideBy8, /*!< Output clock divided by 8. */ +} clock_output_divider_t; + +/*! + * @brief The enumerator of clock root. + */ +typedef enum _clock_root +{ + kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */ + kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */ + kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */ + kCLOCK_CsiClkRoot, /*!< CSI clock root. */ + kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */ + kCLOCK_TraceClkRoot, /*!< Trace clock root. */ + kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */ + kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */ + kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */ + kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */ + kCLOCK_CanClkRoot, /*!< CAN clock root. */ + kCLOCK_UartClkRoot, /*!< UART clock root. */ + kCLOCK_LcdifClkRoot, /*!< LCD clock root. */ + kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */ + kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */ + kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */ +} clock_root_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux)); +} + +/*! + * @brief Set clock divider value. + * + * Example, set the ARM clock divider to divide by 2: + * @code + CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2); + @endcode + * + * Example, set the LPI2C clock divider to divide by 5. + * @code + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5); + @endcode + * + * Only @ref kCLOCK_Lpi2cDiv, @ref kCLOCK_CanDiv, @ref kCLOCK_UartDiv, @ref kCLOCK_Sai1Div, + * @ref kCLOCK_Sai2Div, @ref kCLOCK_Sai3Div , @ref kCLOCK_PerclkDiv can use the divider kCLOCK_MiscDivByxxx. + * + * @param divider Which divider node to set. + * @param value Clock div value to set, different divider has different value range. See @ref clock_div_value_t + * for details. + * Divided clock frequency = Undivided clock frequency / (value + 1) + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6UL); + + reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index])); + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << shift)); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param name Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @brief Gets the frequency of selected clock root. + * + * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t. + * @return The frequency of selected clock root. + */ +uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot); + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Check if Sys PFD is enabled + * + * @param pfd PFD control name + * @return PFD bypass status. + * - true: power on. + * - false: power off. + */ +bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Check if Usb1 PFD is enabled + * + * @param pfd PFD control name. + * @return PFD bypass status. + * - true: power on. + * - false: power off. + */ +bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name Clock Output Inferfaces + * @{ + */ + +/*! + * @brief Set the clock source and the divider of the clock output1. + * + * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t. + * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t. + */ +void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider); + +/*! + * @brief Set the clock source and the divider of the clock output2. + * + * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t. + * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t. + */ +void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider); + +/*! + * @brief Get the frequency of clock output1 clock signal. + * + * @return The frequency of clock output1 clock signal. + */ +uint32_t CLOCK_GetClockOutCLKO1Freq(void); + +/*! + * @brief Get the frequency of clock output2 clock signal. + * + * @return The frequency of clock output2 clock signal. + */ +uint32_t CLOCK_GetClockOutClkO2Freq(void); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.c new file mode 100644 index 0000000000..2cc0fd799a --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.c @@ -0,0 +1,86 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexram_allocate.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "driver.soc_flexram_allocate" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * param config allocate configuration. + * retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) +{ + assert(config != NULL); + + uint8_t dtcmBankNum = config->dtcmBankNum; + uint8_t itcmBankNum = config->itcmBankNum; + uint8_t ocramBankNum = config->ocramBankNum; + uint8_t i = 0U; + uint32_t bankCfg = 0U; + status_t status = kStatus_Success; + + /* check the arguments */ + if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) + { + status = kStatus_InvalidArgument; + } + else + { + /* flexram bank config value */ + for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++) + { + if (i < ocramBankNum) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum + itcmBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U); + continue; + } + } + + IOMUXC_GPR->GPR17 = bankCfg; + + /* select ram allocate source from FLEXRAM_BANK_CFG */ + FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg); + } + + return status; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.h new file mode 100644 index 0000000000..47448afe8d --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_flexram_allocate.h @@ -0,0 +1,87 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXRAM_ALLOCATE_H_ +#define _FSL_FLEXRAM_ALLOCATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexram + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SOC_FLEXRAM_ALLOCATE driver version 2.0.2. */ +#define FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief FLEXRAM bank type */ +enum +{ + kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ + kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ + kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ + kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ +}; + +/*! @brief FLEXRAM bank allocate source */ +typedef enum _flexram_bank_allocate_src +{ + kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ + kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ +} flexram_bank_allocate_src_t; + +/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */ +typedef struct _flexram_allocate_ram +{ + const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */ + const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */ + const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */ +} flexram_allocate_ram_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * @param config allocate configuration. + * @retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); + +/*! + * @brief FLEXRAM set allocate on-chip ram source + * @param src bank config source select value. + */ +static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) +{ + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_iomuxc.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000..9756b13242 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_iomuxc.h @@ -0,0 +1,1241 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.2. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\> + * + * @{ + */ +#define IOMUXC_GPIO_EMC_00_SEMC_DA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_TMR2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX1 0x401F813CU, 0x6U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX2 0x401F8140U, 0x6U, 0, 0, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX3 0x401F8144U, 0x6U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TXD 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RXD 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TXD 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RXD 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TXD 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RXD 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI_A_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x401F81F0U, 0x6U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +/*@}*/ + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister != 0UL) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister != 0UL) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | + IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | + IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); + base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); + base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_nic301.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_nic301.h new file mode 100644 index 0000000000..f6ef00c5df --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_nic301.h @@ -0,0 +1,308 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_NIC301_H_ +#define _FSL_NIC301_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup nic301 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nic301" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief NIC301 driver version 2.0.1. */ +#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +#define GPV0_BASE (0x41000000UL) +#define GPV1_BASE (0x41100000UL) +#define GPV4_BASE (0x41400000UL) + +#define NIC_FN_MOD2_OFFSET (0x024UL) +#define NIC_FN_MOD_AHB_OFFSET (0x028UL) +#define NIC_WR_TIDEMARK_OFFSET (0x040UL) +#define NIC_READ_QOS_OFFSET (0x100UL) +#define NIC_WRITE_QOS_OFFSET (0x104UL) +#define NIC_FN_MOD_OFFSET (0x108UL) + +#define NIC_LCD_BASE (GPV0_BASE + 0x44000) +#define NIC_CSI_BASE (GPV0_BASE + 0x45000) +#define NIC_PXP_BASE (GPV0_BASE + 0x46000) + +#define NIC_DCP_BASE (GPV1_BASE + 0x42000) +#define NIC_ENET_BASE (GPV1_BASE + 0x43000) +#define NIC_USBO2_BASE (GPV1_BASE + 0x44000) +#define NIC_USDHC1_BASE (GPV1_BASE + 0x45000) +#define NIC_USDHC2_BASE (GPV1_BASE + 0x46000) +#define NIC_TestPort_BASE (GPV1_BASE + 0x47000) + +#define NIC_CM7_BASE (GPV4_BASE + 0x42000) +#define NIC_DMA_BASE (GPV4_BASE + 0x43000) + +#define NIC_QOS_MASK (0xF) +#define NIC_WR_TIDEMARK_MASK (0x7) +#define NIC_FN_MOD_AHB_MASK (0x7) +#define NIC_FN_MOD_MASK (0x1) +#define NIC_FN_MOD2_MASK (0x1) + +typedef enum _nic_reg +{ + /* read_qos */ + kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET, + + /* write_qos */ + kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET, + + /* fn_mod */ + kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET, + + /* fn_mod2 */ + kNIC_REG_FN_MOD2_DCP = NIC_ENET_BASE + NIC_FN_MOD2_OFFSET, + + /* fn_mod_ahb */ + kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET, + kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET, + kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET, + + /* wr_tidemark */ + kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET, +} nic_reg_t; + +/* fn_mod2 */ +typedef enum _nic_fn_mod2 +{ + kNIC_FN_MOD2_ENABLE = 0, + kNIC_FN_MOD2_BYPASS, +} nic_fn_mod2_t; + +/* fn_mod_ahb */ +typedef enum _nic_fn_mod_ahb +{ + kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0, + kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE, + kNIC_FN_MOD_AHB_LOCK_OVERRIDE, +} nic_fn_mod_ahb_t; + +/* fn_mod */ +typedef enum _nic_fn_mod +{ + kNIC_FN_MOD_ReadIssue = 0, + kNIC_FN_MOD_WriteIssue, +} nic_fn_mod_t; + +/* read_qos/write_qos */ +typedef enum _nic_qos +{ + kNIC_QOS_0 = 0, + kNIC_QOS_1, + kNIC_QOS_2, + kNIC_QOS_3, + kNIC_QOS_4, + kNIC_QOS_5, + kNIC_QOS_6, + kNIC_QOS_7, + kNIC_QOS_8, + kNIC_QOS_9, + kNIC_QOS_10, + kNIC_QOS_11, + kNIC_QOS_12, + kNIC_QOS_13, + kNIC_QOS_14, + kNIC_QOS_15, +} nic_qos_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set read_qos Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 15) + */ +static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); + __DSB(); +} + +/*! + * @brief Get read_qos Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_qos_t NIC_GetReadQos(nic_reg_t base) +{ + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); +} + +/*! + * @brief Set write_qos Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 15) + */ +static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); + __DSB(); +} + +/*! + * @brief Get write_qos Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base) +{ + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); +} + +/*! + * @brief Set fn_mod_ahb Value + * + * @param base Base address of GPV address + * @param value Target value + */ +static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v) +{ + *(volatile uint32_t *)(base) = v; + __DSB(); +} + +/*! + * @brief Get fn_mod_ahb Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base) +{ + return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK); +} + +/*! + * @brief Set wr_tidemark Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 7) + */ +static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK); + __DSB(); +} + +/*! + * @brief Get wr_tidemark Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline uint8_t NIC_GetWrTideMark(nic_reg_t base) +{ + return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK); +} + +/*! + * @brief Set fn_mod Value + * + * @param base Base address of GPV address + * @param value Target value + */ +static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) +{ + *(volatile uint32_t *)(base) = value; + __DSB(); +} + +/*! + * @brief Get fn_mod Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base) +{ + return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK); +} + +/*! + * @brief Set fn_mod2 Value + * + * @param base Base address of GPV address + * @param value Target value + */ +static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value) +{ + *(volatile uint32_t *)(base) = value; + __DSB(); +} + +/*! + * @brief Get fn_mod2 Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base) +{ + return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK); +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _FSL_NIC301_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.c new file mode 100644 index 0000000000..a57714efe9 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.c @@ -0,0 +1,162 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_romapi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "driver.romapi" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Interface for the ROM FLEXSPI NOR flash driver. + */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t lengthInBytes); + uint32_t reserved1; + void (*clear_cache)(uint32_t instance); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber); + uint32_t reserved2; +} flexspi_nor_driver_interface_t; + +/*! + * @brief Root of the bootloader api tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing */ + const uint32_t version; /*!< Bootloader version number */ + const uint8_t *copyright; /*!< Bootloader Copyright */ + const uint32_t reserved0; + flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FLEXSPI NOR flash api */ +} bootloader_api_entry_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#define g_bootloaderTree ((bootloader_api_entry_t *)*(uint32_t *)0x0020001cU) + +#define api_flexspi_nor_erase_sector \ + ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x002106E7U) +/******************************************************************************* + * Codes + ******************************************************************************/ + +/******************************************************************************* + * ROM FLEXSPI NOR driver + ******************************************************************************/ +#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI + +/*! + * @brief Initialize Serial NOR flash via FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) +{ + return g_bootloaderTree->flexSpiNorDriver->init(instance, config); +} + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dstAddr A pointer to the desired flash memory to be programmed. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + */ +status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src) +{ + return g_bootloaderTree->flexSpiNorDriver->program(instance, config, dstAddr, src); +} + +/*! + * @brief Erase Flash Region specified by address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * @param length The length, given in bytes to be erased. + */ +status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) +{ + return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length); +} + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR +/*! + * @brief Erase one sector specified by address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + */ +status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start) +{ + return api_flexspi_nor_erase_sector(instance, config, start); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL +/*! @brief Erase all the Serial NOR flash connected on FLEXSPI. */ +status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) +{ + return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER +/*! @brief FLEXSPI command */ +status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) +{ + return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT +/*! @brief Configure FLEXSPI Lookup table. */ +status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, + uint32_t seqIndex, + const uint32_t *lutBase, + uint32_t seqNumber) +{ + return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */ + +/*! @brief Software reset for the FLEXSPI logic. */ +void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance) +{ + g_bootloaderTree->flexSpiNorDriver->clear_cache(instance); +} + +#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.h new file mode 100644 index 0000000000..a57c587e23 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1052/drivers/fsl_romapi.h @@ -0,0 +1,565 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ROMAPI_H_ +#define _FSL_ROMAPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup romapi + * @{ + */ + +/*! @brief ROMAPI version 1.1.1. */ +#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 1U)) +/*! @brief ROM FLEXSPI NOR driver version 1.4.0. */ +#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U)) + +/*! + * @name Common ROMAPI fearures info defines + * @{ + */ +/* @brief ROM has FLEXSPI NOR API. */ +#define FSL_ROM_HAS_FLEXSPINOR_API (1) +/* @brief ROM has run bootloader API. */ +#define FSL_ROM_HAS_RUNBOOTLOADER_API (0) +/* @brief ROM has FLEXSPI NOR get config API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0) +/* @brief ROM has flash init API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1) +/* @brief ROM has erase API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1) +/* @brief ROM has erase sector API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1) +/* @brief ROM has erase block API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (0) +/* @brief ROM has erase all API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (1) +/* @brief ROM has page program API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1) +/* @brief ROM has update lut API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1) +/* @brief ROM has FLEXSPI command API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1) + +/*@}*/ + +#define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/ +#define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/ + +#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Generate bit mask */ +#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset)) + +/*! @brief FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */ +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */ + +#define CMD_SDR 0x01U +#define CMD_DDR 0x21U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x22U +#define CADDR_SDR 0x03U +#define CADDR_DDR 0x23U +#define MODE1_SDR 0x04U +#define MODE1_DDR 0x24U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x25U +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x26U +#define MODE8_SDR 0x07U +#define MODE8_DDR 0x27U +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x28U +#define READ_SDR 0x09U +#define READ_DDR 0x29U +#define LEARN_SDR 0x0AU +#define LEARN_DDR 0x2AU +#define DATSZ_SDR 0x0BU +#define DATSZ_DDR 0x2BU +#define DUMMY_SDR 0x0CU +#define DUMMY_DDR 0x2CU +#define DUMMY_RWDS_SDR 0x0DU +#define DUMMY_RWDS_DDR 0x2DU +#define JMP_ON_CS 0x1FU +#define STOP 0U + +#define FLEXSPI_1PAD 0U +#define FLEXSPI_2PAD 1U +#define FLEXSPI_4PAD 2U +#define FLEXSPI_8PAD 3U + +/* Lookup table related defintions */ +#define NOR_CMD_INDEX_READ 0U +#define NOR_CMD_INDEX_READSTATUS 1U +#define NOR_CMD_INDEX_WRITEENABLE 2U +#define NOR_CMD_INDEX_ERASESECTOR 3U +#define NOR_CMD_INDEX_PAGEPROGRAM 4U +#define NOR_CMD_INDEX_CHIPERASE 5U +#define NOR_CMD_INDEX_DUMMY 6U +#define NOR_CMD_INDEX_ERASEBLOCK 7U + +/*! + * NOR LUT sequence index used for default LUT assignment + * NOTE: + * The will take effect if the lut sequences are not customized. + */ +#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ + +/*! + * @name Support for init FLEXSPI NOR configuration + * @{ + */ +/*! @brief Flash Pad Definitions */ +enum +{ + kSerialFlash_1Pad = 1U, + kSerialFlash_2Pads = 2U, + kSerialFlash_4Pads = 4U, + kSerialFlash_8Pads = 8U, +}; + +/*! @brief FLEXSPI clock configuration type */ +enum +{ + kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ + kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ +}; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +enum _flexspi_read_sample_clk +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, +}; + +/*! @brief Flash Type Definition */ +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +/*! @brief Flash Configuration Command Type */ +enum +{ + kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ + kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /*!< Reset device command */ +}; + +/*! @brief Defintions for FLEXSPI Serial Clock Frequency */ +enum _flexspi_serial_clk_freq +{ + kFLEXSPISerialClk_NoChange = 0U, + kFLEXSPISerialClk_30MHz = 1U, + kFLEXSPISerialClk_50MHz = 2U, + kFLEXSPISerialClk_60MHz = 3U, + kFLEXSPISerialClk_75MHz = 4U, + kFLEXSPISerialClk_80MHz = 5U, + kFLEXSPISerialClk_100MHz = 6U, + kFLEXSPISerialClk_133MHz = 7U, + kFLEXSPISerialClk_166MHz = 8U, + kFLEXSPISerialClk_200MHz = 9U, +}; + +/*! @brief Misc feature bit definitions */ +enum +{ + kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ + kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ + kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ + kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ + kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ + kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ + kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ + kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ +}; + +enum +{ + kSerialNorType_StandardSPI, /*!< Device that support Standard SPI and Extended SPI mode */ + kSerialNorType_HyperBus, /*!< Device that supports HyperBus only */ + kSerialNorType_XPI, /*!< Device that works under DPI, QPI or OPI mode */ + kSerialNorType_NoCmd, /*!< Device that works under No command mode (XIP mode/Performance Enhance + mode/continous read mode) */ +}; + +/*@}*/ + +/*! + * @name FLEXSPI NOR Configuration + * @{ + */ + +/*! @brief FLEXSPI LUT Sequence structure */ +typedef struct _flexspi_lut_seq +{ + uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +typedef struct +{ + uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/*! @brief FLEXSPI Memory Configuration Block */ +typedef struct _flexspi_mem_config +{ + uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ + uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */ + uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */ + uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ + uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ + uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + flexspi_lut_seq_t + configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ + uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + details */ + uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ + uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ + uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + Chapter for more details */ + uint8_t + lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ + uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; + +/*! @brief Serial NOR configuration block */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ + uint32_t pageSize; /*!< Page size of Serial NOR */ + uint32_t sectorSize; /*!< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /*!< Reserved for future use */ + uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ + uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ + uint32_t blockSize; /*!< Block size */ + uint32_t reserve2[11]; /*!< Reserved for future use */ +} flexspi_nor_config_t; + +/*@}*/ + +/*! @brief Manufacturer ID */ +enum +{ + kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ + kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ + kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ + kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ +}; + +/*! @brief ROM FLEXSPI NOR flash status */ +enum _flexspi_nor_status +{ + kStatus_ROM_FLEXSPI_SequenceExecutionTimeout = + MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ + kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ + kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */ + kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ + kStatus_ROM_FLEXSPINOR_SFDP_NotFound = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ + kStatus_ROM_FLEXSPINOR_Flash_NotFound = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ +}; + +typedef enum _flexspi_operation +{ + kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ + kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ + kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ + kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPIOperation_End = kFLEXSPIOperation_Read, +} flexspi_operation_t; + +/*! @brief FLEXSPI Transfer Context */ +typedef struct _flexspi_xfer +{ + flexspi_operation_t operation; /*!< FLEXSPI operation */ + uint32_t baseAddress; /*!< FLEXSPI operation base address */ + uint32_t seqId; /*!< Sequence Id */ + uint32_t seqNum; /*!< Sequence Number */ + bool isParallelModeEnable; /*!< Is a parallel transfer */ + uint32_t *txBuffer; /*!< Tx buffer */ + uint32_t txSize; /*!< Tx size in bytes */ + uint32_t *rxBuffer; /*!< Rx buffer */ + uint32_t rxSize; /*!< Rx size in bytes */ +} flexspi_xfer_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize Serial NOR flash via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ +/*! + * @brief Program data to Serial NOR flash via FLEXSPI. + * + * This function programs the NOR flash memory with the dest address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dstAddr A pointer to the desired flash memory to be programmed. + * NOTE: + * It is recommended that use page aligned access; + * If the dstAddr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR +/*! + * @brief Erase one sector specified by address + * + * This function erases one of NOR flash sectors based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param address The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,The driver automatically + * aligns address down with the sector address. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL +/*! + * @brief Erase all the Serial NOR flash connected on FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */ + +/*! + * @brief Erase Flash Region specified by address and length + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access NOR flash; + * If dstAddr is not aligned with the sector,the driver automatically + * aligns address down with the sector address. + * @param length The length, given in bytes to be erased. + * NOTE: + * It is recommended that use sector-aligned access NOR flash; + * If length is not aligned with the sector,the driver automatically + * aligns up with the sector. + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + +/*@}*/ + +/*! + * @name Command + * @{ + */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER +/*! + * @brief FLEXSPI command + * + * This function is used to perform the command write sequence to the NOR flash. + * + * @param instance storage the index of FLEXSPI. + * @param xfer A pointer to the storage FLEXSPI Transfer Context. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */ +/*@}*/ + +/*! + * @name UpdateLut + * @{ + */ +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT +/*! + * @brief Configure FLEXSPI Lookup table + * + * @param instance storage the index of FLEXSPI. + * @param seqIndex storage the sequence Id. + * @param lutBase A pointer to the look-up-table for command sequences. + * @param seqNumber storage sequence number. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, + uint32_t seqIndex, + const uint32_t *lutBase, + uint32_t seqNumber); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */ + +/*@}*/ + +/*! + * @name ClearCache + * @{ + */ + +/*! + * @brief Software reset for the FLEXSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param instance storage the index of FLEXSPI. + */ +void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance); + +/*@}*/ + +#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _FSL_ROMAPI_H_ */ |