diff options
Diffstat (limited to 'bsps/arm/imx')
| -rw-r--r-- | bsps/arm/imx/headers.am | 22 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h | 64 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h | 111 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h | 162 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h | 54 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h | 61 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h | 49 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h | 104 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h | 174 | ||||
| -rw-r--r-- | bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h | 62 | ||||
| -rw-r--r-- | bsps/arm/imx/include/bsp.h | 84 | ||||
| -rw-r--r-- | bsps/arm/imx/include/bsp/irq.h | 38 | ||||
| -rw-r--r-- | bsps/arm/imx/include/tm27.h | 24 |
13 files changed, 1009 insertions, 0 deletions
diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am new file mode 100644 index 0000000000..dd18164254 --- /dev/null +++ b/bsps/arm/imx/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/imx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/imx/include/tm27.h + +include_arm_freescale_imxdir = $(includedir)/arm/freescale/imx +include_arm_freescale_imx_HEADERS = +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h +include_arm_freescale_imx_HEADERS += ../../../../../../bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h new file mode 100644 index 0000000000..5633de6f50 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ccmvar.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_ccmvar.h 292565 2015-12-21 20:17:24Z gonzo $ + */ + +#ifndef IMX_CCMVAR_H +#define IMX_CCMVAR_H + +/* + * We need a clock management system that works across unrelated SoCs and + * devices. For now, to keep imx development moving, define some barebones + * functionality that can be shared within the imx family by having each SoC + * implement functions with a common name. + * + * The usb enable functions are best-effort. They turn on the usb otg, host, + * and phy clocks in a SoC-specific manner, but it may take a lot more than that + * to make usb work on a given board. In particular, it can require specific + * pinmux setup of gpio pins connected to external phy parts, voltage regulators + * and overcurrent detectors, and so on. On such boards, u-boot or other early + * board setup code has to handle those things. + */ + +uint32_t imx_ccm_ipg_hz(void); +uint32_t imx_ccm_perclk_hz(void); +uint32_t imx_ccm_sdhci_hz(void); +uint32_t imx_ccm_uart_hz(void); +uint32_t imx_ccm_ahb_hz(void); + +#ifndef __rtems__ +void imx_ccm_usb_enable(device_t _usbdev); +void imx_ccm_usbphy_enable(device_t _phydev); +void imx_ccm_ssi_configure(device_t _ssidev); +void imx_ccm_hdmi_enable(void); +void imx_ccm_ipu_enable(int ipu); + +/* Routines to get and set the arm clock root divisor register. */ +uint32_t imx_ccm_get_cacrr(void); +void imx_ccm_set_cacrr(uint32_t _divisor); +#endif /* __rtems__ */ + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h new file mode 100644 index 0000000000..299ed2bd7a --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_ecspireg.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_ECSPIREG_H +#define IMX_ECSPIREG_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t rxdata; + uint32_t txdata; + uint32_t conreg; +#define IMX_ECSPI_CONREG_BURST_LENGTH(val) BSP_FLD32(val, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_GET(reg) BSP_FLD32GET(reg, 20, 31) +#define IMX_ECSPI_CONREG_BURST_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 20, 31) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT(val) BSP_FLD32(val, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define IMX_ECSPI_CONREG_CHANNEL_SELECT_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define IMX_ECSPI_CONREG_DRCTL(val) BSP_FLD32(val, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define IMX_ECSPI_CONREG_DRCTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define IMX_ECSPI_CONREG_PRE_DIVIDER(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONREG_PRE_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONREG_POST_DIVIDER(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONREG_POST_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONREG_CHANNEL_MODE(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONREG_CHANNEL_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONREG_SMC BSP_BIT32(3) +#define IMX_ECSPI_CONREG_XCH BSP_BIT32(2) +#define IMX_ECSPI_CONREG_HT BSP_BIT32(1) +#define IMX_ECSPI_CONREG_EN BSP_BIT32(0) + uint32_t configreg; +#define IMX_ECSPI_CONFIGREG_HT_LENGTH(val) BSP_FLD32(val, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 28) +#define IMX_ECSPI_CONFIGREG_HT_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL(val) BSP_FLD32(val, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define IMX_ECSPI_CONFIGREG_SCLK_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) +#define IMX_ECSPI_CONFIGREG_DATA_CTL(val) BSP_FLD32(val, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_ECSPI_CONFIGREG_DATA_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_ECSPI_CONFIGREG_SS_POL(val) BSP_FLD32(val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_POL_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define IMX_ECSPI_CONFIGREG_SS_CTL(val) BSP_FLD32(val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define IMX_ECSPI_CONFIGREG_SS_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define IMX_ECSPI_CONFIGREG_SCLK_POL(val) BSP_FLD32(val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_POL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA(val) BSP_FLD32(val, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define IMX_ECSPI_CONFIGREG_SCLK_PHA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define IMX_ECSPI_TC BSP_BIT32(7) +#define IMX_ECSPI_RO BSP_BIT32(6) +#define IMX_ECSPI_RF BSP_BIT32(5) +#define IMX_ECSPI_RDR BSP_BIT32(4) +#define IMX_ECSPI_RR BSP_BIT32(3) +#define IMX_ECSPI_TF BSP_BIT32(2) +#define IMX_ECSPI_TDR BSP_BIT32(1) +#define IMX_ECSPI_TE BSP_BIT32(0) + uint32_t intreg; + uint32_t dmareg; +#define IMX_ECSPI_DMAREG_RXTDEN BSP_BIT32(31) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH(val) BSP_FLD32(val, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_ECSPI_DMAREG_RXDEN BSP_BIT32(23) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_DMAREG_RX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_DMAREG_TEDEN BSP_BIT32(7) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD(val) BSP_FLD32(val, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_ECSPI_DMAREG_TX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t statreg; + uint32_t periodreg; +#define IMX_ECSPI_PERIODREG_CSD_CTL(val) BSP_FLD32(val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_ECSPI_PERIODREG_CSD_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_ECSPI_PERIODREG_CSRC BSP_BIT32(15) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD(val) BSP_FLD32(val, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_GET(reg) BSP_FLD32GET(reg, 0, 14) +#define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 14) + uint32_t testreg; +#define IMX_ECSPI_TESTREG_LBC BSP_BIT32(31) +#define IMX_ECSPI_TESTREG_RXCNT(val) BSP_FLD32(val, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_GET(reg) BSP_FLD32GET(reg, 8, 14) +#define IMX_ECSPI_TESTREG_RXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 14) +#define IMX_ECSPI_TESTREG_TXCNT(val) BSP_FLD32(val, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define IMX_ECSPI_TESTREG_TXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) + uint32_t reserved_24[7]; + uint32_t msgdata; +} imx_ecspi; + +#endif /* IMX_ECSPIREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h new file mode 100644 index 0000000000..924166c70d --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_GPCREG_H +#define IMX_GPCREG_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t lpcr_a7_bsc; + uint32_t lpcr_a7_ad; + uint32_t lpcr_m4; + uint32_t reserved_0c[2]; + uint32_t slpcr; + uint32_t reserved_18[2]; + uint32_t mlpcr; + uint32_t pgc_ack_sel_a7; + uint32_t pgc_ack_sel_m4; + uint32_t misc; + uint32_t imr1_core0_a7; + uint32_t imr2_core0_a7; + uint32_t imr3_core0_a7; + uint32_t imr4_core0_a7; + uint32_t imr1_core1_a7; + uint32_t imr2_core1_a7; + uint32_t imr3_core1_a7; + uint32_t imr4_core1_a7; + uint32_t imr1_m4; + uint32_t imr2_m4; + uint32_t imr3_m4; + uint32_t imr4_m4; + uint32_t reserved_60[4]; + uint32_t isr1_a7; + uint32_t isr2_a7; + uint32_t isr3_a7; + uint32_t isr4_a7; + uint32_t isr1_m4; + uint32_t isr2_m4; + uint32_t isr3_m4; + uint32_t isr4_m4; + uint32_t reserved_90[8]; + uint32_t slt0_cfg; + uint32_t slt1_cfg; + uint32_t slt2_cfg; + uint32_t slt3_cfg; + uint32_t slt4_cfg; + uint32_t slt5_cfg; + uint32_t slt6_cfg; + uint32_t slt7_cfg; + uint32_t slt8_cfg; + uint32_t slt9_cfg; + uint32_t reserved_d8[5]; + uint32_t pgc_cpu_mapping; +#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2) +#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1) +#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0) +#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4) +#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3) +#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2) +#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1) +#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0) + uint32_t cpu_pgc_sw_pup_req; + uint32_t reserved_f4; + uint32_t pu_pgc_sw_pup_req; + uint32_t cpu_pgc_sw_pdn_req; + uint32_t reserved_100; + uint32_t pu_pgc_sw_pdn_req; + uint32_t reserved_108[10]; + uint32_t cpu_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status0; + uint32_t a7_mix_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status2; + uint32_t m4_mix_pgc_pup_status0; + uint32_t m4_mix_pgc_pup_status1; + uint32_t m4_mix_pgc_pup_status2; + uint32_t a7_pu_pgc_pup_status0; + uint32_t a7_pu_pgc_pup_status1; + uint32_t a7_pu_pgc_pup_status2; + uint32_t m4_pu_pgc_pup_status0; + uint32_t m4_pu_pgc_pup_status1; + uint32_t m4_pu_pgc_pup_status2; + uint32_t reserved_164[3]; + uint32_t cpu_pgc_pdn_status1; + uint32_t reserved_174[6]; + uint32_t a7_pu_pgc_pdn_status0; + uint32_t a7_pu_pgc_pdn_status1; + uint32_t a7_pu_pgc_pdn_status2; + uint32_t m4_pu_pgc_pdn_status0; + uint32_t m4_pu_pgc_pdn_status1; + uint32_t m4_pu_pgc_pdn_status2; + uint32_t reserved_1a4[3]; + uint32_t a7_mix_pdn_flg; + uint32_t a7_pu_pdn_flg; + uint32_t m4_mix_pdn_flg; + uint32_t m4_pu_pdn_flg; +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6) +#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0) + uint32_t reserved_1c0[400]; + uint32_t pgc_a7core0_ctrl; + uint32_t pgc_a7core0_pupscr; + uint32_t pgc_a7core0_pdnscr; + uint32_t pgc_a7core0_sr; + uint32_t reserved_810[12]; + uint32_t pgc_a7core1_ctrl; + uint32_t pgc_a7core1_pupscr; + uint32_t pgc_a7core1_pdnscr; + uint32_t pgc_a7core1_sr; + uint32_t reserved_850[12]; + uint32_t pgc_a7scu_ctrl; + uint32_t pgc_a7scu_pupscr; + uint32_t pgc_a7scu_pdnscr; + uint32_t pgc_a7scu_sr; + uint32_t pgc_scu_auxsw; + uint32_t reserved_894[11]; + uint32_t pgc_mix_ctrl; + uint32_t pgc_mix_pupscr; + uint32_t pgc_mix_pdnscr; + uint32_t pgc_mix_sr; + uint32_t reserved_8d0[12]; + uint32_t pgc_mipi_ctrl; + uint32_t pgc_mipi_pupscr; + uint32_t pgc_mipi_pdnscr; + uint32_t pgc_mipi_sr; + uint32_t reserved_910[12]; + uint32_t pgc_pcie_ctrl; + uint32_t pgc_pcie_pupscr; + uint32_t pgc_pcie_pdnscr; + uint32_t pgc_pcie_sr; + uint32_t reserved_950[176]; + uint32_t pgc_mipi_auxsw; + uint32_t reserved_c14[15]; + uint32_t pgc_pcie_auxsw; + uint32_t reserved_c54[43]; + uint32_t pgc_hsic_ctrl; + uint32_t pgc_hsic_pupscr; + uint32_t pgc_hsic_pdnscr; + uint32_t pgc_hsic_sr; +} imx_gpc; + +#endif /* IMX_GPCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h new file mode 100644 index 0000000000..0f1b7f13c5 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_I2CREG_H +#define IMX_I2CREG_H + +#include <bsp/utility.h> + +typedef struct { + uint16_t iadr; +#define IMX_I2C_IADR_ADR(val) BSP_FLD16(val, 1, 7) +#define IMX_I2C_IADR_ADR_GET(reg) BSP_FLD16GET(reg, 1, 7) +#define IMX_I2C_IADR_ADR_SET(reg, val) BSP_FLD16SET(reg, val, 1, 7) + uint16_t reserved_02; + uint16_t ifdr; +#define IMX_I2C_IFDR_IC(val) BSP_FLD16(val, 0, 5) +#define IMX_I2C_IFDR_IC_GET(reg) BSP_FLD16GET(reg, 0, 5) +#define IMX_I2C_IFDR_IC_SET(reg, val) BSP_FLD16SET(reg, val, 0, 5) + uint16_t reserved_06; + uint16_t i2cr; +#define IMX_I2C_I2CR_IEN BSP_BIT16(7) +#define IMX_I2C_I2CR_IIEN BSP_BIT16(6) +#define IMX_I2C_I2CR_MSTA BSP_BIT16(5) +#define IMX_I2C_I2CR_MTX BSP_BIT16(4) +#define IMX_I2C_I2CR_TXAK BSP_BIT16(3) +#define IMX_I2C_I2CR_RSTA BSP_BIT16(2) + uint16_t reserved_0a; + uint16_t i2sr; +#define IMX_I2C_I2SR_ICF BSP_BIT16(7) +#define IMX_I2C_I2SR_IAAS BSP_BIT16(6) +#define IMX_I2C_I2SR_IBB BSP_BIT16(5) +#define IMX_I2C_I2SR_IAL BSP_BIT16(4) +#define IMX_I2C_I2SR_SRW BSP_BIT16(2) +#define IMX_I2C_I2SR_IIF BSP_BIT16(1) +#define IMX_I2C_I2SR_RXAK BSP_BIT16(0) + uint16_t reserved_0e; + uint16_t i2dr; +#define IMX_I2C_I2DR_DATA(val) BSP_FLD16(val, 0, 7) +#define IMX_I2C_I2DR_DATA_GET(reg) BSP_FLD16GET(reg, 0, 7) +#define IMX_I2C_I2DR_DATA_SET(reg, val) BSP_FLD16SET(reg, val, 0, 7) +} imx_i2c; + +#endif /* IMX_I2CREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h new file mode 100644 index 0000000000..b84fde26de --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxreg.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxreg.h 322015 2017-08-03 14:43:41Z ian $ + */ + +#ifndef IMX_IOMUXREG_H +#define IMX_IOMUXREG_H + +#define IMX_IOMUXREG_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) +#define IMX_IOMUXREG_SHIFTIN(__x, __mask) ((__x) * IMX_IOMUXREG_LOWEST_SET_BIT(__mask)) + +#define IMX_IOMUXREG_BIT(n) (1 << (n)) +#define IMX_IOMUXREG_BITS(__m, __n) \ + ((IMX_IOMUXREG_BIT(MAX((__m), (__n)) + 1) - 1) ^ (IMX_IOMUXREG_BIT(MIN((__m), (__n))) - 1)) + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0C +#define IOMUXC_GPR3_HDMI_MASK (3 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI0 (0 << 2) +#define IOMUXC_GPR3_HDMI_IPU1_DI1 (1 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI0 (2 << 2) +#define IOMUXC_GPR3_HDMI_IPU2_DI1 (3 << 2) + +#define IOMUX_GPR13 0x34 +#define IOMUX_GPR13_SATA_PHY_8(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(26, 24)) +#define IOMUX_GPR13_SATA_PHY_7(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(23, 19)) +#define IOMUX_GPR13_SATA_PHY_6(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(18, 16)) +#define IOMUX_GPR13_SATA_SPEED(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 15)) +#define IOMUX_GPR13_SATA_PHY_5(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 14)) +#define IOMUX_GPR13_SATA_PHY_4(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(13, 11)) +#define IOMUX_GPR13_SATA_PHY_3(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(10, 7)) +#define IOMUX_GPR13_SATA_PHY_2(n) IMX_IOMUXREG_SHIFTIN(n, IMX_IOMUXREG_BITS(6, 2)) +#define IOMUX_GPR13_SATA_PHY_1(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 1)) +#define IOMUX_GPR13_SATA_PHY_0(n) IMX_IOMUXREG_SHIFTIN(n, (1 << 0)) + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h new file mode 100644 index 0000000000..8050b56a84 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_iomuxvar.h @@ -0,0 +1,49 @@ +/*- + * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_iomuxvar.h 321938 2017-08-02 18:28:06Z ian $ + */ + +#ifndef IMX_IOMUXVAR_H +#define IMX_IOMUXVAR_H + +/* + * IOMUX interface functions + */ +void iomux_set_function(u_int pin, u_int fn); +void iomux_set_pad(u_int pin, u_int cfg); +u_int iomux_get_pad_config(u_int pin); + +/* + * The IOMUX Controller device has a small set of "general purpose registers" + * which control various aspects of SoC operation that really have nothing to do + * with IO pin assignments or pad control. These functions let other soc level + * code manipulate these values. + */ +uint32_t imx_iomux_gpr_get(u_int regaddr); +void imx_iomux_gpr_set(u_int regaddr, uint32_t val); +void imx_iomux_gpr_set_masked(u_int regaddr, uint32_t clrbits, uint32_t setbits); + +#endif diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h new file mode 100644 index 0000000000..b5f3490b79 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_SRCREG_H +#define IMX_SRCREG_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t scr; +#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_SCR_LOCK BSP_BIT32(30) +#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) + uint32_t a7rcr0; +#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21) +#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13) +#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12) +#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9) +#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8) +#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5) +#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0) + uint32_t a7rcr1; +#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1) + uint32_t m4rcr; +#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30) +#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3) +#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2) +#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1) +#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0) + uint32_t reserved_10; + uint32_t ercr; + uint32_t reserved_18; + uint32_t hsicphy_rcr; + uint32_t usbophy1_rcr; + uint32_t usbophy2_rcr; + uint32_t mipiphy_rcr; + uint32_t pciephy_rcr; + uint32_t reserved_30[10]; + uint32_t sbmr1; + uint32_t srsr; + uint32_t reserved_60[2]; + uint32_t sisr; + uint32_t simr; + uint32_t sbmr2; + uint32_t gpr1; + uint32_t gpr2; + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t reserved_9c[985]; + uint32_t ddrc_rcr; +} imx_src; + +#endif /* IMX_SRCREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h new file mode 100644 index 0000000000..35862601e2 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_uartreg.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_UARTREG_H +#define IMX_UARTREG_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t urxd; +#define IMX_UART_URXD_CHARRDY BSP_BIT32(15) +#define IMX_UART_URXD_ERR BSP_BIT32(14) +#define IMX_UART_URXD_OVRRUN BSP_BIT32(13) +#define IMX_UART_URXD_FRMERR BSP_BIT32(12) +#define IMX_UART_URXD_BRK BSP_BIT32(11) +#define IMX_UART_URXD_PRERR BSP_BIT32(10) +#define IMX_UART_URXD_RX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_URXD_RX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_URXD_RX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_04[15]; + uint32_t utxd; +#define IMX_UART_UTXD_TX_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_UART_UTXD_TX_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_UART_UTXD_TX_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t reserved_44[15]; + uint32_t ucr1; +#define IMX_UART_UCR1_ADEN BSP_BIT32(15) +#define IMX_UART_UCR1_ADBR BSP_BIT32(14) +#define IMX_UART_UCR1_TRDYEN BSP_BIT32(13) +#define IMX_UART_UCR1_IDEN BSP_BIT32(12) +#define IMX_UART_UCR1_ICD(val) BSP_FLD32(val, 10, 11) +#define IMX_UART_UCR1_ICD_GET(reg) BSP_FLD32GET(reg, 10, 11) +#define IMX_UART_UCR1_ICD_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11) +#define IMX_UART_UCR1_RRDYEN BSP_BIT32(9) +#define IMX_UART_UCR1_RXDMAEN BSP_BIT32(8) +#define IMX_UART_UCR1_IREN BSP_BIT32(7) +#define IMX_UART_UCR1_TXMPTYEN BSP_BIT32(6) +#define IMX_UART_UCR1_RTSDEN BSP_BIT32(5) +#define IMX_UART_UCR1_SNDBRK BSP_BIT32(4) +#define IMX_UART_UCR1_TXDMAEN BSP_BIT32(3) +#define IMX_UART_UCR1_ATDMAEN BSP_BIT32(2) +#define IMX_UART_UCR1_DOZE BSP_BIT32(1) +#define IMX_UART_UCR1_UARTEN BSP_BIT32(0) + uint32_t ucr2; +#define IMX_UART_UCR2_ESCI BSP_BIT32(15) +#define IMX_UART_UCR2_IRTS BSP_BIT32(14) +#define IMX_UART_UCR2_CTSC BSP_BIT32(13) +#define IMX_UART_UCR2_CTS BSP_BIT32(12) +#define IMX_UART_UCR2_ESCEN BSP_BIT32(11) +#define IMX_UART_UCR2_RTEC(val) BSP_FLD32(val, 9, 10) +#define IMX_UART_UCR2_RTEC_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define IMX_UART_UCR2_RTEC_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10) +#define IMX_UART_UCR2_PREN BSP_BIT32(8) +#define IMX_UART_UCR2_PROE BSP_BIT32(7) +#define IMX_UART_UCR2_STPB BSP_BIT32(6) +#define IMX_UART_UCR2_WS BSP_BIT32(5) +#define IMX_UART_UCR2_RTSEN BSP_BIT32(4) +#define IMX_UART_UCR2_ATEN BSP_BIT32(3) +#define IMX_UART_UCR2_TXEN BSP_BIT32(2) +#define IMX_UART_UCR2_RXEN BSP_BIT32(1) +#define IMX_UART_UCR2_SRST BSP_BIT32(0) + uint32_t ucr3; +#define IMX_UART_UCR3_DPEC(val) BSP_FLD32(val, 14, 15) +#define IMX_UART_UCR3_DPEC_GET(reg) BSP_FLD32GET(reg, 14, 15) +#define IMX_UART_UCR3_DPEC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) +#define IMX_UART_UCR3_DTREN BSP_BIT32(13) +#define IMX_UART_UCR3_PARERREN BSP_BIT32(12) +#define IMX_UART_UCR3_FRAERREN BSP_BIT32(11) +#define IMX_UART_UCR3_DSR BSP_BIT32(10) +#define IMX_UART_UCR3_DCD BSP_BIT32(9) +#define IMX_UART_UCR3_RI BSP_BIT32(8) +#define IMX_UART_UCR3_ADNIMP BSP_BIT32(7) +#define IMX_UART_UCR3_RXDSEN BSP_BIT32(6) +#define IMX_UART_UCR3_AIRINTEN BSP_BIT32(5) +#define IMX_UART_UCR3_AWAKEN BSP_BIT32(4) +#define IMX_UART_UCR3_DTRDEN BSP_BIT32(3) +#define IMX_UART_UCR3_RXDMUXSEL BSP_BIT32(2) +#define IMX_UART_UCR3_INVT BSP_BIT32(1) +#define IMX_UART_UCR3_ACIEN BSP_BIT32(0) + uint32_t ucr4; +#define IMX_UART_UCR4_CTSTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UCR4_CTSTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UCR4_CTSTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UCR4_INVR BSP_BIT32(9) +#define IMX_UART_UCR4_ENIRI BSP_BIT32(8) +#define IMX_UART_UCR4_WKEN BSP_BIT32(7) +#define IMX_UART_UCR4_IDDMAEN BSP_BIT32(6) +#define IMX_UART_UCR4_IRSC BSP_BIT32(5) +#define IMX_UART_UCR4_LPBYP BSP_BIT32(4) +#define IMX_UART_UCR4_TCEN BSP_BIT32(3) +#define IMX_UART_UCR4_BKEN BSP_BIT32(2) +#define IMX_UART_UCR4_OREN BSP_BIT32(1) +#define IMX_UART_UCR4_DREN BSP_BIT32(0) + uint32_t ufcr; +#define IMX_UART_UFCR_TXTL(val) BSP_FLD32(val, 10, 15) +#define IMX_UART_UFCR_TXTL_GET(reg) BSP_FLD32GET(reg, 10, 15) +#define IMX_UART_UFCR_TXTL_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15) +#define IMX_UART_UFCR_RFDIV(val) BSP_FLD32(val, 7, 9) +#define IMX_UART_UFCR_RFDIV_GET(reg) BSP_FLD32GET(reg, 7, 9) +#define IMX_UART_UFCR_RFDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 9) +#define IMX_UART_UFCR_DCEDTE BSP_BIT32(6) +#define IMX_UART_UFCR_RXTL(val) BSP_FLD32(val, 0, 5) +#define IMX_UART_UFCR_RXTL_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_UART_UFCR_RXTL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t usr1; +#define IMX_UART_USR1_PARITYERR BSP_BIT32(15) +#define IMX_UART_USR1_RTSS BSP_BIT32(14) +#define IMX_UART_USR1_TRDY BSP_BIT32(13) +#define IMX_UART_USR1_RTSD BSP_BIT32(12) +#define IMX_UART_USR1_ESCF BSP_BIT32(11) +#define IMX_UART_USR1_FRAMERR BSP_BIT32(10) +#define IMX_UART_USR1_RRDY BSP_BIT32(9) +#define IMX_UART_USR1_AGTIM BSP_BIT32(8) +#define IMX_UART_USR1_DTRD BSP_BIT32(7) +#define IMX_UART_USR1_RXDS BSP_BIT32(6) +#define IMX_UART_USR1_AIRINT BSP_BIT32(5) +#define IMX_UART_USR1_AWAKE BSP_BIT32(4) +#define IMX_UART_USR1_SAD BSP_BIT32(3) + uint32_t usr2; +#define IMX_UART_USR2_ADET BSP_BIT32(15) +#define IMX_UART_USR2_TXFE BSP_BIT32(14) +#define IMX_UART_USR2_DTRF BSP_BIT32(13) +#define IMX_UART_USR2_IDLE BSP_BIT32(12) +#define IMX_UART_USR2_ACST BSP_BIT32(11) +#define IMX_UART_USR2_RIDELT BSP_BIT32(10) +#define IMX_UART_USR2_RIIN BSP_BIT32(9) +#define IMX_UART_USR2_IRINT BSP_BIT32(8) +#define IMX_UART_USR2_WAKE BSP_BIT32(7) +#define IMX_UART_USR2_DCDDELT BSP_BIT32(6) +#define IMX_UART_USR2_DCDIN BSP_BIT32(5) +#define IMX_UART_USR2_RTSF BSP_BIT32(4) +#define IMX_UART_USR2_TXDC BSP_BIT32(3) +#define IMX_UART_USR2_BRCD BSP_BIT32(2) +#define IMX_UART_USR2_ORE BSP_BIT32(1) +#define IMX_UART_USR2_RDR BSP_BIT32(0) + uint32_t uesc; + uint32_t utim; + uint32_t ubir; + uint32_t ubmr; + uint32_t ubrc; + uint32_t onems; + uint32_t uts; +#define IMX_UART_UTS_FRCPERR BSP_BIT32(13) +#define IMX_UART_UTS_LOOP BSP_BIT32(12) +#define IMX_UART_UTS_DBGEN BSP_BIT32(11) +#define IMX_UART_UTS_LOOPIR BSP_BIT32(10) +#define IMX_UART_UTS_RXDBG BSP_BIT32(9) +#define IMX_UART_UTS_TXEMPTY BSP_BIT32(6) +#define IMX_UART_UTS_RXEMPTY BSP_BIT32(5) +#define IMX_UART_UTS_TXFULL BSP_BIT32(4) +#define IMX_UART_UTS_RXFULL BSP_BIT32(3) +#define IMX_UART_UTS_SOFTRST BSP_BIT32(0) + uint32_t umcr; +#define IMX_UART_UMCR_SLADDR(val) BSP_FLD32(val, 8, 15) +#define IMX_UART_UMCR_SLADDR_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define IMX_UART_UMCR_SLADDR_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define IMX_UART_UMCR_SADEN BSP_BIT32(3) +#define IMX_UART_UMCR_TXB8 BSP_BIT32(2) +#define IMX_UART_UMCR_SLAM BSP_BIT32(1) +#define IMX_UART_UMCR_MDEN BSP_BIT32(0) +} imx_uart; + +#endif /* IMX_UARTREG_H */ diff --git a/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h new file mode 100644 index 0000000000..e26dfb2cc3 --- /dev/null +++ b/bsps/arm/imx/include/arm/freescale/imx/imx_wdogreg.h @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2012, 2013 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Oleksandr Rybalko under sponsorship + * from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/freescale/imx/imx_wdogreg.h 291367 2015-11-26 17:26:52Z ian $ + */ + +#define WDOG_CLK_FREQ 32768 + +#define WDOG_CR_REG 0x00 /* Control Register */ +#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */ +#define WDOG_CR_WT_SHIFT 8 +#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */ +#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */ +#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */ +#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */ +#define WDOG_CR_WDE (1 << 2) /* WDog Enable */ +#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */ +#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */ + +#define WDOG_SR_REG 0x02 /* Service Register */ +#define WDOG_SR_STEP1 0x5555 +#define WDOG_SR_STEP2 0xaaaa + +#define WDOG_RSR_REG 0x04 /* Reset Status Register */ +#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */ +#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */ +#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */ + +#define WDOG_ICR_REG 0x06 /* Interrupt Control Register */ +#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */ +#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */ +#define WDOG_ICR_WTCT_MASK 0x00ff +#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */ + +#define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */ +#define WDOG_MCR_PDE (1 << 0) + diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h new file mode 100644 index 0000000000..b5fb7127df --- /dev/null +++ b/bsps/arm/imx/include/bsp.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_BSP_H +#define LIBBSP_ARM_IMX_BSP_H + +#include <bspopts.h> + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#ifndef ASM + +#include <rtems.h> + +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_GIC_DIST_BASE 0x31001000 + +#define BSP_ARM_GIC_CPUIF_BASE 0x31002000 + +#define BSP_ARM_A9MPCORE_GT_BASE 0 + +#define BSP_ARM_A9MPCORE_SCU_BASE 0 + +void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq); + +void *imx_get_reg_of_node(const void *fdt, int node); + +int imx_iomux_configure_pins(const void *fdt, uint32_t phandle); + +rtems_vector_number imx_get_irq_of_node( + const void *fdt, + int node, + size_t index +); + +void imx_uart_console_drain(void); + +/** + * @brief Registers an IMX I2C bus driver. + * + * @param[in] bus_path The I2C bus driver device path, e.g. "/dev/i2c-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "i2c0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int i2c_bus_register_imx(const char *bus_path, const char *alias_or_path); + +/** + * @brief Registers an IMX ECSPI bus driver. + * + * @param[in] bus_path The ECSPI bus driver device path, e.g. "/dev/spi-0". + * @param[in] alias_or_path The FDT alias or path, e.g. "spi0". + * + * @retval 0 Successful operation. + * @retval -1 An error occurred. The errno is set to indicate the error. + */ +int spi_bus_register_imx(const char *bus_path, const char *alias_or_path); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_BSP_H */ diff --git a/bsps/arm/imx/include/bsp/irq.h b/bsps/arm/imx/include/bsp/irq.h new file mode 100644 index 0000000000..73d2e69b30 --- /dev/null +++ b/bsps/arm/imx/include/bsp/irq.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_IMX_IRQ_H +#define LIBBSP_ARM_IMX_IRQ_H + +#ifndef ASM + +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#include <bsp/arm-gic-irq.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 159 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_IMX_IRQ_H */ diff --git a/bsps/arm/imx/include/tm27.h b/bsps/arm/imx/include/tm27.h new file mode 100644 index 0000000000..c17c0107b4 --- /dev/null +++ b/bsps/arm/imx/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/arm-gic-tm27.h> + +#endif /* __tm27_h */ |