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-rw-r--r--bsps/arm/gdbarmsim/include/bsp/irq.h95
-rw-r--r--bsps/arm/gdbarmsim/include/bsp/swi.h110
2 files changed, 205 insertions, 0 deletions
diff --git a/bsps/arm/gdbarmsim/include/bsp/irq.h b/bsps/arm/gdbarmsim/include/bsp/irq.h
new file mode 100644
index 0000000000..3c86d22797
--- /dev/null
+++ b/bsps/arm/gdbarmsim/include/bsp/irq.h
@@ -0,0 +1,95 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Dummy interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_DUMMY_IRQ_H
+#define LIBBSP_ARM_DUMMY_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define DUMMY_IRQ_WDT 0
+#define DUMMY_IRQ_SOFTWARE 1
+#define DUMMY_IRQ_ARM_CORE_0 2
+#define DUMMY_IRQ_ARM_CORE_1 3
+#define DUMMY_IRQ_TIMER_0 4
+#define DUMMY_IRQ_TIMER_1 5
+#define DUMMY_IRQ_UART_0 6
+#define DUMMY_IRQ_UART_1 7
+#define DUMMY_IRQ_PWM 8
+#define DUMMY_IRQ_I2C_0 9
+#define DUMMY_IRQ_SPI_SSP_0 10
+#define DUMMY_IRQ_SSP_1 11
+#define DUMMY_IRQ_PLL 12
+#define DUMMY_IRQ_RTC 13
+#define DUMMY_IRQ_EINT_0 14
+#define DUMMY_IRQ_EINT_1 15
+#define DUMMY_IRQ_EINT_2 16
+#define DUMMY_IRQ_EINT_3 17
+#define DUMMY_IRQ_ADC_0 18
+#define DUMMY_IRQ_I2C_1 19
+#define DUMMY_IRQ_BOD 20
+#define DUMMY_IRQ_ETHERNET 21
+#define DUMMY_IRQ_USB 22
+#define DUMMY_IRQ_CAN 23
+#define DUMMY_IRQ_SD_MMC 24
+#define DUMMY_IRQ_DMA 25
+#define DUMMY_IRQ_TIMER_2 26
+#define DUMMY_IRQ_TIMER_3 27
+#define DUMMY_IRQ_UART_2 28
+#define DUMMY_IRQ_UART_3 29
+#define DUMMY_IRQ_I2C_2 30
+#define DUMMY_IRQ_I2S 31
+
+#define DUMMY_IRQ_PRIORITY_VALUE_MIN 0U
+#define DUMMY_IRQ_PRIORITY_VALUE_MAX 15U
+
+/**
+ * @brief Minimum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MIN DUMMY_IRQ_WDT
+
+/**
+ * @brief Maximum vector number.
+ */
+#define BSP_INTERRUPT_VECTOR_MAX DUMMY_IRQ_I2S
+
+void bsp_interrupt_dispatch(void);
+
+#if 0
+void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority);
+
+unsigned lpc24xx_irq_priority( rtems_vector_number vector);
+#endif
+
+/** @} */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_DUMMY_IRQ_H */
diff --git a/bsps/arm/gdbarmsim/include/bsp/swi.h b/bsps/arm/gdbarmsim/include/bsp/swi.h
new file mode 100644
index 0000000000..e9eb434a58
--- /dev/null
+++ b/bsps/arm/gdbarmsim/include/bsp/swi.h
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * @ingroup arm_gdbarmsim
+ *
+ * @brief Software interrupt definitions.
+ */
+
+/**
+ * @defgroup gdbarmsim_swi SWI Definitions
+ *
+ * @ingroup arm_gdbarmsim
+ *
+ * @brief Software interrupt definitions.
+ */
+
+/*
+ * Copied from libgloss 1 Oct 2009.
+ * Minor modifications to work with RTEMS.
+ */
+
+/* SWI numbers for RDP (Demon) monitor. */
+#define SWI_WriteC 0x0
+#define SWI_Write0 0x2
+#define SWI_ReadC 0x4
+#define SWI_CLI 0x5
+#define SWI_GetEnv 0x10
+#define SWI_Exit 0x11
+#define SWI_EnterOS 0x16
+
+#define SWI_GetErrno 0x60
+#define SWI_Clock 0x61
+#define SWI_Time 0x63
+#define SWI_Remove 0x64
+#define SWI_Rename 0x65
+#define SWI_Open 0x66
+
+#define SWI_Close 0x68
+#define SWI_Write 0x69
+#define SWI_Read 0x6a
+#define SWI_Seek 0x6b
+#define SWI_Flen 0x6c
+
+#define SWI_IsTTY 0x6e
+#define SWI_TmpNam 0x6f
+#define SWI_InstallHandler 0x70
+#define SWI_GenerateError 0x71
+
+
+/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */
+#define AngelSWI_ARM 0x123456
+#ifdef __thumb__
+#define AngelSWI 0xAB
+#else
+#define AngelSWI AngelSWI_ARM
+#endif
+/* For Thumb-2 code use the BKPT instruction instead of SWI. */
+#ifdef __thumb2__
+#define AngelSWIInsn "bkpt"
+#define AngelSWIAsm bkpt
+#else
+#define AngelSWIInsn "swi"
+#define AngelSWIAsm swi
+#endif
+
+/* The reason codes: */
+#define AngelSWI_Reason_Open 0x01
+#define AngelSWI_Reason_Close 0x02
+#define AngelSWI_Reason_WriteC 0x03
+#define AngelSWI_Reason_Write0 0x04
+#define AngelSWI_Reason_Write 0x05
+#define AngelSWI_Reason_Read 0x06
+#define AngelSWI_Reason_ReadC 0x07
+#define AngelSWI_Reason_IsTTY 0x09
+#define AngelSWI_Reason_Seek 0x0A
+#define AngelSWI_Reason_FLen 0x0C
+#define AngelSWI_Reason_TmpNam 0x0D
+#define AngelSWI_Reason_Remove 0x0E
+#define AngelSWI_Reason_Rename 0x0F
+#define AngelSWI_Reason_Clock 0x10
+#define AngelSWI_Reason_Time 0x11
+#define AngelSWI_Reason_System 0x12
+#define AngelSWI_Reason_Errno 0x13
+#define AngelSWI_Reason_GetCmdLine 0x15
+#define AngelSWI_Reason_HeapInfo 0x16
+#define AngelSWI_Reason_EnterSVC 0x17
+#define AngelSWI_Reason_ReportException 0x18
+#define ADP_Stopped_ApplicationExit ((2 << 16) + 38)
+#define ADP_Stopped_RunTimeError ((2 << 16) + 35)
+
+#if defined(ARM_RDI_MONITOR) && !defined(__ASSEMBLER__)
+
+static inline int
+do_AngelSWI (int reason, void * arg)
+{
+ int value;
+ __asm__ volatile ("mov r0, %1; mov r1, %2; " AngelSWIInsn " %a3; mov %0, r0"
+ : "=r" (value) /* Outputs */
+ : "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
+ /* Clobbers r0 and r1, and lr if in supervisor mode */);
+ /* Accordingly to page 13-77 of ARM DUI 0040D other registers
+ can also be clobbered. Some memory positions may also be
+ changed by a system call, so they should not be kept in
+ registers. Note: we are assuming the manual is right and
+ Angel is respecting the APCS. */
+ return value;
+}
+
+#endif