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-rw-r--r--bsps/arm/beagle/clock/clock.c2
-rw-r--r--bsps/arm/beagle/include/bsp.h42
-rw-r--r--bsps/arm/beagle/irq/irq.c2
-rw-r--r--bsps/arm/beagle/pwmss/pwmss.c10
-rw-r--r--bsps/arm/beagle/start/bspstart.c29
-rw-r--r--bsps/arm/beagle/start/bspstarthooks.c31
-rw-r--r--bsps/arm/beagle/start/bspstartmmu.c2
7 files changed, 74 insertions, 44 deletions
diff --git a/bsps/arm/beagle/clock/clock.c b/bsps/arm/beagle/clock/clock.c
index d42b051c98..a32dde86bf 100644
--- a/bsps/arm/beagle/clock/clock.c
+++ b/bsps/arm/beagle/clock/clock.c
@@ -290,7 +290,7 @@ static void beagle_clock_handler_install(rtems_interrupt_handler isr)
clock_isr = isr;
}
-#define Clock_driver_support_at_tick() beagle_clock_at_tick()
+#define Clock_driver_support_at_tick(arg) beagle_clock_at_tick()
#define Clock_driver_support_initialize_hardware() beagle_clock_initialize()
#define Clock_driver_support_install_isr(isr) \
beagle_clock_handler_install(isr)
diff --git a/bsps/arm/beagle/include/bsp.h b/bsps/arm/beagle/include/bsp.h
index 80a9cc291d..a5c9bc0459 100644
--- a/bsps/arm/beagle/include/bsp.h
+++ b/bsps/arm/beagle/include/bsp.h
@@ -116,19 +116,19 @@ read16(uint32_t address)
/* Data synchronization barrier */
static inline void dsb(void)
{
- asm volatile("dsb" : : : "memory");
+ __asm__ volatile("dsb" : : : "memory");
}
/* Instruction synchronization barrier */
static inline void isb(void)
{
- asm volatile("isb" : : : "memory");
+ __asm__ volatile("isb" : : : "memory");
}
/* flush data cache */
static inline void flush_data_cache(void)
{
- asm volatile(
+ __asm__ volatile(
"mov r0, #0\n"
"mcr p15, #0, r0, c7, c10, #4\n"
: /* No outputs */
@@ -229,7 +229,7 @@ static inline uint32_t read_sctlr(void)
{
uint32_t ctl;
- asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
+ __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
: [ctl] "=r" (ctl));
return ctl;
}
@@ -237,7 +237,7 @@ static inline uint32_t read_sctlr(void)
/* Write System Control Register */
static inline void write_sctlr(uint32_t ctl)
{
- asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
+ __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
: : [ctl] "r" (ctl));
isb();
}
@@ -247,7 +247,7 @@ static inline uint32_t read_actlr(void)
{
uint32_t ctl;
- asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
+ __asm__ volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
: [ctl] "=r" (ctl));
return ctl;
}
@@ -255,7 +255,7 @@ static inline uint32_t read_actlr(void)
/* Write Auxiliary Control Register */
static inline void write_actlr(uint32_t ctl)
{
- asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
+ __asm__ volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
: : [ctl] "r" (ctl));
isb();
}
@@ -263,7 +263,7 @@ static inline void write_actlr(uint32_t ctl)
/* Write Translation Table Base Control Register */
static inline void write_ttbcr(uint32_t bcr)
{
- asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
+ __asm__ volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
: : [bcr] "r" (bcr));
isb();
@@ -274,7 +274,7 @@ static inline uint32_t read_dacr(void)
{
uint32_t dacr;
- asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
+ __asm__ volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
: [dacr] "=r" (dacr));
return dacr;
@@ -284,7 +284,7 @@ static inline uint32_t read_dacr(void)
/* Write Domain Access Control Register */
static inline void write_dacr(uint32_t dacr)
{
- asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
+ __asm__ volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
: : [dacr] "r" (dacr));
isb();
@@ -295,16 +295,16 @@ static inline void refresh_tlb(void)
dsb();
/* Invalidate entire unified TLB */
- asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
+ __asm__ volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
: : [zero] "r" (0));
/* Invalidate all instruction caches to PoU.
* Also flushes branch target cache. */
- asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
+ __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 0"
: : [zero] "r" (0));
/* Invalidate entire branch predictor array */
- asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
+ __asm__ volatile("mcr p15, 0, %[zero], c7, c5, 6"
: : [zero] "r" (0)); /* flush BTB */
dsb();
@@ -316,7 +316,7 @@ static inline uint32_t read_ttbr0(void)
{
uint32_t bar;
- asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+ __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
: [bar] "=r" (bar));
return bar & ARM_TTBR_ADDR_MASK;
@@ -328,7 +328,7 @@ static inline uint32_t read_ttbr0_unmasked(void)
{
uint32_t bar;
- asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
+ __asm__ volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
: [bar] "=r" (bar));
return bar;
@@ -344,22 +344,12 @@ static inline void write_ttbr0(uint32_t bar)
base address of the l1 page table. We therefore add the
flags here and remove them in the read_ttbr0 */
uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
- asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
+ __asm__ volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
: : [bar] "r" (v));
refresh_tlb();
}
-/* Behaviour on fatal error; default: test-friendly.
- * set breakpoint to bsp_fatal_extension.
- */
-/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
-/*#define BSP_PRESS_KEY_FOR_RESET 1 */
-#define BSP_PRINT_EXCEPTION_CONTEXT 1
- /* human-readable exception info */
-#define BSP_RESET_BOARD_AT_EXIT 1
- /* causes qemu to exit, signaling end of test */
-
/**
* @brief Beagleboard specific set up of the MMU.
*
diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 29a4e391e8..0ae82aa95e 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -1,7 +1,7 @@
/**
* @file
*
- * @ingroup bsp_interrupt
+ * @ingroup RTEMSImplClassicIntr
* @ingroup arm_beagle
*
* @brief Interrupt support.
diff --git a/bsps/arm/beagle/pwmss/pwmss.c b/bsps/arm/beagle/pwmss/pwmss.c
index 0fde3db5a9..f3aaf8fc3f 100644
--- a/bsps/arm/beagle/pwmss/pwmss.c
+++ b/bsps/arm/beagle/pwmss/pwmss.c
@@ -38,7 +38,7 @@
#include <bsp.h>
#include <bsp/pwmss.h>
#include <bsp/beagleboneblack.h>
-
+#include <rtems/error.h>
/**
* @brief This function configures the L3 and L4_PER system clocks.
@@ -56,7 +56,10 @@
*/
rtems_status_code pwmss_module_clk_config(BBB_PWMSS pwmss_id)
{
- uint32_t clkctrl;
+ /* we initialize clkctrl here to nonsentical value as this is going
+ * to be assigned later anyway. Here assigning 0 is just to kill
+ * warning emitted by the C compiler. */
+ uint32_t clkctrl = 0;
/* calculate the address of the clock control register for the PWMSS
* module we are configuring */
@@ -66,6 +69,9 @@ rtems_status_code pwmss_module_clk_config(BBB_PWMSS pwmss_id)
clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL;
} else if(pwmss_id == BBB_PWMSS2) {
clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL;
+ } else {
+ /* wrong clock configuration, let's panic here. */
+ rtems_error(RTEMS_ERROR_PANIC, "beagle: unsupported pwmss module clock configuration value!");
}
/* when the module is functional the IDLEST bits (16 -17) of the
diff --git a/bsps/arm/beagle/start/bspstart.c b/bsps/arm/beagle/start/bspstart.c
index 8ad7a8cc36..9dba40daee 100644
--- a/bsps/arm/beagle/start/bspstart.c
+++ b/bsps/arm/beagle/start/bspstart.c
@@ -1,9 +1,28 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
@@ -102,7 +121,7 @@ int beagle_get_node_unit(phandle_t node)
if (strstr(prop_val, name) != NULL) {
for (i = strlen(prop) - 1; i >= 0; i--) {
- if (!isdigit(prop[i]))
+ if (!isdigit((int)prop[i]))
break;
}
diff --git a/bsps/arm/beagle/start/bspstarthooks.c b/bsps/arm/beagle/start/bspstarthooks.c
index bdbdac29e6..69d5256f52 100644
--- a/bsps/arm/beagle/start/bspstarthooks.c
+++ b/bsps/arm/beagle/start/bspstarthooks.c
@@ -1,19 +1,34 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
#include <bsp/start.h>
#include <bsp/arm-cp15-start.h>
-BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
-{
-}
-
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
{
bsp_start_copy_sections();
diff --git a/bsps/arm/beagle/start/bspstartmmu.c b/bsps/arm/beagle/start/bspstartmmu.c
index 478eb8c26b..6a7c9366ca 100644
--- a/bsps/arm/beagle/start/bspstartmmu.c
+++ b/bsps/arm/beagle/start/bspstartmmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Copyright (c) 2014 Chris Johns. All rights reserved.
*
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 17:01:22 +0000