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-rw-r--r--bsps/arm/beagle/include/bsp/bbb-gpio.h45
-rw-r--r--bsps/arm/beagle/include/bsp/bbb-pwm.h178
-rw-r--r--bsps/arm/beagle/include/bsp/beagleboneblack.h72
-rw-r--r--bsps/arm/beagle/include/bsp/i2c.h211
-rw-r--r--bsps/arm/beagle/include/bsp/irq.h23
5 files changed, 529 insertions, 0 deletions
diff --git a/bsps/arm/beagle/include/bsp/bbb-gpio.h b/bsps/arm/beagle/include/bsp/bbb-gpio.h
new file mode 100644
index 0000000000..ceb12a4dec
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/bbb-gpio.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief BeagleBone Black GPIO functions.
+ */
+#define BBB_DIGITAL_IN 2
+#define BBB_DIGITAL_OUT 1
+
+/**
+ * @brief BeagleBone Black GPIO pad configuration.
+ */
+#define BBB_PUDEN (1 << 3)
+#define BBB_PUDDIS ~BBB_PUDEN
+#define BBB_PU_EN (1 << 4)
+#define BBB_PD_EN ~BBB_PU_EN
+#define BBB_MUXMODE(X) (X & 0x7)
+#define BBB_RXACTIVE (1 << 5)
+#define BBB_SLEWCTRL (1 << 6)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
diff --git a/bsps/arm/beagle/include/bsp/bbb-pwm.h b/bsps/arm/beagle/include/bsp/bbb-pwm.h
new file mode 100644
index 0000000000..cf5d6fe552
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/bbb-pwm.h
@@ -0,0 +1,178 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black PWM support definitions.
+ */
+
+/**
+ * Copyright (c) 2016 Punit Vara <punitvara@gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/** Some constants are taken from
+ * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
+#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief BeagleBone Black PWM Macros.
+ */
+#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))
+#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))
+
+/**
+ * @brief The set of possible PWM subsystem module
+ *
+ * Enumerated type to define various instance of pwm module.
+ */
+typedef enum{
+ BBB_PWMSS0 = 0,
+ BBB_PWMSS1,
+ BBB_PWMSS2,
+ BBB_PWMSS_COUNT
+}BBB_PWMSS;
+
+typedef enum{
+ BBB_P8_13_2B = 3,
+ BBB_P8_19_2A,
+ BBB_P8_45_2A,
+ BBB_P8_46_2B,
+ BBB_P8_34_1B,
+ BBB_P8_36_1A,
+ BBB_P9_14_1A,
+ BBB_P9_16_1B,
+ BBB_P9_21_0B,
+ BBB_P9_22_0A,
+ BBB_P9_29_0B,
+ BBB_P9_31_0A
+}bbb_pwm_pin_t;
+
+#define BBB_P8_13_MUX_PWM 4
+#define BBB_P8_19_MUX_PWM 4
+#define BBB_P8_45_MUX_PWM 3
+#define BBB_P8_46_MUX_PWM 3
+#define BBB_P8_34_MUX_PWM 2
+#define BBB_P8_36_MUX_PWM 2
+#define BBB_P9_14_MUX_PWM 6
+#define BBB_P9_16_MUX_PWM 6
+#define BBB_P9_21_MUX_PWM 3
+#define BBB_P9_22_MUX_PWM 3
+#define BBB_P9_29_MUX_PWM 1
+#define BBB_P9_31_MUX_PWM 1
+#define BBB_PWM_FREQ_THRESHOLD 0.5f
+
+/**
+ * @brief BeagleBone Black PWM API.
+ */
+
+/**
+ * @brief This function intilizes clock for pwm sub system.
+ *
+ * @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if not successful
+ *
+ **/
+bool beagle_pwm_init(BBB_PWMSS pwmss_id);
+
+/* PWMSS setting
+ * set pulse argument of epwm module
+ *
+ * @param pwm_id : EPWMSS number , 0~2
+ * @param pwm_freq : frequency to be generated
+ * @param dutyA : Duty Cycle(in percentage) in PWM channel A
+ * @param dutyB : Duty Cycle(in percentage) in PWM channel B
+ *
+ * @return : 1 for success
+ * @return : 0 for failed
+ *
+ * @example : beagle_pwm_configure(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
+ * // duty cycle is 50% for ePWM0A , 25% for ePWM0B
+ *
+ * @Note :
+ * find an number nearst 65535 for TBPRD , to improve duty precision,
+ *
+ * Using big TBPRD can increase the range of CMPA and CMPB ,
+ * and it means we can get better precision on duty cycle.
+ *
+ * EX : 20.25% duty cycle
+ * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
+ * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250)
+ * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500)
+ *
+ * Divisor = CLKDIV * HSPCLKDIV
+ * 1 TBPRD : 10 ns (default)
+ * 65535 TBPRD : 655350 ns
+ * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cycle
+ *
+ * accrooding to that , we must find a Divisor value , let X nearest 65535 .
+ * so , Divisor must Nearest Cycle/655350
+ */
+int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b);
+
+/**
+ * @brief This API enables the particular PWM module.
+ *
+ * @param pwmid It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_pwm_enable(BBB_PWMSS pwmid);
+
+/**
+ * @brief This API disables the particular PWM module.
+ *
+ * @param pwmid It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_pwm_disable(BBB_PWMSS pwmid);
+
+/**
+ * @brief This function enables pinmuxing for PWM module.
+ *
+ * @param pin_no It is individual pin at which freuqency need to be generated.
+ * It should be according to pwm sub system.
+ *
+ * @param pwm_id It is the instance number of EPWM of pwmsubsystem.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id);
+
+/**
+ * @brief This function determines whether PWMSS-wide clocks enabled or not.
+ *
+ * @param pwmss_id It is the instance number of PWMSS which clocks need to be
+ * checked.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_pwmss_is_running(unsigned int pwmss_id);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_BBB_PWM_H */
diff --git a/bsps/arm/beagle/include/bsp/beagleboneblack.h b/bsps/arm/beagle/include/bsp/beagleboneblack.h
new file mode 100644
index 0000000000..c62f4aa92d
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/beagleboneblack.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+
+/* In general GPIOs of BeagleBone Black/White can be addressed
+ * using two 46-pin dual-row expansion connectors P9 and P8,
+ * which are also known as Expansion A and Expansion B Connectors,
+ * respectively.
+ *
+ * Each Expansion Connector consists of 23 pins. So 2x23 pins would
+ * be available. It has 4 GPIO Banks each consists of 32 pins each.
+ * Toatal number of pins are 128 (32x4).
+ *
+ * So for mapping between generalized pin name and the unique pin
+ * numbers in this header file Macros are declared.
+ */
+
+/* USER LEDs of BeagleBone Black */
+#define BBB_LED_USR0 53 /* USR LED0 */
+#define BBB_LED_USR1 54 /* USR LED1 */
+#define BBB_LED_USR2 55 /* USR LED2 */
+#define BBB_LED_USR3 56 /* USR LED3 */
+
+/* Header P8 of BeagleBone Black */
+#define BBB_P8_7 66 /* GPIO2_2 */
+#define BBB_P8_8 67 /* GPIO2_3 */
+#define BBB_P8_9 69 /* GPIO2_5 */
+#define BBB_P8_10 68 /* GPIO2_4 */
+#define BBB_P8_11 45 /* GPIO1_13 */
+#define BBB_P8_12 44 /* GPIO1_12 */
+#define BBB_P8_13 23 /* GPIO0_23 */
+#define BBB_P8_14 26 /* GPIO0_26 */
+#define BBB_P8_15 47 /* GPIO1_15 */
+#define BBB_P8_16 46 /* GPIO1_14 */
+#define BBB_P8_17 27 /* GPIO0_27 */
+#define BBB_P8_18 65 /* GPIO2_1 */
+#define BBB_P8_19 22 /* GPIO0_22 */
+#define BBB_P8_26 61 /* GPIO1_29 */
+
+/* Header P9 of BeagleBone Black */
+#define BBB_P9_11 30 /* GPIO0_30 */
+#define BBB_P9_12 60 /* GPIO1_28 */
+#define BBB_P9_13 31 /* GPIO0_31 */
+#define BBB_P9_14 50 /* GPIO1_18 */
+#define BBB_P9_15 48 /* GPIO1_16 */
+#define BBB_P9_16 51 /* GPIO1_19 */
+#define BBB_P9_17 5 /* GPIO0_5 */
+#define BBB_P9_18 4 /* GPIO0_4 */
+#define BBB_P9_23 49 /* GPIO1_17 */
+#define BBB_P9_24 15 /* GPIO0_15 */
+#define BBB_P9_26 14 /* GPIO1_14 */
+#define BBB_P9_27 115/* GPIO3_19 */
+#define BBB_P9_30 112/* GPIO3_16 */
+#define BBB_P9_41 20 /* GPIO0_20 */
+#define BBB_P9_42 7 /* GPIO0_7 */
+
+#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */ \ No newline at end of file
diff --git a/bsps/arm/beagle/include/bsp/i2c.h b/bsps/arm/beagle/include/bsp/i2c.h
new file mode 100644
index 0000000000..3ada3c4b0d
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/i2c.h
@@ -0,0 +1,211 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief I2C support API.
+ */
+
+/*
+ * Copyright (c) 2012 Claas Ziemke. All rights reserved.
+ *
+ * Claas Ziemke
+ * Kernerstrasse 11
+ * 70182 Stuttgart
+ * Germany
+ * <claas.ziemke@gmx.net>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_I2C_H
+#define LIBBSP_ARM_BEAGLE_I2C_H
+
+#include <rtems.h>
+#include <dev/i2c/i2c.h>
+#include <bsp.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define BBB_I2C_CON_EN (1 << 15) /* I2C module enable */
+#define BBB_I2C_CON_BE (1 << 14) /* Big endian mode */
+#define BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
+ /* (master mode only) */
+#define BBB_I2C_CON_XA (1 << 8) /* Expand address */
+#define BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+#define BBB_I2C_CON_CLR 0x0 /* Clear configuration register */
+/* I2C Status Register (I2C_STAT): */
+
+#define BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */
+#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define BBB_I2C_STAT_GC (1 << 5)
+#define BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define BBB_I2C_IE_GC_IE (1 << 5)
+#define BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C SYSC Register (I2C_SYSC): */
+#define BBB_I2C_SYSC_SRST (1 << 1)
+
+#define BBB_I2C_TIMEOUT 1000
+
+#define BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */
+
+#define BBB_CONFIG_SYS_I2C_SPEED 100000
+#define BBB_CONFIG_SYS_I2C_SLAVE 1
+#define BBB_I2C_ALL_FLAGS 0x7FFF
+#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF
+
+#define BBB_I2C_SYSCLK 48000000
+#define BBB_I2C_INTERNAL_CLK 12000000
+#define BBB_I2C_SPEED_CLK 100000
+
+#define BBB_I2C_IRQ_ERROR \
+ ( AM335X_I2C_IRQSTATUS_NACK \
+ | AM335X_I2C_IRQSTATUS_ROVR \
+ | AM335X_I2C_IRQSTATUS_AL \
+ | AM335X_I2C_IRQSTATUS_ARDY \
+ | AM335X_I2C_IRQSTATUS_RRDY \
+ | AM335X_I2C_IRQSTATUS_XRDY \
+ | AM335X_I2C_IRQSTATUS_XUDF )
+
+#define BBB_I2C_IRQ_USED \
+ ( AM335X_I2C_IRQSTATUS_ARDY \
+ | AM335X_I2C_IRQSTATUS_XRDY )
+
+#define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
+#define BBB_I2C_1_BUS_PATH "/dev/i2c-1"
+#define BBB_I2C_2_BUS_PATH "/dev/i2c-2"
+
+#define BBB_I2C0_IRQ 70
+#define BBB_I2C1_IRQ 71
+#define BBB_I2C2_IRQ 30
+
+#define BBB_MODE2 2
+#define BBB_MODE3 3
+
+typedef enum {
+ I2C0,
+ I2C1,
+ I2C2,
+ I2C_COUNT
+} bbb_i2c_id_t;
+
+typedef struct i2c_regs {
+ uint32_t BBB_I2C_REVNB_LO;
+ uint32_t BBB_I2C_REVNB_HI;
+ uint32_t dummy1[ 2 ];
+ uint32_t BBB_I2C_SYSC;
+ uint32_t dummy2[ 4 ];
+ uint32_t BBB_I2C_IRQSTATUS_RAW;
+ uint32_t BBB_I2C_IRQSTATUS;
+ uint32_t BBB_I2C_IRQENABLE_SET;
+ uint32_t BBB_I2C_IRQENABLE_CLR;
+ uint32_t BBB_I2C_WE;
+ uint32_t BBB_I2C_DMARXENABLE_SET;
+ uint32_t BBB_I2C_DMATXENABLE_SET;
+ uint32_t BBB_I2C_DMARXENABLE_CLR;
+ uint32_t BBB_I2C_DMATXENABLE_CLR;
+ uint32_t BBB_I2C_DMARXWAKE_EN;
+ uint32_t BBB_I2C_DMATXWAKE_EN;
+ uint32_t dummy3[ 16 ];
+ uint32_t BBB_I2C_SYSS;
+ uint32_t BBB_I2C_BUF;
+ uint32_t BBB_I2C_CNT;
+ uint32_t BBB_I2C_DATA;
+ uint32_t dummy4;
+ uint32_t BBB_I2C_CON;
+ uint32_t BBB_I2C_OA;
+ uint32_t BBB_I2C_SA;
+ uint32_t BBB_I2C_PSC;
+ uint32_t BBB_I2C_SCLL;
+ uint32_t BBB_I2C_SCLH;
+ uint32_t BBB_I2C_SYSTEST;
+ uint32_t BBB_I2C_BUFSTAT;
+ uint32_t BBB_I2C_OA1;
+ uint32_t BBB_I2C_OA2;
+ uint32_t BBB_I2C_OA3;
+ uint32_t BBB_I2C_ACTOA;
+ uint32_t BBB_I2C_SBLOCK;
+} bbb_i2c_regs;
+
+typedef struct bbb_i2c_bus {
+ i2c_bus base;
+ volatile bbb_i2c_regs *regs;
+ i2c_msg *msgs;
+ uint32_t msg_todo;
+ uint32_t current_msg_todo;
+ uint8_t *current_msg_byte;
+ uint32_t current_todo;
+ bool read;
+ bool hold;
+ rtems_id task_id;
+ rtems_vector_number irq;
+ uint32_t input_clock;
+ uint32_t already_transferred;
+} bbb_i2c_bus;
+
+int am335x_i2c_bus_register(
+ const char *bus_path,
+ uintptr_t register_base,
+ uint32_t input_clock,
+ rtems_vector_number irq
+);
+
+static inline int bbb_register_i2c_0( void )
+{
+ return am335x_i2c_bus_register(
+ BBB_I2C_0_BUS_PATH,
+ AM335X_I2C0_BASE,
+ I2C_BUS_CLOCK_DEFAULT,
+ BBB_I2C0_IRQ
+ );
+}
+
+static inline int bbb_register_i2c_1( void )
+{
+ return am335x_i2c_bus_register(
+ BBB_I2C_1_BUS_PATH,
+ AM335X_I2C1_BASE,
+ I2C_BUS_CLOCK_DEFAULT,
+ BBB_I2C1_IRQ
+ );
+}
+
+static inline int bbb_register_i2c_2( void )
+{
+ return am335x_i2c_bus_register(
+ BBB_I2C_2_BUS_PATH,
+ AM335X_I2C2_BASE,
+ I2C_BUS_CLOCK_DEFAULT,
+ BBB_I2C2_IRQ
+ );
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_I2C_H */
diff --git a/bsps/arm/beagle/include/bsp/irq.h b/bsps/arm/beagle/include/bsp/irq.h
new file mode 100644
index 0000000000..4cbf3a271f
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/irq.h
@@ -0,0 +1,23 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Basic BSP IRQ info.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_IRQ_H
+#define LIBBSP_ARM_BEAGLE_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 127
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 12:32:29 +0000