diff options
25 files changed, 1303 insertions, 562 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index 7f281f20c9..2f2f17a259 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,29 @@ +2000-10-24 Alan Cudmore <alanc@linuxstart.com> and + Joel Sherrill <joel@OARcorp.com> + + * This is a major reworking of the mips64orion port to use + gcc predefines as much as possible and a big push to multilib + the mips port. The mips64orion port was copied/renamed to mips + to be more like other GNU tools. Alan did most of the technical + work of determining how to map old macro names used by the mips64orion + port to standard compiler macro definitions. Joel did the merge + with CVS magic to keep individual file history and did the BSP + modifications. Details follow: + * Makefile.am: idtmon.h in mips64orion port not present. + * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. + * cpu.c: Comments added. + * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. + First attempt at exception/interrupt processing for ISA level 1 + and minus any use of IDT/MON added. + * idtcpu.h: Conditionals changed to use gcc predefines. + * iregdef.h: Ditto. + * cpu_asm.h: No real change. Merger required commit. + * rtems/Makefile.am: Ditto. + * rtems/score/Makefile.am: Ditto. + * rtems/score/cpu.h: Change MIPS64ORION to MIPS. + * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert + from using RTEMS_CPU_MODEL to gcc predefines to figre things out. + 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Include compile.am. diff --git a/c/src/exec/score/cpu/mips/Makefile.am b/c/src/exec/score/cpu/mips/Makefile.am index 1d4a588d2e..7d4724c4d5 100644 --- a/c/src/exec/score/cpu/mips/Makefile.am +++ b/c/src/exec/score/cpu/mips/Makefile.am @@ -10,7 +10,7 @@ SUBDIRS = rtems C_FILES = cpu.c C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) -H_FILES = asm.h cpu_asm.h idtcpu.h idtmon.h iregdef.h +H_FILES = asm.h cpu_asm.h idtcpu.h iregdef.h S_FILES = cpu_asm.S S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) @@ -44,7 +44,7 @@ all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ .PRECIOUS: $(REL) -EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h idtmon.h iregdef.h \ +EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h iregdef.h \ rtems.c include $(top_srcdir)/../../../../../../automake/subdirs.am diff --git a/c/src/exec/score/cpu/mips/asm.h b/c/src/exec/score/cpu/mips/asm.h index edabbe8fcc..060be295bf 100644 --- a/c/src/exec/score/cpu/mips/asm.h +++ b/c/src/exec/score/cpu/mips/asm.h @@ -24,8 +24,8 @@ */ /* @(#)asm.h 03/15/96 1.1 */ -#ifndef __MIPS64ORION_ASM_h -#define __MIPS64ORION_ASM_h +#ifndef __NO_CPU_ASM_h +#define __NO_CPU_ASM_h /* * Indicate we are in an assembly file and get the basic CPU definitions. @@ -96,7 +96,27 @@ #define PUBLIC(sym) .globl SYM (sym) #define EXTERN(sym) .globl SYM (sym) +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif XDS + #endif /* end of include file */ - diff --git a/c/src/exec/score/cpu/mips/configure.in b/c/src/exec/score/cpu/mips/configure.in index 5c3d7b182a..d5ef3ed5ad 100644 --- a/c/src/exec/score/cpu/mips/configure.in +++ b/c/src/exec/score/cpu/mips/configure.in @@ -9,10 +9,10 @@ AC_CONFIG_AUX_DIR(../../../../../..) RTEMS_CANONICAL_TARGET_CPU -AM_INIT_AUTOMAKE(rtems-c-src-exec-score-cpu-mips64orion,$RTEMS_VERSION,no) +AM_INIT_AUTOMAKE(rtems-c-src-exec-score-cpu-mips,$RTEMS_VERSION,no) AM_MAINTAINER_MODE -RTEMS_ENV_RTEMSCPU +RTEMS_ENV_RTEMSBSP RTEMS_CHECK_CPU RTEMS_CANONICAL_HOST @@ -24,6 +24,9 @@ RTEMS_CANONICALIZE_TOOLS RTEMS_CHECK_NEWLIB +# Check if there is custom/*.cfg for this BSP +RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP) + # Explicitly list all Makefiles here AC_OUTPUT( Makefile diff --git a/c/src/exec/score/cpu/mips/cpu.c b/c/src/exec/score/cpu/mips/cpu.c index 1d56652622..db9ae911b4 100644 --- a/c/src/exec/score/cpu/mips/cpu.c +++ b/c/src/exec/score/cpu/mips/cpu.c @@ -1,22 +1,24 @@ /* * Mips CPU Dependent Source * - * Author: Craig Lebakken <craigl@transition.com> + * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and + * Joel Sherrill <joel@OARcorp.com>. * - * COPYRIGHT (c) 1996 by Transition Networks Inc. + * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> + * COPYRIGHT (c) 1996 by Transition Networks Inc. * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the + * suitability of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -124,7 +126,7 @@ void _CPU_ISR_install_raw_handler( * This is where we install the interrupt handler into the "raw" interrupt * table used by the CPU to dispatch interrupt handlers. */ - +/* Q: This will become necessary for Non IDT/Sim use...*/ #if 0 /* not necessary */ /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ add_ext_int_func( vector, new_handler ); diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S index 9770a5f2f9..c04c1e7d30 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ b/c/src/exec/score/cpu/mips/cpu_asm.S @@ -19,7 +19,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -45,16 +45,8 @@ name:; \ #define ENDFRAME(name) \ .end name - #define EXCP_STACK_SIZE (NREGS*R_SZ) - -#if __ghs__ -#define sd sw -#define ld lw -#define dmtc0 mtc0 -#define dsll sll -#define dmfc0 mfc0 -#endif +#define ISR_VEC_SIZE 4 #if 1 /* 32 bit unsigned32 types */ #define sint sw @@ -141,6 +133,8 @@ unsigned32 _CPU_ISR_Get_level( void ) */ } #endif + +#if __mips == 3 /* return the current exception level for the 4650 */ FRAME(_CPU_ISR_Get_level,sp,0,ra) mfc0 v0,C0_SR @@ -163,8 +157,8 @@ _CPU_ISR_Set_1: nop bnez a0,_CPU_ISR_Set_2 nop - nop - mfc0 t0,C0_SR + nop + mfc0 t0, C0_SR nop li t1,~SR_EXL and t0,t1 @@ -182,7 +176,7 @@ _CPU_ISR_Set_2: nop mtc0 t0,C0_SR /* first disable ie bit (recommended) */ nop - ori t0,SR_EXL|SR_IE /* enable exception level */ + ori t0, SR_EXL|SR_IE /* enable exception level */ nop mtc0 t0,C0_SR nop @@ -191,6 +185,32 @@ _CPU_ISR_Set_exit: nop ENDFRAME(_CPU_ISR_Set_level) +#elif __mips == 1 + +/* MIPS ISA 1 ( R3000 ) */ +/* These routines might not be needed for the R3000 */ +/* Q:Who calls _CPU_ISR_Get/Set_level? */ +FRAME(_CPU_ISR_Get_level,sp,0,ra) + mfc0 v0,C0_SR + nop + andi v0, SR_IEC + j ra +ENDFRAME(_CPU_ISR_Get_level) + +FRAME(_CPU_ISR_Set_level,sp,0,ra) + nop + mfc0 t0,C0_SR + andi a0, SR_IEC + or t0, a0 + mtc0 t0,C0_SR + nop + j ra +ENDFRAME(_CPU_ISR_Set_level) + +#else + #error "__mips is set to 1 or 3" +#endif + /* * _CPU_Context_save_fp_context * @@ -323,6 +343,8 @@ ENDFRAME(_CPU_Context_restore_fp) * { * } */ +#if __mips == 3 +/* MIPS ISA Level 3 ( R4xxx ) */ FRAME(_CPU_Context_switch,sp,0,ra) @@ -337,7 +359,6 @@ FRAME(_CPU_Context_switch,sp,0,ra) sd ra,RA_OFFSET*8(a0) /* save current context */ sd sp,SP_OFFSET*8(a0) sd fp,FP_OFFSET*8(a0) - sd s0,S0_OFFSET*8(a0) sd s1,S1_OFFSET*8(a0) sd s2,S2_OFFSET*8(a0) sd s3,S3_OFFSET*8(a0) @@ -375,6 +396,62 @@ _CPU_Context_1: nop ENDFRAME(_CPU_Context_switch) +#elif __mips == 1 +/* MIPS ISA Level 1 ( R3000 ) */ + +FRAME(_CPU_Context_switch,sp,0,ra) + + mfc0 t0,C0_SR + li t1,~SR_IEC + sw t0,C0_SR_OFFSET*4(a0) /* save status register */ + and t0,t1 + mtc0 t0,C0_SR /* first disable ie bit (recommended) */ + + sw ra,RA_OFFSET*4(a0) /* save current context */ + sw sp,SP_OFFSET*4(a0) + sw fp,FP_OFFSET*4(a0) + sw s0,S0_OFFSET*4(a0) + sw s1,S1_OFFSET*4(a0) + sw s2,S2_OFFSET*4(a0) + sw s3,S3_OFFSET*4(a0) + sw s4,S4_OFFSET*4(a0) + sw s5,S5_OFFSET*4(a0) + sw s6,S6_OFFSET*4(a0) + sw s7,S7_OFFSET*4(a0) + + mfc0 t0,C0_EPC + sw t0,C0_EPC_OFFSET*4(a0) + +_CPU_Context_switch_restore: + lw s0,S0_OFFSET*4(a1) /* restore context */ + lw s1,S1_OFFSET*4(a1) + lw s2,S2_OFFSET*4(a1) + lw s3,S3_OFFSET*4(a1) + lw s4,S4_OFFSET*4(a1) + lw s5,S5_OFFSET*4(a1) + lw s6,S6_OFFSET*4(a1) + lw s7,S7_OFFSET*4(a1) + lw fp,FP_OFFSET*4(a1) + lw sp,SP_OFFSET*4(a1) + lw ra,RA_OFFSET*4(a1) + lw t0,C0_EPC_OFFSET*4(a1) + mtc0 t0,C0_EPC + lw t1, C0_SR_OFFSET*4(a1) + mtc0 t1,C0_SR + + /* Q:Changes needed to SR_IEC bit in SR/_CPU_Context_switch_restore? */ + +_CPU_Context_1: + j ra + nop +ENDFRAME(_CPU_Context_switch) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + /* * _CPU_Context_restore * @@ -392,12 +469,28 @@ void _CPU_Context_restore( } #endif +#if __mips == 3 + FRAME(_CPU_Context_restore,sp,0,ra) dadd a1,a0,zero j _CPU_Context_switch_restore nop ENDFRAME(_CPU_Context_restore) +#elif __mips == 1 + +FRAME(_CPU_Context_restore,sp,0,ra) + add a1,a0,zero + j _CPU_Ccontext_switch_restore + nop +ENDFRAME(_CPU_Context_restore) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + EXTERN(_ISR_Nest_level, SZ_INT) EXTERN(_Thread_Dispatch_disable_level,SZ_INT) EXTERN(_Context_Switch_necessary,SZ_INT) @@ -438,6 +531,9 @@ void _ISR_Handler() * */ #endif + +#if __mips == 3 +/* ----------------------------------------------------------------------------- */ FRAME(_ISR_Handler,sp,0,ra) .set noreorder #if USE_IDTKIT @@ -487,8 +583,9 @@ FRAME(_ISR_Handler,sp,0,ra) /* determine if an interrupt generated this exception */ mfc0 k0,C0_CAUSE and k1,k0,CAUSE_EXCMASK - bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */ - mfc0 k1,C0_SR + bnez k1,_ISR_Handler_prom_exit /* not an external interrup +t, pass exception to Monitor */ + mfc0 k1,C0_SR and k0,k1 and k0,CAUSE_IPMASK beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ @@ -661,11 +758,11 @@ _ISR_Handler_quick_exit: nop _ISR_Handler_prom_exit: -#ifdef CPU_R3000 +#if __mips == 1 la k0, (R_VEC+((48)*8)) #endif -#ifdef CPU_R4000 +#if __mips == 3 la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ #endif j k0 @@ -675,6 +772,268 @@ _ISR_Handler_prom_exit: ENDFRAME(_ISR_Handler) +/* ---------------------------------------------------------------------- */ +#elif __mips == 1 +/* MIPS ISA Level 1 */ + +FRAME(_ISR_Handler,sp,0,ra) +.set noreorder + + /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ + + addiu sp,sp,-EXCP_STACK_SIZE /* wastes alot of stack space for context?? */ + + sw ra, R_RA*R_SZ(sp) /* store ra on the stack */ + sw v0, R_V0*R_SZ(sp) + sw v1, R_V1*R_SZ(sp) + sw a0, R_A0*R_SZ(sp) + sw a1, R_A1*R_SZ(sp) + sw a2, R_A2*R_SZ(sp) + sw a3, R_A3*R_SZ(sp) + sw t0, R_T0*R_SZ(sp) + sw t1, R_T1*R_SZ(sp) + sw t2, R_T2*R_SZ(sp) + sw t3, R_T3*R_SZ(sp) + sw t4, R_T4*R_SZ(sp) + sw t5, R_T5*R_SZ(sp) + sw t6, R_T6*R_SZ(sp) + sw t7, R_T7*R_SZ(sp) + mflo k0 + sw t8, R_T8*R_SZ(sp) + sw k0, R_MDLO*R_SZ(sp) + sw t9, R_T9*R_SZ(sp) + mfhi k0 + sw gp, R_GP*R_SZ(sp) + sw fp, R_FP*R_SZ(sp) + sw k0, R_MDHI*R_SZ(sp) + .set noat + sw AT, R_AT*R_SZ(sp) + .set at + + /* Q: Why hardcode -40 for stack add??? */ + /* This needs to be figured out.........*/ + addiu sp,sp,-40 + sw ra,32(sp) /* store ra on the stack */ + +/* determine if an interrupt generated this exception */ + + mfc0 k0,C0_CAUSE + and k1,k0,CAUSE_EXCMASK + beq k1, 0, _ISR_Handler_1 + nop + +_ISR_Handler_Exception: + nop + b _ISR_Handler_Exception /* Jump to the exception code */ + nop + +_ISR_Handler_1: + + mfc0 k1,C0_SR + and k0,k1 + and k0,CAUSE_IPMASK + beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */ + /* but if it's not an exception or an interrupt, + /* Then where did it come from??? */ + nop + + /* + * save some or all context on stack + * may need to save some special interrupt information for exit + * + * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) + * if ( _ISR_Nest_level == 0 ) + * switch to software interrupt stack + * #endif + */ + + /* + * _ISR_Nest_level++; + */ + lw t0,_ISR_Nest_level + addi t0,t0,1 + sw t0,_ISR_Nest_level + /* + * _Thread_Dispatch_disable_level++; + */ + lw t1,_Thread_Dispatch_disable_level + addi t1,t1,1 + sw t1,_Thread_Dispatch_disable_level + + /* + * while ( interrupts_pending(cause_reg) ) { + * vector = BITFIELD_TO_INDEX(cause_reg); + * (*_ISR_Vector_table[ vector ])( vector ); + * } + */ + /* k0 has the SR interrupt bits */ + la t3, _ISR_vector_table + + /* The bits you look at can be prioritized here just by */ + /* changing what bit is looked at. I.E. SR_IBITx */ + /* This code might become a loop, servicing all ints before returning.. */ + /* Right now, it will go thru the whole list once */ + +_ISR_check_bit_0: + and k1, k0, SR_IBIT1 + beq k1, zero, _ISR_check_bit_1 + nop + li t1, ISR_VEC_SIZE*0 + add t3, t1 + jal t3 + nop +_ISR_check_bit_1: + and k1, k0, SR_IBIT2 + beq k1, zero, _ISR_check_bit_2 + nop + li t1, ISR_VEC_SIZE*1 + add t3, t1 + jal t3 + nop +_ISR_check_bit_2: + and k1, k0, SR_IBIT3 + beq k1, zero, _ISR_check_bit_3 + nop + li t1, ISR_VEC_SIZE*2 + add t3, t1 + jal t3 + nop +_ISR_check_bit_3: + and k1, k0, SR_IBIT4 + beq k1, zero, _ISR_check_bit_4 + nop + li t1, ISR_VEC_SIZE*3 + add t3, t1 + jal t3 + nop +_ISR_check_bit_4: + and k1, k0, SR_IBIT5 + beq k1, zero, _ISR_check_bit_5 + nop + li t1, ISR_VEC_SIZE*4 + add t3, t1 + jal t3 + nop +_ISR_check_bit_5: + and k1, k0, SR_IBIT6 + beq k1, zero, _ISR_check_bit_6 + nop + li t1, ISR_VEC_SIZE*5 + add t3, t1 + jal t3 + nop +_ISR_check_bit_6: + and k1, k0, SR_IBIT7 + beq k1, zero, _ISR_check_bit_7 + nop + li t1, ISR_VEC_SIZE*6 + add t3, t1 + jal t3 + nop +_ISR_check_bit_7: + and k1, k0, SR_IBIT8 + beq k1, zero, _ISR_exit_int_check + nop + li t1, ISR_VEC_SIZE*7 + add t3, t1 + jal t3 + nop + +_ISR_exit_int_check: + + /* + * --_ISR_Nest_level; + */ + lw t2,_ISR_Nest_level + addi t2,t2,-1 + sw t2,_ISR_Nest_level + /* + * --_Thread_Dispatch_disable_level; + */ + lw t1,_Thread_Dispatch_disable_level + addi t1,t1,-1 + sw t1,_Thread_Dispatch_disable_level + /* + * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) + * goto the label "exit interrupt (simple case)" + */ + or t0,t2,t1 + bne t0,zero,_ISR_Handler_exit + nop + /* + * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) + * restore stack + * #endif + * + * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) + * goto the label "exit interrupt (simple case)" + */ + lw t0,_Context_Switch_necessary + lw t1,_ISR_Signals_to_thread_executing + or t0,t0,t1 + beq t0,zero,_ISR_Handler_exit + nop + /* + * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch + */ + jal _Thread_Dispatch + nop + /* + * prepare to get out of interrupt + * return from interrupt (maybe to _ISR_Dispatch) + * + * LABEL "exit interrupt (simple case): + * prepare to get out of interrupt + * return from interrupt + */ + +_ISR_Handler_exit: + ld ra,32(sp) + addiu sp,sp,40 /* Q: Again with the 40...Is this needed? */ + +/* restore interrupt context from stack */ + + lw k0, R_MDLO*R_SZ(sp) + mtlo k0 + lw k0, R_MDHI*R_SZ(sp) + lw a2, R_A2*R_SZ(sp) + mthi k0 + lw a3, R_A3*R_SZ(sp) + lw t0, R_T0*R_SZ(sp) + lw t1, R_T1*R_SZ(sp) + lw t2, R_T2*R_SZ(sp) + lw t3, R_T3*R_SZ(sp) + lw t4, R_T4*R_SZ(sp) + lw t5, R_T5*R_SZ(sp) + lw t6, R_T6*R_SZ(sp) + lw t7, R_T7*R_SZ(sp) + lw t8, R_T8*R_SZ(sp) + lw t9, R_T9*R_SZ(sp) + lw gp, R_GP*R_SZ(sp) + lw fp, R_FP*R_SZ(sp) + lw ra, R_RA*R_SZ(sp) + lw a0, R_A0*R_SZ(sp) + lw a1, R_A1*R_SZ(sp) + lw v1, R_V1*R_SZ(sp) + lw v0, R_V0*R_SZ(sp) + .set noat + lw AT, R_AT*R_SZ(sp) + .set at + + addiu sp,sp,EXCP_STACK_SIZE + + rfe /* Might not need to do RFE here... */ + j ra + nop + + .set reorder +ENDFRAME(_ISR_Handler) + +#else + + #error "__mips is not set to 1 or 3 " + +#endif FRAME(mips_enable_interrupts,sp,0,ra) mfc0 t0,C0_SR /* get status reg */ @@ -696,6 +1055,8 @@ FRAME(mips_disable_interrupts,sp,0,ra) nop ENDFRAME(mips_disable_interrupts) +#if __mips == 3 + FRAME(mips_enable_global_interrupts,sp,0,ra) mfc0 t0,C0_SR /* get status reg */ nop @@ -715,6 +1076,33 @@ FRAME(mips_disable_global_interrupts,sp,0,ra) nop ENDFRAME(mips_disable_global_interrupts) +#elif __mips == 1 + +FRAME(mips_enable_global_interrupts,sp,0,ra) + mfc0 t0,C0_SR /* get status reg */ + nop + ori t0,SR_IEC + mtc0 t0,C0_SR /* save updated status reg */ + j ra + nop +ENDFRAME(mips_enable_global_interrupts) + +FRAME(mips_disable_global_interrupts,sp,0,ra) + li t1,SR_IEC + mfc0 t0,C0_SR /* get status reg */ + not t1 + and t0,t1 + mtc0 t0,C0_SR /* save updated status reg */ + j ra + nop +ENDFRAME(mips_disable_global_interrupts) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + /* return the value of the status register in v0. Used for debugging */ FRAME(mips_get_sr,sp,0,ra) mfc0 v0,C0_SR @@ -732,6 +1120,47 @@ FRAME(mips_break,sp,0,ra) nop ENDFRAME(mips_break) + +/************************************************************************** +** +** enable_int(mask) - enables interrupts - mask is positioned so it only +** needs to be or'ed into the status reg. This +** also does some other things !!!! caution should +** be used if invoking this while in the middle +** of a debugging session where the client may have +** nested interrupts. +** +****************************************************************************/ +FRAME(enable_int,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR + or a0,1 + or t0,a0 + mtc0 t0,C0_SR + j ra + nop + .set reorder +ENDFRAME(enable_int) + + +/*************************************************************************** +** +** disable_int(mask) - disable the interrupt - mask is the complement +** of the bits to be cleared - i.e. to clear ext int +** 5 the mask would be - 0xffff7fff +** +****************************************************************************/ +FRAME(disable_int,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR + nop + and t0,a0 + mtc0 t0,C0_SR + j ra + nop +ENDFRAME(disable_int) + + /*PAGE * * _CPU_Internal_threads_Idle_thread_body @@ -749,13 +1178,27 @@ ENDFRAME(mips_break) * hook with caution. */ +#if __mips == 3 + FRAME(_CPU_Thread_Idle_body,sp,0,ra) wait /* enter low power mode */ j _CPU_Thread_Idle_body nop ENDFRAME(_CPU_Thread_Idle_body) -#define VEC_CODE_LENGTH 10*4 +#elif __mips == 1 + +FRAME(_CPU_Thread_Idle_body,sp,0,ra) + nop /* no wait instruction */ + j _CPU_Thread_Idle_body + nop +ENDFRAME(_CPU_Thread_Idle_body) + +#else + + #error "__mips not set to 1 or 3" + +#endif /************************************************************************** ** @@ -770,10 +1213,12 @@ ENDFRAME(_CPU_Thread_Idle_body) ** ***************************************************************************/ -#define INITEXCFRM ((2*4)+4) /* ra + 2 arguments */ +#define VEC_CODE_LENGTH 10*4 + FRAME(init_exc_vecs,sp,0,ra) -/* This code yanked from SIM */ -#if defined(CPU_R3000) + +#if __mips == 1 + .set noreorder la t1,exc_utlb_code la t2,exc_norm_code @@ -793,7 +1238,7 @@ FRAME(init_exc_vecs,sp,0,ra) addiu t2,4 move t5,ra # assumes clear_cache doesnt use t5 li a0,UT_VEC - jal clear_cache + jal clear_cache /* Check out clear cache.... */ li a1,VEC_CODE_LENGTH nop li a0,E_VEC @@ -803,8 +1248,9 @@ FRAME(init_exc_vecs,sp,0,ra) j ra nop .set reorder -#endif -#if defined(CPU_R4000) + +#elif __mips == 3 + .set reorder move t5,ra # assumes clear_cache doesnt use t5 @@ -874,98 +1320,60 @@ FRAME(init_exc_vecs,sp,0,ra) move ra,t5 # restore ra j ra + +#else + #error "__mips not set to 1 or 3" #endif + ENDFRAME(init_exc_vecs) +FRAME(exc_norm_code,sp,0,ra) + la k0, _ISR_Handler /* generic external int hndlr */ + j k0 + nop +ENDFRAME(exc_norm_code) -#if defined(CPU_R4000) -FRAME(exc_tlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif +/* +** Again, reliance on SIM. Not good. +*/ +#if __mips == 3 -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif +FRAME(exc_tlb_code,sp,0,ra) + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop - ENDFRAME(exc_tlb_code) - FRAME(exc_xtlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop ENDFRAME(exc_xtlb_code) - FRAME(exc_cache_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop - ENDFRAME(exc_cache_code) - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 +#elif __mips == 1 +/* ------------------------------------------------------ */ +FRAME(exc_tlb_code,sp,0,ra) + la k0, (R_VEC+((48)*8)) /* Need something else here besides IDT/SIM call */ + j k0 nop - subu sp, EXCP_STACK_SIZE /* set up local stack frame */ -ENDFRAME(exc_norm_code) -#endif +ENDFRAME(exc_tlb_code) -/************************************************************************** -** -** enable_int(mask) - enables interrupts - mask is positioned so it only -** needs to be or'ed into the status reg. This -** also does some other things !!!! caution should -** be used if invoking this while in the middle -** of a debugging session where the client may have -** nested interrupts. -** -****************************************************************************/ -FRAME(enable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - or a0,1 - or t0,a0 - mtc0 t0,C0_SR - j ra - nop - .set reorder -ENDFRAME(enable_int) +FRAME(exc_cache_code,sp,0,ra) + la k0, (R_VEC+((48)*8)) + j k0 + nop +ENDFRAME(exc_cache_code) +#else -/*************************************************************************** -** -** disable_int(mask) - disable the interrupt - mask is the complement -** of the bits to be cleared - i.e. to clear ext int -** 5 the mask would be - 0xffff7fff -** -****************************************************************************/ -FRAME(disable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - nop - and t0,a0 - mtc0 t0,C0_SR - j ra - nop -ENDFRAME(disable_int) + #error "__mips is not set to 1 or 3" +#endif diff --git a/c/src/exec/score/cpu/mips/cpu_asm.h b/c/src/exec/score/cpu/mips/cpu_asm.h index 08fc0975d9..287b881068 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.h +++ b/c/src/exec/score/cpu/mips/cpu_asm.h @@ -16,7 +16,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/exec/score/cpu/mips/idtcpu.h b/c/src/exec/score/cpu/mips/idtcpu.h index f921e85ef6..cfb2fe626a 100644 --- a/c/src/exec/score/cpu/mips/idtcpu.h +++ b/c/src/exec/score/cpu/mips/idtcpu.h @@ -45,7 +45,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define K1SIZE 0x20000000 #define K2BASE 0xc0000000 #define K2SIZE 0x20000000 -#if defined(CPU_R4000) +#if __mips == 3 #define KSBASE 0xe0000000 #define KSSIZE 0x20000000 #endif @@ -56,11 +56,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** Exception Vectors */ -#if defined(CPU_R3000) +#if __mips == 1 #define UT_VEC K0BASE /* utlbmiss vector */ #define E_VEC (K0BASE+0x80) /* exception vevtor */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ #define C_VEC (K0BASE+0x100) /* cache error vector */ @@ -89,7 +89,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define MINCACHE 0x200 /* 512 For 3041. */ #define MAXCACHE 0x40000 /* 256*1024 256k */ -#if defined(CPU_R4000) +#if __mips == 3 /* R4000 configuration register definitions */ #define CFG_CM 0x80000000 /* Master-Checker mode */ #define CFG_ECMASK 0x70000000 /* System Clock Ratio */ @@ -184,7 +184,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** TLB resource defines */ -#if defined(CPU_R3000) +#if __mips == 1 #define N_TLB_ENTRIES 64 #define TLB_PGSIZE 0x1000 #define RANDBASE 8 @@ -214,7 +214,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBCTXT_VPNMASK 0x001ffffc #define TLBCTXT_VPNSHIFT 2 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define N_TLB_ENTRIES 48 #define TLBHI_VPN2MASK 0xffffe000 @@ -249,7 +249,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBPGMASK_MASK 0x01ffe000 #endif -#if defined(CPU_R3000) +#if __mips == 1 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -300,7 +300,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -375,30 +375,30 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT */ #define C0_INX $0 /* tlb index */ #define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_TLBLO $2 /* tlb entry low */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_TLBLO0 $2 /* tlb entry low 0 */ #define C0_TLBLO1 $3 /* tlb entry low 1 */ #endif #define C0_CTXT $4 /* tlb context */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_PAGEMASK $5 /* tlb page mask */ #define C0_WIRED $6 /* number of wired tlb entries */ #endif #define C0_BADVADDR $8 /* bad virtual address */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COUNT $9 /* cycle count */ #endif #define C0_TLBHI $10 /* tlb entry hi */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COMPARE $11 /* cyccle count comparator */ #endif @@ -407,11 +407,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define C0_EPC $14 /* exception pc */ #define C0_PRID $15 /* revision identifier */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_CONFIG $3 /* configuration register R3081*/ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_CONFIG $16 /* configuration register */ #define C0_LLADDR $17 /* linked load address */ #define C0_WATCHLO $18 /* watchpoint trap register */ diff --git a/c/src/exec/score/cpu/mips/idtmon.h b/c/src/exec/score/cpu/mips/idtmon.h deleted file mode 100644 index 2dacfe052e..0000000000 --- a/c/src/exec/score/cpu/mips/idtmon.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtmon.h - General header file for the IDT Prom Monitor -** -** Copyright 1989 Integrated Device Technology, Inc. -** All Rights Reserved. -** -** June 1989 - D.Cahoon -*/ -#ifndef __IDTMON_H__ -#define __IDTMON_H__ - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - -/* -** M_BUSWIDTH -** Memory bus width (including bank interleaving) in bytes -** used when doing memory sizing to prevent bus capacitance -** reporting ghost memory locations -*/ -#if defined(CPU_R3000) -#define M_BUSWIDTH 8 /* 32bit memory bank interleaved */ -#endif -#if defined(CPU_R4000) -#define M_BUSWIDTH 16 /* 64 bit memory bank interleaved */ -#endif - -/* -** this is the default value for the number of bytes to add in calculating -** the checksums in the checksum command -*/ -#define CHK_SUM_CNT 0x20000 /* number of bytes to calc chksum for */ - -/* -** Monitor modes -*/ -#define MODE_MONITOR 5 /* IDT Prom Monitor is executing */ -#define MODE_USER 0xa /* USER is executing */ - -/* -** memory reference widths -*/ -#define SW_BYTE 1 -#define SW_HALFWORD 2 -#define SW_WORD 4 -#define SW_TRIBYTEL 12 -#define SW_TRIBYTER 20 - -#ifdef CPU_R4000 -/* -** definitions for select_cache call -*/ -#define DCACHE 0 -#define ICACHE 1 -#define SCACHE 2 - -#endif - -#ifndef ASM -typedef struct { - unsigned int mem_size; - unsigned int icache_size; - unsigned int dcache_size; -#ifdef CPU_R4000 - unsigned int scache_size; -#endif - - } mem_config; - -#endif - -/* -** general equates for diagnostics and boolean functions -*/ -#define PASS 0 -#define FAIL 1 - -#ifndef TRUE -#define TRUE 1 -#endif TRUE -#ifndef NULL -#define NULL 0 -#endif NULL - -#ifndef FALSE -#define FALSE 0 -#endif FALSE - - -/* -** portablility equates -*/ - -#ifndef BOOL -#define BOOL unsigned int -#endif BOOL - -#ifndef GLOBAL -#define GLOBAL /**/ -#endif GLOBAL - -#ifndef MLOCAL -#define MLOCAL static -#endif MLOCAL - - -#ifdef XDS -#define CONST const -#else -#define CONST -#endif XDS - -#define u_char unsigned char -#define u_short unsigned short -#define u_int unsigned int -/* -** assembly instructions for compatability between xds and mips -*/ -#ifndef XDS -#define sllv sll -#define srlv srl -#endif XDS -/* -** debugger macros for assembly language routines. Allows the -** programmer to set up the necessary stack frame info -** required by debuggers to do stack traces. -*/ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif XDS -#endif /* __IDTMON_H__ */ diff --git a/c/src/exec/score/cpu/mips/iregdef.h b/c/src/exec/score/cpu/mips/iregdef.h index f0953da852..ca50207a3b 100644 --- a/c/src/exec/score/cpu/mips/iregdef.h +++ b/c/src/exec/score/cpu/mips/iregdef.h @@ -221,10 +221,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_SR 67 #define R_CAUSE 68 #define R_TLBHI 69 -#if defined(CPU_R3000) +#if __mips == 1 #define R_TLBLO 70 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO0 70 #endif #define R_BADVADDR 71 @@ -236,10 +236,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_PRID 77 #define R_FCSR 78 #define R_FEIR 79 -#if defined(CPU_R3000) +#if __mips == 1 #define NREGS 80 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO1 80 #define R_PAGEMASK 81 #define R_WIRED 82 @@ -296,15 +296,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_RA R_R31 /* Ketan added the following */ -#ifdef CPU_R3000 +#ifdef __mips == 1 #define sreg sw #define lreg lw #define rmfc0 mfc0 #define rmtc0 mtc0 #define R_SZ 4 -#endif CPU_R3000 +#endif /* __mips == 1 */ -#ifdef CPU_R4000 +/* #ifdef __mips == 3 */ #if __mips < 3 #define sreg sw #define lreg lw @@ -318,7 +318,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define rmtc0 dmtc0 #define R_SZ 8 #endif -#endif CPU_R4000 +/* #endif __mips == 3 */ /* Ketan till here */ #endif /* __IREGDEF_H__ */ diff --git a/c/src/exec/score/cpu/mips/rtems/score/cpu.h b/c/src/exec/score/cpu/mips/rtems/score/cpu.h index 35d936ec7e..7527ddecdf 100644 --- a/c/src/exec/score/cpu/mips/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/mips/rtems/score/cpu.h @@ -18,7 +18,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -93,7 +93,7 @@ extern void mips_fatal_error ( int error ); /* * Does RTEMS manage a dedicated interrupt stack in software? * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. * If FALSE, nothing is done. * * If the CPU supports a dedicated interrupt stack in hardware, @@ -162,19 +162,18 @@ extern void mips_fatal_error ( int error ); * If there is a FP coprocessor such as the i387 or mc68881, then * the answer is TRUE. * - * The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific. + * The macro name "MIPS_HAS_FPU" should be made CPU specific. * It indicates whether or not this CPU model has FP support. For * example, it would be possible to have an i386_nofp CPU model * which set this to false to indicate that you have an i386 without * an i387 and wish to leave floating point support out of RTEMS. */ -#if ( MIPS64ORION_HAS_FPU == 1 ) +#if ( MIPS_HAS_FPU == 1 ) #define CPU_HARDWARE_FP TRUE #else #define CPU_HARDWARE_FP FALSE #endif -#define CPU_SOFTWARE_FP FALSE /* * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? @@ -444,7 +443,7 @@ typedef struct { */ /* - * Macros to access MIPS64ORION specific additions to the CPU Table + * Macros to access MIPS specific additions to the CPU Table */ #define rtems_cpu_configuration_get_clicks_per_microsecond() \ diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips.h b/c/src/exec/score/cpu/mips/rtems/score/mips.h index 2ec96da0a4..90e959bd47 100644 --- a/c/src/exec/score/cpu/mips/rtems/score/mips.h +++ b/c/src/exec/score/cpu/mips/rtems/score/mips.h @@ -15,7 +15,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -28,8 +28,8 @@ */ /* @(#)mips64orion.h 08/29/96 1.3 */ -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h +#ifndef _INCLUDE_MIPS_h +#define _INCLUDE_MIPS_h #ifdef __cplusplus extern "C" { @@ -44,40 +44,33 @@ extern "C" { * of the family. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" #else - -#error "Unsupported CPU Model" - +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" #endif /* * Define the name of the CPU family. */ -#define CPU_NAME "MIPS R46xxx" +#define CPU_NAME "MIPS" #ifdef __cplusplus } #endif -#endif /* ! _INCLUDE_MIPS64ORION_h */ +#endif /* ! _INCLUDE_MIPS_h */ /* end of include file */ diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h b/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h index 2ec96da0a4..90e959bd47 100644 --- a/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h +++ b/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h @@ -15,7 +15,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -28,8 +28,8 @@ */ /* @(#)mips64orion.h 08/29/96 1.3 */ -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h +#ifndef _INCLUDE_MIPS_h +#define _INCLUDE_MIPS_h #ifdef __cplusplus extern "C" { @@ -44,40 +44,33 @@ extern "C" { * of the family. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" #else - -#error "Unsupported CPU Model" - +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" #endif /* * Define the name of the CPU family. */ -#define CPU_NAME "MIPS R46xxx" +#define CPU_NAME "MIPS" #ifdef __cplusplus } #endif -#endif /* ! _INCLUDE_MIPS64ORION_h */ +#endif /* ! _INCLUDE_MIPS_h */ /* end of include file */ diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index 7f281f20c9..2f2f17a259 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,29 @@ +2000-10-24 Alan Cudmore <alanc@linuxstart.com> and + Joel Sherrill <joel@OARcorp.com> + + * This is a major reworking of the mips64orion port to use + gcc predefines as much as possible and a big push to multilib + the mips port. The mips64orion port was copied/renamed to mips + to be more like other GNU tools. Alan did most of the technical + work of determining how to map old macro names used by the mips64orion + port to standard compiler macro definitions. Joel did the merge + with CVS magic to keep individual file history and did the BSP + modifications. Details follow: + * Makefile.am: idtmon.h in mips64orion port not present. + * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. + * cpu.c: Comments added. + * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. + First attempt at exception/interrupt processing for ISA level 1 + and minus any use of IDT/MON added. + * idtcpu.h: Conditionals changed to use gcc predefines. + * iregdef.h: Ditto. + * cpu_asm.h: No real change. Merger required commit. + * rtems/Makefile.am: Ditto. + * rtems/score/Makefile.am: Ditto. + * rtems/score/cpu.h: Change MIPS64ORION to MIPS. + * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert + from using RTEMS_CPU_MODEL to gcc predefines to figre things out. + 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Include compile.am. diff --git a/cpukit/score/cpu/mips/Makefile.am b/cpukit/score/cpu/mips/Makefile.am index 1d4a588d2e..7d4724c4d5 100644 --- a/cpukit/score/cpu/mips/Makefile.am +++ b/cpukit/score/cpu/mips/Makefile.am @@ -10,7 +10,7 @@ SUBDIRS = rtems C_FILES = cpu.c C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) -H_FILES = asm.h cpu_asm.h idtcpu.h idtmon.h iregdef.h +H_FILES = asm.h cpu_asm.h idtcpu.h iregdef.h S_FILES = cpu_asm.S S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) @@ -44,7 +44,7 @@ all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ .PRECIOUS: $(REL) -EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h idtmon.h iregdef.h \ +EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h iregdef.h \ rtems.c include $(top_srcdir)/../../../../../../automake/subdirs.am diff --git a/cpukit/score/cpu/mips/asm.h b/cpukit/score/cpu/mips/asm.h index edabbe8fcc..060be295bf 100644 --- a/cpukit/score/cpu/mips/asm.h +++ b/cpukit/score/cpu/mips/asm.h @@ -24,8 +24,8 @@ */ /* @(#)asm.h 03/15/96 1.1 */ -#ifndef __MIPS64ORION_ASM_h -#define __MIPS64ORION_ASM_h +#ifndef __NO_CPU_ASM_h +#define __NO_CPU_ASM_h /* * Indicate we are in an assembly file and get the basic CPU definitions. @@ -96,7 +96,27 @@ #define PUBLIC(sym) .globl SYM (sym) #define EXTERN(sym) .globl SYM (sym) +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif XDS + #endif /* end of include file */ - diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c index 1d56652622..db9ae911b4 100644 --- a/cpukit/score/cpu/mips/cpu.c +++ b/cpukit/score/cpu/mips/cpu.c @@ -1,22 +1,24 @@ /* * Mips CPU Dependent Source * - * Author: Craig Lebakken <craigl@transition.com> + * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and + * Joel Sherrill <joel@OARcorp.com>. * - * COPYRIGHT (c) 1996 by Transition Networks Inc. + * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> + * COPYRIGHT (c) 1996 by Transition Networks Inc. * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the + * suitability of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -124,7 +126,7 @@ void _CPU_ISR_install_raw_handler( * This is where we install the interrupt handler into the "raw" interrupt * table used by the CPU to dispatch interrupt handlers. */ - +/* Q: This will become necessary for Non IDT/Sim use...*/ #if 0 /* not necessary */ /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ add_ext_int_func( vector, new_handler ); diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S index 9770a5f2f9..c04c1e7d30 100644 --- a/cpukit/score/cpu/mips/cpu_asm.S +++ b/cpukit/score/cpu/mips/cpu_asm.S @@ -19,7 +19,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -45,16 +45,8 @@ name:; \ #define ENDFRAME(name) \ .end name - #define EXCP_STACK_SIZE (NREGS*R_SZ) - -#if __ghs__ -#define sd sw -#define ld lw -#define dmtc0 mtc0 -#define dsll sll -#define dmfc0 mfc0 -#endif +#define ISR_VEC_SIZE 4 #if 1 /* 32 bit unsigned32 types */ #define sint sw @@ -141,6 +133,8 @@ unsigned32 _CPU_ISR_Get_level( void ) */ } #endif + +#if __mips == 3 /* return the current exception level for the 4650 */ FRAME(_CPU_ISR_Get_level,sp,0,ra) mfc0 v0,C0_SR @@ -163,8 +157,8 @@ _CPU_ISR_Set_1: nop bnez a0,_CPU_ISR_Set_2 nop - nop - mfc0 t0,C0_SR + nop + mfc0 t0, C0_SR nop li t1,~SR_EXL and t0,t1 @@ -182,7 +176,7 @@ _CPU_ISR_Set_2: nop mtc0 t0,C0_SR /* first disable ie bit (recommended) */ nop - ori t0,SR_EXL|SR_IE /* enable exception level */ + ori t0, SR_EXL|SR_IE /* enable exception level */ nop mtc0 t0,C0_SR nop @@ -191,6 +185,32 @@ _CPU_ISR_Set_exit: nop ENDFRAME(_CPU_ISR_Set_level) +#elif __mips == 1 + +/* MIPS ISA 1 ( R3000 ) */ +/* These routines might not be needed for the R3000 */ +/* Q:Who calls _CPU_ISR_Get/Set_level? */ +FRAME(_CPU_ISR_Get_level,sp,0,ra) + mfc0 v0,C0_SR + nop + andi v0, SR_IEC + j ra +ENDFRAME(_CPU_ISR_Get_level) + +FRAME(_CPU_ISR_Set_level,sp,0,ra) + nop + mfc0 t0,C0_SR + andi a0, SR_IEC + or t0, a0 + mtc0 t0,C0_SR + nop + j ra +ENDFRAME(_CPU_ISR_Set_level) + +#else + #error "__mips is set to 1 or 3" +#endif + /* * _CPU_Context_save_fp_context * @@ -323,6 +343,8 @@ ENDFRAME(_CPU_Context_restore_fp) * { * } */ +#if __mips == 3 +/* MIPS ISA Level 3 ( R4xxx ) */ FRAME(_CPU_Context_switch,sp,0,ra) @@ -337,7 +359,6 @@ FRAME(_CPU_Context_switch,sp,0,ra) sd ra,RA_OFFSET*8(a0) /* save current context */ sd sp,SP_OFFSET*8(a0) sd fp,FP_OFFSET*8(a0) - sd s0,S0_OFFSET*8(a0) sd s1,S1_OFFSET*8(a0) sd s2,S2_OFFSET*8(a0) sd s3,S3_OFFSET*8(a0) @@ -375,6 +396,62 @@ _CPU_Context_1: nop ENDFRAME(_CPU_Context_switch) +#elif __mips == 1 +/* MIPS ISA Level 1 ( R3000 ) */ + +FRAME(_CPU_Context_switch,sp,0,ra) + + mfc0 t0,C0_SR + li t1,~SR_IEC + sw t0,C0_SR_OFFSET*4(a0) /* save status register */ + and t0,t1 + mtc0 t0,C0_SR /* first disable ie bit (recommended) */ + + sw ra,RA_OFFSET*4(a0) /* save current context */ + sw sp,SP_OFFSET*4(a0) + sw fp,FP_OFFSET*4(a0) + sw s0,S0_OFFSET*4(a0) + sw s1,S1_OFFSET*4(a0) + sw s2,S2_OFFSET*4(a0) + sw s3,S3_OFFSET*4(a0) + sw s4,S4_OFFSET*4(a0) + sw s5,S5_OFFSET*4(a0) + sw s6,S6_OFFSET*4(a0) + sw s7,S7_OFFSET*4(a0) + + mfc0 t0,C0_EPC + sw t0,C0_EPC_OFFSET*4(a0) + +_CPU_Context_switch_restore: + lw s0,S0_OFFSET*4(a1) /* restore context */ + lw s1,S1_OFFSET*4(a1) + lw s2,S2_OFFSET*4(a1) + lw s3,S3_OFFSET*4(a1) + lw s4,S4_OFFSET*4(a1) + lw s5,S5_OFFSET*4(a1) + lw s6,S6_OFFSET*4(a1) + lw s7,S7_OFFSET*4(a1) + lw fp,FP_OFFSET*4(a1) + lw sp,SP_OFFSET*4(a1) + lw ra,RA_OFFSET*4(a1) + lw t0,C0_EPC_OFFSET*4(a1) + mtc0 t0,C0_EPC + lw t1, C0_SR_OFFSET*4(a1) + mtc0 t1,C0_SR + + /* Q:Changes needed to SR_IEC bit in SR/_CPU_Context_switch_restore? */ + +_CPU_Context_1: + j ra + nop +ENDFRAME(_CPU_Context_switch) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + /* * _CPU_Context_restore * @@ -392,12 +469,28 @@ void _CPU_Context_restore( } #endif +#if __mips == 3 + FRAME(_CPU_Context_restore,sp,0,ra) dadd a1,a0,zero j _CPU_Context_switch_restore nop ENDFRAME(_CPU_Context_restore) +#elif __mips == 1 + +FRAME(_CPU_Context_restore,sp,0,ra) + add a1,a0,zero + j _CPU_Ccontext_switch_restore + nop +ENDFRAME(_CPU_Context_restore) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + EXTERN(_ISR_Nest_level, SZ_INT) EXTERN(_Thread_Dispatch_disable_level,SZ_INT) EXTERN(_Context_Switch_necessary,SZ_INT) @@ -438,6 +531,9 @@ void _ISR_Handler() * */ #endif + +#if __mips == 3 +/* ----------------------------------------------------------------------------- */ FRAME(_ISR_Handler,sp,0,ra) .set noreorder #if USE_IDTKIT @@ -487,8 +583,9 @@ FRAME(_ISR_Handler,sp,0,ra) /* determine if an interrupt generated this exception */ mfc0 k0,C0_CAUSE and k1,k0,CAUSE_EXCMASK - bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */ - mfc0 k1,C0_SR + bnez k1,_ISR_Handler_prom_exit /* not an external interrup +t, pass exception to Monitor */ + mfc0 k1,C0_SR and k0,k1 and k0,CAUSE_IPMASK beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ @@ -661,11 +758,11 @@ _ISR_Handler_quick_exit: nop _ISR_Handler_prom_exit: -#ifdef CPU_R3000 +#if __mips == 1 la k0, (R_VEC+((48)*8)) #endif -#ifdef CPU_R4000 +#if __mips == 3 la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ #endif j k0 @@ -675,6 +772,268 @@ _ISR_Handler_prom_exit: ENDFRAME(_ISR_Handler) +/* ---------------------------------------------------------------------- */ +#elif __mips == 1 +/* MIPS ISA Level 1 */ + +FRAME(_ISR_Handler,sp,0,ra) +.set noreorder + + /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ + + addiu sp,sp,-EXCP_STACK_SIZE /* wastes alot of stack space for context?? */ + + sw ra, R_RA*R_SZ(sp) /* store ra on the stack */ + sw v0, R_V0*R_SZ(sp) + sw v1, R_V1*R_SZ(sp) + sw a0, R_A0*R_SZ(sp) + sw a1, R_A1*R_SZ(sp) + sw a2, R_A2*R_SZ(sp) + sw a3, R_A3*R_SZ(sp) + sw t0, R_T0*R_SZ(sp) + sw t1, R_T1*R_SZ(sp) + sw t2, R_T2*R_SZ(sp) + sw t3, R_T3*R_SZ(sp) + sw t4, R_T4*R_SZ(sp) + sw t5, R_T5*R_SZ(sp) + sw t6, R_T6*R_SZ(sp) + sw t7, R_T7*R_SZ(sp) + mflo k0 + sw t8, R_T8*R_SZ(sp) + sw k0, R_MDLO*R_SZ(sp) + sw t9, R_T9*R_SZ(sp) + mfhi k0 + sw gp, R_GP*R_SZ(sp) + sw fp, R_FP*R_SZ(sp) + sw k0, R_MDHI*R_SZ(sp) + .set noat + sw AT, R_AT*R_SZ(sp) + .set at + + /* Q: Why hardcode -40 for stack add??? */ + /* This needs to be figured out.........*/ + addiu sp,sp,-40 + sw ra,32(sp) /* store ra on the stack */ + +/* determine if an interrupt generated this exception */ + + mfc0 k0,C0_CAUSE + and k1,k0,CAUSE_EXCMASK + beq k1, 0, _ISR_Handler_1 + nop + +_ISR_Handler_Exception: + nop + b _ISR_Handler_Exception /* Jump to the exception code */ + nop + +_ISR_Handler_1: + + mfc0 k1,C0_SR + and k0,k1 + and k0,CAUSE_IPMASK + beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */ + /* but if it's not an exception or an interrupt, + /* Then where did it come from??? */ + nop + + /* + * save some or all context on stack + * may need to save some special interrupt information for exit + * + * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) + * if ( _ISR_Nest_level == 0 ) + * switch to software interrupt stack + * #endif + */ + + /* + * _ISR_Nest_level++; + */ + lw t0,_ISR_Nest_level + addi t0,t0,1 + sw t0,_ISR_Nest_level + /* + * _Thread_Dispatch_disable_level++; + */ + lw t1,_Thread_Dispatch_disable_level + addi t1,t1,1 + sw t1,_Thread_Dispatch_disable_level + + /* + * while ( interrupts_pending(cause_reg) ) { + * vector = BITFIELD_TO_INDEX(cause_reg); + * (*_ISR_Vector_table[ vector ])( vector ); + * } + */ + /* k0 has the SR interrupt bits */ + la t3, _ISR_vector_table + + /* The bits you look at can be prioritized here just by */ + /* changing what bit is looked at. I.E. SR_IBITx */ + /* This code might become a loop, servicing all ints before returning.. */ + /* Right now, it will go thru the whole list once */ + +_ISR_check_bit_0: + and k1, k0, SR_IBIT1 + beq k1, zero, _ISR_check_bit_1 + nop + li t1, ISR_VEC_SIZE*0 + add t3, t1 + jal t3 + nop +_ISR_check_bit_1: + and k1, k0, SR_IBIT2 + beq k1, zero, _ISR_check_bit_2 + nop + li t1, ISR_VEC_SIZE*1 + add t3, t1 + jal t3 + nop +_ISR_check_bit_2: + and k1, k0, SR_IBIT3 + beq k1, zero, _ISR_check_bit_3 + nop + li t1, ISR_VEC_SIZE*2 + add t3, t1 + jal t3 + nop +_ISR_check_bit_3: + and k1, k0, SR_IBIT4 + beq k1, zero, _ISR_check_bit_4 + nop + li t1, ISR_VEC_SIZE*3 + add t3, t1 + jal t3 + nop +_ISR_check_bit_4: + and k1, k0, SR_IBIT5 + beq k1, zero, _ISR_check_bit_5 + nop + li t1, ISR_VEC_SIZE*4 + add t3, t1 + jal t3 + nop +_ISR_check_bit_5: + and k1, k0, SR_IBIT6 + beq k1, zero, _ISR_check_bit_6 + nop + li t1, ISR_VEC_SIZE*5 + add t3, t1 + jal t3 + nop +_ISR_check_bit_6: + and k1, k0, SR_IBIT7 + beq k1, zero, _ISR_check_bit_7 + nop + li t1, ISR_VEC_SIZE*6 + add t3, t1 + jal t3 + nop +_ISR_check_bit_7: + and k1, k0, SR_IBIT8 + beq k1, zero, _ISR_exit_int_check + nop + li t1, ISR_VEC_SIZE*7 + add t3, t1 + jal t3 + nop + +_ISR_exit_int_check: + + /* + * --_ISR_Nest_level; + */ + lw t2,_ISR_Nest_level + addi t2,t2,-1 + sw t2,_ISR_Nest_level + /* + * --_Thread_Dispatch_disable_level; + */ + lw t1,_Thread_Dispatch_disable_level + addi t1,t1,-1 + sw t1,_Thread_Dispatch_disable_level + /* + * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) + * goto the label "exit interrupt (simple case)" + */ + or t0,t2,t1 + bne t0,zero,_ISR_Handler_exit + nop + /* + * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) + * restore stack + * #endif + * + * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) + * goto the label "exit interrupt (simple case)" + */ + lw t0,_Context_Switch_necessary + lw t1,_ISR_Signals_to_thread_executing + or t0,t0,t1 + beq t0,zero,_ISR_Handler_exit + nop + /* + * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch + */ + jal _Thread_Dispatch + nop + /* + * prepare to get out of interrupt + * return from interrupt (maybe to _ISR_Dispatch) + * + * LABEL "exit interrupt (simple case): + * prepare to get out of interrupt + * return from interrupt + */ + +_ISR_Handler_exit: + ld ra,32(sp) + addiu sp,sp,40 /* Q: Again with the 40...Is this needed? */ + +/* restore interrupt context from stack */ + + lw k0, R_MDLO*R_SZ(sp) + mtlo k0 + lw k0, R_MDHI*R_SZ(sp) + lw a2, R_A2*R_SZ(sp) + mthi k0 + lw a3, R_A3*R_SZ(sp) + lw t0, R_T0*R_SZ(sp) + lw t1, R_T1*R_SZ(sp) + lw t2, R_T2*R_SZ(sp) + lw t3, R_T3*R_SZ(sp) + lw t4, R_T4*R_SZ(sp) + lw t5, R_T5*R_SZ(sp) + lw t6, R_T6*R_SZ(sp) + lw t7, R_T7*R_SZ(sp) + lw t8, R_T8*R_SZ(sp) + lw t9, R_T9*R_SZ(sp) + lw gp, R_GP*R_SZ(sp) + lw fp, R_FP*R_SZ(sp) + lw ra, R_RA*R_SZ(sp) + lw a0, R_A0*R_SZ(sp) + lw a1, R_A1*R_SZ(sp) + lw v1, R_V1*R_SZ(sp) + lw v0, R_V0*R_SZ(sp) + .set noat + lw AT, R_AT*R_SZ(sp) + .set at + + addiu sp,sp,EXCP_STACK_SIZE + + rfe /* Might not need to do RFE here... */ + j ra + nop + + .set reorder +ENDFRAME(_ISR_Handler) + +#else + + #error "__mips is not set to 1 or 3 " + +#endif FRAME(mips_enable_interrupts,sp,0,ra) mfc0 t0,C0_SR /* get status reg */ @@ -696,6 +1055,8 @@ FRAME(mips_disable_interrupts,sp,0,ra) nop ENDFRAME(mips_disable_interrupts) +#if __mips == 3 + FRAME(mips_enable_global_interrupts,sp,0,ra) mfc0 t0,C0_SR /* get status reg */ nop @@ -715,6 +1076,33 @@ FRAME(mips_disable_global_interrupts,sp,0,ra) nop ENDFRAME(mips_disable_global_interrupts) +#elif __mips == 1 + +FRAME(mips_enable_global_interrupts,sp,0,ra) + mfc0 t0,C0_SR /* get status reg */ + nop + ori t0,SR_IEC + mtc0 t0,C0_SR /* save updated status reg */ + j ra + nop +ENDFRAME(mips_enable_global_interrupts) + +FRAME(mips_disable_global_interrupts,sp,0,ra) + li t1,SR_IEC + mfc0 t0,C0_SR /* get status reg */ + not t1 + and t0,t1 + mtc0 t0,C0_SR /* save updated status reg */ + j ra + nop +ENDFRAME(mips_disable_global_interrupts) + +#else + + #error "__mips is not set to 1 or 3" + +#endif + /* return the value of the status register in v0. Used for debugging */ FRAME(mips_get_sr,sp,0,ra) mfc0 v0,C0_SR @@ -732,6 +1120,47 @@ FRAME(mips_break,sp,0,ra) nop ENDFRAME(mips_break) + +/************************************************************************** +** +** enable_int(mask) - enables interrupts - mask is positioned so it only +** needs to be or'ed into the status reg. This +** also does some other things !!!! caution should +** be used if invoking this while in the middle +** of a debugging session where the client may have +** nested interrupts. +** +****************************************************************************/ +FRAME(enable_int,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR + or a0,1 + or t0,a0 + mtc0 t0,C0_SR + j ra + nop + .set reorder +ENDFRAME(enable_int) + + +/*************************************************************************** +** +** disable_int(mask) - disable the interrupt - mask is the complement +** of the bits to be cleared - i.e. to clear ext int +** 5 the mask would be - 0xffff7fff +** +****************************************************************************/ +FRAME(disable_int,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR + nop + and t0,a0 + mtc0 t0,C0_SR + j ra + nop +ENDFRAME(disable_int) + + /*PAGE * * _CPU_Internal_threads_Idle_thread_body @@ -749,13 +1178,27 @@ ENDFRAME(mips_break) * hook with caution. */ +#if __mips == 3 + FRAME(_CPU_Thread_Idle_body,sp,0,ra) wait /* enter low power mode */ j _CPU_Thread_Idle_body nop ENDFRAME(_CPU_Thread_Idle_body) -#define VEC_CODE_LENGTH 10*4 +#elif __mips == 1 + +FRAME(_CPU_Thread_Idle_body,sp,0,ra) + nop /* no wait instruction */ + j _CPU_Thread_Idle_body + nop +ENDFRAME(_CPU_Thread_Idle_body) + +#else + + #error "__mips not set to 1 or 3" + +#endif /************************************************************************** ** @@ -770,10 +1213,12 @@ ENDFRAME(_CPU_Thread_Idle_body) ** ***************************************************************************/ -#define INITEXCFRM ((2*4)+4) /* ra + 2 arguments */ +#define VEC_CODE_LENGTH 10*4 + FRAME(init_exc_vecs,sp,0,ra) -/* This code yanked from SIM */ -#if defined(CPU_R3000) + +#if __mips == 1 + .set noreorder la t1,exc_utlb_code la t2,exc_norm_code @@ -793,7 +1238,7 @@ FRAME(init_exc_vecs,sp,0,ra) addiu t2,4 move t5,ra # assumes clear_cache doesnt use t5 li a0,UT_VEC - jal clear_cache + jal clear_cache /* Check out clear cache.... */ li a1,VEC_CODE_LENGTH nop li a0,E_VEC @@ -803,8 +1248,9 @@ FRAME(init_exc_vecs,sp,0,ra) j ra nop .set reorder -#endif -#if defined(CPU_R4000) + +#elif __mips == 3 + .set reorder move t5,ra # assumes clear_cache doesnt use t5 @@ -874,98 +1320,60 @@ FRAME(init_exc_vecs,sp,0,ra) move ra,t5 # restore ra j ra + +#else + #error "__mips not set to 1 or 3" #endif + ENDFRAME(init_exc_vecs) +FRAME(exc_norm_code,sp,0,ra) + la k0, _ISR_Handler /* generic external int hndlr */ + j k0 + nop +ENDFRAME(exc_norm_code) -#if defined(CPU_R4000) -FRAME(exc_tlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif +/* +** Again, reliance on SIM. Not good. +*/ +#if __mips == 3 -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif +FRAME(exc_tlb_code,sp,0,ra) + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop - ENDFRAME(exc_tlb_code) - FRAME(exc_xtlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop ENDFRAME(exc_xtlb_code) - FRAME(exc_cache_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif + la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ j k0 nop - ENDFRAME(exc_cache_code) - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 +#elif __mips == 1 +/* ------------------------------------------------------ */ +FRAME(exc_tlb_code,sp,0,ra) + la k0, (R_VEC+((48)*8)) /* Need something else here besides IDT/SIM call */ + j k0 nop - subu sp, EXCP_STACK_SIZE /* set up local stack frame */ -ENDFRAME(exc_norm_code) -#endif +ENDFRAME(exc_tlb_code) -/************************************************************************** -** -** enable_int(mask) - enables interrupts - mask is positioned so it only -** needs to be or'ed into the status reg. This -** also does some other things !!!! caution should -** be used if invoking this while in the middle -** of a debugging session where the client may have -** nested interrupts. -** -****************************************************************************/ -FRAME(enable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - or a0,1 - or t0,a0 - mtc0 t0,C0_SR - j ra - nop - .set reorder -ENDFRAME(enable_int) +FRAME(exc_cache_code,sp,0,ra) + la k0, (R_VEC+((48)*8)) + j k0 + nop +ENDFRAME(exc_cache_code) +#else -/*************************************************************************** -** -** disable_int(mask) - disable the interrupt - mask is the complement -** of the bits to be cleared - i.e. to clear ext int -** 5 the mask would be - 0xffff7fff -** -****************************************************************************/ -FRAME(disable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - nop - and t0,a0 - mtc0 t0,C0_SR - j ra - nop -ENDFRAME(disable_int) + #error "__mips is not set to 1 or 3" +#endif diff --git a/cpukit/score/cpu/mips/idtcpu.h b/cpukit/score/cpu/mips/idtcpu.h index f921e85ef6..cfb2fe626a 100644 --- a/cpukit/score/cpu/mips/idtcpu.h +++ b/cpukit/score/cpu/mips/idtcpu.h @@ -45,7 +45,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define K1SIZE 0x20000000 #define K2BASE 0xc0000000 #define K2SIZE 0x20000000 -#if defined(CPU_R4000) +#if __mips == 3 #define KSBASE 0xe0000000 #define KSSIZE 0x20000000 #endif @@ -56,11 +56,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** Exception Vectors */ -#if defined(CPU_R3000) +#if __mips == 1 #define UT_VEC K0BASE /* utlbmiss vector */ #define E_VEC (K0BASE+0x80) /* exception vevtor */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ #define C_VEC (K0BASE+0x100) /* cache error vector */ @@ -89,7 +89,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define MINCACHE 0x200 /* 512 For 3041. */ #define MAXCACHE 0x40000 /* 256*1024 256k */ -#if defined(CPU_R4000) +#if __mips == 3 /* R4000 configuration register definitions */ #define CFG_CM 0x80000000 /* Master-Checker mode */ #define CFG_ECMASK 0x70000000 /* System Clock Ratio */ @@ -184,7 +184,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** TLB resource defines */ -#if defined(CPU_R3000) +#if __mips == 1 #define N_TLB_ENTRIES 64 #define TLB_PGSIZE 0x1000 #define RANDBASE 8 @@ -214,7 +214,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBCTXT_VPNMASK 0x001ffffc #define TLBCTXT_VPNSHIFT 2 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define N_TLB_ENTRIES 48 #define TLBHI_VPN2MASK 0xffffe000 @@ -249,7 +249,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBPGMASK_MASK 0x01ffe000 #endif -#if defined(CPU_R3000) +#if __mips == 1 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -300,7 +300,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -375,30 +375,30 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT */ #define C0_INX $0 /* tlb index */ #define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_TLBLO $2 /* tlb entry low */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_TLBLO0 $2 /* tlb entry low 0 */ #define C0_TLBLO1 $3 /* tlb entry low 1 */ #endif #define C0_CTXT $4 /* tlb context */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_PAGEMASK $5 /* tlb page mask */ #define C0_WIRED $6 /* number of wired tlb entries */ #endif #define C0_BADVADDR $8 /* bad virtual address */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COUNT $9 /* cycle count */ #endif #define C0_TLBHI $10 /* tlb entry hi */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COMPARE $11 /* cyccle count comparator */ #endif @@ -407,11 +407,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define C0_EPC $14 /* exception pc */ #define C0_PRID $15 /* revision identifier */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_CONFIG $3 /* configuration register R3081*/ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_CONFIG $16 /* configuration register */ #define C0_LLADDR $17 /* linked load address */ #define C0_WATCHLO $18 /* watchpoint trap register */ diff --git a/cpukit/score/cpu/mips/iregdef.h b/cpukit/score/cpu/mips/iregdef.h index f0953da852..ca50207a3b 100644 --- a/cpukit/score/cpu/mips/iregdef.h +++ b/cpukit/score/cpu/mips/iregdef.h @@ -221,10 +221,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_SR 67 #define R_CAUSE 68 #define R_TLBHI 69 -#if defined(CPU_R3000) +#if __mips == 1 #define R_TLBLO 70 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO0 70 #endif #define R_BADVADDR 71 @@ -236,10 +236,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_PRID 77 #define R_FCSR 78 #define R_FEIR 79 -#if defined(CPU_R3000) +#if __mips == 1 #define NREGS 80 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO1 80 #define R_PAGEMASK 81 #define R_WIRED 82 @@ -296,15 +296,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_RA R_R31 /* Ketan added the following */ -#ifdef CPU_R3000 +#ifdef __mips == 1 #define sreg sw #define lreg lw #define rmfc0 mfc0 #define rmtc0 mtc0 #define R_SZ 4 -#endif CPU_R3000 +#endif /* __mips == 1 */ -#ifdef CPU_R4000 +/* #ifdef __mips == 3 */ #if __mips < 3 #define sreg sw #define lreg lw @@ -318,7 +318,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define rmtc0 dmtc0 #define R_SZ 8 #endif -#endif CPU_R4000 +/* #endif __mips == 3 */ /* Ketan till here */ #endif /* __IREGDEF_H__ */ diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h index edabbe8fcc..060be295bf 100644 --- a/cpukit/score/cpu/mips/rtems/asm.h +++ b/cpukit/score/cpu/mips/rtems/asm.h @@ -24,8 +24,8 @@ */ /* @(#)asm.h 03/15/96 1.1 */ -#ifndef __MIPS64ORION_ASM_h -#define __MIPS64ORION_ASM_h +#ifndef __NO_CPU_ASM_h +#define __NO_CPU_ASM_h /* * Indicate we are in an assembly file and get the basic CPU definitions. @@ -96,7 +96,27 @@ #define PUBLIC(sym) .globl SYM (sym) #define EXTERN(sym) .globl SYM (sym) +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif XDS + #endif /* end of include file */ - diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h index f921e85ef6..cfb2fe626a 100644 --- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h +++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h @@ -45,7 +45,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define K1SIZE 0x20000000 #define K2BASE 0xc0000000 #define K2SIZE 0x20000000 -#if defined(CPU_R4000) +#if __mips == 3 #define KSBASE 0xe0000000 #define KSSIZE 0x20000000 #endif @@ -56,11 +56,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** Exception Vectors */ -#if defined(CPU_R3000) +#if __mips == 1 #define UT_VEC K0BASE /* utlbmiss vector */ #define E_VEC (K0BASE+0x80) /* exception vevtor */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ #define C_VEC (K0BASE+0x100) /* cache error vector */ @@ -89,7 +89,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define MINCACHE 0x200 /* 512 For 3041. */ #define MAXCACHE 0x40000 /* 256*1024 256k */ -#if defined(CPU_R4000) +#if __mips == 3 /* R4000 configuration register definitions */ #define CFG_CM 0x80000000 /* Master-Checker mode */ #define CFG_ECMASK 0x70000000 /* System Clock Ratio */ @@ -184,7 +184,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** TLB resource defines */ -#if defined(CPU_R3000) +#if __mips == 1 #define N_TLB_ENTRIES 64 #define TLB_PGSIZE 0x1000 #define RANDBASE 8 @@ -214,7 +214,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBCTXT_VPNMASK 0x001ffffc #define TLBCTXT_VPNSHIFT 2 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define N_TLB_ENTRIES 48 #define TLBHI_VPN2MASK 0xffffe000 @@ -249,7 +249,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBPGMASK_MASK 0x01ffe000 #endif -#if defined(CPU_R3000) +#if __mips == 1 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -300,7 +300,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -375,30 +375,30 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT */ #define C0_INX $0 /* tlb index */ #define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_TLBLO $2 /* tlb entry low */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_TLBLO0 $2 /* tlb entry low 0 */ #define C0_TLBLO1 $3 /* tlb entry low 1 */ #endif #define C0_CTXT $4 /* tlb context */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_PAGEMASK $5 /* tlb page mask */ #define C0_WIRED $6 /* number of wired tlb entries */ #endif #define C0_BADVADDR $8 /* bad virtual address */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COUNT $9 /* cycle count */ #endif #define C0_TLBHI $10 /* tlb entry hi */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COMPARE $11 /* cyccle count comparator */ #endif @@ -407,11 +407,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define C0_EPC $14 /* exception pc */ #define C0_PRID $15 /* revision identifier */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_CONFIG $3 /* configuration register R3081*/ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_CONFIG $16 /* configuration register */ #define C0_LLADDR $17 /* linked load address */ #define C0_WATCHLO $18 /* watchpoint trap register */ diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h index f0953da852..ca50207a3b 100644 --- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h +++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h @@ -221,10 +221,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_SR 67 #define R_CAUSE 68 #define R_TLBHI 69 -#if defined(CPU_R3000) +#if __mips == 1 #define R_TLBLO 70 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO0 70 #endif #define R_BADVADDR 71 @@ -236,10 +236,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_PRID 77 #define R_FCSR 78 #define R_FEIR 79 -#if defined(CPU_R3000) +#if __mips == 1 #define NREGS 80 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO1 80 #define R_PAGEMASK 81 #define R_WIRED 82 @@ -296,15 +296,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_RA R_R31 /* Ketan added the following */ -#ifdef CPU_R3000 +#ifdef __mips == 1 #define sreg sw #define lreg lw #define rmfc0 mfc0 #define rmtc0 mtc0 #define R_SZ 4 -#endif CPU_R3000 +#endif /* __mips == 1 */ -#ifdef CPU_R4000 +/* #ifdef __mips == 3 */ #if __mips < 3 #define sreg sw #define lreg lw @@ -318,7 +318,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define rmtc0 dmtc0 #define R_SZ 8 #endif -#endif CPU_R4000 +/* #endif __mips == 3 */ /* Ketan till here */ #endif /* __IREGDEF_H__ */ diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index 35d936ec7e..7527ddecdf 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -18,7 +18,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -93,7 +93,7 @@ extern void mips_fatal_error ( int error ); /* * Does RTEMS manage a dedicated interrupt stack in software? * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. * If FALSE, nothing is done. * * If the CPU supports a dedicated interrupt stack in hardware, @@ -162,19 +162,18 @@ extern void mips_fatal_error ( int error ); * If there is a FP coprocessor such as the i387 or mc68881, then * the answer is TRUE. * - * The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific. + * The macro name "MIPS_HAS_FPU" should be made CPU specific. * It indicates whether or not this CPU model has FP support. For * example, it would be possible to have an i386_nofp CPU model * which set this to false to indicate that you have an i386 without * an i387 and wish to leave floating point support out of RTEMS. */ -#if ( MIPS64ORION_HAS_FPU == 1 ) +#if ( MIPS_HAS_FPU == 1 ) #define CPU_HARDWARE_FP TRUE #else #define CPU_HARDWARE_FP FALSE #endif -#define CPU_SOFTWARE_FP FALSE /* * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? @@ -444,7 +443,7 @@ typedef struct { */ /* - * Macros to access MIPS64ORION specific additions to the CPU Table + * Macros to access MIPS specific additions to the CPU Table */ #define rtems_cpu_configuration_get_clicks_per_microsecond() \ diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 2ec96da0a4..90e959bd47 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -15,7 +15,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -28,8 +28,8 @@ */ /* @(#)mips64orion.h 08/29/96 1.3 */ -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h +#ifndef _INCLUDE_MIPS_h +#define _INCLUDE_MIPS_h #ifdef __cplusplus extern "C" { @@ -44,40 +44,33 @@ extern "C" { * of the family. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" #else - -#error "Unsupported CPU Model" - +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" #endif /* * Define the name of the CPU family. */ -#define CPU_NAME "MIPS R46xxx" +#define CPU_NAME "MIPS" #ifdef __cplusplus } #endif -#endif /* ! _INCLUDE_MIPS64ORION_h */ +#endif /* ! _INCLUDE_MIPS_h */ /* end of include file */ |