diff options
| -rw-r--r-- | c/src/exec/score/cpu/mips/ChangeLog | 7 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/mips/cpu_asm.S | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/ChangeLog | 7 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/cpu_asm.S | 4 |
4 files changed, 16 insertions, 6 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index b17132b015..0480a7d542 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2002-07-16 Greg Menke <gregory.menke@gsfc.nasa.gov> + + * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled + deadlock caused by interrupt arriving while dispatching. + 2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * configure.ac: RTEMS_TOP(../../../..). @@ -72,7 +77,7 @@ end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it - to obtain FPU defines without systax errors generated by the C + to obtain FPU defines without syntax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores. diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S index 657c490d96..9614705e44 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ b/c/src/exec/score/cpu/mips/cpu_asm.S @@ -56,7 +56,7 @@ * left it in... */ -#define INSTRUMENT_ISR_VECTORING +/* #define INSTRUMENT_ISR_VECTORING */ /* #define INSTRUMENT_EXECUTING_THREAD */ @@ -484,7 +484,7 @@ _CPU_Context_switch_restore: #if __mips == 3 or t2,SR_EXL + SR_IE #elif __mips == 1 - or t2,SR_IEC + SR_IEP /* save current & previous int enable */ + or t2,SR_IEC + SR_IEP + SR_IEO /* save current & previous int enable */ #endif and t0,t2 /* keep only the per-task bits */ diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index b17132b015..0480a7d542 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2002-07-16 Greg Menke <gregory.menke@gsfc.nasa.gov> + + * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled + deadlock caused by interrupt arriving while dispatching. + 2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * configure.ac: RTEMS_TOP(../../../..). @@ -72,7 +77,7 @@ end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it - to obtain FPU defines without systax errors generated by the C + to obtain FPU defines without syntax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores. diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S index 657c490d96..9614705e44 100644 --- a/cpukit/score/cpu/mips/cpu_asm.S +++ b/cpukit/score/cpu/mips/cpu_asm.S @@ -56,7 +56,7 @@ * left it in... */ -#define INSTRUMENT_ISR_VECTORING +/* #define INSTRUMENT_ISR_VECTORING */ /* #define INSTRUMENT_EXECUTING_THREAD */ @@ -484,7 +484,7 @@ _CPU_Context_switch_restore: #if __mips == 3 or t2,SR_EXL + SR_IE #elif __mips == 1 - or t2,SR_IEC + SR_IEP /* save current & previous int enable */ + or t2,SR_IEC + SR_IEP + SR_IEO /* save current & previous int enable */ #endif and t0,t2 /* keep only the per-task bits */ |