diff options
| -rw-r--r-- | c/src/lib/libbsp/i386/ChangeLog | 12 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i386/shared/irq/irq_asm.S | 13 |
2 files changed, 23 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/i386/ChangeLog b/c/src/lib/libbsp/i386/ChangeLog index 0ee055b220..57ac17391a 100644 --- a/c/src/lib/libbsp/i386/ChangeLog +++ b/c/src/lib/libbsp/i386/ChangeLog @@ -1,3 +1,15 @@ +2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> + + PR 1729/cpukit + * shared/irq/irq_asm.S: Add next step in SMP support. This adds an + allocated array of the Per_CPU structures to support multiple cpus vs + a single instance of the structure which is still used if SMP support + is disabled. Configuration support is also added to explicitly enable + or disable SMP. But SMP can only be enabled for the CPUs which will + support it initially -- SPARC and i386. With the stub BSP support, a + BSP can be run as a single core SMP system from an RTEMS data + structure standpoint. + 2011-03-01 Ralf Corsépius <ralf.corsepius@rtems.org> * acinclude.m4: Regenerate (Reflect the i386ex and tx_386ex BSP have diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S index 8634a25589..d899f47448 100644 --- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S +++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S @@ -4,6 +4,9 @@ * * Copyright (C) 1998 valette@crf.canon.fr * + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. @@ -12,6 +15,7 @@ */ #include <rtems/asm.h> +#include <rtems/system.h> #include <bspopts.h> #include <bsp/irq_asm.h> #include <rtems/score/cpu.h> @@ -140,8 +144,13 @@ PUBLIC (ISR_STOP) ISR_STOP: .check_stack_switch: movl esp, ebp /* ebp = previous stack pointer */ - - movl $SYM(_Per_CPU_Information), ebx +#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP) + movl $SYM(_Per_CPU_Information_p), ebx + call SYM(bsp_smp_processor_id) + mov (ebx,eax,4), ebx +#else + movl $SYM(_Per_CPU_Information), ebx +#endif /* is this the outermost interrupt? */ cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx) |