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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-09-02 15:29:10 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-03-24 11:10:48 +0100 |
commit | aebf6b661954b4b0ca65342af504b41631bdef78 (patch) | |
tree | d8fe9135b523c81b4efa661513979397e42bd2f7 /testsuites/validation/tc-intr-raise-on.c | |
parent | validation: Test Event Manager (diff) | |
download | rtems-aebf6b661954b4b0ca65342af504b41631bdef78.tar.bz2 |
validation: Test Interrupt Manager
The test source code is generated from specification items
by the "./spec2modules.py" script contained in the
git://git.rtems.org/rtems-central.git Git repository.
Please read the "How-To" section in the "Software Requirements Engineering"
chapter of the RTEMS Software Engineering manual to get more information about
the process.
Update #3716.
Diffstat (limited to 'testsuites/validation/tc-intr-raise-on.c')
-rw-r--r-- | testsuites/validation/tc-intr-raise-on.c | 70 |
1 files changed, 44 insertions, 26 deletions
diff --git a/testsuites/validation/tc-intr-raise-on.c b/testsuites/validation/tc-intr-raise-on.c index efe468aebd..4d305258b3 100644 --- a/testsuites/validation/tc-intr-raise-on.c +++ b/testsuites/validation/tc-intr-raise-on.c @@ -63,7 +63,7 @@ /** * @defgroup RTEMSTestCaseRtemsIntrReqRaiseOn spec:/rtems/intr/req/raise-on * - * @ingroup RTEMSTestSuiteTestsuitesValidation0 + * @ingroup RTEMSTestSuiteTestsuitesValidationIntr * * @{ */ @@ -154,6 +154,12 @@ typedef struct { struct { /** + * @brief This member defines the pre-condition indices for the next + * action. + */ + size_t pci[ 3 ]; + + /** * @brief This member defines the pre-condition states for the next action. */ size_t pcs[ 3 ]; @@ -332,21 +338,21 @@ static void CheckRaiseOn( T_rsc_success( sc ); if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) { - T_false( IsPending( ctx ) ); + Disable( ctx ); + RaiseOn( ctx ); - if ( attr->can_disable ) { - Disable( ctx ); - RaiseOn( ctx ); - T_true( IsPending( ctx ) ); + /* + * Some interrupt controllers will signal a pending interrupt if it is + * disabled (for example ARM GIC), others will not signal a pending + * interrupt if it is disabled (for example Freescale/NXP MPIC). + */ + (void) IsPending( ctx ); - sc = rtems_interrupt_vector_enable( ctx->vector ); - T_rsc_success( sc ); + sc = rtems_interrupt_vector_enable( ctx->vector ); + T_rsc_success( sc ); - while ( ctx->interrupt_count < 1 ) { - /* Wait */ - } - } else { - ++ctx->interrupt_count; + while ( ctx->interrupt_count < 1 ) { + /* Wait */ } T_false( IsPending( ctx ) ); @@ -672,14 +678,25 @@ static inline RtemsIntrReqRaiseOn_Entry RtemsIntrReqRaiseOn_PopEntry( ]; } +static void RtemsIntrReqRaiseOn_SetPreConditionStates( + RtemsIntrReqRaiseOn_Context *ctx +) +{ + ctx->Map.pcs[ 0 ] = ctx->Map.pci[ 0 ]; + ctx->Map.pcs[ 1 ] = ctx->Map.pci[ 1 ]; + + if ( ctx->Map.entry.Pre_CanRaiseOn_NA ) { + ctx->Map.pcs[ 2 ] = RtemsIntrReqRaiseOn_Pre_CanRaiseOn_NA; + } else { + ctx->Map.pcs[ 2 ] = ctx->Map.pci[ 2 ]; + } +} + static void RtemsIntrReqRaiseOn_TestVariant( RtemsIntrReqRaiseOn_Context *ctx ) { RtemsIntrReqRaiseOn_Pre_Vector_Prepare( ctx, ctx->Map.pcs[ 0 ] ); RtemsIntrReqRaiseOn_Pre_CPU_Prepare( ctx, ctx->Map.pcs[ 1 ] ); - RtemsIntrReqRaiseOn_Pre_CanRaiseOn_Prepare( - ctx, - ctx->Map.entry.Pre_CanRaiseOn_NA ? RtemsIntrReqRaiseOn_Pre_CanRaiseOn_NA : ctx->Map.pcs[ 2 ] - ); + RtemsIntrReqRaiseOn_Pre_CanRaiseOn_Prepare( ctx, ctx->Map.pcs[ 2 ] ); RtemsIntrReqRaiseOn_Action( ctx ); RtemsIntrReqRaiseOn_Post_Status_Check( ctx, ctx->Map.entry.Post_Status ); RtemsIntrReqRaiseOn_Post_Pending_Check( ctx, ctx->Map.entry.Post_Pending ); @@ -697,19 +714,19 @@ T_TEST_CASE_FIXTURE( RtemsIntrReqRaiseOn, &RtemsIntrReqRaiseOn_Fixture ) ctx->Map.index = 0; for ( - ctx->Map.pcs[ 0 ] = RtemsIntrReqRaiseOn_Pre_Vector_Valid; - ctx->Map.pcs[ 0 ] < RtemsIntrReqRaiseOn_Pre_Vector_NA; - ++ctx->Map.pcs[ 0 ] + ctx->Map.pci[ 0 ] = RtemsIntrReqRaiseOn_Pre_Vector_Valid; + ctx->Map.pci[ 0 ] < RtemsIntrReqRaiseOn_Pre_Vector_NA; + ++ctx->Map.pci[ 0 ] ) { for ( - ctx->Map.pcs[ 1 ] = RtemsIntrReqRaiseOn_Pre_CPU_Online; - ctx->Map.pcs[ 1 ] < RtemsIntrReqRaiseOn_Pre_CPU_NA; - ++ctx->Map.pcs[ 1 ] + ctx->Map.pci[ 1 ] = RtemsIntrReqRaiseOn_Pre_CPU_Online; + ctx->Map.pci[ 1 ] < RtemsIntrReqRaiseOn_Pre_CPU_NA; + ++ctx->Map.pci[ 1 ] ) { for ( - ctx->Map.pcs[ 2 ] = RtemsIntrReqRaiseOn_Pre_CanRaiseOn_Yes; - ctx->Map.pcs[ 2 ] < RtemsIntrReqRaiseOn_Pre_CanRaiseOn_NA; - ++ctx->Map.pcs[ 2 ] + ctx->Map.pci[ 2 ] = RtemsIntrReqRaiseOn_Pre_CanRaiseOn_Yes; + ctx->Map.pci[ 2 ] < RtemsIntrReqRaiseOn_Pre_CanRaiseOn_NA; + ++ctx->Map.pci[ 2 ] ) { ctx->Map.entry = RtemsIntrReqRaiseOn_PopEntry( ctx ); @@ -717,6 +734,7 @@ T_TEST_CASE_FIXTURE( RtemsIntrReqRaiseOn, &RtemsIntrReqRaiseOn_Fixture ) continue; } + RtemsIntrReqRaiseOn_SetPreConditionStates( ctx ); RtemsIntrReqRaiseOn_TestVariant( ctx ); } } |