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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-09-02 15:29:10 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-03-24 11:10:48 +0100 |
commit | aebf6b661954b4b0ca65342af504b41631bdef78 (patch) | |
tree | d8fe9135b523c81b4efa661513979397e42bd2f7 /testsuites/validation/tc-intr-is-pending.c | |
parent | validation: Test Event Manager (diff) | |
download | rtems-aebf6b661954b4b0ca65342af504b41631bdef78.tar.bz2 |
validation: Test Interrupt Manager
The test source code is generated from specification items
by the "./spec2modules.py" script contained in the
git://git.rtems.org/rtems-central.git Git repository.
Please read the "How-To" section in the "Software Requirements Engineering"
chapter of the RTEMS Software Engineering manual to get more information about
the process.
Update #3716.
Diffstat (limited to 'testsuites/validation/tc-intr-is-pending.c')
-rw-r--r-- | testsuites/validation/tc-intr-is-pending.c | 87 |
1 files changed, 57 insertions, 30 deletions
diff --git a/testsuites/validation/tc-intr-is-pending.c b/testsuites/validation/tc-intr-is-pending.c index 4963827538..93be686038 100644 --- a/testsuites/validation/tc-intr-is-pending.c +++ b/testsuites/validation/tc-intr-is-pending.c @@ -63,7 +63,7 @@ /** * @defgroup RTEMSTestCaseRtemsIntrReqIsPending spec:/rtems/intr/req/is-pending * - * @ingroup RTEMSTestSuiteTestsuitesValidation0 + * @ingroup RTEMSTestSuiteTestsuitesValidationIntr * * @{ */ @@ -152,6 +152,12 @@ typedef struct { struct { /** + * @brief This member defines the pre-condition indices for the next + * action. + */ + size_t pci[ 3 ]; + + /** * @brief This member defines the pre-condition states for the next action. */ size_t pcs[ 3 ]; @@ -284,14 +290,21 @@ static void CheckIsPending( if ( has_installed_entries ) { /* * We cannot test this vector thoroughly, since it is used by a device - * driver. + * driver. It may be pending or not. For example in SMP configurations, + * it may be pending while being serviced right now on another processor. */ - T_false( IsPending( ctx ) ); + (void) IsPending( ctx ); } else if ( !attr->is_maskable ) { /* We can only safely test maskable interrupts */ T_false( IsPending( ctx ) ); + } else if ( IsPending( ctx ) ) { + /* + * If there is already an interrupt pending, then it is probably raised + * by a peripheral which we cannot control. + */ } else if ( - attr->can_disable && ( attr->can_clear || attr->cleared_by_acknowledge ) + attr->can_raise && attr->can_disable && + ( attr->can_clear || attr->cleared_by_acknowledge ) ) { rtems_interrupt_entry entry; rtems_interrupt_level level; @@ -307,19 +320,21 @@ static void CheckIsPending( T_rsc_success( sc ); if ( !IsPending( ctx) && ( attr->can_enable || IsEnabled( ctx ) ) ) { - if ( attr->can_disable ) { - Disable( ctx ); - Raise( ctx ); - T_true( IsPending( ctx ) ); - - sc = rtems_interrupt_vector_enable( ctx->vector ); - T_rsc_success( sc ); - - while ( ctx->interrupt_count < 1 ) { - /* Wait */ - } - } else { - ++ctx->interrupt_count; + Disable( ctx ); + Raise( ctx ); + + /* + * Some interrupt controllers will signal a pending interrupt if it is + * disabled (for example ARM GIC), others will not signal a pending + * interrupt if it is disabled (for example Freescale/NXP MPIC). + */ + (void) IsPending( ctx ); + + sc = rtems_interrupt_vector_enable( ctx->vector ); + T_rsc_success( sc ); + + while ( ctx->interrupt_count < 1 ) { + /* Wait */ } rtems_interrupt_local_disable( level ); @@ -593,16 +608,27 @@ static inline RtemsIntrReqIsPending_Entry RtemsIntrReqIsPending_PopEntry( ]; } +static void RtemsIntrReqIsPending_SetPreConditionStates( + RtemsIntrReqIsPending_Context *ctx +) +{ + ctx->Map.pcs[ 0 ] = ctx->Map.pci[ 0 ]; + ctx->Map.pcs[ 1 ] = ctx->Map.pci[ 1 ]; + + if ( ctx->Map.entry.Pre_IsPending_NA ) { + ctx->Map.pcs[ 2 ] = RtemsIntrReqIsPending_Pre_IsPending_NA; + } else { + ctx->Map.pcs[ 2 ] = ctx->Map.pci[ 2 ]; + } +} + static void RtemsIntrReqIsPending_TestVariant( RtemsIntrReqIsPending_Context *ctx ) { RtemsIntrReqIsPending_Pre_Vector_Prepare( ctx, ctx->Map.pcs[ 0 ] ); RtemsIntrReqIsPending_Pre_Pending_Prepare( ctx, ctx->Map.pcs[ 1 ] ); - RtemsIntrReqIsPending_Pre_IsPending_Prepare( - ctx, - ctx->Map.entry.Pre_IsPending_NA ? RtemsIntrReqIsPending_Pre_IsPending_NA : ctx->Map.pcs[ 2 ] - ); + RtemsIntrReqIsPending_Pre_IsPending_Prepare( ctx, ctx->Map.pcs[ 2 ] ); RtemsIntrReqIsPending_Action( ctx ); RtemsIntrReqIsPending_Post_Status_Check( ctx, ctx->Map.entry.Post_Status ); RtemsIntrReqIsPending_Post_IsPending_Check( @@ -623,21 +649,22 @@ T_TEST_CASE_FIXTURE( RtemsIntrReqIsPending, &RtemsIntrReqIsPending_Fixture ) ctx->Map.index = 0; for ( - ctx->Map.pcs[ 0 ] = RtemsIntrReqIsPending_Pre_Vector_Valid; - ctx->Map.pcs[ 0 ] < RtemsIntrReqIsPending_Pre_Vector_NA; - ++ctx->Map.pcs[ 0 ] + ctx->Map.pci[ 0 ] = RtemsIntrReqIsPending_Pre_Vector_Valid; + ctx->Map.pci[ 0 ] < RtemsIntrReqIsPending_Pre_Vector_NA; + ++ctx->Map.pci[ 0 ] ) { for ( - ctx->Map.pcs[ 1 ] = RtemsIntrReqIsPending_Pre_Pending_Obj; - ctx->Map.pcs[ 1 ] < RtemsIntrReqIsPending_Pre_Pending_NA; - ++ctx->Map.pcs[ 1 ] + ctx->Map.pci[ 1 ] = RtemsIntrReqIsPending_Pre_Pending_Obj; + ctx->Map.pci[ 1 ] < RtemsIntrReqIsPending_Pre_Pending_NA; + ++ctx->Map.pci[ 1 ] ) { for ( - ctx->Map.pcs[ 2 ] = RtemsIntrReqIsPending_Pre_IsPending_Yes; - ctx->Map.pcs[ 2 ] < RtemsIntrReqIsPending_Pre_IsPending_NA; - ++ctx->Map.pcs[ 2 ] + ctx->Map.pci[ 2 ] = RtemsIntrReqIsPending_Pre_IsPending_Yes; + ctx->Map.pci[ 2 ] < RtemsIntrReqIsPending_Pre_IsPending_NA; + ++ctx->Map.pci[ 2 ] ) { ctx->Map.entry = RtemsIntrReqIsPending_PopEntry( ctx ); + RtemsIntrReqIsPending_SetPreConditionStates( ctx ); RtemsIntrReqIsPending_TestVariant( ctx ); } } |