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authorSebastian Huber <sebastian.huber@embedded-brains.de>2013-08-05 14:54:11 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2013-08-09 23:02:38 +0200
commitd19cce29dcaffa7c679407bc211ee09c2d9dc40a (patch)
tree2e0eb6211f0199680fcf9445b644a25495e53732 /testsuites/sptests/sp37
parentscore: Add and use _Per_CPU_Acquire_all(). (diff)
downloadrtems-d19cce29dcaffa7c679407bc211ee09c2d9dc40a.tar.bz2
score: Per-CPU thread dispatch disable level
Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
Diffstat (limited to 'testsuites/sptests/sp37')
-rw-r--r--testsuites/sptests/sp37/init.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c
index cd4e516d62..efb92b82a2 100644
--- a/testsuites/sptests/sp37/init.c
+++ b/testsuites/sptests/sp37/init.c
@@ -348,7 +348,11 @@ rtems_timer_service_routine test_unblock_task(
_Thread_Disable_dispatch();
status = rtems_task_resume( blocked_task_id );
_Thread_Unnest_dispatch();
+#if defined( RTEMS_SMP )
directive_failed_with_level( status, "rtems_task_resume", 1 );
+#else
+ directive_failed( status, "rtems_task_resume" );
+#endif
}
rtems_task Init(
@@ -383,9 +387,7 @@ rtems_task Init(
/*
* Test clock tick from outside ISR
*/
- _Thread_Disable_dispatch();
status = rtems_clock_tick();
- _Thread_Enable_dispatch();
directive_failed( status, "rtems_clock_tick" );
puts( "clock_tick from task level" );
@@ -422,9 +424,7 @@ rtems_task Init(
/* we expect to be preempted from this call */
for ( i=0 ; i<100 && blocked_task_status != 3 ; i++ ) {
- _Thread_Disable_dispatch();
status = rtems_clock_tick();
- _Thread_Enable_dispatch();
directive_failed( status, "rtems_clock_tick" );
}
switch ( blocked_task_status ) {