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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-01-05 11:17:08 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-01-05 11:17:08 -0600 |
| commit | b6c1578bb91fb54c826141e0f8bbd9cb2009f3cf (patch) | |
| tree | 6d4c9af3892de78428add886865bae7db15efbc1 /testsuites/rhealstone/rhilatency/rhilatency.adoc | |
| parent | rhealstone/*.c: Add Print_Warning() call to indicate debug enabled (diff) | |
| download | rtems-b6c1578bb91fb54c826141e0f8bbd9cb2009f3cf.tar.bz2 | |
rhealstone: Add rh prefix to all test names
This makes them easier to spot as a group in wildcard searches.
Diffstat (limited to 'testsuites/rhealstone/rhilatency/rhilatency.adoc')
| -rw-r--r-- | testsuites/rhealstone/rhilatency/rhilatency.adoc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuites/rhealstone/rhilatency/rhilatency.adoc b/testsuites/rhealstone/rhilatency/rhilatency.adoc new file mode 100644 index 0000000000..2f8a980142 --- /dev/null +++ b/testsuites/rhealstone/rhilatency/rhilatency.adoc @@ -0,0 +1,21 @@ += Interrupt Latency Benchmark + +This benchmark measures the time between the CPU's receipt of an interrupt +request and the execution of the first intruction in that interrupt service +routine. + +== Directives + + * Intall_tm27_vector + * Cause_tm27_intr + + +== Methodology + +This benchmark takes advantage of the existing tm27 test support implemented +by most BSP's to achieve as much hardware independence as possible. Most BSPs +have an instruction to install an interrupt vector, and then provide code for +the ISR. rtems/testsuites/tmtests/tm27 uses this to test a variety of interrupt +related concepts. The benchmark is simple, the vector is installed, the time +is started, the interrupt is caused, and the time is ended in the first +instruction of the ISR. This is the only Rhealstone that is not an average. |