bsps/arm: Add BSP for ZynqMP RPU

17 files changed, 385 insertions, 2 deletions

diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
new file mode 100644
index 0000000000..ba70c44d7d
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+default:
+- enabled-by: true
+  value:
+  - -march=armv7-r
+  - -mthumb
+  - -mfpu=vfpv3-d16
+  - -mfloat-abi=hard
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
new file mode 100644
index 0000000000..d08f048060
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
@@ -0,0 +1,96 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: xilinx_zynqmp_mercuryxu5_rpu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+cppflags: []
+enabled-by: true
+family: xilinx-zynqmp-rpu
+includes:
+- bsps/include/xil/
+- bsps/include/xil/${XIL_SUPPORT_PATH}/
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
+- destination: ${BSP_INCLUDEDIR}/peripheral_maps
+  source:
+  - bsps/include/peripheral_maps/xilinx_zynqmp.h
+links:
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: ../start
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: optclkfastidle
+- role: build-dependency
+  uid: optclkuart
+- role: build-dependency
+  uid: optconirq
+- role: build-dependency
+  uid: ../../optconminor
+- role: build-dependency
+  uid: optint0len
+- role: build-dependency
+  uid: optint0ori
+- role: build-dependency
+  uid: optint1len
+- role: build-dependency
+  uid: optint1ori
+- role: build-dependency
+  uid: optramlen
+- role: build-dependency
+  uid: optramori
+- role: build-dependency
+  uid: optresetvec
+- role: build-dependency
+  uid: optnocachelen
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../objdevserialzynq
+- role: build-dependency
+  uid: ../../objdevspizynq
+- role: build-dependency
+  uid: ../../objdevspixil
+- role: build-dependency
+  uid: ../../objmem
+- role: build-dependency
+  uid: ../../opto0
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: ../../bspopts
+- role: build-dependency
+  uid: ../../objxilinxsupport
+source:
+- bsps/shared/cache/nocache.c
+- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
+- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+- bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
+- bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c
+- bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c
+- bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
+- bsps/shared/dev/clock/xil-ttc.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/gettargethash-default.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/start/stackalloc.c
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
new file mode 100644
index 0000000000..a3654f3f42
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
@@ -0,0 +1,46 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  MEMORY {
+    RAM_INT_0 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_0_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_0_LENGTH:#010x}
+    RAM_INT_1 : ORIGIN = ${ZYNQMP_RPU_RAM_INT_1_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_INT_1_LENGTH:#010x}
+    RAM       : ORIGIN = ${ZYNQMP_RPU_RAM_ORIGIN:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_ORIGIN:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}
+    NOCACHE   : ORIGIN = ${ZYNQMP_RPU_RAM_LENGTH:#010x} - ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}, LENGTH = ${ZYNQMP_RPU_RAM_NOCACHE_LENGTH:#010x}
+  }
+
+  REGION_ALIAS ("REGION_START",          RAM_INT_0);
+  REGION_ALIAS ("REGION_VECTOR",         RAM_INT_0);
+  REGION_ALIAS ("REGION_TEXT",           RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
+  REGION_ALIAS ("REGION_RODATA",         RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
+  REGION_ALIAS ("REGION_DATA",           RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",      RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",            RAM);
+  REGION_ALIAS ("REGION_WORK",           RAM);
+  REGION_ALIAS ("REGION_STACK",          RAM);
+  REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  INCLUDE linkcmds.armv4
+
+  # define symbols needed by the R5 xil_cache.c
+  _stack_end = bsp_section_stack_end;
+  __undef_stack = bsp_section_stack_begin;
+copyrights:
+- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml
new file mode 100644
index 0000000000..e303a8bf9f
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by:
+  - arm/lm3s6965_qemu
+  - arm/realview_pbx_a9_qemu
+  - arm/xilinx_zynq_a9_qemu
+  value: true
+- enabled-by: true
+  value: false
+description: |
+  This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing.  This can significantly reduce simulation times.
+enabled-by: true
+links: []
+name: CLOCK_DRIVER_USE_FAST_IDLE
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml
new file mode 100644
index 0000000000..77c8f30fff
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 100000000
+description: |
+  Zynq UART clock frequency in Hz
+enabled-by: true
+format: '{}'
+links: []
+name: ZYNQ_CLOCK_UART
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml
new file mode 100644
index 0000000000..ea13fa4561
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: true
+description: |
+  use interrupt driven mode for console devices (used by default)
+enabled-by: true
+links: []
+name: ZYNQ_CONSOLE_USE_INTERRUPTS
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml
new file mode 100644
index 0000000000..13b436ad2e
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00010000
+description: ''
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_INT_0_LENGTH
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml
new file mode 100644
index 0000000000..b33306b28e
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00000000
+description: ''
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_INT_0_ORIGIN
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml
new file mode 100644
index 0000000000..093aff6eb4
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00010000
+description: ''
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_INT_1_LENGTH
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml
new file mode 100644
index 0000000000..5574289975
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00020000
+description: ''
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_INT_1_ORIGIN
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml
new file mode 100644
index 0000000000..017c02235c
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00100000
+description: |
+  length of nocache RAM region
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_NOCACHE_LENGTH
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
new file mode 100644
index 0000000000..09a3965906
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 Reflex Aerospace GmbH ( https://www.reflexaerospace.com/ )
+default:
+- enabled-by: true
+  value: true
+description: |
+  Sets the target processing unit to the RPU (R5F) cores.
+enabled-by: true
+format: '{}'
+links: []
+name: ZYNQMP_PROC_UNIT_RPU
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml
new file mode 100644
index 0000000000..966ae09b19
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: arm/xilinx_zynqmp_ultra96
+  value: 0x80000000
+- enabled-by: true
+  value: 0x10000000
+description: |
+  override a BSP's default RAM length
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_LENGTH
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml
new file mode 100644
index 0000000000..ceb8401c37
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- assert-aligned: 1048576
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 0x00100000
+description: ''
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQMP_RPU_RAM_ORIGIN
+type: build
diff --git a/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml
new file mode 100644
index 0000000000..bac5c79627
--- /dev/null
+++ b/spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: false
+description: |
+  reset vector address for BSP start
+enabled-by: true
+links: []
+name: BSP_START_RESET_VECTOR
+type: build
diff --git a/spec/build/bsps/objxilinxsupportr5.yml b/spec/build/bsps/objxilinxsupportr5.yml
index db402af8ca..d800b83247 100644
--- a/spec/build/bsps/objxilinxsupportr5.yml
+++ b/spec/build/bsps/objxilinxsupportr5.yml
@@ -5,7 +5,8 @@ copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 cppflags: []
 cxxflags: []
-enabled-by: false
+enabled-by:
+- arm/xilinx_zynqmp_mercuryxu5_rpu
 includes: []
 install:
 - destination: ${BSP_INCLUDEDIR}
diff --git a/spec/build/bsps/optxilsupportpath.yml b/spec/build/bsps/optxilsupportpath.yml
index 7c6daa9043..85bcc7e059 100644
--- a/spec/build/bsps/optxilsupportpath.yml
+++ b/spec/build/bsps/optxilsupportpath.yml
@@ -6,7 +6,8 @@ build-type: option
 copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 default:
-- enabled-by: []
+- enabled-by:
+  - arm/xilinx_zynqmp_mercuryxu5_rpu
   value: arm/cortexr5
 - enabled-by: bsps/microblaze/microblaze_fpga
   value: microblaze