diff options
author | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2023-11-21 15:54:34 +0100 |
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committer | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2023-11-28 13:36:41 +0100 |
commit | 02f2316be7aff38f657cdae1a332ff161a6d7292 (patch) | |
tree | 3f67c1b5115a73dc9cb50d20b5c6b61df05b6a4c /spec | |
parent | bsps/imx*: imx_gpio from pointer to fdt property (diff) | |
download | rtems-02f2316be7aff38f657cdae1a332ff161a6d7292.tar.bz2 |
bsp/imxrt1166: Support GPIO CS pins in LPSPI
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
Diffstat (limited to 'spec')
-rw-r--r-- | spec/build/bsps/arm/imxrt/grp.yml | 2 | ||||
-rw-r--r-- | spec/build/bsps/arm/imxrt/optlpspimaxcs.yml | 21 |
2 files changed, 23 insertions, 0 deletions
diff --git a/spec/build/bsps/arm/imxrt/grp.yml b/spec/build/bsps/arm/imxrt/grp.yml index 6191823899..12e50c5376 100644 --- a/spec/build/bsps/arm/imxrt/grp.yml +++ b/spec/build/bsps/arm/imxrt/grp.yml @@ -25,6 +25,8 @@ links: - role: build-dependency uid: optlinkcmds - role: build-dependency + uid: optlpspimaxcs +- role: build-dependency uid: optmemdtcmsz - role: build-dependency uid: optmemextramnocachesz diff --git a/spec/build/bsps/arm/imxrt/optlpspimaxcs.yml b/spec/build/bsps/arm/imxrt/optlpspimaxcs.yml new file mode 100644 index 0000000000..d7cc0ff644 --- /dev/null +++ b/spec/build/bsps/arm/imxrt/optlpspimaxcs.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2023 embedded brains GmbH & Co. KG +default: +- enabled-by: arm/imxrt1166-cm7-saltshaker + value: 8 +- enabled-by: true + value: 0 +description: | + Maximum number of (combined) native and GPIO chip selects per LPSPI. If only + native chip selects are used, this can be set to 0 to save some processing + cycles on SPI transfers. Otherwise you have to set it to at least 4. +enabled-by: true +format: '{}' +links: [] +name: IMXRT_LPSPI_MAX_CS +type: build |