diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-12 10:26:38 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-17 08:31:48 +0100 |
commit | d2664faa39cfd17fa20c84d0ff1623335c21bdac (patch) | |
tree | c6503cc795816f0c4f03ed74fd764878e017979b /spec/build/cpukit | |
parent | build: Format build items (diff) | |
download | rtems-d2664faa39cfd17fa20c84d0ff1623335c21bdac.tar.bz2 |
build: Replace variant patterns with a list
Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
Diffstat (limited to 'spec/build/cpukit')
-rw-r--r-- | spec/build/cpukit/optarchbits.yml | 21 | ||||
-rw-r--r-- | spec/build/cpukit/optboothartid.yml | 2 |
2 files changed, 17 insertions, 6 deletions
diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml index 0ec4a9fe7e..ba8d52aa61 100644 --- a/spec/build/cpukit/optarchbits.yml +++ b/spec/build/cpukit/optarchbits.yml @@ -11,15 +11,26 @@ default-by-variant: - value: - '64' variants: - - riscv/mpfs64.* - - riscv/noel64.* - - riscv/rv64.* + - riscv/mpfs64imafdc + - riscv/noel64imac + - riscv/noel64imafd + - riscv/noel64imafdc + - riscv/rv64imac + - riscv/rv64imafd + - riscv/rv64imafdc - value: - '32' variants: - riscv/griscv - - riscv/noel32.* - - riscv/rv32.* + - riscv/noel32im + - riscv/noel32imafd + - riscv/rv32i + - riscv/rv32iac + - riscv/rv32im + - riscv/rv32imac + - riscv/rv32imafc + - riscv/rv32imafd + - riscv/rv32imafdc description: The architecture word bits for the clang target triple. enabled-by: - and: diff --git a/spec/build/cpukit/optboothartid.yml b/spec/build/cpukit/optboothartid.yml index f6cf6da6d4..e23154d4b4 100644 --- a/spec/build/cpukit/optboothartid.yml +++ b/spec/build/cpukit/optboothartid.yml @@ -9,7 +9,7 @@ default: 0 default-by-variant: - value: 1 variants: - - riscv/mpfs64.* + - riscv/mpfs64imafdc description: | boot hartid (processor number) of risc-v cpu (default 0) enabled-by: riscv |