diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-07-01 15:21:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-07-12 08:26:46 +0200 |
| commit | 5cc075712e628191477d0c9d074e15b6a7c1e1e3 (patch) | |
| tree | 0c56dc58c1dc73e06dcec72f8e8933183e5fff5f /spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml | |
| parent | bsps/m68k/uC5282: Change license to BSD-2 (diff) | |
| download | rtems-5cc075712e628191477d0c9d074e15b6a7c1e1e3.tar.bz2 | |
irq/arm-gicv3.h: Customize CPU Interface init
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
Diffstat (limited to 'spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml')
| -rw-r--r-- | spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml new file mode 100644 index 0000000000..aea536d7d1 --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 1 +default-by-variant: +- value: null + variants: + - aarch64/.* +description: | + Defines the initial value of the ICC_IGRPEN0 register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_IGRPEN0 +type: build |