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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-07-01 15:21:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-07-12 08:26:46 +0200 |
| commit | 5cc075712e628191477d0c9d074e15b6a7c1e1e3 (patch) | |
| tree | 0c56dc58c1dc73e06dcec72f8e8933183e5fff5f /spec/build/bsps/dev/irq/objarmgicv3.yml | |
| parent | bsps/m68k/uC5282: Change license to BSD-2 (diff) | |
| download | rtems-5cc075712e628191477d0c9d074e15b6a7c1e1e3.tar.bz2 | |
irq/arm-gicv3.h: Customize CPU Interface init
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
Diffstat (limited to 'spec/build/bsps/dev/irq/objarmgicv3.yml')
| -rw-r--r-- | spec/build/bsps/dev/irq/objarmgicv3.yml | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/spec/build/bsps/dev/irq/objarmgicv3.yml b/spec/build/bsps/dev/irq/objarmgicv3.yml new file mode 100644 index 0000000000..aa84ae5416 --- /dev/null +++ b/spec/build/bsps/dev/irq/objarmgicv3.yml @@ -0,0 +1,31 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/dev/irq + source: + - bsps/include/dev/irq/arm-gicv3.h +links: +- role: build-dependency + uid: optarmgic-icc-bpr0 +- role: build-dependency + uid: optarmgic-icc-bpr1 +- role: build-dependency + uid: optarmgic-icc-ctrl +- role: build-dependency + uid: optarmgic-icc-igrpen0 +- role: build-dependency + uid: optarmgic-icc-igrpen1 +- role: build-dependency + uid: optarmgic-icc-pmr +- role: build-dependency + uid: optarmgic-icc-sre +source: +- bsps/shared/dev/irq/arm-gicv3.c +type: build |