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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-12 10:26:38 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-17 08:31:48 +0100 |
| commit | d2664faa39cfd17fa20c84d0ff1623335c21bdac (patch) | |
| tree | c6503cc795816f0c4f03ed74fd764878e017979b /spec/build/bsps/arm/xilinx-zynq | |
| parent | build: Format build items (diff) | |
| download | rtems-d2664faa39cfd17fa20c84d0ff1623335c21bdac.tar.bz2 | |
build: Replace variant patterns with a list
Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
Diffstat (limited to 'spec/build/bsps/arm/xilinx-zynq')
6 files changed, 15 insertions, 9 deletions
diff --git a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml index 0b10b47bc2..39cb972a74 100644 --- a/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml +++ b/spec/build/bsps/arm/xilinx-zynq/opta9periphclk.yml @@ -9,10 +9,10 @@ default: 100000000 default-by-variant: - value: 333333333 variants: - - arm/xilinx_zynq_zc702.* + - arm/xilinx_zynq_zc702 - value: 666666667 variants: - - arm/xilinx_zynq_zedboard.* + - arm/xilinx_zynq_zedboard description: | ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml b/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml index 1664b0fc31..23b1410385 100644 --- a/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml +++ b/spec/build/bsps/arm/xilinx-zynq/optcachedata.yml @@ -9,7 +9,9 @@ default: true default-by-variant: - value: false variants: - - arm/.*qemu + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu description: | enable data cache enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml b/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml index b191133af9..f172cc4b58 100644 --- a/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml +++ b/spec/build/bsps/arm/xilinx-zynq/optcacheinst.yml @@ -9,7 +9,9 @@ default: true default-by-variant: - value: false variants: - - arm/.*qemu + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu description: | enable instruction cache enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml b/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml index 1f93f52a8a..57b7187cdf 100644 --- a/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml +++ b/spec/build/bsps/arm/xilinx-zynq/optclkcpu1x.yml @@ -9,10 +9,10 @@ default: 111111111 default-by-variant: - value: 111111111 variants: - - arm/xilinx_zynq_zc702.* + - arm/xilinx_zynq_zc702 - value: 111111111 variants: - - arm/xilinx_zynq_zedboard.* + - arm/xilinx_zynq_zedboard description: | Zynq cpu_1x clock frequency in Hz enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml index b800b20428..61333a11f1 100644 --- a/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml +++ b/spec/build/bsps/arm/xilinx-zynq/optclkfastidle.yml @@ -9,7 +9,9 @@ default: false default-by-variant: - value: true variants: - - arm/.*qemu + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu description: | This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. enabled-by: true diff --git a/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml index 7d69273eb2..56a6056687 100644 --- a/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml +++ b/spec/build/bsps/arm/xilinx-zynq/optclkuart.yml @@ -9,10 +9,10 @@ default: 50000000 default-by-variant: - value: 50000000 variants: - - arm/xilinx_zynq_zc702.* + - arm/xilinx_zynq_zc702 - value: 50000000 variants: - - arm/xilinx_zynq_zedboard.* + - arm/xilinx_zynq_zedboard description: | Zynq UART clock frequency in Hz enabled-by: true |