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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-18 22:00:54 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-23 09:19:28 +0100 |
| commit | e164df5e33608576443b4cd5923a9046358ee773 (patch) | |
| tree | fe00beb9b25f50087d5a88f6401ffbb7b6059d4f /spec/build/bsps/arm/grp.yml | |
| parent | bsps/arm: Add arm-data-cache-loop-set-way.h (diff) | |
| download | rtems-e164df5e33608576443b4cd5923a9046358ee773.tar.bz2 | |
bsps/arm: Clear SCTLR[M, I, A, C] in start.S
Initialize the data and unified cache levels. Invalidate the
instruction cache levels.
Update #4202.
Diffstat (limited to 'spec/build/bsps/arm/grp.yml')
0 files changed, 0 insertions, 0 deletions