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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-22 13:00:27 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-23 09:24:49 +0100 |
| commit | 9f3a08ef2de99714d679aecf6b1ecb4e11869424 (patch) | |
| tree | 0d876016ae1dd067b1815dd79715cc7edc752f1e /spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml | |
| parent | bsps/arm: Invalidate TLB in start.S (diff) | |
| download | rtems-9f3a08ef2de99714d679aecf6b1ecb4e11869424.tar.bz2 | |
bsps: Use header file for GIC architecture support
This avoids a function call overhead in the interrupt dispatching.
Update #4202.
Diffstat (limited to 'spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml')
| -rw-r--r-- | spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml index c6732c4d47..b4b43ab106 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml @@ -129,7 +129,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c |