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| author | Chris Johns <chrisj@rtems.org> | 2018-01-23 13:23:55 +1100 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2018-02-01 14:59:55 +1100 |
| commit | 05015dc1886d08e9f9f3ed453688c52cebd4cc3f (patch) | |
| tree | 6b1401a111e2548a87aec4aa7e781f209233f9a9 /missing | |
| parent | bsps: Rework cache manager implementation (diff) | |
| download | rtems-05015dc1886d08e9f9f3ed453688c52cebd4cc3f.tar.bz2 | |
Xilinx AXI I2C driver IP race condition causes clock glitch.
Setting the PIRQ to 0 before reading the data produces a short clock pulse.
Moving the write to after reading the data fixes the issue.
Close #3173
Diffstat (limited to 'missing')
0 files changed, 0 insertions, 0 deletions