SPARC: optimize IRQ enable & disable

* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation

This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.

It was also possible to reduce the interrupt trap handler by
five instructions due to this.

1 files changed, 27 insertions, 4 deletions

diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t
index 5ed0ec6334..cd5602c2db 100644
--- a/doc/cpu_supplement/sparc.t
+++ b/doc/cpu_supplement/sparc.t
@@ -851,7 +851,12 @@ supported by the SPARC architecture with level fifteen (15)
 being the highest priority.  Level zero (0) indicates that
 interrupts are fully enabled.  Interrupt requests for interrupts
 with priorities less than or equal to the current interrupt mask
-level are ignored.
+level are ignored. Level fifteen (15) is a non-maskable interrupt
+(NMI), which makes it unsuitable for standard usage since it can
+affect the real-time behaviour by interrupting critical sections
+and spinlocks. Disabling traps stops also the NMI interrupt from
+happening. It can however be used for power-down or other
+critical events.
 
 Although RTEMS supports 256 interrupt levels, the
 SPARC only supports sixteen.  RTEMS interrupt levels 0 through
@@ -859,14 +864,21 @@ SPARC only supports sixteen.  RTEMS interrupt levels 0 through
 other RTEMS interrupt levels are undefined and their behavior is
 unpredictable.
 
+Many LEON SPARC v7/v8 systems features an extended interrupt controller
+which adds an extra step of interrupt decoding to allow handling of
+interrupt 16-31. When such an extended interrupt is generated the CPU
+traps into a specific interrupt trap level 1-14 and software reads out from
+the interrupt controller which extended interrupt source actually caused the
+interrupt.
+
 @subsection Disabling of Interrupts by RTEMS
 
 During the execution of directive calls, critical
 sections of code may be executed.  When these sections are
-encountered, RTEMS disables interrupts to level seven (15)
-before the execution of this section and restores them to the
+encountered, RTEMS disables interrupts to level fifteen (15)
+before the execution of the section and restores them to the
 previous level upon completion of the section.  RTEMS has been
-optimized to insure that interrupts are disabled for less than
+optimized to ensure that interrupts are disabled for less than
 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ 
 Mhz ERC32 with zero wait states.
 These numbers will vary based the number of wait states and
@@ -887,6 +899,17 @@ occur due to the inability of RTEMS to protect its critical
 sections.  However, ISRs that make no system calls may safely
 execute as non-maskable interrupts.
 
+Interrupts are disabled or enabled by performing a system call
+to the Operating System reserved software traps 9
+(SPARC_SWTRAP_IRQDIS) or 10 (SPARC_SWTRAP_IRQDIS). The trap is
+generated by the software trap (Ticc) instruction or indirectly
+by calling sparc_disable_interrupts() or sparc_enable_interrupts()
+functions. Disabling interrupts return the previous interrupt level
+(on trap entry) in register G1 and sets PSR.PIL to 15 to disable
+all maskable interrupts. The interrupt level can be restored by
+trapping into the enable interrupt handler with G1 containing the
+new interrupt level.
+
 @subsection Interrupt Stack
 
 The SPARC architecture does not provide for a