Test document.

1 files changed, 690 insertions, 0 deletions

diff --git a/doc/tools/bmenu/testdoc.texi b/doc/tools/bmenu/testdoc.texi
new file mode 100644
index 0000000000..da56254117
--- /dev/null
+++ b/doc/tools/bmenu/testdoc.texi
@@ -0,0 +1,690 @@
+@ifinfo
+@node Avenger Control Electronics System, Avenger Control Electronics System General System, DOCS PREV, DOCS UP
+@end ifinfo
+@chapter Avenger Control Electronics System
+@ifinfo
+@menu
+* Avenger Control Electronics System General System::
+* Avenger Control Electronics System System Modes::
+* Avenger Control Electronics System System BIT::
+@end menu
+@end ifinfo
+
+@ifinfo
+@node General System, Avenger Control Electronics System Monitor and Control Avenger, Avenger Control Electronics System, DOCS UP
+@end ifinfo
+@section General System
+@ifinfo
+@menu
+* Avenger Control Electronics System Monitor and Control Avenger::
+* Avenger Control Electronics System Control Weapons::
+* Avenger Control Electronics System Handle Tone Signals::
+* Avenger Control Electronics System Provide AVDAS::
+* Avenger Control Electronics System Perform Initial Power-On Sequence::
+* Avenger Control Electronics System Perform Post-power-on Initialization -- Deleted::
+* Avenger Control Electronics System Update AVDAS Port::
+* Avenger Control Electronics System Handle Minor Faults::
+* Avenger Control Electronics System General Mode::
+* Avenger Control Electronics System Mode Transition::
+* Avenger Control Electronics System Boot BIT::
+* Avenger Control Electronics System Background BIT::
+@end menu
+@end ifinfo
+
+@ifinfo
+@node Monitor and Control Avenger, Avenger Control Electronics System Control Weapons, General System, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Monitor and Control Avenger
+
+The AFCC shall be the main computer that monitors and controls all AVENGER
+system functions.  [MNTMN 1-21.b, MNTMN 11-3]
+
+@ifinfo
+@node Control Weapons, Avenger Control Electronics System Handle Tone Signals, Monitor and Control Avenger, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Control Weapons
+
+The AFCC shall be capable of tracking a single target, and controlling the
+missile and machine-gun systems.  [FUNCTIONAL]
+
+@ifinfo
+@node Handle Tone Signals, Avenger Control Electronics System Provide AVDAS, Control Weapons, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Handle Tone Signals
+
+The AFCC shall receive a tone signal from the IEA and IFF system.  [MNTMN
+11-3.a(3), MNTMN 11-3.b(1)] The AFCC shall generate a test tone.  [MNTMN
+11-3.a(3), MNTMN 11-3.b(2)] The AFCC shall also amplify the tone signals
+(target acquisition tone and IFF tone) from the IEA and IFF system and
+apply them to the communications system via the gunner's control box to
+the CVC helmet.  [MNTMN 11-3.a(3), MNTMN 11-3.b(2)] The IFF audio tone
+shall be mixed with the missile acquisition tone and built-in-test tone
+inside the AFCC.  [MNTMN 11-3.a(3), MNTMN 12-5.b(3&4)].
+
+@ifinfo
+@node Provide AVDAS, Avenger Control Electronics System Perform Initial Power-On Sequence, Handle Tone Signals, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Provide AVDAS
+
+The AFCC shall provide system status information on the AVDAS serial test
+port.  [FUNCTIONAL]
+
+@ifinfo
+@node Perform Initial Power-On Sequence, Avenger Control Electronics System Perform Post-power-on Initialization -- Deleted, Provide AVDAS, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Perform Initial Power-On Sequence
+
+During power-on, the AFCC shall perform the following:
+
+@itemize @bullet
+
+@item initialize all software programmable peripherals,
+
+@item set all A/D output values to zero,
+
+@item safe the laser range finder by setting both first return and last return to a high state,
+
+@item safe the machine-gun system,
+
+@item set the turret drive to high speed mode,
+
+@item set the following outputs inactive
+
+@enumerate 1
+@item  FLIR fire permit, missile active, RSO authorize, and uncage verify
+
+@item  sight fire permit, missile active, RSO authorize, and uncage verify
+
+@item  sight display active, and driven reticle
+
+@item  power interlock
+
+@item  FLIR field of view
+
+@item  IFF challenge
+
+@item  gunner palm grips and drift switch
+
+@item  fire command
+
+@item  uncage command
+
+@item  BIT initiate command
+
+@item  ATAS power on
+
+@item  sequence command
+
+@item  arm command
+
+@item  activate command
+
+@item  autotrack lock on command
+
+@item  laser fire command,
+
+@end enumerate
+
+@item set the following inputs to the indicated state
+
+@enumerate 1
+@item  uncage mode to AUTO
+
+@item  helicopter mode to OFF
+
+@item  track mode to MANUAL
+
+@item  turret drive mode to STAB.
+@end enumerate
+
+@item initialize the missile range tables in RAM from values in EPROM,
+
+@item clear the north reference value and fire permit limits.  [FUNCTIONAL]
+@end itemize
+
+@ifinfo
+@node Perform Post-power-on Initialization -- Deleted, Avenger Control Electronics System Update AVDAS Port, Perform Initial Power-On Sequence, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Perform Post-power-on Initialization -- Deleted
+
+Requirement was deleted.
+
+@ifinfo
+@node Update AVDAS Port, Avenger Control Electronics System Handle Minor Faults, Perform Post-power-on Initialization -- Deleted, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Update AVDAS Port
+
+The AFCC shall update the AVDAS port every 100ms.  [FUNCTIONAL]
+
+@ifinfo
+@node Handle Minor Faults, Avenger Control Electronics System System Modes, Update AVDAS Port, Avenger Control Electronics System System Modes
+@end ifinfo
+@subsection Handle Minor Faults
+
+Detection of a minor fault shall cause an error message to be displayed on
+the CDT and the system fault light to be lit.
+
+
+@ifinfo
+@node System Modes, Avenger Control Electronics System General Mode, Handle Minor Faults, DOCS UP
+@end ifinfo
+@section System Modes
+@ifinfo
+@menu
+* Avenger Control Electronics System General Mode::
+* Avenger Control Electronics System Mode Transition::
+* Avenger Control Electronics System Boot BIT::
+* Avenger Control Electronics System Background BIT::
+@end menu
+@end ifinfo
+
+
+@ifinfo
+@node General Mode, Avenger Control Electronics System Process System Mode Periodically -- Deleted, System Modes, Avenger Control Electronics System System BIT
+@end ifinfo
+@subsection General Mode
+@ifinfo
+@menu
+* Avenger Control Electronics System Process System Mode Periodically -- Deleted::
+* Avenger Control Electronics System Determine System Mode::
+* Avenger Control Electronics System OFF Mode::
+* Avenger Control Electronics System COMM Mode::
+* Avenger Control Electronics System SAFE Mode::
+* Avenger Control Electronics System RUN Mode::
+* Avenger Control Electronics System ENGAGE Mode::
+* Avenger Control Electronics System Mode Fault::
+* Avenger Control Electronics System ENGAGE Mode Processing::
+* Avenger Control Electronics System Process Transition to OFF Mode::
+* Avenger Control Electronics System Process Transition to COMM Mode::
+* Avenger Control Electronics System Process Transition to SAFE Mode::
+* Avenger Control Electronics System Process Transition to RUN Mode::
+* Avenger Control Electronics System Process Transition to ENGAGE Mode::
+@end menu
+@end ifinfo
+
+
+@ifinfo
+@node Process System Mode Periodically -- Deleted, Avenger Control Electronics System Determine System Mode, General Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection Process System Mode Periodically -- Deleted
+
+Requirement was deleted.
+
+@ifinfo
+@node Determine System Mode, Avenger Control Electronics System OFF Mode, Process System Mode Periodically -- Deleted, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection Determine System Mode
+
+The AFCC shall determine the system mode from the state of the system mode
+switch on the gunner's console and the remote mode indication from the
+remote terminal.  [FUNCTIONAL]
+
+@ifinfo
+@node OFF Mode, Avenger Control Electronics System COMM Mode, Determine System Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection OFF Mode
+
+If the system mode switch is in the OFF position, the system mode shall be
+OFF.  [FUNCTIONAL]
+
+@ifinfo
+@node COMM Mode, Avenger Control Electronics System SAFE Mode, OFF Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection COMM Mode
+
+If the system mode switch is in the COMM position, the system mode shall
+be COMM.  [FUNCTIONAL]
+
+@ifinfo
+@node SAFE Mode, Avenger Control Electronics System RUN Mode, COMM Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection SAFE Mode
+
+If the system mode switch is in the SAFE position, the system mode shall
+be SAFE.  [FUNCTIONAL]
+
+@ifinfo
+@node RUN Mode, Avenger Control Electronics System ENGAGE Mode, SAFE Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection RUN Mode
+
+If the system mode switch is in the RUN position, the system mode shall be
+RUN.  [FUNCTIONAL]
+
+@ifinfo
+@node ENGAGE Mode, Avenger Control Electronics System Mode Fault, RUN Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection ENGAGE Mode
+
+If the system mode switch is in the ENGAGE position, the system mode shall
+be ENGAGE or REMOTE.  [FUNCTIONAL]
+
+@ifinfo
+@node Mode Fault, Avenger Control Electronics System ENGAGE Mode Processing, ENGAGE Mode, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection Mode Fault
+
+If the system mode switch is not in a valid position, the system mode
+shall remain unchanged and the AFCC shall output 'MODE FAULT' to the CDT.
+[FUNCTIONAL]
+
+@ifinfo
+@node ENGAGE Mode Processing, Avenger Control Electronics System Mode Transition, Mode Fault, Avenger Control Electronics System Mode Transition
+@end ifinfo
+@subsubsection ENGAGE Mode Processing
+
+When the system is in the ENGAGE mode, the AFCC shall:
+
+@itemize @bullet
+
+@item perform auto slew processing,
+
+@item perform lead angle processing,
+
+@item perform autotrack processing,
+
+@item output rate commands to the turret drive system,
+
+@item control the firing of the weapons systems.  [FUNCTIONAL]
+
+@end itemize
+
+@ifinfo
+@node Mode Transition, Avenger Control Electronics System Process Transition to OFF Mode, ENGAGE Mode Processing, Avenger Control Electronics System System BIT
+@end ifinfo
+@subsection Mode Transition
+@ifinfo
+@menu
+* Avenger Control Electronics System Process Transition to OFF Mode::
+* Avenger Control Electronics System Process Transition to COMM Mode::
+* Avenger Control Electronics System Process Transition to SAFE Mode::
+* Avenger Control Electronics System Process Transition to RUN Mode::
+* Avenger Control Electronics System Process Transition to ENGAGE Mode::
+@end menu
+@end ifinfo
+
+The AFCC can operate in one of the following modes:  OFF, COMM, SAFE, RUN,
+or ENGAGE.  The mode transitions are depicted in Figure 3-1.
+
+@ifhtml
+@html
+<CENTER>
+<IMG SRC="modes.gif" ALT="Figure 3-1 Mode Transitions">
+</CENTER>
+@end html
+@end ifhtml
+
+@ifset use-ascii
+@example
+Figure 3-1 Mode Transitions - modes.gif
+@end example
+@end ifset
+
+@ifset use-tex
+@example
+Figure 3-1 Mode Transitions - modes.gif
+@end example
+@end ifset
+
+
+@ifinfo
+@node Process Transition to OFF Mode, Avenger Control Electronics System Process Transition to COMM Mode, Mode Transition, Avenger Control Electronics System Boot BIT
+@end ifinfo
+@subsubsection Process Transition to OFF Mode
+
+When the AFCC detects a valid transition to the OFF mode, the following
+actions shall be performed:
+
+@itemize @bullet
+
+@item update the elapsed time counter for the last mode the system was in,
+
+@item output 'OFF MODE' to the CDT,
+
+@item safe the laser by setting the last and first return to a high state,
+
+@item disable the turret drive system,
+
+@item disable the missile system,
+
+@item disable the machine-gun system,
+
+@item deactivate the sight and reticle,
+
+@item update the EEPROM with the current elapsed time and count values,
+
+@item disable continuous BIT,
+
+@item insure that the machine-gun cool down has completed before clearing the power hold circuit.  [FUNCTIONAL]
+
+@end itemize
+
+
+@ifinfo
+@node Process Transition to COMM Mode, Avenger Control Electronics System Process Transition to SAFE Mode, Process Transition to OFF Mode, Avenger Control Electronics System Boot BIT
+@end ifinfo
+@subsubsection Process Transition to COMM Mode
+
+When the AFCC detects a valid transition to the COMM mode, the following
+actions shall be performed:
+
+@itemize @bullet
+
+@item update the elapsed time counter for the last mode the system was in,
+
+@item output `COMM MODE' to the CDT,
+
+@item safe the laser by setting the last and first return to a high state,
+
+@item disable the turret drive system,
+
+@item disable the missile system,
+
+@item disable the machine-gun system,
+
+@item deactivate the sight and reticle,
+
+@item reset the power hold circuit to insure power if the system is put in the OFF mode,
+
+@item enable current monitoring.  [OPMAN 2-27.b(2), FUNCTIONAL]
+
+@end itemize
+
+@ifinfo
+@node Process Transition to SAFE Mode, Avenger Control Electronics System Process Transition to RUN Mode, Process Transition to COMM Mode, Avenger Control Electronics System Boot BIT
+@end ifinfo
+@subsubsection Process Transition to SAFE Mode
+
+When the AFCC detects a valid transition to the SAFE mode, the following
+actions shall be performed:
+
+@itemize @bullet
+
+@item update the elapsed time counter for the last mode the system was in,
+
+@item output `SAFE MODE' to the CDT,
+
+@item safe the laser by setting the last and first return to a high state,
+
+@item disable the turret drive system,
+
+@item disable the missile system,
+
+@item disable the machine-gun system,
+
+@item deactivate the sight and reticle,
+
+@item reset the power hold circuit to insure power if the system is put in the OFF mode,
+
+@item enable current monitoring.  [FUNCTIONAL]
+
+@end itemize
+
+@ifinfo
+@node Process Transition to RUN Mode, Avenger Control Electronics System Process Transition to ENGAGE Mode, Process Transition to SAFE Mode, Avenger Control Electronics System Boot BIT
+@end ifinfo
+@subsubsection Process Transition to RUN Mode
+
+When the AFCC detects a valid transition to the RUN mode, the following
+actions shall be performed:
+
+@itemize @bullet
+
+@item update the elapsed time counter for the last mode the system was in,
+
+@item output `RUN MODE' to the CDT,
+
+@item safe the laser by setting the last and first return to a high state,
+
+@item enable the turret drive system,
+
+@item disable the missile system,
+
+@item disable the machine-gun system,
+
+@item deactivate the sight and reticle,
+
+@item reset the power hold circuit to insure power if the system is put in the OFF mode,
+
+@item enable current monitoring.  [FUNCTIONAL]
+
+@end itemize
+
+@ifinfo
+@node Process Transition to ENGAGE Mode, Avenger Control Electronics System System BIT, Process Transition to RUN Mode, Avenger Control Electronics System Boot BIT
+@end ifinfo
+@subsubsection Process Transition to ENGAGE Mode
+
+When the AFCC detects a valid transition to the ENGAGE mode, the following
+actions shall be performed:
+
+@itemize @bullet
+
+@item update the elapsed time counter for the last mode the system was in,
+
+@item output `ENGAGE MODE' to the CDT,
+
+@item enable the turret drive system,
+
+@item enable the missile system power,
+
+@item reset the power hold circuit to insure power if the system is put in the OFF mode,
+
+@item enable current monitoring.  [FUNCTIONAL]
+
+@end itemize
+
+@ifinfo
+@node System BIT, Avenger Control Electronics System Boot BIT, Process Transition to ENGAGE Mode, DOCS UP
+@end ifinfo
+@section System BIT
+@ifinfo
+@menu
+* Avenger Control Electronics System Boot BIT::
+* Avenger Control Electronics System Background BIT::
+@end menu
+@end ifinfo
+
+
+@ifinfo
+@node Boot BIT, Avenger Control Electronics System Perform ROM Checksum, System BIT, DOCS UP
+@end ifinfo
+@subsection Boot BIT
+@ifinfo
+@menu
+* Avenger Control Electronics System Perform ROM Checksum::
+* Avenger Control Electronics System Boot Test AFCC Boards::
+* Avenger Control Electronics System Boot Test CPU Board::
+* Avenger Control Electronics System Boot Test AFCC Controller Board DAC's::
+* Avenger Control Electronics System Boot Test Interface Board Discrete Inputs::
+* Avenger Control Electronics System Boot Test AFCC Controller Board Relay and Discrete Outputs::
+* Avenger Control Electronics System Boot Check Voltages::
+* Avenger Control Electronics System Boot Handle Fatal Error::
+* Avenger Control Electronics System Perform Background BIT::
+* Avenger Control Electronics System Background Process CPU and Software Exceptions::
+* Avenger Control Electronics System Background Test AFCC Controller Board DAC's::
+* Avenger Control Electronics System Background Test AFCC Controller Board Relay and Discrete Outputs::
+* Avenger Control Electronics System Perform RAM Checksum::
+* Avenger Control Electronics System Background Monitor Voltages::
+* Avenger Control Electronics System Background Handle Fatal Error::
+@end menu
+@end ifinfo
+
+
+@ifinfo
+@node Perform ROM Checksum, Avenger Control Electronics System Boot Test AFCC Boards, Boot BIT, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Perform ROM Checksum
+
+During initialization of the AFCC, the AFCC shall checksum the code image
+stored in ROM to insure that it is correct.  If the checksum does not
+match the code image, the system shall halt.
+
+@ifinfo
+@node Boot Test AFCC Boards, Avenger Control Electronics System Boot Test CPU Board, Perform ROM Checksum, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Test AFCC Boards
+
+During initialization of the AFCC, all boards shall be tested to determine
+their functional state.  If all tests performed on a board pass, the board
+shall have a functional state of passed.  If any test performed on a board
+fails, the board shall have a functional state of failed.
+
+@ifinfo
+@node Boot Test CPU Board, Avenger Control Electronics System Boot Test AFCC Controller Board DAC's, Boot Test AFCC Boards, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Test CPU Board
+
+During initialization of the AFCC, the AFCC shall test the following CPU
+board components by invoking all non-destructive card-level diagnostic
+tests provided by the CPU board vendor.  If any CPU board component fails
+diagnostic testing, a fatal error shall occur.
+
+@ifinfo
+@node Boot Test AFCC Controller Board DAC's, Avenger Control Electronics System Boot Test Interface Board Discrete Inputs, Boot Test CPU Board, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Test AFCC Controller Board DAC's
+
+During initialization of the AFCC, the AFCC shall utilize the DAC test
+capability of the AFCC Controller board to verify that the DAC components
+of the AFCC Controller board are set to their initial values.  If any DAC
+component is not properly set, a fatal error shall occur.
+
+@ifinfo
+@node Boot Test Interface Board Discrete Inputs, Avenger Control Electronics System Boot Test AFCC Controller Board Relay and Discrete Outputs, Boot Test AFCC Controller Board DAC's, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Test Interface Board Discrete Inputs
+
+During initialization of the AFCC, the AFCC shall utilize the discrete
+input loopback capability of the AFCC Interface board to test that the
+discrete input components of the AFCC Interface board are working
+properly.  If any discrete input component does not function properly, a
+fatal error shall occur.
+
+@ifinfo
+@node Boot Test AFCC Controller Board Relay and Discrete Outputs, Avenger Control Electronics System Boot Check Voltages, Boot Test Interface Board Discrete Inputs, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Test AFCC Controller Board Relay and Discrete Outputs
+
+During initialization of the AFCC, the AFCC shall utilize the relay and
+discrete output test capability of the AFCC Controller board to verify
+that the relay and discrete output components of the AFCC Controller board
+are set to their initial values.  If any relay or discrete output
+component is not properly set, a fatal error shall occur.
+
+@ifinfo
+@node Boot Check Voltages, Avenger Control Electronics System Boot Handle Fatal Error, Boot Test AFCC Controller Board Relay and Discrete Outputs, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Check Voltages
+
+During initialization of the AFCC, the +5 volt, +15 volt, -15 volt, and
++28 volt power supplies shall be checked to insure that they are within
+tolerance.  If any of the power supplies are out of tolerance, a fatal
+error shall occur.
+
+@ifinfo
+@node Boot Handle Fatal Error, Avenger Control Electronics System Background BIT, Boot Check Voltages, Avenger Control Electronics System Background BIT
+@end ifinfo
+@subsubsection Boot Handle Fatal Error
+
+If a fatal error occurs during initialization, the AFCC shall attempt to
+output a diagnostic message to the CDT and halt initialization.
+
+@ifinfo
+@node Background BIT, Avenger Control Electronics System Perform Background BIT, Boot Handle Fatal Error, DOCS UP
+@end ifinfo
+@subsection Background BIT
+@ifinfo
+@menu
+* Avenger Control Electronics System Perform Background BIT::
+* Avenger Control Electronics System Background Process CPU and Software Exceptions::
+* Avenger Control Electronics System Background Test AFCC Controller Board DAC's::
+* Avenger Control Electronics System Background Test AFCC Controller Board Relay and Discrete Outputs::
+* Avenger Control Electronics System Perform RAM Checksum::
+* Avenger Control Electronics System Background Monitor Voltages::
+* Avenger Control Electronics System Background Handle Fatal Error::
+@end menu
+@end ifinfo
+
+
+@ifinfo
+@node Perform Background BIT, Avenger Control Electronics System Background Process CPU and Software Exceptions, Background BIT, DOCS UP
+@end ifinfo
+@subsubsection Perform Background BIT
+
+During normal operation of the AFCC, the AFCC shall perform background BIT
+of various system components.  Background BIT shall be performed during
+system idle time.
+
+@ifinfo
+@node Background Process CPU and Software Exceptions, Avenger Control Electronics System Background Test AFCC Controller Board DAC's, Perform Background BIT, DOCS UP
+@end ifinfo
+@subsubsection Background Process CPU and Software Exceptions
+
+During normal operation of the AFCC, the AFCC shall recognize all CPU and
+software exceptions.  If any exception occurs, a fatal error shall occur.
+
+@ifinfo
+@node Background Test AFCC Controller Board DAC's, Avenger Control Electronics System Background Test AFCC Controller Board Relay and Discrete Outputs, Background Process CPU and Software Exceptions, DOCS UP
+@end ifinfo
+@subsubsection Background Test AFCC Controller Board DAC's
+
+During background BIT, the AFCC shall utilize the DAC test capability of
+the AFCC Controller board to verify that the DAC components of the AFCC
+Controller board are set to their last written values.  If any DAC
+component is not properly set, a fatal error shall occur.
+
+@ifinfo
+@node Background Test AFCC Controller Board Relay and Discrete Outputs, Avenger Control Electronics System Perform RAM Checksum, Background Test AFCC Controller Board DAC's, DOCS UP
+@end ifinfo
+@subsubsection Background Test AFCC Controller Board Relay and Discrete Outputs
+
+During background BIT, the AFCC shall utilize the relay and discrete
+output test capability of the AFCC Controller board to verify that the
+relay and discrete output components of the AFCC Controller board are set
+to their last written values.  If any relay or discrete output component
+is not properly set, a fatal error shall occur.
+
+@ifinfo
+@node Perform RAM Checksum, Avenger Control Electronics System Background Monitor Voltages, Background Test AFCC Controller Board Relay and Discrete Outputs, DOCS UP
+@end ifinfo
+@subsubsection Perform RAM Checksum
+
+During background BIT, the AFCC shall checksum the code image to insure
+that it is correct.  If the checksum does not match the code image, a
+fatal error shall occur.
+
+@ifinfo
+@node Background Monitor Voltages, Avenger Control Electronics System Background Handle Fatal Error, Perform RAM Checksum, DOCS UP
+@end ifinfo
+@subsubsection Background Monitor Voltages
+
+During background BIT, the AFCC shall monitor the +5 volt, +15 volt, -15
+volt, and +28 volt power supplies to insure that they are within
+tolerance.  If any of the power supplies are out of tolerance, a fatal
+error shall occur.
+
+@ifinfo
+@node Background Handle Fatal Error, DOCS NEXT, Background Monitor Voltages, DOCS UP
+@end ifinfo
+@subsubsection Background Handle Fatal Error
+
+When the AFCC detects a fatal error, the following shall be attempted:
+
+@enumerate a
+
+@item light the fault light on the gunner console,
+
+@item stop the execution of all tasks,
+
+@item reset all hardware outputs to a safe state,
+
+@item store a failure code or message in the EEPROM,
+
+@item output a diagnostic message to the CDT and Console port,
+
+@item halt the system.
+
+@end enumerate
+
+