path: root/doc/supplements
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authorJoel Sherrill <>1998-10-19 19:39:55 +0000
committerJoel Sherrill <>1998-10-19 19:39:55 +0000
commit69b5f9d261eb13de28d0e06ccae23f9cef2bf626 (patch)
tree696a0acb1e0d8972a457588ececd74cab76f73d2 /doc/supplements
parent34f058eef5b08555be610e475b6135b400ef9d16 (diff)
Renamed memmodel.texi to memmodel.t.
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1 files changed, 0 insertions, 119 deletions
diff --git a/doc/supplements/sparc/memmodel.texi b/doc/supplements/sparc/memmodel.texi
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-@c COPYRIGHT (c) 1988-1998.
-@c On-Line Applications Research Corporation (OAR).
-@c All rights reserved.
-@c $Id$
-@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
-@end ifinfo
-@chapter Memory Model
-* Memory Model Introduction::
-* Memory Model Flat Memory Model::
-@end menu
-@end ifinfo
-@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
-@end ifinfo
-@section Introduction
-A processor may support any combination of memory
-models ranging from pure physical addressing to complex demand
-paged virtual memory systems. RTEMS supports a flat memory
-model which ranges contiguously over the processor's allowable
-address space. RTEMS does not support segmentation or virtual
-memory of any kind. The appropriate memory model for RTEMS
-provided by the targeted processor and related characteristics
-of that model are described in this chapter.
-@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
-@end ifinfo
-@section Flat Memory Model
-The SPARC architecture supports a flat 32-bit address
-space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
-gigabytes). Each address is represented by a 32-bit value and
-is byte addressable. The address may be used to reference a
-single byte, half-word (2-bytes), word (4 bytes), or doubleword
-(8 bytes). Memory accesses within this address space are
-performed in big endian fashion by the SPARC. Memory accesses
-which are not properly aligned generate a "memory address not
-aligned" trap (type number 7). The following table lists the
-alignment requirements for a variety of data accesses:
-@ifset use-ascii
- +--------------+-----------------------+
- | Data Type | Alignment Requirement |
- +--------------+-----------------------+
- | byte | 1 |
- | half-word | 2 |
- | word | 4 |
- | doubleword | 8 |
- +--------------+-----------------------+
-@end group
-@end example
-@end ifset
-@ifset use-tex
-@sp 1
-\hbox to 1.75in{\enskip\hfil#\hfil}&
-\hbox to 1.75in{\enskip\hfil#\hfil}&
-&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
-@end tex
-@end ifset
-@ifset use-html
-<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
- <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
-<TR><TD ALIGN=center>byte</TD>
- <TD ALIGN=center>1</TD></TR>
-<TR><TD ALIGN=center>half-word</TD>
- <TD ALIGN=center>2</TD></TR>
-<TR><TD ALIGN=center>word</TD>
- <TD ALIGN=center>4</TD></TR>
-<TR><TD ALIGN=center>doubleword</TD>
- <TD ALIGN=center>8</TD></TR>
- </TABLE>
-@end html
-@end ifset
-Doubleword load and store operations must use a pair
-of registers as their source or destination. This pair of
-registers must be an adjacent pair of registers with the first
-of the pair being even numbered. For example, a valid
-destination for a doubleword load might be input registers 0 and
-1 (i0 and i1). The pair i1 and i2 would be invalid. [NOTE:
-Some assemblers for the SPARC do not generate an error if an odd
-numbered register is specified as the beginning register of the
-pair. In this case, the assembler assumes that what the
-programmer meant was to use the even-odd pair which ends at the
-specified register. This may or may not have been a correct
-RTEMS does not support any SPARC Memory Management
-Units, therefore, virtual memory or segmentation systems
-involving the SPARC are not supported.