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authorJoel Sherrill <joel.sherrill@OARcorp.com>1998-10-19 19:53:26 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1998-10-19 19:53:26 +0000
commit2df2befc332068c3a4f87202a6b5b55b4838e57a (patch)
tree36b0b4658184539ff0d101dc83ee26c75b12151f /doc/supplements
parent17c26806a46ff3e468f4a8fae2483478452a4cd8 (diff)
downloadrtems-2df2befc332068c3a4f87202a6b5b55b4838e57a.tar.bz2
No node info
Diffstat (limited to 'doc/supplements')
-rw-r--r--doc/supplements/sparc/timeERC32.t46
1 files changed, 1 insertions, 45 deletions
diff --git a/doc/supplements/sparc/timeERC32.t b/doc/supplements/sparc/timeERC32.t
index 0fcbc748c9..dd2d12edbc 100644
--- a/doc/supplements/sparc/timeERC32.t
+++ b/doc/supplements/sparc/timeERC32.t
@@ -11,36 +11,8 @@
\global\advance \smallskipamount by -4pt
@end tex
-@ifinfo
-@node ERC32 Timing Data, ERC32 Timing Data Introduction, Timing Specification Terminology, Top
-@end ifinfo
@chapter ERC32 Timing Data
-@ifinfo
-@menu
-* ERC32 Timing Data Introduction::
-* ERC32 Timing Data Hardware Platform::
-* ERC32 Timing Data Interrupt Latency::
-* ERC32 Timing Data Context Switch::
-* ERC32 Timing Data Directive Times::
-* ERC32 Timing Data Task Manager::
-* ERC32 Timing Data Interrupt Manager::
-* ERC32 Timing Data Clock Manager::
-* ERC32 Timing Data Timer Manager::
-* ERC32 Timing Data Semaphore Manager::
-* ERC32 Timing Data Message Manager::
-* ERC32 Timing Data Event Manager::
-* ERC32 Timing Data Signal Manager::
-* ERC32 Timing Data Partition Manager::
-* ERC32 Timing Data Region Manager::
-* ERC32 Timing Data Dual-Ported Memory Manager::
-* ERC32 Timing Data I/O Manager::
-* ERC32 Timing Data Rate Monotonic Manager::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node ERC32 Timing Data Introduction, ERC32 Timing Data Hardware Platform, ERC32 Timing Data, ERC32 Timing Data
-@end ifinfo
+
@section Introduction
The timing data for RTEMS on the ERC32 implementation
@@ -52,9 +24,6 @@ provided. Also, provided is a description of the interrupt
latency and the context switch times as they pertain to the
SPARC version of RTEMS.
-@ifinfo
-@node ERC32 Timing Data Hardware Platform, ERC32 Timing Data Interrupt Latency, ERC32 Timing Data Introduction, ERC32 Timing Data
-@end ifinfo
@section Hardware Platform
All times reported in this chapter were measured
@@ -82,9 +51,6 @@ with one microsecond accuracy. All sources of hardware
interrupts were disabled, although traps were enabled and the
interrupt level of the SPARC allows all interrupts.
-@ifinfo
-@node ERC32 Timing Data Interrupt Latency, ERC32 Timing Data Context Switch, ERC32 Timing Data Hardware Platform, ERC32 Timing Data
-@end ifinfo
@section Interrupt Latency
The maximum period with traps disabled or the
@@ -127,9 +93,6 @@ generated on the SIS benchmark platform using the ERC32's
ability to forcibly generate an arbitrary interrupt as the
source of the "benchmark" interrupt.
-@ifinfo
-@node ERC32 Timing Data Context Switch, RTEMS_CPU_MODEL Timing Data Directive Times, ERC32 Timing Data Interrupt Latency, ERC32 Timing Data
-@end ifinfo
@section Context Switch
The RTEMS processor context switch time is 10
@@ -155,10 +118,3 @@ the numeric coprocessor.
The following table summarizes the context switch
times for the ERC32 benchmark platform:
-@include timetbl.texi
-
-@tex
-\global\advance \smallskipamount by 4pt
-@end tex
-
-